1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Oxide Computer Company 14 */ 15 16 #ifndef _SYS_AMDZEN_DF_H 17 #define _SYS_AMDZEN_DF_H 18 19 /* 20 * This file contains definitions for the registers that appears in the AMD Zen 21 * Data Fabric. The data fabric is the main component which routes transactions 22 * between entities (e.g. CPUS, DRAM, PCIe, etc.) in the system. The data fabric 23 * itself is made up of up to 8 PCI functions. There can be multiple instances 24 * of the data fabric. There is one instance per die. In most AMD processors 25 * after Zen 1, there is only a single die per socket, for more background see 26 * the uts/i86pc/os/cpuid.c big theory statement. All data fabric instances 27 * appear on PCI bus 0. The first instance shows up on device 0x18. Subsequent 28 * instances simply increment that number by one. 29 * 30 * There are currently four major revisions of the data fabric that are 31 * supported here, which are v2 (Zen 1), v3 (Zen 2/3), v3.5 (Zen 2/3 with DDR5), 32 * and v4 (Zen 4). In many cases, while the same logical thing exists in 33 * different generations, they often have different shapes and sometimes things 34 * with the same shape show up in different locations. As DFv4 has been extended 35 * across several different lines, things haven't been quite as smooth as we'd 36 * like in terms of DF representation. Certain things end up moving around much 37 * more liberally while revving the minor version of the DF, though at least we 38 * can still identify it as such. 39 * 40 * The major (relevant to us) distinction that we have found so far is that 41 * starting in DF 4v2 and greater, the way that DRAM was structured and the 42 * corresponding DRAM channel remap settings were moved. Because the DRAM base 43 * address registers were moved to 0x200, we call this DF_REV_4D2. If this 44 * gets much more nuanced, we should likely figure out if we want to encode 45 * minor versions in these constants and offer function pointers to get common 46 * things rather than forcing it onto clients. Note that this is very much a 47 * rough approximation and not really great. There are many places where the 48 * width of fields has changed slightly between minor revs, but are eating up 49 * more reserved bits, or not using quite as many. 50 * 51 * To make things a little easier for clients, each register definition encodes 52 * enough information to also include which hardware generations it supports, 53 * the actual PCI function it appears upon, and the register offset. This is to 54 * make sure that consumers don't have to guess some of this information in the 55 * latter cases and we can try to guarantee we're not accessing an incorrect 56 * register for our platform (unfortunately at runtime). 57 * 58 * Register definitions have the following form: 59 * 60 * DF_<reg name>_<vers> 61 * 62 * Here <reg name> is something that describes the register. This may not be the 63 * exact same as the PPR (processor programming reference); however, the PPR 64 * name for the register will be included above it in a comment (though these 65 * have sometimes changed from time to time). For example, DF_DRAM_HOLE. If a 66 * given register is the same in all currently supported versions, then there is 67 * no version suffix appended. Otherwise, the first version it is supported in 68 * is appended. For example, DF_DRAM_BASE_V2, DF_DRAM_BASE_V3, DF_DRAM_BASE_V4, 69 * etc. or DF_FIDMASK0_V3P5, etc. If the register offset is the same in multiple 70 * versions, then there they share the earliest version. 71 * 72 * For fields there are currently macros to extract these or chain them together 73 * leveraging bitx32() and bitset32(). Fields have the forms: 74 * 75 * DF_<reg name>_<vers>_GET_<field> 76 * DF_<reg name>_<vers>_SET_<field> 77 * 78 * Like in the above, if there are cases where a single field is the same across 79 * all versions, then the <vers> portion will be elided. There are many cases 80 * where the register definition does not change, but the fields themselves do 81 * change with each version because each hardware rev opts to be slightly 82 * different. 83 * 84 * When adding support for a new chip, please look carefully through the 85 * requisite documentation to ensure that they match what we see here. There are 86 * often cases where there may be a subtle thing or you hit a case like V3P5 87 * that until you dig deeper just seem to be weird. 88 */ 89 90 #include <sys/bitext.h> 91 92 #ifdef __cplusplus 93 extern "C" { 94 #endif 95 96 typedef enum df_rev { 97 DF_REV_UNKNOWN = 0, 98 DF_REV_2 = 1 << 0, 99 DF_REV_3 = 1 << 1, 100 DF_REV_3P5 = 1 << 2, 101 DF_REV_4 = 1 << 3, 102 /* 103 * This is a synthetic revision we make up per the theory statement that 104 * covers devices that have an updated DRAM layout. 105 */ 106 DF_REV_4D2 = 1 << 4 107 } df_rev_t; 108 109 #define DF_REV_ALL_3 (DF_REV_3 | DF_REV_3P5) 110 #define DF_REV_ALL_23 (DF_REV_2 | DF_REV_ALL_3) 111 #define DF_REV_ALL_4 (DF_REV_4 | DF_REV_4D2) 112 #define DF_REV_ALL (DF_REV_ALL_23 | DF_REV_ALL_4) 113 114 typedef struct df_reg_def { 115 df_rev_t drd_gens; 116 uint8_t drd_func; 117 uint16_t drd_reg; 118 } df_reg_def_t; 119 120 /* 121 * This set of registers provides us access to the count of instances in the 122 * data fabric and then a number of different pieces of information about them 123 * like their type. Note, these registers require indirect access because the 124 * information cannot be broadcast. 125 */ 126 127 /* 128 * DF::FabricBlockInstanceCount -- Describes the number of instances in the data 129 * fabric. With v4, also includes versioning information. 130 */ 131 /*CSTYLED*/ 132 #define DF_FBICNT (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 133 .drd_func = 0, .drd_reg = 0x40 } 134 #define DF_FBICNT_V4_GET_MAJOR(r) bitx32(r, 27, 24) 135 #define DF_FBICNT_V4_GET_MINOR(r) bitx32(r, 23, 16) 136 #define DF_FBICNT_GET_COUNT(r) bitx32(r, 7, 0) 137 138 /* 139 * DF::FabricBlockInstanceInformation0 -- get basic information about a fabric 140 * instance. 141 */ 142 /*CSTYLED*/ 143 #define DF_FBIINFO0 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 144 .drd_func = 0, .drd_reg = 0x44 } 145 #define DF_FBIINFO0_GET_SUBTYPE(r) bitx32(r, 26, 24) 146 #define DF_SUBTYPE_NONE 0 147 typedef enum { 148 DF_CAKE_SUBTYPE_GMI = 1, 149 DF_CAKE_SUBTYPE_xGMI = 2 150 } df_cake_subtype_t; 151 152 typedef enum { 153 DF_IOM_SUBTYPE_IOHUB = 1, 154 } df_iom_subtype_t; 155 156 typedef enum { 157 DF_CS_SUBTYPE_UMC = 1, 158 /* 159 * The subtype changed beginning in DFv4. Prior to DFv4, the secondary 160 * type was CCIX. Starting with DFv4, this is now CMP. It is unclear if 161 * these are the same thing or not. 162 */ 163 DF_CS_SUBTYPE_CCIX = 2, 164 DF_CS_SUBTYPE_CMP = 2 165 } df_cs_subtype_t; 166 167 /* 168 * Starting in DFv4 they introduced a CCM subtype; however, kept the CPU 169 * compatible with prior DF revisions in v4.0. Starting with v4.1, they moved 170 * this to a value of one and the less asked about the ACM the better. 171 * Unfortunately this doesn't fit nicely with the major DF revisions which we 172 * use for register access. 173 */ 174 typedef enum { 175 DF_CCM_SUBTYPE_CPU_V2 = 0, 176 DF_CCM_SUBTYPE_ACM_V4 = 1, 177 DF_CCM_SUBTYPE_CPU_V4P1 = 1 178 } df_ccm_subtype_v4_t; 179 180 typedef enum { 181 DF_NCM_SUBTYPE_MMHUB = 1, 182 DF_NCM_SUBTYPE_DCE = 2, 183 DF_NCM_SUBTYPE_IOMMU = 4 184 } df_ncm_subtype_t; 185 186 187 #define DF_FBIINFO0_GET_HAS_MCA(r) bitx32(r, 23, 23) 188 #define DF_FBIINFO0_GET_FTI_DCNT(r) bitx32(r, 21, 20) 189 #define DF_FBIINFO0_GET_FTI_PCNT(r) bitx32(r, 18, 16) 190 #define DF_FBIINFO0_GET_SDP_RESPCNT(r) bitx32(r, 14, 14) 191 #define DF_FBIINFO0_GET_SDP_PCNT(r) bitx32(r, 13, 12) 192 #define DF_FBIINFO0_GET_FTI_WIDTH(r) bitx32(r, 9, 8) 193 typedef enum { 194 DF_FTI_W_64 = 0, 195 DF_FTI_W_128, 196 DF_FTI_W_256, 197 DF_FTI_W_512 198 } df_fti_width_t; 199 #define DF_FBIINFO0_V3_GET_ENABLED(r) bitx32(r, 6, 6) 200 #define DF_FBIINFO0_GET_SDP_WIDTH(r) bitx32(r, 5, 4) 201 typedef enum { 202 DF_SDP_W_64 = 0, 203 DF_SDP_W_128, 204 DF_SDP_W_256, 205 DF_SDP_W_512 206 } df_sdp_width_t; 207 #define DF_FBIINFO0_GET_TYPE(r) bitx32(r, 3, 0) 208 typedef enum { 209 DF_TYPE_CCM = 0, 210 DF_TYPE_GCM, 211 DF_TYPE_NCM, 212 DF_TYPE_IOMS, 213 DF_TYPE_CS, 214 DF_TYPE_NCS, 215 DF_TYPE_TCDX, 216 DF_TYPE_PIE, 217 DF_TYPE_SPF, 218 DF_TYPE_LLC, 219 DF_TYPE_CAKE, 220 DF_TYPE_ICNG, 221 DF_TYPE_PFX, 222 DF_TYPE_CNLI 223 } df_type_t; 224 225 /* 226 * DF::FabricBlockInstanceInformation1 -- get basic information about a fabric 227 * instance. This appears to have been dropped starting in DF 4D2. 228 */ 229 /*CSTYLED*/ 230 #define DF_FBIINFO1 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \ 231 DF_REV_4, .drd_func = 0, .drd_reg = 0x48 } 232 #define DF_FBINFO1_GET_FTI3_NINSTID(r) bitx32(r, 31, 24) 233 #define DF_FBINFO1_GET_FTI2_NINSTID(r) bitx32(r, 23, 16) 234 #define DF_FBINFO1_GET_FTI1_NINSTID(r) bitx32(r, 15, 8) 235 #define DF_FBINFO1_GET_FTI0_NINSTID(r) bitx32(r, 7, 0) 236 237 /* 238 * DF::FabricBlockInstanceInformation2 -- get basic information about a fabric 239 * instance. This appears to have been dropped starting in DF 4D2. 240 */ 241 /*CSTYLED*/ 242 #define DF_FBIINFO2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \ 243 DF_REV_4, .drd_func = 0, .drd_reg = 0x4c } 244 #define DF_FBINFO2_GET_FTI5_NINSTID(r) bitx32(r, 15, 8) 245 #define DF_FBINFO2_GET_FTI4_NINSTID(r) bitx32(r, 7, 0) 246 247 /* 248 * DF::FabricBlockInstanceInformation3 -- obtain the basic IDs for a given 249 * instance. 250 */ 251 /*CSTYLED*/ 252 #define DF_FBIINFO3 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 253 .drd_func = 0, .drd_reg = 0x50 } 254 #define DF_FBIINFO3_V2_GET_BLOCKID(r) bitx32(r, 15, 8) 255 #define DF_FBIINFO3_V3_GET_BLOCKID(r) bitx32(r, 13, 8) 256 #define DF_FBIINFO3_V3P5_GET_BLOCKID(r) bitx32(r, 11, 8) 257 #define DF_FBIINFO3_V4_GET_BLOCKID(r) bitx32(r, 19, 8) 258 #define DF_FBIINFO3_GET_INSTID(r) bitx32(r, 7, 0) 259 260 /* 261 * DF::DfCapability -- Describes the capabilities that the DF has. 262 */ 263 /*CSTYLED*/ 264 #define DF_CAPAB (df_reg_def_t){ .drd_gens = DF_REV_ALL, \ 265 .drd_func = 0, .drd_reg = 0x90 } 266 #define DF_CAPAB_GET_EXTCSREMAP(r) bitx32(r, 2, 2); 267 #define DF_CAPAB_GET_SPF(r) bitx32(r, 1, 1); 268 #define DF_CAPAB_GET_POISON(r) bitx32(r, 0, 0); 269 270 /* 271 * DF::Skt0CsTargetRemap0, DF::Skt0CsTargetRemap1, DF::Skt1CsTargetRemap0, 272 * DF::Skt1CsTargetRemap1 -- The next set of registers provide access to 273 * chip-select remapping. Caution, while these have a documented DF generation 274 * that they are specific to, it seems they still aren't always implemented and 275 * are specific to Milan (v3) and Genoa (v4). The actual remap extraction is the 276 * same between both. 277 */ 278 #define DF_CS_REMAP_GET_CSX(r, x) bitx32(r, (3 + (4 * (x))), (4 * ((x)))) 279 /*CSTYLED*/ 280 #define DF_SKT0_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 281 .drd_func = 0, .drd_reg = 0x60 } 282 /*CSTYLED*/ 283 #define DF_SKT1_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 284 .drd_func = 0, .drd_reg = 0x68 } 285 /*CSTYLED*/ 286 #define DF_SKT0_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 287 .drd_func = 0, .drd_reg = 0x64 } 288 /*CSTYLED*/ 289 #define DF_SKT1_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 290 .drd_func = 0, .drd_reg = 0x6c } 291 /* 292 * DF::CsTargetRemap0A, DF::CsTargetRemap0B, etc. -- These registers contain the 293 * remap engines in DFv4. Note, that while v3 used 0/1 as REMAP[01], as 294 * referring to the same logical set of things, here [0-3] is used for different 295 * things and A/B distinguish the different actual CS values. This was redone to 296 * allow for a wider channel selection in the 4D2 parts, see the subsequent 297 * section. 298 */ 299 /*CSTYLED*/ 300 #define DF_CS_REMAP0A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 301 .drd_func = 7, .drd_reg = 0x180 } 302 /*CSTYLED*/ 303 #define DF_CS_REMAP0B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 304 .drd_func = 7, .drd_reg = 0x184 } 305 /*CSTYLED*/ 306 #define DF_CS_REMAP1A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 307 .drd_func = 7, .drd_reg = 0x188 } 308 /*CSTYLED*/ 309 #define DF_CS_REMAP1B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 310 .drd_func = 7, .drd_reg = 0x18c } 311 /*CSTYLED*/ 312 #define DF_CS_REMAP2A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 313 .drd_func = 7, .drd_reg = 0x190 } 314 /*CSTYLED*/ 315 #define DF_CS_REMAP2B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 316 .drd_func = 7, .drd_reg = 0x194 } 317 /*CSTYLED*/ 318 #define DF_CS_REMAP3A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 319 .drd_func = 7, .drd_reg = 0x198 } 320 /*CSTYLED*/ 321 #define DF_CS_REMAP3B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \ 322 .drd_func = 7, .drd_reg = 0x19c } 323 324 /* 325 * DF::CsTargetRemap0A, DF::CsTargetRemap0B, etc. -- D42 edition. This has 326 * changed the actual size of the remap values so that they are now 5 bits wide, 327 * allowing for up to 32 channels. This is indicated by bit 2 (EXTCSREMAP) in 328 * DF::DfCapability. As a result, there are now only 6 remaps per register, so 329 * there are now 3 registers [ABC] per remap target [0123]. 330 * changing around where the registers actually are. 331 */ 332 #define DF_CS_REMAP_GET_CSX_V4B(r, x) bitx32(r, (4 + (5 * (x))), (5 * ((x)))) 333 /*CSTYLED*/ 334 #define DF_CS_REMAP0A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 335 .drd_func = 7, .drd_reg = 0x180 } 336 /*CSTYLED*/ 337 #define DF_CS_REMAP0B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 338 .drd_func = 7, .drd_reg = 0x184 } 339 /*CSTYLED*/ 340 #define DF_CS_REMAP0C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 341 .drd_func = 7, .drd_reg = 0x188 } 342 /*CSTYLED*/ 343 #define DF_CS_REMAP1A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 344 .drd_func = 7, .drd_reg = 0x198 } 345 /*CSTYLED*/ 346 #define DF_CS_REMAP1B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 347 .drd_func = 7, .drd_reg = 0x19c } 348 /*CSTYLED*/ 349 #define DF_CS_REMAP1C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 350 .drd_func = 7, .drd_reg = 0x1a0 } 351 /*CSTYLED*/ 352 #define DF_CS_REMAP2A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 353 .drd_func = 7, .drd_reg = 0x1b0 } 354 /*CSTYLED*/ 355 #define DF_CS_REMAP2B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 356 .drd_func = 7, .drd_reg = 0x1b4 } 357 /*CSTYLED*/ 358 #define DF_CS_REMAP2C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 359 .drd_func = 7, .drd_reg = 0x1b8 } 360 /*CSTYLED*/ 361 #define DF_CS_REMAP3A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 362 .drd_func = 7, .drd_reg = 0x1c8 } 363 /*CSTYLED*/ 364 #define DF_CS_REMAP3B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 365 .drd_func = 7, .drd_reg = 0x1cc } 366 /*CSTYLED*/ 367 #define DF_CS_REMAP3C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 368 .drd_func = 7, .drd_reg = 0x1d0 } 369 370 /* 371 * DF::CfgAddressCntl -- This register contains the information about the 372 * configuration of PCIe buses. We care about finding which one has our BUS A, 373 * which is required to map it to the in-package northbridge instance. 374 */ 375 /*CSTYLED*/ 376 #define DF_CFG_ADDR_CTL_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 377 .drd_func = 0, \ 378 .drd_reg = 0x84 } 379 /*CSTYLED*/ 380 #define DF_CFG_ADDR_CTL_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 381 .drd_func = 0, \ 382 .drd_reg = 0xc04 } 383 #define DF_CFG_ADDR_CTL_GET_BUS_NUM(r) bitx32(r, 7, 0) 384 385 /* 386 * DF::CfgAddressMap -- This next set of registers covers PCI Bus configuration 387 * address maps. The layout here changes at v4. This routes a given PCI bus to a 388 * device. 389 */ 390 /*CSTYLED*/ 391 #define DF_CFGMAP_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 392 .drd_func = 0, \ 393 .drd_reg = 0xa0 + ((x) * 4) } 394 #define DF_MAX_CFGMAP 8 395 #define DF_MAX_CFGMAP_TURIN 16 396 #define DF_CFGMAP_V2_GET_BUS_LIMIT(r) bitx32(r, 31, 24) 397 #define DF_CFGMAP_V2_GET_BUS_BASE(r) bitx32(r, 23, 16) 398 #define DF_CFGMAP_V2_GET_DEST_ID(r) bitx32(r, 11, 4) 399 #define DF_CFGMAP_V3_GET_DEST_ID(r) bitx32(r, 13, 4) 400 #define DF_CFGMAP_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4) 401 #define DF_CFGMAP_V2_GET_WE(r) bitx32(r, 1, 1) 402 #define DF_CFGMAP_V2_GET_RE(r) bitx32(r, 0, 0) 403 404 /* 405 * DF::CfgBaseAddress, DF::CfgLimitAddress -- DFv4 variants of the above now in 406 * two registers and more possible entries! 407 */ 408 /*CSTYLED*/ 409 #define DF_CFGMAP_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 410 .drd_func = 0, \ 411 .drd_reg = 0xc80 + ((x) * 8) } 412 /*CSTYLED*/ 413 #define DF_CFGMAP_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 414 .drd_func = 0, \ 415 .drd_reg = 0xc84 + ((x) * 8) } 416 #define DF_CFGMAP_BASE_V4_GET_BASE(r) bitx32(r, 23, 16) 417 #define DF_CFGMAP_BASE_V4_GET_SEG(r) bitx32(r, 15, 8) 418 #define DF_CFGMAP_BASE_V4_GET_WE(r) bitx32(r, 1, 1) 419 #define DF_CFGMAP_BASE_V4_GET_RE(r) bitx32(r, 0, 0) 420 #define DF_CFGMAP_LIMIT_V4_GET_LIMIT(r) bitx32(r, 23, 16) 421 #define DF_CFGMAP_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0) 422 423 /* 424 * DF::X86IOBaseAddress, DF::X86IOLimitAddress -- Base and limit registers for 425 * routing I/O space. These are fairly similar prior to DFv4. The number of 426 * these was increased in Turin. We expect this'll hold true for future server 427 * parts. 428 */ 429 /*CSTYLED*/ 430 #define DF_IO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 431 .drd_func = 0, \ 432 .drd_reg = 0xc0 + ((x) * 8) } 433 /*CSTYLED*/ 434 #define DF_IO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 435 .drd_func = 0, \ 436 .drd_reg = 0xd00 + ((x) * 8) } 437 #define DF_MAX_IO_RULES 8 438 #define DF_MAX_IO_RULES_TURIN 16 439 #define DF_IO_BASE_SHIFT 12 440 #define DF_IO_BASE_V2_GET_BASE(r) bitx32(r, 24, 12) 441 #define DF_IO_BASE_V2_GET_IE(r) bitx32(r, 5, 5) 442 #define DF_IO_BASE_V2_GET_WE(r) bitx32(r, 1, 1) 443 #define DF_IO_BASE_V2_GET_RE(r) bitx32(r, 0, 0) 444 #define DF_IO_BASE_V2_SET_BASE(r, v) bitset32(r, 24, 12, v) 445 #define DF_IO_BASE_V2_SET_IE(r, v) bitset32(r, 5, 5, v) 446 #define DF_IO_BASE_V2_SET_WE(r, v) bitset32(r, 1, 1, v) 447 #define DF_IO_BASE_V2_SET_RE(r, v) bitset32(r, 0, 0, v) 448 449 #define DF_IO_BASE_V4_GET_BASE(r) bitx32(r, 28, 16) 450 #define DF_IO_BASE_V4_GET_IE(r) bitx32(r, 5, 5) 451 #define DF_IO_BASE_V4_GET_WE(r) bitx32(r, 1, 1) 452 #define DF_IO_BASE_V4_GET_RE(r) bitx32(r, 0, 0) 453 #define DF_IO_BASE_V4_SET_BASE(r, v) bitset32(r, 28, 16, v) 454 #define DF_IO_BASE_V4_SET_IE(r, v) bitset32(r, 5, 5, v) 455 #define DF_IO_BASE_V4_SET_WE(r, v) bitset32(r, 1, 1, v) 456 #define DF_IO_BASE_V4_SET_RE(r, v) bitset32(r, 0, 0, v) 457 458 /*CSTYLED*/ 459 #define DF_IO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 460 .drd_func = 0, \ 461 .drd_reg = 0xc4 + ((x) * 8) } 462 /*CSTYLED*/ 463 #define DF_IO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 464 .drd_func = 0, \ 465 .drd_reg = 0xd04 + ((x) * 8) } 466 #define DF_MAX_IO_LIMIT ((1 << 24) - 1) 467 #define DF_IO_LIMIT_SHIFT 12 468 #define DF_IO_LIMIT_EXCL (1 << DF_IO_LIMIT_SHIFT) 469 #define DF_IO_LIMIT_V2_GET_LIMIT(r) bitx32(r, 24, 12) 470 #define DF_IO_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0) 471 #define DF_IO_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0) 472 #define DF_IO_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0) 473 #define DF_IO_LIMIT_V2_SET_LIMIT(r, v) bitset32(r, 24, 12, v) 474 #define DF_IO_LIMIT_V2_SET_DEST_ID(r, v) bitset32(r, 7, 0, v) 475 #define DF_IO_LIMIT_V3_SET_DEST_ID(r, v) bitset32(r, 9, 0, v) 476 #define DF_IO_LIMIT_V3P5_SET_DEST_ID(r, v) bitset32(r, 3, 0, v) 477 478 #define DF_IO_LIMIT_V4_GET_LIMIT(r) bitx32(r, 28, 16) 479 #define DF_IO_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0) 480 #define DF_IO_LIMIT_V4_SET_LIMIT(r, v) bitset32(r, 28, 16, v) 481 #define DF_IO_LIMIT_V4_SET_DEST_ID(r, v) bitset32(r, 11, 0, v) 482 483 /* 484 * DF::DramHoleControl -- This controls MMIO below 4 GiB. Note, both this and 485 * the Top of Memory (TOM) need to be set consistently. 486 */ 487 /*CSTYLED*/ 488 #define DF_DRAM_HOLE_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 489 .drd_func = 0, \ 490 .drd_reg = 0x104 } 491 /*CSTYLED*/ 492 #define DF_DRAM_HOLE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 493 .drd_func = 7, \ 494 .drd_reg = 0x104 } 495 #define DF_DRAM_HOLE_GET_BASE(r) bitx32(r, 31, 24) 496 #define DF_DRAM_HOLE_BASE_SHIFT 24 497 #define DF_DRAM_HOLE_GET_VALID(r) bitx32(r, 0, 0) 498 499 /* 500 * DF::DramBaseAddress, DF::DramLimitAddress -- DRAM rules, these are split into 501 * a base and limit. While DFv2, 3, and 3.5 all have the same addresses, they 502 * have different bit patterns entirely. DFv4 is in a different location and 503 * further splits this into four registers. We do all of the pre-DFv4 stuff and 504 * follow with DFv4. In DFv2-3.5 the actual values of the bits (e.g. the meaning 505 * of the channel interleave value) are the same, even though where those bits 506 * are in the register changes. 507 * 508 * In DF v2, v3, and v3.5 the set of constants for interleave values are the 509 * same, so we define them once at the v2 version. 510 */ 511 /*CSTYLED*/ 512 #define DF_DRAM_BASE_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 513 .drd_func = 0, \ 514 .drd_reg = 0x110 + ((r) * 8) } 515 #define DF_DRAM_BASE_V2_GET_BASE(r) bitx32(r, 31, 12) 516 #define DF_DRAM_BASE_V2_BASE_SHIFT 28 517 #define DF_DRAM_BASE_V2_GET_ILV_ADDR(r) bitx32(r, 10, 8) 518 #define DF_DRAM_BASE_V2_GET_ILV_CHAN(r) bitx32(r, 7, 4) 519 #define DF_DRAM_BASE_V2_ILV_CHAN_1 0x0 520 #define DF_DRAM_BASE_V2_ILV_CHAN_2 0x1 521 #define DF_DRAM_BASE_V2_ILV_CHAN_4 0x3 522 #define DF_DRAM_BASE_V2_ILV_CHAN_8 0x5 523 #define DF_DRAM_BASE_V2_ILV_CHAN_6 0x6 524 #define DF_DRAM_BASE_V2_ILV_CHAN_COD4_2 0xc 525 #define DF_DRAM_BASE_V2_ILV_CHAN_COD2_4 0xd 526 #define DF_DRAM_BASE_V2_ILV_CHAN_COD1_8 0xe 527 #define DF_DRAM_BASE_V2_GET_HOLE_EN(r) bitx32(r, 1, 1) 528 #define DF_DRAM_BASE_V2_GET_VALID(r) bitx32(r, 0, 0) 529 530 #define DF_DRAM_BASE_V3_GET_ILV_ADDR(r) bitx32(r, 11, 9) 531 #define DF_DRAM_BASE_V3_GET_ILV_SOCK(r) bitx32(r, 8, 8) 532 #define DF_DRAM_BASE_V3_GET_ILV_DIE(r) bitx32(r, 7, 6) 533 #define DF_DRAM_BASE_V3_GET_ILV_CHAN(r) bitx32(r, 5, 2) 534 535 #define DF_DRAM_BASE_V3P5_GET_ILV_ADDR(r) bitx32(r, 11, 9) 536 #define DF_DRAM_BASE_V3P5_GET_ILV_SOCK(r) bitx32(r, 8, 8) 537 #define DF_DRAM_BASE_V3P5_GET_ILV_DIE(r) bitx32(r, 7, 7) 538 #define DF_DRAM_BASE_V3P5_GET_ILV_CHAN(r) bitx32(r, 6, 2) 539 540 /* 541 * Shared definitions for the DF DRAM interleaving address start bits. While the 542 * bitfield / register definition is different between DFv2/3/3.5 and DFv4, the 543 * actual contents of the base address register and the base are shared. 544 */ 545 #define DF_DRAM_ILV_ADDR_8 0 546 #define DF_DRAM_ILV_ADDR_9 1 547 #define DF_DRAM_ILV_ADDR_10 2 548 #define DF_DRAM_ILV_ADDR_11 3 549 #define DF_DRAM_ILV_ADDR_12 4 550 #define DF_DRAM_ILV_ADDR_BASE 8 551 552 /*CSTYLED*/ 553 #define DF_DRAM_LIMIT_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 554 .drd_func = 0, \ 555 .drd_reg = 0x114 + ((r) * 8) } 556 #define DF_DRAM_LIMIT_V2_GET_LIMIT(r) bitx32(r, 31, 12) 557 #define DF_DRAM_LIMIT_V2_LIMIT_SHIFT 28 558 #define DF_DRAM_LIMIT_V2_LIMIT_EXCL (1 << 28) 559 /* These are in the base register for v3, v3.5 */ 560 #define DF_DRAM_LIMIT_V2_GET_ILV_DIE(r) bitx32(r, 11, 10) 561 #define DF_DRAM_LIMIT_V2_GET_ILV_SOCK(r) bitx32(r, 8, 8) 562 #define DF_DRAM_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0) 563 564 #define DF_DRAM_LIMIT_V3_GET_BUS_BREAK(r) bitx32(r, 10, 10) 565 #define DF_DRAM_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0) 566 567 #define DF_DRAM_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0) 568 569 /* 570 * DF::DramBaseAddress, DF::DramLimitAddress, DF::DramAddressCtl, 571 * DF::DramAddressIntlv -- DFv4 edition. Here all the controls around the 572 * target, interleaving, hashing, and more is split out from the base and limit 573 * registers and put into dedicated control and interleave registers. 574 * 575 * In the 4D2 variant, the base and limit are the same, just at different 576 * addresses. The control register is subtly different with additional 577 * interleave options. 578 */ 579 /*CSTYLED*/ 580 #define DF_DRAM_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 581 .drd_func = 7, \ 582 .drd_reg = 0xe00 + ((x) * 0x10) } 583 /*CSTYLED*/ 584 #define DF_DRAM_BASE_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 585 .drd_func = 7, \ 586 .drd_reg = 0x200 + ((x) * 0x10) } 587 #define DF_DRAM_BASE_V4_GET_ADDR(r) bitx32(r, 27, 0) 588 #define DF_DRAM_BASE_V4_BASE_SHIFT 28 589 /*CSTYLED*/ 590 #define DF_DRAM_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 591 .drd_func = 7, \ 592 .drd_reg = 0xe04 + ((x) * 0x10) } 593 /*CSTYLED*/ 594 #define DF_DRAM_LIMIT_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 595 .drd_func = 7, \ 596 .drd_reg = 0x204 + ((x) * 0x10) } 597 #define DF_DRAM_LIMIT_V4_GET_ADDR(r) bitx32(r, 27, 0) 598 #define DF_DRAM_LIMIT_V4_LIMIT_SHIFT 28 599 #define DF_DRAM_LIMIT_V4_LIMIT_EXCL (1 << 28) 600 601 /*CSTYLED*/ 602 #define DF_DRAM_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 603 .drd_func = 7, \ 604 .drd_reg = 0xe08 + ((x) * 0x10) } 605 /*CSTYLED*/ 606 #define DF_DRAM_CTL_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 607 .drd_func = 7, \ 608 .drd_reg = 0208 + ((x) * 0x10) } 609 #define DF_DRAM_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16) 610 #define DF_DRAM_CTL_V4D2_GET_HASH_1T(r) bitx32(r, 15, 15) 611 /* 612 * It seems that this was added in DF V4.1 (no relation to 4D2). It was reserved 613 * prior to this, so we leave it without a version suffix for now. 614 */ 615 #define DF_DRAM_CTL_V4_GET_COL_SWIZ(r) bitx32(r, 11, 11) 616 #define DF_DRAM_CTL_V4_GET_HASH_1G(r) bitx32(r, 10, 10) 617 #define DF_DRAM_CTL_V4_GET_HASH_2M(r) bitx32(r, 9, 9) 618 #define DF_DRAM_CTL_V4_GET_HASH_64K(r) bitx32(r, 8, 8) 619 #define DF_DRAM_CTL_V4D2_GET_HASH_4K(r) bitx32(r, 7, 7) 620 #define DF_DRAM_CTL_V4_GET_REMAP_SEL(r) bitx32(r, 7, 5) 621 #define DF_DRAM_CTL_V4D2_GET_REMAP_SEL(r) bitx32(r, 6, 5) 622 #define DF_DRAM_CTL_V4_GET_REMAP_EN(r) bitx32(r, 4, 4) 623 #define DF_DRAM_CTL_V4_GET_SCM(r) bitx32(r, 2, 2) 624 #define DF_DRAM_CTL_V4_GET_HOLE_EN(r) bitx32(r, 1, 1) 625 #define DF_DRAM_CTL_V4_GET_VALID(r) bitx32(r, 0, 0) 626 627 /*CSTYLED*/ 628 #define DF_DRAM_ILV_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \ 629 .drd_func = 7, \ 630 .drd_reg = 0xe0c + ((x) * 0x10) } 631 /*CSTYLED*/ 632 #define DF_DRAM_ILV_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \ 633 .drd_func = 7, \ 634 .drd_reg = 0x20c + ((x) * 0x10) } 635 #define DF_DRAM_ILV_V4_GET_SOCK(r) bitx32(r, 18, 18) 636 #define DF_DRAM_ILV_V4_GET_DIE(r) bitx32(r, 13, 12) 637 /* 638 * We're cheating a bit here. We combine the various different non-overlapping 639 * values in the 4D2 variants. In particular, most client parts stick to the 640 * first few values while the rest are sometimes used in the moniker "DF 4.5". 641 */ 642 #define DF_DRAM_ILV_V4D2_GET_CHAN(r) bitx32(r, 9, 4) 643 #define DF_DRAM_ILV_V4D2_CHAN_1 0x0 644 #define DF_DRAM_ILV_V4D2_CHAN_2 0x1 645 #define DF_DRAM_ILV_V4D2_CHAN_4 0x3 646 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_16S8CH_1K 0xc 647 #define DF_DRAM_ILV_V4D2_CHAN_NPS0_24CH_1K 0xe 648 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_2CH_1K 0x10 649 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_4CH_1K 0x11 650 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_8S4CH_1K 0x12 651 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_3CH_1K 0x13 652 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_6CH_1K 0x14 653 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_12CH_1K 0x15 654 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_5CH_1K 0x16 655 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_10CH_1K 0x17 656 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_2CH_2K 0x20 657 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_4CH_2K 0x21 658 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_8S4CH_2K 0x22 659 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_16S8CH_2K 0x23 660 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_3CH_2K 0x24 661 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_6CH_2K 0x25 662 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_12CH_2K 0x26 663 #define DF_DRAM_ILV_V4D2_CHAN_NPS0_24CH_2K 0x27 664 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_5CH_2K 0x28 665 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_10CH_2K 0x29 666 #define DF_DRAM_ILV_V4_GET_CHAN(r) bitx32(r, 8, 4) 667 #define DF_DRAM_ILV_V4_CHAN_1 0x0 668 #define DF_DRAM_ILV_V4_CHAN_2 0x1 669 #define DF_DRAM_ILV_V4_CHAN_4 0x3 670 #define DF_DRAM_ILV_V4_CHAN_8 0x5 671 #define DF_DRAM_ILV_V4_CHAN_16 0x7 672 #define DF_DRAM_ILV_V4_CHAN_32 0x8 673 #define DF_DRAM_ILV_V4_CHAN_NPS4_2CH 0x10 674 #define DF_DRAM_ILV_V4_CHAN_NPS2_4CH 0x11 675 #define DF_DRAM_ILV_V4_CHAN_NPS1_8CH 0x12 676 #define DF_DRAM_ILV_V4_CHAN_NPS4_3CH 0x13 677 #define DF_DRAM_ILV_V4_CHAN_NPS2_6CH 0x14 678 #define DF_DRAM_ILV_V4_CHAN_NPS1_12CH 0x15 679 #define DF_DRAM_ILV_V4_CHAN_NPS2_5CH 0x16 680 #define DF_DRAM_ILV_V4_CHAN_NPS1_10CH 0x17 681 #define DF_DRAM_ILV_V4_GET_ADDR(r) bitx32(r, 2, 0) 682 683 /* 684 * DF::DramOffset -- These exist only for CS entries, e.g. a UMC. There is 685 * generally only one of these in Zen 1-3. This register changes in Zen 4 and 686 * there are up to 3 instances there. This register corresponds to each DRAM 687 * rule that the UMC has starting at the second one. This is because the first 688 * DRAM rule in a channel always is defined to start at offset 0, so there is no 689 * entry here. 690 */ 691 /*CSTYLED*/ 692 #define DF_DRAM_OFFSET_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 693 .drd_func = 0, \ 694 .drd_reg = 0x1b4 } 695 /*CSTYLED*/ 696 #define DF_DRAM_OFFSET_V4(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 697 .drd_func = 7, \ 698 .drd_reg = 0x140 + ((r) * 4) } 699 #define DF_DRAM_OFFSET_V2_GET_OFFSET(r) bitx32(r, 31, 20) 700 #define DF_DRAM_OFFSET_V3_GET_OFFSET(r) bitx32(r, 31, 12) 701 #define DF_DRAM_OFFSET_V4_GET_OFFSET(r) bitx32(r, 24, 1) 702 #define DF_DRAM_OFFSET_SHIFT 28 703 #define DF_DRAM_OFFSET_GET_EN(r) bitx32(r, 0, 0) 704 705 /* 706 * DF::VGAEn -- This controls whether or not the historical x86 VGA 707 * compatibility region is enabled or not. 708 */ 709 /*CSTYLED*/ 710 #define DF_VGA_EN_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 711 .drd_func = 0, \ 712 .drd_reg = 0x80 } 713 /*CSTYLED*/ 714 #define DF_VGA_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 715 .drd_func = 0, \ 716 .drd_reg = 0xc08 } 717 718 #define DF_VGA_EN_GET_FABID(r) bitx32(r, 15, 4) 719 #define DF_VGA_EN_GET_CPUDIS(r) bitx32(r, 2, 2) 720 #define DF_VGA_EN_GET_NP(r) bitx32(r, 1, 1) 721 #define DF_VGA_EN_GET_EN(r) bitx32(r, 0, 0) 722 723 /* 724 * DF::MmioPciCfgBaseAddr, DF::MmioPciCfgBaseAddrExt, DF::MmioPciCfgLimitAddr, 725 * DF::MmioPciCfgLimitAddrExt -- These are DFv4 additions that control where PCI 726 * extended configuration space is and whether or not the DF honors this. This 727 * must match the values programmed into the CPU. Prior to DFv4, there was not a 728 * DF setting for this. The encoded values of the base and limit are the same. 729 */ 730 /*CSTYLED*/ 731 #define DF_ECAM_BASE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 732 .drd_func = 0, \ 733 .drd_reg = 0xc10 } 734 /*CSTYLED*/ 735 #define DF_ECAM_BASE_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 736 .drd_func = 0, \ 737 .drd_reg = 0xc14 } 738 /*CSTYLED*/ 739 #define DF_ECAM_LIMIT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 740 .drd_func = 0, \ 741 .drd_reg = 0xc18 } 742 /*CSTYLED*/ 743 #define DF_ECAM_LIMIT_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 744 .drd_func = 0, \ 745 .drd_reg = 0xc1c } 746 #define DF_ECAM_V4_GET_ADDR(r) bitx32(r, 31, 20) 747 #define DF_ECAM_V4_ADDR_SHIFT 20 748 #define DF_ECAM_LIMIT_EXCL (1 << DF_ECAM_V4_ADDR_SHIFT) 749 #define DF_ECAM_BASE_V4_GET_EN(r) bitx32(r, 0, 0) 750 #define DF_ECAM_EXT_V4_GET_ADDR(r) bitx32(r, 23, 0) 751 #define DF_ECAM_EXT_V4_ADDR_SHIFT 32 752 753 /* 754 * DF::MmioBaseAddress, DF::MmioLimitAddress, DF::MmioAddressControl -- These 755 * control the various MMIO rules for a given system. 756 */ 757 /*CSTYLED*/ 758 #define DF_MMIO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 759 .drd_func = 0, \ 760 .drd_reg = 0x200 + ((x) * 0x10) } 761 /*CSTYLED*/ 762 #define DF_MMIO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 763 .drd_func = 0, \ 764 .drd_reg = 0x204 + ((x) * 0x10) } 765 /*CSTYLED*/ 766 #define DF_MMIO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 767 .drd_func = 0, \ 768 .drd_reg = 0xd80 + ((x) * 0x10) } 769 /*CSTYLED*/ 770 #define DF_MMIO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 771 .drd_func = 0, \ 772 .drd_reg = 0xd84 + ((x) * 0x10) } 773 #define DF_MMIO_SHIFT 16 774 #define DF_MMIO_LIMIT_EXCL (1 << DF_MMIO_SHIFT) 775 #define DF_MAX_MMIO_RULES 16 776 #define DF_MAX_MMIO_RULES_TURIN 32 777 /*CSTYLED*/ 778 #define DF_MMIO_CTL_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 779 .drd_func = 0, \ 780 .drd_reg = 0x208 + ((x) * 0x10) } 781 /*CSTYLED*/ 782 #define DF_MMIO_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 783 .drd_func = 0, \ 784 .drd_reg = 0xd88 + ((x) * 0x10) } 785 #define DF_MMIO_CTL_V2_GET_NP(r) bitx32(r, 12, 12) 786 #define DF_MMIO_CTL_V2_GET_DEST_ID(r) bitx32(r, 11, 4) 787 #define DF_MMIO_CTL_V2_SET_NP(r, v) bitset32(r, 12, 12, v) 788 #define DF_MMIO_CTL_V2_SET_DEST_ID(r, v) bitset32(r, 11, 4, v) 789 790 #define DF_MMIO_CTL_V3_GET_NP(r) bitx32(r, 16, 16) 791 #define DF_MMIO_CTL_V3_GET_DEST_ID(r) bitx32(r, 13, 4) 792 #define DF_MMIO_CTL_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4) 793 #define DF_MMIO_CTL_V3_SET_NP(r, v) bitset32(r, 16, 16, v) 794 #define DF_MMIO_CTL_V3_SET_DEST_ID(r, v) bitset32(r, 13, 4, v) 795 #define DF_MMIO_CTL_V3P5_SET_DEST_ID(r, v) bitset32(r, 7, 4, v) 796 797 #define DF_MMIO_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16) 798 #define DF_MMIO_CTL_V4_GET_NP(r) bitx32(r, 3, 3) 799 #define DF_MMIO_CTL_V4_SET_DEST_ID(r, v) bitset32(r, 27, 16, v) 800 #define DF_MMIO_CTL_V4_SET_NP(r, v) bitset32(r, 3, 3, v) 801 802 #define DF_MMIO_CTL_GET_CPU_DIS(r) bitx32(r, 2, 2) 803 #define DF_MMIO_CTL_GET_WE(r) bitx32(r, 1, 1) 804 #define DF_MMIO_CTL_GET_RE(r) bitx32(r, 0, 0) 805 #define DF_MMIO_CTL_SET_CPU_DIS(r, v) bitset32(r, 2, 2, v) 806 #define DF_MMIO_CTL_SET_WE(r, v) bitset32(r, 1, 1, v) 807 #define DF_MMIO_CTL_SET_RE(r, v) bitset32(r, 0, 0, v) 808 809 /* 810 * DF::MmioExtAddress -- New in DFv4, this allows extending the number of bits 811 * used for MMIO. 812 */ 813 /*CSTYLED*/ 814 #define DF_MMIO_EXT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 815 .drd_func = 0, \ 816 .drd_reg = 0xd8c + ((x) * 0x10) } 817 #define DF_MMIO_EXT_V4_GET_LIMIT(r) bitx32(r, 23, 16) 818 #define DF_MMIO_EXT_V4_GET_BASE(r) bitx32(r, 7, 0) 819 #define DF_MMIO_EXT_V4_SET_LIMIT(r) bitset32(r, 23, 16) 820 #define DF_MMIO_EXT_V4_SET_BASE(r) bitset32(r, 7, 0) 821 822 /* 823 * DF::DfGlobalCtrl -- This register we generally only care about in the 824 * DFv3/3.5 timeframe when it has the actual hash controls, hence its current 825 * definition. It technically exists in DFv2/v4, but is not relevant. 826 */ 827 /*CSTYLED*/ 828 #define DF_GLOB_CTL_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \ 829 .drd_func = 0, \ 830 .drd_reg = 0x3F8 } 831 #define DF_GLOB_CTL_V3_GET_HASH_1G(r) bitx32(r, 22, 22) 832 #define DF_GLOB_CTL_V3_GET_HASH_2M(r) bitx32(r, 21, 21) 833 #define DF_GLOB_CTL_V3_GET_HASH_64K(r) bitx32(r, 20, 20) 834 835 /* 836 * DF::SystemCfg -- This register describes the basic information about the data 837 * fabric that we're talking to. Don't worry, this is different in every 838 * generation, even when the address is the same. Somehow despite all these 839 * differences the actual things like defined types are somehow the same. 840 */ 841 typedef enum { 842 DF_DIE_TYPE_CPU = 0, 843 DF_DIE_TYPE_APU, 844 DF_DIE_TYPE_dGPU 845 } df_die_type_t; 846 847 /*CSTYLED*/ 848 #define DF_SYSCFG_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 849 .drd_func = 1, \ 850 .drd_reg = 0x200 } 851 #define DF_SYSCFG_V2_GET_SOCK_ID(r) bitx32(r, 27, 27) 852 #define DF_SYSCFG_V2_GET_DIE_ID(r) bitx32(r, 25, 24) 853 #define DF_SYSCFG_V2_GET_MY_TYPE(r) bitx32(r, 22, 21) 854 #define DF_SYSCFG_V2_GET_LOCAL_IS_ME(r) bitx32(r, 19, 16) 855 #define DF_SYSCFG_V2_GET_LOCAL_TYPE3(r) bitx32(r, 13, 12) 856 #define DF_SYSCFG_V2_GET_LOCAL_TYPE2(r) bitx32(r, 11, 10) 857 #define DF_SYSCFG_V2_GET_LOCAL_TYPE1(r) bitx32(r, 9, 8) 858 #define DF_SYSCFG_V2_GET_LOCAL_TYPE0(r) bitx32(r, 7, 6) 859 #define DF_SYSCFG_V2_GET_OTHER_SOCK(r) bitx32(r, 5, 5) 860 #define DF_SYSCFG_V2_GET_DIE_PRESENT(r) bitx32(r, 4, 0) 861 #define DF_SYSCFG_V2_DIE_PRESENT(x) bitx32(r, 3, 0) 862 863 /*CSTYLED*/ 864 #define DF_SYSCFG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 865 .drd_func = 1, \ 866 .drd_reg = 0x200 } 867 #define DF_SYSCFG_V3_GET_NODE_ID(r) bitx32(r, 30, 28) 868 #define DF_SYSCFG_V3_GET_OTHER_SOCK(r) bitx32(r, 27, 27) 869 #define DF_SYSCFG_V3_GET_OTHER_TYPE(r) bitx32(r, 26, 25) 870 #define DF_SYSCFG_V3_GET_MY_TYPE(r) bitx32(r, 24, 23) 871 #define DF_SYSCFG_V3_GET_DIE_TYPE(r) bitx32(r, 18, 11) 872 #define DF_SYSCFG_V3_GET_DIE_PRESENT(r) bitx32(r, 7, 0) 873 874 /*CSTYLED*/ 875 #define DF_SYSCFG_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 876 .drd_func = 1, \ 877 .drd_reg = 0x140 } 878 #define DF_SYSCFG_V3P5_GET_NODE_ID(r) bitx32(r, 19, 16) 879 #define DF_SYSCFG_V3P5_GET_OTHER_SOCK(r) bitx32(r, 8, 8) 880 #define DF_SYSCFG_V3P5_GET_NODE_MAP(r) bitx32(r, 4, 4) 881 #define DF_SYSCFG_V3P5_GET_OTHER_TYPE(r) bitx32(r, 3, 2) 882 #define DF_SYSCFG_V3P5_GET_MY_TYPE(r) bitx32(r, 1, 0) 883 884 /*CSTYLED*/ 885 #define DF_SYSCFG_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 886 .drd_func = 4, \ 887 .drd_reg = 0x180 } 888 #define DF_SYSCFG_V4_GET_NODE_ID(r) bitx32(r, 27, 16) 889 #define DF_SYSCFG_V4_GET_OTHER_SOCK(r) bitx32(r, 8, 8) 890 #define DF_SYSCFG_V4_GET_NODE_MAP(r) bitx32(r, 4, 4) 891 #define DF_SYSCFG_V4_GET_OTHER_TYPE(r) bitx32(r, 3, 2) 892 #define DF_SYSCFG_V4_GET_MY_TYPE(r) bitx32(r, 1, 0) 893 894 /* 895 * DF::SystemComponentCnt -- Has a count of how many things are here. However, 896 * this does not seem defined for DFv3.5 897 */ 898 /*CSTYLED*/ 899 #define DF_COMPCNT_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 900 .drd_func = 1, \ 901 .drd_reg = 0x204 } 902 #define DF_COMPCNT_V2_GET_IOMS(r) bitx32(r, 23, 16) 903 #define DF_COMPCNT_V2_GET_GCM(r) bitx32(r, 15, 8) 904 #define DF_COMPCNT_V2_GET_PIE(r) bitx32(r, 7, 0) 905 906 /*CSTYLED*/ 907 #define DF_COMPCNT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 908 .drd_func = 4, \ 909 .drd_reg = 0x184 } 910 #define DF_COMPCNT_V4_GET_IOS(r) bitx32(r, 31, 26) 911 #define DF_COMPCNT_V4_GET_GCM(r) bitx32(r, 25, 16) 912 #define DF_COMPCNT_V4_GET_IOM(r) bitx32(r, 15, 8) 913 #define DF_COMPCNT_V4_GET_PIE(r) bitx32(r, 7, 0) 914 915 /* 916 * This next section contains a bunch of register definitions for how to take 917 * apart ID masks. The register names and sets have changed across every DF 918 * revision. This will be done in chunks that define all DFv2, then v3, etc. 919 */ 920 921 /* 922 * DF::SystemFabricIdMask -- DFv2 style breakdowns of IDs. Note, unlike others 923 * the socket and die shifts are not relative to a node mask, but are global. 924 */ 925 /*CSTYLED*/ 926 #define DF_FIDMASK_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 927 .drd_func = 1, \ 928 .drd_reg = 0x208 } 929 #define DF_FIDMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28) 930 #define DF_FIDMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24) 931 #define DF_FIDMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16) 932 #define DF_FIDMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8) 933 934 /* 935 * DF::SystemFabricIdMask0, DF::SystemFabricIdMask1 -- The DFv3 variant of 936 * breaking down an ID into bits and shifts. Unlike in DFv2, the socket and die 937 * are relative to a node ID. For more, see amdzen_determine_fabric_decomp() in 938 * uts/intel/io/amdzen/amdzen.c. 939 */ 940 /*CSTYLED*/ 941 #define DF_FIDMASK0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 942 .drd_func = 1, \ 943 .drd_reg = 0x208 } 944 #define DF_FIDMASK0_V3_GET_NODE_MASK(r) bitx32(r, 25, 16) 945 #define DF_FIDMASK0_V3_GET_COMP_MASK(r) bitx32(r, 9, 0) 946 /*CSTYLED*/ 947 #define DF_FIDMASK1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 948 .drd_func = 1, \ 949 .drd_reg = 0x20c } 950 #define DF_FIDMASK1_V3_GET_SOCK_MASK(r) bitx32(r, 26, 24) 951 #define DF_FIDMASK1_V3_GET_DIE_MASK(r) bitx32(r, 18, 16) 952 #define DF_FIDMASK1_V3_GET_SOCK_SHIFT(r) bitx32(r, 9, 8) 953 #define DF_FIDMASK1_V3_GET_NODE_SHIFT(r) bitx32(r, 3, 0) 954 955 /* 956 * DF::SystemFabricIdMask0, DF::SystemFabricIdMask1, DF::SystemFabricIdMask2 -- 957 * DFv3.5 and DFv4 have the same format here, but in different registers. 958 */ 959 /*CSTYLED*/ 960 #define DF_FIDMASK0_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 961 .drd_func = 1, \ 962 .drd_reg = 0x150 } 963 /*CSTYLED*/ 964 #define DF_FIDMASK0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 965 .drd_func = 4, \ 966 .drd_reg = 0x1b0 } 967 #define DF_FIDMASK0_V3P5_GET_NODE_MASK(r) bitx32(r, 31, 16) 968 #define DF_FIDMASK0_V3P5_GET_COMP_MASK(r) bitx32(r, 15, 0) 969 /*CSTYLED*/ 970 #define DF_FIDMASK1_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 971 .drd_func = 1, \ 972 .drd_reg = 0x154 } 973 /*CSTYLED*/ 974 #define DF_FIDMASK1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 975 .drd_func = 4, \ 976 .drd_reg = 0x1b4 } 977 #define DF_FIDMASK1_V3P5_GET_SOCK_SHIFT(r) bitx32(r, 11, 8) 978 #define DF_FIDMASK1_V3P5_GET_NODE_SHIFT(r) bitx32(r, 3, 0) 979 /*CSTYLED*/ 980 #define DF_FIDMASK2_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \ 981 .drd_func = 1, \ 982 .drd_reg = 0x158 } 983 /*CSTYLED*/ 984 #define DF_FIDMASK2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 985 .drd_func = 4, \ 986 .drd_reg = 0x1b8 } 987 #define DF_FIDMASK2_V3P5_GET_SOCK_MASK(r) bitx32(r, 31, 16) 988 #define DF_FIDMASK2_V3P5_GET_DIE_MASK(r) bitx32(r, 15, 0) 989 990 /* 991 * DF::DieFabricIdMask -- This is a Zeppelin, DFv2 special. There are a couple 992 * instances of this for different types of devices; however, this is where the 993 * component mask is actually stored. This is replicated for a CPU, APU, and 994 * dGPU, each with slightly different values. We need to look at DF_SYSCFG_V2 to 995 * determine which type of die we have and use the appropriate one when looking 996 * at this. This makes the Zen 1 CPUs and APUs have explicitly different set up 997 * here. Look, it got better in DFv3. 998 */ 999 /*CSTYLED*/ 1000 #define DF_DIEMASK_CPU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 1001 .drd_func = 1, \ 1002 .drd_reg = 0x22c } 1003 /*CSTYLED*/ 1004 #define DF_DIEMASK_APU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \ 1005 .drd_func = 1, \ 1006 .drd_reg = 0x24c } 1007 #define DF_DIEMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28) 1008 #define DF_DIEMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24) 1009 #define DF_DIEMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16) 1010 #define DF_DIEMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8) 1011 #define DF_DIEMASK_V2_GET_COMP_MASK(r) bitx32(r, 7, 0) 1012 1013 /* 1014 * DF::CCDEnable -- This register is present for CCMs and ACMs. Despite its 1015 * name, the interpretation is not quite straightforward. That is, it only 1016 * indirectly tells us about whether or not there are two CCDs or not. A CCM 1017 * port can be in wide mode where its two SDPs (Scalable Data Ports) are in fact 1018 * instead connected to a single CCD. If wide mode is enabled in DF::CCMConfig4, 1019 * then a value of 0x3 just indicates that both SDP ports are connected to a 1020 * single CCD. 1021 * 1022 * The CCX related fields are only valid when the dense mode is enabled in the 1023 * global DF controls. If a CPU doesn't support that, then that field is 1024 * reserved. We don't generally recommend this as a way of determining if 1025 * multiple CCX units are present on the CCD because it is tied to DFv4. 1026 */ 1027 #define DF_MAX_CCDS_PER_CCM 2 1028 /*CSTYLED*/ 1029 #define DF_CCD_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1030 .drd_func = 1, \ 1031 .drd_reg = 0x104 } 1032 #define DF_CCD_EN_V4_GET_CCX_EN(r) bitx32(r, 17, 16) 1033 #define DF_CCD_EN_V4_GET_CCD_EN(r) bitx32(r, 1, 0) 1034 1035 1036 /* 1037 * DF::PhysicalCoreEnable0, etc. -- These registers can be used to tell us which 1038 * cores are actually enabled. This appears to have been introduced in DFv3. 1039 * DFv4 expanded this from two registers to several more. The number that are 1040 * valid vary based upon the CPU family. 1041 */ 1042 /*CSTYLED*/ 1043 #define DF_PHYS_CORE_EN0_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \ 1044 .drd_func = 1, \ 1045 .drd_reg = 0x300 } 1046 /*CSTYLED*/ 1047 #define DF_PHYS_CORE_EN1_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \ 1048 .drd_func = 1, \ 1049 .drd_reg = 0x304 } 1050 /*CSTYLED*/ 1051 #define DF_PHYS_CORE_EN0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1052 .drd_func = 1, \ 1053 .drd_reg = 0x140 } 1054 /*CSTYLED*/ 1055 #define DF_PHYS_CORE_EN1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1056 .drd_func = 1, \ 1057 .drd_reg = 0x144 } 1058 /*CSTYLED*/ 1059 #define DF_PHYS_CORE_EN2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1060 .drd_func = 1, \ 1061 .drd_reg = 0x148 } 1062 /*CSTYLED*/ 1063 #define DF_PHYS_CORE_EN3_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1064 .drd_func = 1, \ 1065 .drd_reg = 0x14c } 1066 /*CSTYLED*/ 1067 #define DF_PHYS_CORE_EN4_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1068 .drd_func = 1, \ 1069 .drd_reg = 0x150 } 1070 /*CSTYLED*/ 1071 #define DF_PHYS_CORE_EN5_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1072 .drd_func = 1, \ 1073 .drd_reg = 0x154 } 1074 1075 /* 1076 * DF::Np2ChannelConfig -- This is used in Milan to contain information about 1077 * how non-power of 2 based channel configuration works. Note, we only know that 1078 * this exists in Milan (and its ThreadRipper equivalent). We don't believe it 1079 * is in other DFv3 products like Rome, Matisse, Vermeer, or the APUs. 1080 */ 1081 /*CSTYLED*/ 1082 #define DF_NP2_CONFIG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \ 1083 .drd_func = 2, \ 1084 .drd_reg = 0x90 } 1085 #define DF_NP2_CONFIG_V3_GET_SPACE1(r) bitx32(r, 13, 8) 1086 #define DF_NP2_CONFIG_V3_GET_SPACE0(r) bitx32(r, 5, 0) 1087 1088 /* 1089 * DF::CCMConfig4 -- This is one of several CCM configuration related registers. 1090 * This varies in each DF revision. That is, while we've found it does exist in 1091 * DFv3, it is at a different address and the bits have rather different 1092 * meanings. A subset of the bits are defined below based upon our needs. 1093 */ 1094 /*CSTYLED*/ 1095 #define DF_CCMCFG4_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1096 .drd_func = 3, \ 1097 .drd_reg = 0x510 } 1098 #define DF_CCMCFG4_V4_GET_WIDE_EN(r) bitx32(r, 26, 26) 1099 1100 /* 1101 * DF::FabricIndirectConfigAccessAddress, DF::FabricIndirectConfigAccessDataLo, 1102 * DF::FabricIndirectConfigAccessDataHi -- These registers are used to define 1103 * Indirect Access, commonly known as FICAA and FICAD for the system. While 1104 * there are multiple copies of the indirect access registers in device 4, we're 1105 * only allowed access to one set of those (which are the ones present here). 1106 * Specifically the OS is given access to set 3. 1107 */ 1108 /*CSTYLED*/ 1109 #define DF_FICAA_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 1110 .drd_func = 4, \ 1111 .drd_reg = 0x5c } 1112 /*CSTYLED*/ 1113 #define DF_FICAA_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1114 .drd_func = 4, \ 1115 .drd_reg = 0x8c } 1116 #define DF_FICAA_V2_SET_INST(r, v) bitset32(r, 23, 16, v) 1117 #define DF_FICAA_V2_SET_64B(r, v) bitset32(r, 14, 14, v) 1118 #define DF_FICAA_V2_SET_FUNC(r, v) bitset32(r, 13, 11, v) 1119 #define DF_FICAA_V2_SET_REG(r, v) bitset32(r, 10, 2, v) 1120 #define DF_FICAA_V2_SET_TARG_INST(r, v) bitset32(r, 0, 0, v) 1121 1122 #define DF_FICAA_V4_SET_REG(r, v) bitset32(r, 10, 1, v) 1123 1124 /*CSTYLED*/ 1125 #define DF_FICAD_LO_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 1126 .drd_func = 4, \ 1127 .drd_reg = 0x98} 1128 /*CSTYLED*/ 1129 #define DF_FICAD_HI_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \ 1130 .drd_func = 4, \ 1131 .drd_reg = 0x9c} 1132 /*CSTYLED*/ 1133 #define DF_FICAD_LO_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1134 .drd_func = 4, \ 1135 .drd_reg = 0xb8} 1136 /*CSTYLED*/ 1137 #define DF_FICAD_HI_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \ 1138 .drd_func = 4, \ 1139 .drd_reg = 0xbc} 1140 1141 #ifdef __cplusplus 1142 } 1143 #endif 1144 1145 #endif /* _SYS_AMDZEN_DF_H */ 1146