xref: /illumos-gate/usr/src/uts/common/sys/termiox.h (revision b4203d75)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*	Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T	*/
23 /*	  All Rights Reserved	*/
24 
25 
26 #ifndef	_SYS_TERMIOX_H
27 #define	_SYS_TERMIOX_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 /* This structure provides an extended terminal interface. */
34 /* Features of this interface are optional and may not be */
35 /* implemented on all machines. */
36 
37 
38 #define	NFF	5
39 
40 /* hardware flow control modes */
41 
42 #define	RTSXOFF	0000001	/* Enable RTS hardware flow control on input */
43 #define	CTSXON	0000002	/* Enable CTS hardware flow control on output */
44 #define	DTRXOFF	0000004	/* Enable DTR hardware flow control on input */
45 #define	CDXON	0000010	/* Enable CD hardware flow control on output */
46 #define	ISXOFF	0000020	/* Enable isochronous hardware flow control on input */
47 
48 /* clock modes */
49 
50 #define	XMTCLK		0000007	/* Transmit Clock Source: */
51 #define	XCIBRG		0000000	/* Get transmit clock from */
52 				/*	internal baud rate generator */
53 #define	XCTSET		0000001	/* Get transmit clock from */
54 				/*	transmitter signal element */
55 				/*	timing (DCE source) lead, */
56 				/*	CCITT V.24 circuit 114, */
57 				/*	EIA-232-D pin 15 */
58 #define	XCRSET		0000002	/* Get transmit clock from */
59 				/*	receiver signal element */
60 				/*	timing (DCE source) lead, */
61 				/*	CCITT V.24 circuit 115, */
62 				/*	EIA-232-D pin 17 */
63 
64 #define	RCVCLK		0000070	/* Receive Clock Source: */
65 #define	RCIBRG		0000000	/* get receive clock from internal */
66 				/*	baud rate generator */
67 #define	RCTSET		0000010	/* Get receive clock from */
68 				/*	transmitter signal element */
69 				/*	timing (DCE source) lead, */
70 				/*	CCITT V.24 circuit 114, */
71 				/*	EIA-232-D pin 15 */
72 #define	RCRSET		0000020	/* Get receive clock from */
73 				/*	receiver signal element */
74 				/*	timing (DCE source) lead, */
75 				/*	CCITT V.24 circuit 115, */
76 				/*	EIA-232-D pin 17 */
77 
78 #define	TSETCLK		0000700	/* Transmitter Signal Element */
79 				/*	timing (DTE source) lead, */
80 				/*	CCITT V.24 circuit 113, */
81 				/*	EIA-232-D pin 24, clock source: */
82 #define	TSETCOFF	0000000	/* TSET clock not provided */
83 #define	TSETCRBRG	0000100	/* Output receive baud rate generator */
84 				/*	on circuit 113 */
85 #define	TSETCTBRG	0000200	/* Output transmit baud rate generator */
86 				/*	on circuit 113 */
87 #define	TSETCTSET	0000300	/* Output transmitter signal element */
88 				/*	timing (DCE source) on circuit 113 */
89 #define	TSETCRSET	0000400	/* Output receiver signal element */
90 				/*	timing (DCE source) on circuit 113 */
91 
92 #define	RSETCLK		0007000	/* Receiver Signal Element */
93 				/*	timing (DTE source) lead, */
94 				/*	CCITT V.24 circuit 128, */
95 				/*	no EIA-232-D pin, clock source: */
96 #define	RSETCOFF	0000000	/* RSET clock not provided */
97 #define	RSETCRBRG	0001000	/* Output receive baud rate generator */
98 				/*	on circuit 128 */
99 #define	RSETCTBRG	0002000	/* Output transmit baud rate generator */
100 				/*	on circuit 128 */
101 #define	RSETCTSET	0003000	/* Output transmitter signal element */
102 				/*	timing (DCE source) on circuit 128 */
103 #define	RSETCRSET	0004000	/* Output receiver signal element */
104 				/*	timing (DCE source) on circuit 128 */
105 
106 
107 struct termiox {
108 	unsigned short x_hflag;		/* hardware flow control modes */
109 	unsigned short x_cflag;		/* clock modes */
110 	unsigned short x_rflag[NFF];	/* reserved modes */
111 	unsigned short x_sflag;		/* spare modes */
112 };
113 
114 #define	XIOC    ('X'<<8)
115 #define	TCGETX  (XIOC|1)
116 #define	TCSETX  (XIOC|2)
117 #define	TCSETXW (XIOC|3)
118 #define	TCSETXF (XIOC|4)
119 
120 #ifdef	__cplusplus
121 }
122 #endif
123 
124 #endif	/* _SYS_TERMIOX_H */
125