1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 
26 #ifndef _NV_SATA_H
27 #define	_NV_SATA_H
28 
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 
35 /*
36  * SGPIO Support
37  * Enable SGPIO support only on x86/x64, because it is implemented using
38  * functions that are only available on x86/x64.
39  */
40 
41 #define	NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
42 
43 typedef struct nv_port nv_port_t;
44 
45 #ifdef SGPIO_SUPPORT
46 typedef struct nv_sgp_cmn nv_sgp_cmn_t;
47 #endif
48 
49 /*
50  * sizes of strings to allocate
51  */
52 #define	NV_STR_LEN	10
53 #define	NV_LOGBUF_LEN	512
54 #define	NV_REASON_LEN	30
55 
56 
57 typedef struct nv_ctl {
58 	/*
59 	 * Each of these are specific to the chipset in use.
60 	 */
61 	uint_t		(*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
62 	void		(*nvc_reg_init)(struct nv_ctl *nvc,
63 			    ddi_acc_handle_t pci_conf_handle);
64 
65 	dev_info_t	*nvc_dip; /* devinfo pointer of controller */
66 
67 	struct nv_port	*nvc_port; /* array of pointers to port struct */
68 
69 	/*
70 	 * handle and base address to register space.
71 	 *
72 	 * 0: port 0 task file
73 	 * 1: port 0 status
74 	 * 2: port 1 task file
75 	 * 3: port 1 status
76 	 * 4: bus master for both ports
77 	 * 5: extended registers for SATA features
78 	 */
79 	ddi_acc_handle_t nvc_bar_hdl[6];
80 	uchar_t		*nvc_bar_addr[6];
81 
82 	/*
83 	 * sata registers in bar 5 which are shared on all devices
84 	 * on the channel.
85 	 */
86 	uint32_t	*nvc_mcp5x_ctl;
87 	uint32_t	*nvc_mcp5x_ncq; /* NCQ status control bits */
88 
89 	kmutex_t	nvc_mutex; /* ctrl level lock */
90 
91 	ddi_intr_handle_t *nvc_htable;	/* For array of interrupts */
92 	int		 nvc_intr_type;	/* What type of interrupt */
93 	int		nvc_intr_cnt;	/* # of intrs count returned */
94 	size_t		nvc_intr_size;	/* Size of intr array to */
95 	uint_t		nvc_intr_pri;   /* Interrupt priority */
96 	int		nvc_intr_cap;	/* Interrupt capabilities */
97 	uint8_t		*nvc_ck804_int_status; /* interrupt status ck804 */
98 
99 	sata_hba_tran_t	nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
100 
101 	/*
102 	 * enable/disable interrupts, controller specific
103 	 */
104 	void		(*nvc_set_intr)(nv_port_t *nvp, int flag);
105 	int		nvc_state;	/* state flags of ctrl see below */
106 	uint16_t	nvc_devid;	/* PCI devid of device */
107 	uint8_t		nvc_revid;	/* PCI revid of device */
108 	boolean_t	dma_40bit;	/* 40bit DMA support */
109 	boolean_t	nvc_mcp5x_flag;	/* is the controller MCP51/MCP55 */
110 
111 #ifdef SGPIO_SUPPORT
112 	uint8_t		nvc_ctlr_num;	/* controller number within the part */
113 	uint32_t	nvc_sgp_csr;	/* SGPIO CSR i/o address */
114 	volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
115 	nv_sgp_cmn_t	*nvc_sgp_cmn;	/* SGPIO shared data */
116 #endif
117 } nv_ctl_t;
118 
119 
120 struct nv_port {
121 
122 	struct nv_ctl	*nvp_ctlp; /* back pointer to controller */
123 
124 	uint8_t		nvp_port_num; /* port number, ie 0 or 1 */
125 
126 	uint8_t		nvp_type;	/* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
127 	uint32_t	nvp_signature;	/* sig acquired from task file regs */
128 	uchar_t		*nvp_cmd_addr;	/* base addr for cmd regs for port */
129 	uchar_t		*nvp_bm_addr;	/* base addr for bus master for port */
130 	uchar_t		*nvp_ctl_addr;	/* base addr for ctrl regs for port */
131 
132 	ddi_acc_handle_t nvp_cmd_hdl;
133 	uchar_t		*nvp_data;	/* data register */
134 	uchar_t		*nvp_error;	/* error register (read) */
135 	uchar_t		*nvp_feature;	/* features (write) */
136 	uchar_t		*nvp_count;	/* sector count */
137 	uchar_t		*nvp_sect;	/* sector number */
138 	uchar_t		*nvp_lcyl;	/* cylinder low byte */
139 	uchar_t		*nvp_hcyl;	/* cylinder high byte */
140 	uchar_t		*nvp_drvhd;	/* drive/head register */
141 	uchar_t		*nvp_status;	/* status/command register */
142 	uchar_t		*nvp_cmd;	/* status/command register */
143 
144 	ddi_acc_handle_t nvp_ctl_hdl;
145 	uchar_t		*nvp_altstatus; /* alternate status (read) */
146 	uchar_t		*nvp_devctl;	/* device control (write) */
147 
148 	ddi_acc_handle_t nvp_bm_hdl;
149 	uchar_t		*nvp_bmisx;
150 	uint32_t	*nvp_bmidtpx;
151 	uchar_t		*nvp_bmicx;
152 
153 	ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
154 	caddr_t		 *nvp_sg_addr;	  /* virtual addr of prd table */
155 	uint32_t	 *nvp_sg_paddr;   /* physical address of prd table */
156 	ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */
157 
158 	uint32_t	*nvp_sstatus;
159 	uint32_t	*nvp_serror;
160 	uint32_t	*nvp_sctrl;
161 	uint32_t	*nvp_sactive;
162 
163 	kmutex_t	nvp_mutex;	/* main per port mutex */
164 	kcondvar_t	nvp_sync_cv;	/* handshake btwn ISR and start thrd */
165 	kcondvar_t	nvp_reset_cv;	/* when reset is synchronous */
166 
167 	/*
168 	 * nvp_slot is a pointer to an array of nv_slot
169 	 */
170 	struct nv_slot	*nvp_slot;
171 	uint32_t	nvp_sactive_cache; /* cache of SACTIVE */
172 	uint8_t		nvp_queue_depth;
173 
174 	/*
175 	 * NCQ flow control.  During NCQ operation, no other commands
176 	 * allowed.  The following are used to enforce this.
177 	 */
178 	int		nvp_ncq_run;
179 	int		nvp_non_ncq_run;
180 	int		nvp_seq;
181 
182 	timeout_id_t	nvp_timeout_id;
183 
184 	clock_t		nvp_reset_time;		/* time of last reset */
185 	clock_t		nvp_link_event_time;	/* time of last plug event */
186 	int		nvp_reset_retry_count;
187 	clock_t		nvp_wait_sig; /* wait before rechecking sig */
188 
189 	int		nvp_state; /* state of port. flags defined below */
190 
191 	uint16_t	*nvp_mcp5x_int_status;
192 	uint16_t	*nvp_mcp5x_int_ctl;
193 
194 #ifdef SGPIO_SUPPORT
195 	uint8_t		nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */
196 #endif
197 	clock_t		nvp_timeout_duration;
198 
199 
200 	/*
201 	 * debug and statistical information
202 	 */
203 	clock_t		nvp_rem_time;
204 	clock_t		nvp_add_time;
205 	clock_t		nvp_trans_link_time;
206 	int		nvp_trans_link_count;
207 
208 	uint8_t		nvp_last_cmd;
209 	uint8_t		nvp_previous_cmd;
210 	int		nvp_reset_count;
211 	char		nvp_first_reset_reason[NV_REASON_LEN];
212 	char		nvp_reset_reason[NV_REASON_LEN];
213 	clock_t		intr_duration;	/* max length of port intr (ticks) */
214 	clock_t		intr_start_time;
215 	int		intr_loop_cnt;
216 };
217 
218 
219 typedef struct nv_device_table {
220 	ushort_t vendor_id;	/* vendor id */
221 	ushort_t device_id;	/* device id */
222 	ushort_t type;		/* chipset type, ck804 or mcp51/mcp55 */
223 } nv_device_table_t;
224 
225 
226 typedef struct nv_slot {
227 	caddr_t		nvslot_v_addr;	/* I/O buffer address */
228 	size_t		nvslot_byte_count; /* # bytes left to read/write */
229 	sata_pkt_t	*nvslot_spkt;
230 	uint8_t		nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN];
231 	clock_t		nvslot_stime;
232 	int		(*nvslot_start)(nv_port_t *nvp, int queue);
233 	void		(*nvslot_intr)(nv_port_t *nvp,
234 			    struct nv_slot *nv_slotp);
235 	uint32_t	nvslot_flags;
236 } nv_slot_t;
237 
238 
239 #ifdef SGPIO_SUPPORT
240 struct nv_sgp_cmn {
241 	uint8_t		nvs_in_use;	/* bit-field of active ctlrs */
242 	uint8_t		nvs_connected;	/* port connected bit-field flag */
243 	uint8_t		nvs_activity;	/* port usage bit-field flag */
244 	int		nvs_cbp;	/* SGPIO Control Block Pointer */
245 	int		nvs_taskq_delay; /* rest time for activity LED taskq */
246 	kmutex_t	nvs_slock;	/* lock for shared data */
247 	kmutex_t	nvs_tlock;	/* lock for taskq */
248 	kcondvar_t	nvs_cv;		/* condition variable for taskq wait */
249 	ddi_taskq_t	*nvs_taskq;	/* activity LED taskq */
250 };
251 
252 struct nv_sgp_cbp2cmn {
253 	uint32_t	c2cm_cbp;	/* ctlr block ptr from pci cfg space */
254 	nv_sgp_cmn_t	*c2cm_cmn;	/* point to common space */
255 };
256 #endif
257 
258 
259 /*
260  * nvslot_flags
261  */
262 #define	NVSLOT_COMPLETE 0x01
263 #define	NVSLOT_NCQ	0x02	/* NCQ is active */
264 #define	NVSLOT_RQSENSE	0x04	/* processing request sense */
265 
266 /*
267  * state values for nv_attach
268  */
269 #define	ATTACH_PROGRESS_NONE			(1 << 0)
270 #define	ATTACH_PROGRESS_STATEP_ALLOC		(1 << 1)
271 #define	ATTACH_PROGRESS_PCI_HANDLE		(1 << 2)
272 #define	ATTACH_PROGRESS_BARS			(1 << 3)
273 #define	ATTACH_PROGRESS_INTR_ADDED		(1 << 4)
274 #define	ATTACH_PROGRESS_MUTEX_INIT		(1 << 5)
275 #define	ATTACH_PROGRESS_CTL_SETUP		(1 << 6)
276 #define	ATTACH_PROGRESS_TRAN_SETUP		(1 << 7)
277 #define	ATTACH_PROGRESS_COUNT			(1 << 8)
278 #define	ATTACH_PROGRESS_CONF_HANDLE		(1 << 9)
279 #define	ATTACH_PROGRESS_SATA_MODULE		(1 << 10)
280 
281 #ifdef DEBUG
282 
283 #define	NV_DEBUG		1
284 
285 #endif /* DEBUG */
286 
287 
288 /*
289  * nv_debug_flags
290  */
291 #define	NVDBG_ALWAYS	0x00001
292 #define	NVDBG_INIT	0x00002
293 #define	NVDBG_ENTRY	0x00004
294 #define	NVDBG_DELIVER	0x00008
295 #define	NVDBG_EVENT	0x00010
296 #define	NVDBG_SYNC	0x00020
297 #define	NVDBG_PKTCOMP	0x00040
298 #define	NVDBG_TIMEOUT	0x00080
299 #define	NVDBG_INFO	0x00100
300 #define	NVDBG_VERBOSE	0x00200
301 #define	NVDBG_INTR	0x00400
302 #define	NVDBG_ERRS	0x00800
303 #define	NVDBG_COOKIES	0x01000
304 #define	NVDBG_HOT	0x02000
305 #define	NVDBG_RESET	0x04000
306 #define	NVDBG_ATAPI	0x08000
307 
308 #define	NVLOG(flag, nvc, nvp, fmt, args ...)		\
309 	if (nv_debug_flags & (flag)) {			\
310 		nv_log(nvc, nvp, fmt, ## args);		\
311 	}
312 
313 
314 #define	NV_SUCCESS	0
315 #define	NV_FAILURE	-1
316 
317 /*
318  * indicates whether nv_wait functions can sleep or not.
319  */
320 #define	NV_SLEEP	1
321 #define	NV_NOSLEEP	2
322 
323 
324 /*
325  * port offsets from base address ioaddr1
326  */
327 #define	NV_DATA		0x00	/* data register 			*/
328 #define	NV_ERROR	0x01	/* error register (read)		*/
329 #define	NV_FEATURE	0x01	/* features (write)			*/
330 #define	NV_COUNT	0x02    /* sector count 			*/
331 #define	NV_SECT		0x03	/* sector number 			*/
332 #define	NV_LCYL		0x04	/* cylinder low byte 			*/
333 #define	NV_HCYL		0x05	/* cylinder high byte 			*/
334 #define	NV_DRVHD	0x06    /* drive/head register 			*/
335 #define	NV_STATUS	0x07	/* status/command register 		*/
336 #define	NV_CMD		0x07	/* status/command register 		*/
337 
338 /*
339  * port offsets from base address ioaddr2
340  */
341 #define	NV_ALTSTATUS	0x02	/* alternate status (read)		*/
342 #define	NV_DEVCTL	0x02	/* device control (write)		*/
343 
344 /*
345  * device control register
346  */
347 #define	ATDC_NIEN    	0x02    /* disable interrupts */
348 #define	ATDC_SRST	0x04	/* controller reset */
349 #define	ATDC_D3		0x08	/* mysterious bit */
350 #define	ATDC_HOB	0x80	/* high order byte to read 48-bit values */
351 
352 /*
353  * MCP5x NCQ and INTR control registers
354  */
355 #define	MCP5X_CTL		0x400 /* queuing control */
356 #define	MCP5X_INT_STATUS	0x440 /* status bits for interrupt */
357 #define	MCP5X_INT_CTL		0x444 /* enable bits for interrupt */
358 #define	MCP5X_NCQ		0x448 /* NCQ status and ctrl bits */
359 
360 /*
361  * if either of these bits are set, when using NCQ, if no other commands are
362  * active while a new command is started, DMA engine can be programmed ahead
363  * of time to save extra interrupt.  Presumably pre-programming is discarded
364  * if a subsequent command ends up finishing first.
365  */
366 #define	MCP_SATA_AE_NCQ_PDEV_FIRST_CMD	(1 << 7)
367 #define	MCP_SATA_AE_NCQ_SDEV_FIRST_CMD	(1 << 23)
368 
369 /*
370  * bit definitions to indicate which NCQ command requires
371  * DMA setup.
372  */
373 #define	MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT	2
374 #define	MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT	18
375 #define	MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK		0x1f
376 
377 
378 /*
379  * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS
380  */
381 #define	MCP5X_INT_SNOTIFY	0x200	/* snotification set */
382 #define	MCP5X_INT_SERROR	0x100	/* serror set */
383 #define	MCP5X_INT_DMA_SETUP	0x80	/* DMA to be programmed */
384 #define	MCP5X_INT_DH_REGFIS	0x40	/* REGFIS received */
385 #define	MCP5X_INT_SDB_FIS	0x20	/* SDB FIS */
386 #define	MCP5X_INT_TX_BACKOUT	0x10	/* TX backout */
387 #define	MCP5X_INT_REM		0x08	/* device removed */
388 #define	MCP5X_INT_ADD		0x04	/* device added */
389 #define	MCP5X_INT_PM		0x02	/* power changed */
390 #define	MCP5X_INT_COMPLETE	0x01	/* device interrupt */
391 
392 /*
393  * Bits above that are not used for now.
394  */
395 #define	MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\
396 	MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\
397 	MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR)
398 
399 /*
400  * Bits for MCP_SATA_AE_CTL
401  */
402 #define	MCP_SATA_AE_CTL_PRI_SWNCQ	(1 << 1) /* software NCQ chan 0 */
403 #define	MCP_SATA_AE_CTL_SEC_SWNCQ	(1 << 2) /* software NCQ chan 1 */
404 
405 #define	NV_DELAY_NSEC(wait_ns)		\
406 {					\
407 	hrtime_t start, end;		\
408 	start = end =  gethrtime();	\
409 	while ((end - start) < wait_ns)	\
410 		end = gethrtime();	\
411 }
412 
413 /*
414  * signature in task file registers after device reset
415  */
416 #define	NV_DISK_SIG	0x00000101
417 #define	NV_ATAPI_SIG	0xeb140101
418 #define	NV_PM_SIG	0x96690101
419 #define	NV_NO_SIG	0x00000000
420 
421 /*
422  * These bar5 offsets are common to mcp51/mcp55/ck804 and thus
423  * prefixed with NV.
424  */
425 #define	NV_SSTATUS	0x00
426 #define	NV_SERROR	0x04
427 #define	NV_SCTRL	0x08
428 #define	NV_SACTIVE	0x0c
429 #define	NV_SNOTIFICATION 0x10
430 
431 #define	CH0_SREG_OFFSET	0x0
432 #define	CH1_SREG_OFFSET	0x40
433 
434 
435 /*
436  * The following config space offsets are needed to enable
437  * bar 5 register access in ck804/mcp51/mcp55
438  */
439 #define	NV_SATA_CFG_20		0x50
440 #define	NV_BAR5_SPACE_EN	0x04
441 #define	NV_40BIT_PRD		0x20
442 
443 #define	NV_SATA_CFG_23		0x60
444 
445 /*
446  * ck804 interrupt status register
447  */
448 
449 /*
450  * offsets to bar 5 registers
451  */
452 #define	CK804_SATA_INT_STATUS	0x440
453 #define	CK804_SATA_INT_EN	0x441
454 
455 
456 /*
457  * bit fields for int status and int enable
458  * registers
459  */
460 #define	CK804_INT_PDEV_INT	0x01 /* completion interrupt */
461 #define	CK804_INT_PDEV_PM	0x02 /* power change */
462 #define	CK804_INT_PDEV_ADD	0x04 /* hot plug */
463 #define	CK804_INT_PDEV_REM	0x08 /* hot remove */
464 #define	CK804_INT_PDEV_HOT	CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM
465 
466 #define	CK804_INT_SDEV_INT	0x10 /* completion interrupt */
467 #define	CK804_INT_SDEV_PM	0x20 /* power change */
468 #define	CK804_INT_SDEV_ADD	0x40 /* hot plug */
469 #define	CK804_INT_SDEV_REM	0x80 /* hot remove */
470 #define	CK804_INT_SDEV_HOT	CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM
471 
472 #define	CK804_INT_PDEV_ALL	CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\
473 				CK804_INT_PDEV_PM
474 #define	CK804_INT_SDEV_ALL	CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\
475 				CK804_INT_SDEV_PM
476 
477 /*
478  * config space offset 42
479  */
480 #define	NV_SATA_CFG_42			0xac
481 
482 /*
483  * bit in CFG_42 which delays hotplug interrupt until
484  * PHY ready
485  */
486 #define	CK804_CFG_DELAY_HOTPLUG_INTR	(0x1 << 12)
487 
488 
489 /*
490  * bar 5 offsets for SATA registers in ck804
491  */
492 #define	CK804_CH1_SSTATUS	0x00
493 #define	CK804_CH1_SERROR	0x04
494 #define	CK804_CH1_SCTRL		0x08
495 #define	CK804_CH1_SACTIVE	0x0c
496 #define	CK804_CH1_SNOTIFICATION	0x10
497 
498 #define	CK804_CH2_SSTATUS	0x40
499 #define	CK804_CH2_SERROR	0x44
500 #define	CK804_CH2_SCTRL		0x48
501 #define	CK804_CH2_SACTIVE	0x4c
502 #define	CK804_CH2_SNOTIFICATION	0x50
503 
504 
505 /*
506  * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55
507  */
508 #define	NV_ADMACTL_X	0x4C0
509 #define	NV_ADMACTL_Y	0x5C0
510 
511 /*
512  * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
513  */
514 #define	NV_HIRQ_EN	0x01 /* hot plug/unplug interrupt enable */
515 #define	NV_CH_RST	0x04 /* reset channel */
516 
517 
518 /*
519  * bar 5 offset for ADMASTAT regs for ck804
520  */
521 #define	CK804_ADMASTAT_X	0x4C4
522 #define	CK804_ADMASTAT_Y	0x5C4
523 
524 /*
525  * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y
526  */
527 #define	CK804_HPIRQ	0x4
528 #define	MCP05_HUIRQ	0x2
529 
530 
531 /*
532  * bar 4 offset to bus master command registers
533  */
534 #define	BMICX_REG	0
535 
536 /*
537  * bit definitions for BMICX_REG
538  */
539 #define	BMICX_SSBM	0x01	/* Start/Stop Bus Master */
540 				/* 1=Start (Enable) */
541 				/* 0=Start (Disable) */
542 
543 /*
544  * NOTE: "read" and "write" are the actions of the DMA engine
545  * on the PCI bus, not the SATA bus.  Therefore for a ATA READ
546  * command, program the DMA engine to "write to memory" mode
547  * (and vice versa).
548  */
549 #define	BMICX_RWCON			0x08 /* Read/Write Control */
550 #define	BMICX_RWCON_WRITE_TO_MEMORY	0x08 /* 1=Write (dev to host) */
551 #define	BMICX_RWCON_READ_FROM_MEMORY	0x00 /* 0=Read  (host to dev) */
552 
553 /*
554  * BMICX bits to preserve during updates
555  */
556 #define	BMICX_MASK	(~(BMICX_SSBM | BMICX_RWCON))
557 
558 /*
559  * bar 4 offset to bus master status register
560  */
561 #define	BMISX_REG	2
562 
563 /*
564  * bit fields for bus master status register
565  */
566 #define	BMISX_BMIDEA	0x01	/* Bus Master IDE Active */
567 #define	BMISX_IDERR	0x02	/* IDE DMA Error */
568 #define	BMISX_IDEINTS	0x04	/* IDE Interrupt Status */
569 
570 /*
571  * bus master status register bits to preserve
572  */
573 #define	BMISX_MASK	0xf8
574 
575 /*
576  * bar4 offset to bus master PRD descriptor table
577  */
578 #define	BMIDTPX_REG	4
579 
580 
581 /*
582  * structure for a single entry in the PRD table
583  * (physical region descriptor table)
584  */
585 typedef struct prde {
586 	uint32_t p_address; /* physical address */
587 	uint32_t p_count;   /* byte count, EOT in high order bit */
588 } prde_t;
589 
590 
591 #define	PRDE_EOT	((uint_t)0x80000000)
592 
593 #define	NV_DMA_NSEGS	257 /* at least 1MB (4KB/pg * 256) + 1 if misaligned */
594 
595 /*
596  * ck804 and mcp55 both have 2 ports per controller
597  */
598 #define	NV_NUM_PORTS	2
599 
600 /*
601  * Number of slots to allocate in data nv_sata structures to handle
602  * multiple commands at once.  This does not reflect the capability of
603  * the drive or the hardware, and in many cases will not match.
604  * 1 or 32 slots are allocated, so in cases where the driver has NCQ
605  * enabled but the drive doesn't support it, or supports fewer than
606  * 32 slots, here may be an over allocation of memory.
607  */
608 #ifdef NCQ
609 #define	NV_QUEUE_SLOTS	32
610 #else
611 #define	NV_QUEUE_SLOTS	1
612 #endif
613 
614 #define	NV_BM_64K_BOUNDARY	0x10000ull
615 
616 #define	NV_MAX_INTR_PER_DEV	20	/* Empirical value */
617 
618 /*
619  * 1 second (in microseconds)
620  */
621 #define	NV_ONE_SEC		1000000
622 
623 /*
624  * 1 millisecond (in microseconds)
625  */
626 #define	NV_ONE_MSEC		1000
627 
628 /*
629  * initial wait before checking for signature, in microseconds
630  */
631 #define	NV_WAIT_SIG	2500
632 
633 
634 /*
635  * Length of port reset (microseconds) - SControl bit 0 set to 1
636  */
637 #define	NV_RESET_LENGTH		1000
638 
639 /*
640  * the maximum number of comresets to issue while
641  * performing link reset in nv_reset()
642  */
643 #define	NV_COMRESET_ATTEMPTS	3
644 
645 /*
646  * amount of time to wait for a signature in reset, in ms, before
647  * issuing another reset
648  */
649 #define	NV_RETRY_RESET_SIG	5000
650 
651 /*
652  * the maximum number of resets to issue to gather signature
653  * before giving up
654  */
655 #define	NV_MAX_RESET_RETRY	8
656 
657 /*
658  * amount of time (us) to wait after receiving a link event
659  * before acting on it.  This is because of flakey hardware
660  * sometimes issues the wrong, multiple, or out of order link
661  * events.
662  */
663 #define	NV_LINK_EVENT_SETTLE	500000
664 
665 /*
666  * The amount of time (ms) a link can be missing
667  * before declaring it removed.
668  */
669 #define	NV_LINK_EVENT_DOWN	200
670 
671 /*
672  * nvp_state flags
673  */
674 #define	NV_DEACTIVATED	0x001
675 #define	NV_ABORTING	0x002
676 #define	NV_FAILED	0x004
677 #define	NV_RESET	0x008
678 #define	NV_RESTORE	0x010
679 #define	NV_LINK_EVENT	0x020
680 #define	NV_ATTACH	0x040
681 #define	NV_HOTPLUG	0x080
682 
683 
684 /*
685  * flags for nv_report_link_event()
686  */
687 #define	NV_ADD_DEV 0
688 #define	NV_REM_DEV 1
689 
690 /*
691  * nvc_state flags
692  */
693 #define	NV_CTRL_SUSPEND		0x1
694 
695 
696 /*
697  * flags for ck804_set_intr/mcp5x_set_intr
698  */
699 #define	NV_INTR_DISABLE		0x1
700 #define	NV_INTR_ENABLE		0x2
701 #define	NV_INTR_CLEAR_ALL	0x4
702 #define	NV_INTR_DISABLE_NON_BLOCKING		0x8
703 
704 
705 #define	NV_BYTES_PER_SEC 512
706 
707 #define	NV_WAIT_REG_CHECK	10	/* 10 microseconds */
708 #define	NV_ATA_NUM_CMDS		256	/* max num ATA cmds possible, 8 bits */
709 #define	NV_PRINT_INTERVAL	40	/* throttle debug msg from flooding */
710 #define	MCP5X_INT_CLEAR		0xffff	/* clear all interrupts */
711 
712 /*
713  * definition labels for the BAR registers
714  */
715 #define	NV_BAR_0 0 /* chan 0 task file regs */
716 #define	NV_BAR_1 1 /* chan 0 status reg */
717 #define	NV_BAR_2 2 /* chan 1 task file regs */
718 #define	NV_BAR_3 3 /* chan 1 status reg */
719 #define	NV_BAR_4 4 /* bus master regs */
720 #define	NV_BAR_5 5 /* extra regs mostly SATA related */
721 
722 /*
723  * transform seconds to microseconds
724  */
725 #define	NV_SEC2USEC(x) x * MICROSEC
726 
727 
728 /*
729  * ck804 maps in task file regs into bar 5.  These are
730  * only used to identify ck804, therefore only this reg is
731  * listed here.
732  */
733 #define	NV_BAR5_TRAN_LEN_CH_X	0x518
734 
735 /*
736  * if after this many iterations through the interrupt
737  * processing loop, declare the interrupt wedged and
738  * disable.
739  */
740 #define	NV_MAX_INTR_LOOP 10
741 
742 /*
743  * flag values for nv_copy_regs_out
744  */
745 #define	NV_COPY_COMPLETE 0x01	/* normal command completion */
746 #define	NV_COPY_ERROR    0x02	/* error, did not complete ok */
747 #define	NV_COPY_SSREGS   0x04	/* SS port registers */
748 
749 #ifdef SGPIO_SUPPORT
750 #define	NV_MAX_CBPS	16		/* Maximum # of Control Block */
751 					/* Pointers.  Corresponds to */
752 					/* each MCP55 and IO55 */
753 #define	SGPIO_LOOP_WAIT_USECS	62500	/* 1/16 second (in usecs) */
754 #define	SGPIO_TQ_NAME_LEN	32
755 
756 /*
757  * The drive number format is ccp (binary).
758  * cc is the controller number (0-based number)
759  * p is the port number (0 or 1)
760  */
761 #define	SGP_DRV_TO_PORT(d)		((d) & 1)
762 #define	SGP_DRV_TO_CTLR(d)		((d) >> 1)
763 #define	SGP_CTLR_PORT_TO_DRV(c, p)	(((c) << 1) | ((p) & 1))
764 #endif
765 
766 #ifdef	__cplusplus
767 }
768 #endif
769 
770 #endif /* _NV_SATA_H */
771