1 
2 /*
3  * This file and its contents are supplied under the terms of the
4  * Common Development and Distribution License ("CDDL"), version 1.0.
5  * You may only use this file in accordance with the terms of version
6  * 1.0 of the CDDL.
7  *
8  * A full copy of the text of the CDDL should have accompanied this
9  * source. A copy of the CDDL is also available via the Internet at
10  * http://www.illumos.org/license/CDDL.
11  */
12 
13 /* This file is automatically generated --- changes will be lost */
14 /* Generation Date : Fri Jun 22 10:51:50 PDT 2018 */
15 /* Directory name: t4_reg.txt, Date: Not specified */
16 /* Directory name: t5_reg.txt, Changeset: 6940:daefc1fa1d8a */
17 /* Directory name: t6_reg.txt, Changeset: 4270:552778f380ec */
18 
19 #define MYPF_BASE 0x1b000
20 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
21 
22 #define PF0_BASE 0x1e000
23 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
24 
25 #define PF1_BASE 0x1e400
26 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
27 
28 #define PF2_BASE 0x1e800
29 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
30 
31 #define PF3_BASE 0x1ec00
32 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
33 
34 #define PF4_BASE 0x1f000
35 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
36 
37 #define PF5_BASE 0x1f400
38 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
39 
40 #define PF6_BASE 0x1f800
41 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
42 
43 #define PF7_BASE 0x1fc00
44 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
45 
46 #define PF_STRIDE 0x400
47 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
48 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
49 
50 #define VF_SGE_BASE 0x0
51 #define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
52 
53 #define VF_MPS_BASE 0x100
54 #define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
55 
56 #define VF_PL_BASE 0x200
57 #define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
58 
59 #define VF_MBDATA_BASE 0x240
60 #define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
61 
62 #define VF_CIM_BASE 0x300
63 #define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
64 
65 #define MYPORT_BASE 0x1c000
66 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
67 
68 #define PORT0_BASE 0x20000
69 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
70 
71 #define PORT1_BASE 0x22000
72 #define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
73 
74 #define PORT2_BASE 0x24000
75 #define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
76 
77 #define PORT3_BASE 0x26000
78 #define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
79 
80 #define PORT_STRIDE 0x2000
81 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
82 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
83 
84 #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
85 #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
86 
87 #define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
88 #define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
89 
90 #define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
91 #define NUM_PCIE_DMA_INSTANCES 4
92 
93 #define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
94 #define NUM_PCIE_CMD_INSTANCES 2
95 
96 #define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
97 #define NUM_PCIE_HMA_INSTANCES 1
98 
99 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
100 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
101 
102 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
103 #define NUM_PCIE_MAILBOX_INSTANCES 1
104 
105 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
106 #define NUM_PCIE_FW_INSTANCES 8
107 
108 #define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
109 #define NUM_PCIE_FUNC_INSTANCES 256
110 
111 #define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
112 #define NUM_PCIE_FID_INSTANCES 2048
113 
114 #define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
115 #define NUM_PCIE_DMA_BUF_INSTANCES 4
116 
117 #define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
118 #define NUM_MC_DDR3PHYDATX8_INSTANCES 9
119 
120 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
121 #define NUM_MC_BIST_STATUS_INSTANCES 18
122 
123 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
124 #define NUM_EDC_BIST_STATUS_INSTANCES 18
125 
126 #define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
127 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
128 
129 #define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
130 #define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
131 
132 #define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
133 #define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
134 
135 #define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
136 #define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
137 
138 #define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
139 #define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
140 
141 #define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
142 #define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
143 
144 #define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
145 #define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
146 
147 #define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
148 #define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
149 
150 #define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
151 #define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
152 
153 #define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
154 #define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
155 
156 #define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
157 #define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
158 
159 #define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
160 #define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
161 
162 #define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
163 #define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
164 
165 #define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
166 #define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
167 
168 #define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
169 #define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
170 
171 #define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
172 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
173 
174 #define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
175 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
176 
177 #define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
178 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
179 
180 #define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
181 #define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
182 
183 #define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
184 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
185 
186 #define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
187 #define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
188 
189 #define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
190 #define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
191 
192 #define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
193 #define NUM_PL_VF_SLICE_L_INSTANCES 8
194 
195 #define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
196 #define NUM_PL_VF_SLICE_H_INSTANCES 8
197 
198 #define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
199 #define NUM_PL_FLR_VF_STATUS_INSTANCES 4
200 
201 #define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
202 #define NUM_PL_VFID_MAP_INSTANCES 256
203 
204 #define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
205 #define NUM_LE_DB_MASK_IPV4_INSTANCES 17
206 
207 #define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
208 #define NUM_LE_DB_MASK_IPV6_INSTANCES 17
209 
210 #define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
211 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
212 
213 #define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
214 #define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
215 
216 #define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
217 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
218 
219 #define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
220 #define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
221 
222 #define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
223 #define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
224 
225 #define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
226 #define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
227 
228 #define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
229 #define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
230 
231 #define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
232 #define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
233 
234 #define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
235 #define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
236 
237 #define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
238 #define NUM_UP_TSCH_CHANNEL_INSTANCES 4
239 
240 #define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
241 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
242 
243 #define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
244 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
245 
246 #define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
247 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
248 
249 #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
250 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
251 
252 #define T5_MYPORT_BASE 0x2c000
253 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
254 
255 #define T5_PORT0_BASE 0x30000
256 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
257 
258 #define T5_PORT1_BASE 0x34000
259 #define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
260 
261 #define T5_PORT2_BASE 0x38000
262 #define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
263 
264 #define T5_PORT3_BASE 0x3c000
265 #define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
266 
267 #define T5_PORT_STRIDE 0x4000
268 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
269 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
270 
271 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
272 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
273 
274 #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
275 #define NUM_PCIE_PF_INT_INSTANCES 8
276 
277 #define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
278 #define NUM_PCIE_VF_INT_INSTANCES 128
279 
280 #define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
281 #define NUM_PCIE_FID_VFID_INSTANCES 2048
282 
283 #define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
284 #define NUM_PCIE_COOKIE_INSTANCES 8
285 
286 #define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
287 #define NUM_PCIE_T5_DMA_INSTANCES 4
288 
289 #define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
290 #define NUM_PCIE_T5_CMD_INSTANCES 3
291 
292 #define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
293 #define NUM_PCIE_T5_HMA_INSTANCES 1
294 
295 #define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
296 #define NUM_PCIE_PHY_PRESET_INSTANCES 11
297 
298 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
299 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
300 
301 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
302 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
303 
304 #define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
305 #define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
306 
307 #define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
308 #define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
309 
310 #define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
311 #define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
312 
313 #define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
314 #define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
315 
316 #define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
317 #define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
318 
319 #define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
320 #define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
321 
322 #define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
323 #define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
324 
325 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
326 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
327 
328 #define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
329 #define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
330 
331 #define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
332 #define NUM_MC_ADR_INSTANCES 2
333 
334 #define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
335 #define NUM_MC_DDRPHY_DP18_INSTANCES 5
336 
337 #define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
338 #define NUM_MC_CE_ERR_DATA_INSTANCES 8
339 
340 #define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
341 #define NUM_MC_CE_COR_DATA_INSTANCES 8
342 
343 #define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
344 #define NUM_MC_UE_ERR_DATA_INSTANCES 8
345 
346 #define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
347 #define NUM_MC_UE_COR_DATA_INSTANCES 8
348 
349 #define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
350 #define NUM_MC_P_BIST_STATUS_INSTANCES 18
351 
352 #define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
353 #define NUM_EDC_H_BIST_STATUS_INSTANCES 18
354 
355 #define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
356 #define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
357 
358 #define SGE_DEBUG1_DBP_THREAD(idx) (A_SGE_DEBUG1_DBP_THREAD + (idx) * 4)
359 #define NUM_SGE_DEBUG1_DBP_THREAD_INSTANCES 4
360 
361 #define SGE_DEBUG0_DBP_THREAD(idx) (A_SGE_DEBUG0_DBP_THREAD + (idx) * 4)
362 #define NUM_SGE_DEBUG0_DBP_THREAD_INSTANCES 5
363 
364 #define SGE_WC_EGRS_BAR2_OFF_PF(idx) (A_SGE_WC_EGRS_BAR2_OFF_PF + (idx) * 4)
365 #define NUM_SGE_WC_EGRS_BAR2_OFF_PF_INSTANCES 8
366 
367 #define SGE_WC_EGRS_BAR2_OFF_VF(idx) (A_SGE_WC_EGRS_BAR2_OFF_VF + (idx) * 4)
368 #define NUM_SGE_WC_EGRS_BAR2_OFF_VF_INSTANCES 8
369 
370 #define PCIE_T6_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
371 #define NUM_PCIE_T6_DMA_INSTANCES 2
372 
373 #define PCIE_T6_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
374 #define NUM_PCIE_T6_CMD_INSTANCES 1
375 
376 #define PCIE_VF_256_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
377 #define NUM_PCIE_VF_256_INT_INSTANCES 128
378 
379 #define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32)
380 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_L_INSTANCES 8
381 
382 #define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32)
383 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_DA_H_INSTANCES 8
384 
385 #define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32)
386 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_L_INSTANCES 8
387 
388 #define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32)
389 #define NUM_MPS_CLS_REQUEST_TRACE_MAC_SA_H_INSTANCES 8
390 
391 #define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32)
392 #define NUM_MPS_CLS_REQUEST_TRACE_PORT_VLAN_INSTANCES 8
393 
394 #define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32)
395 #define NUM_MPS_CLS_REQUEST_TRACE_ENCAP_INSTANCES 8
396 
397 #define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4)
398 #define NUM_MPS_CLS_RESULT_TRACE_INSTANCES 8
399 
400 #define MPS_CLS_DIPIPV4_ID_TABLE(idx) (A_MPS_CLS_DIPIPV4_ID_TABLE + (idx) * 8)
401 #define NUM_MPS_CLS_DIPIPV4_ID_TABLE_INSTANCES 4
402 
403 #define MPS_CLS_DIPIPV4_MASK_TABLE(idx) (A_MPS_CLS_DIPIPV4_MASK_TABLE + (idx) * 8)
404 #define NUM_MPS_CLS_DIPIPV4_MASK_TABLE_INSTANCES 4
405 
406 #define MPS_CLS_DIPIPV6ID_0_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_0_TABLE + (idx) * 32)
407 #define NUM_MPS_CLS_DIPIPV6ID_0_TABLE_INSTANCES 2
408 
409 #define MPS_CLS_DIPIPV6ID_1_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_1_TABLE + (idx) * 32)
410 #define NUM_MPS_CLS_DIPIPV6ID_1_TABLE_INSTANCES 2
411 
412 #define MPS_CLS_DIPIPV6ID_2_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_2_TABLE + (idx) * 32)
413 #define NUM_MPS_CLS_DIPIPV6ID_2_TABLE_INSTANCES 2
414 
415 #define MPS_CLS_DIPIPV6ID_3_TABLE(idx) (A_MPS_CLS_DIPIPV6ID_3_TABLE + (idx) * 32)
416 #define NUM_MPS_CLS_DIPIPV6ID_3_TABLE_INSTANCES 2
417 
418 #define MPS_CLS_DIPIPV6MASK_0_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_0_TABLE + (idx) * 32)
419 #define NUM_MPS_CLS_DIPIPV6MASK_0_TABLE_INSTANCES 2
420 
421 #define MPS_CLS_DIPIPV6MASK_1_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_1_TABLE + (idx) * 32)
422 #define NUM_MPS_CLS_DIPIPV6MASK_1_TABLE_INSTANCES 2
423 
424 #define MPS_CLS_DIPIPV6MASK_2_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_2_TABLE + (idx) * 32)
425 #define NUM_MPS_CLS_DIPIPV6MASK_2_TABLE_INSTANCES 2
426 
427 #define MPS_CLS_DIPIPV6MASK_3_TABLE(idx) (A_MPS_CLS_DIPIPV6MASK_3_TABLE + (idx) * 32)
428 #define NUM_MPS_CLS_DIPIPV6MASK_3_TABLE_INSTANCES 2
429 
430 #define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4)
431 #define NUM_MPS_RX_HASH_LKP_TABLE_INSTANCES 4
432 
433 #define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4)
434 #define NUM_LE_DB_DBG_MATCH_DATA_MASK_INSTANCES 8
435 
436 #define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4)
437 #define NUM_LE_DB_DBG_MATCH_DATA_INSTANCES 8
438 
439 #define LE_DB_DBGI_REQ_DATA_T6(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
440 #define NUM_LE_DB_DBGI_REQ_DATA_T6_INSTANCES 11
441 
442 #define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
443 #define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
444 
445 #define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
446 #define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
447 
448 #define LE_HASH_MASK_GEN_IPV4T6(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
449 #define NUM_LE_HASH_MASK_GEN_IPV4T6_INSTANCES 8
450 
451 #define T6_LE_HASH_MASK_GEN_IPV6T5(idx) (A_T6_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
452 #define NUM_T6_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 8
453 
454 #define LE_DB_PSV_FILTER_MASK_TUP_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 + (idx) * 4)
455 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV4_INSTANCES 3
456 
457 #define LE_DB_PSV_FILTER_MASK_FLT_IPV4(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 + (idx) * 4)
458 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV4_INSTANCES 2
459 
460 #define LE_DB_PSV_FILTER_MASK_TUP_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 + (idx) * 4)
461 #define NUM_LE_DB_PSV_FILTER_MASK_TUP_IPV6_INSTANCES 9
462 
463 #define LE_DB_PSV_FILTER_MASK_FLT_IPV6(idx) (A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 + (idx) * 4)
464 #define NUM_LE_DB_PSV_FILTER_MASK_FLT_IPV6_INSTANCES 2
465 
466 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
467 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_T6_INSTANCES 8
468 
469 #define MC_DDRPHY_DP18_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
470 #define NUM_MC_DDRPHY_DP18_T6_INSTANCES 9
471 
472 #define MC_CE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
473 #define NUM_MC_CE_ERR_DATA_T6_INSTANCES 16
474 
475 #define MC_UE_ERR_DATA_T6_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
476 #define NUM_MC_UE_ERR_DATA_T6_INSTANCES 16
477 
478 #define CIM_CTL_MAILBOX_VF_STATUS_T6(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
479 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_T6_INSTANCES 8
480 
481 #define CIM_CTL_MAILBOX_VFN_CTL_T6(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 4)
482 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_T6_INSTANCES 256
483 
484 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
485 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
486 
487 #define EDC_T5_STRIDE (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
488 #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx)
489 
490 /* registers for module SGE */
491 #define SGE_BASE_ADDR 0x1000
492 
493 #define A_SGE_PF_KDOORBELL 0x0
494 
495 #define S_QID    15
496 #define M_QID    0x1ffffU
497 #define V_QID(x) ((x) << S_QID)
498 #define G_QID(x) (((x) >> S_QID) & M_QID)
499 
500 #define S_DBPRIO    14
501 #define V_DBPRIO(x) ((x) << S_DBPRIO)
502 #define F_DBPRIO    V_DBPRIO(1U)
503 
504 #define S_PIDX    0
505 #define M_PIDX    0x3fffU
506 #define V_PIDX(x) ((x) << S_PIDX)
507 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
508 
509 #define A_SGE_VF_KDOORBELL 0x0
510 
511 #define S_DBTYPE    13
512 #define V_DBTYPE(x) ((x) << S_DBTYPE)
513 #define F_DBTYPE    V_DBTYPE(1U)
514 
515 #define S_PIDX_T5    0
516 #define M_PIDX_T5    0x1fffU
517 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
518 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
519 
520 #define S_SYNC_T6    14
521 #define V_SYNC_T6(x) ((x) << S_SYNC_T6)
522 #define F_SYNC_T6    V_SYNC_T6(1U)
523 
524 #define A_SGE_PF_GTS 0x4
525 
526 #define S_INGRESSQID    16
527 #define M_INGRESSQID    0xffffU
528 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
529 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
530 
531 #define S_TIMERREG    13
532 #define M_TIMERREG    0x7U
533 #define V_TIMERREG(x) ((x) << S_TIMERREG)
534 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
535 
536 #define S_SEINTARM    12
537 #define V_SEINTARM(x) ((x) << S_SEINTARM)
538 #define F_SEINTARM    V_SEINTARM(1U)
539 
540 #define S_CIDXINC    0
541 #define M_CIDXINC    0xfffU
542 #define V_CIDXINC(x) ((x) << S_CIDXINC)
543 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
544 
545 #define A_SGE_VF_GTS 0x4
546 #define A_SGE_PF_KTIMESTAMP_LO 0x8
547 #define A_SGE_VF_KTIMESTAMP_LO 0x8
548 #define A_SGE_PF_KTIMESTAMP_HI 0xc
549 
550 #define S_TSTAMPVAL    0
551 #define M_TSTAMPVAL    0xfffffffU
552 #define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
553 #define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
554 
555 #define A_SGE_VF_KTIMESTAMP_HI 0xc
556 #define A_SGE_CONTROL 0x1008
557 
558 #define S_FLSPLITMODE    20
559 #define M_FLSPLITMODE    0x3U
560 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
561 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
562 
563 #define S_RXPKTCPLMODE    18
564 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
565 #define F_RXPKTCPLMODE    V_RXPKTCPLMODE(1U)
566 
567 #define S_EGRSTATUSPAGESIZE    17
568 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
569 #define F_EGRSTATUSPAGESIZE    V_EGRSTATUSPAGESIZE(1U)
570 
571 #define S_PKTSHIFT    10
572 #define M_PKTSHIFT    0x7U
573 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
574 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
575 
576 #define S_INGPADBOUNDARY    4
577 #define M_INGPADBOUNDARY    0x7U
578 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
579 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
580 
581 #define S_GLOBALENABLE    0
582 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
583 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
584 
585 #define S_IGRALLCPLTOFL    31
586 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
587 #define F_IGRALLCPLTOFL    V_IGRALLCPLTOFL(1U)
588 
589 #define S_FLSPLITMIN    22
590 #define M_FLSPLITMIN    0x1ffU
591 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
592 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
593 
594 #define S_INGHINTENABLE1    15
595 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
596 #define F_INGHINTENABLE1    V_INGHINTENABLE1(1U)
597 
598 #define S_INGHINTENABLE0    14
599 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
600 #define F_INGHINTENABLE0    V_INGHINTENABLE0(1U)
601 
602 #define S_INGINTCOMPAREIDX    13
603 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
604 #define F_INGINTCOMPAREIDX    V_INGINTCOMPAREIDX(1U)
605 
606 #define S_INGPCIEBOUNDARY    7
607 #define M_INGPCIEBOUNDARY    0x7U
608 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
609 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
610 
611 #define A_SGE_HOST_PAGE_SIZE 0x100c
612 
613 #define S_HOSTPAGESIZEPF7    28
614 #define M_HOSTPAGESIZEPF7    0xfU
615 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
616 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
617 
618 #define S_HOSTPAGESIZEPF6    24
619 #define M_HOSTPAGESIZEPF6    0xfU
620 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
621 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
622 
623 #define S_HOSTPAGESIZEPF5    20
624 #define M_HOSTPAGESIZEPF5    0xfU
625 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
626 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
627 
628 #define S_HOSTPAGESIZEPF4    16
629 #define M_HOSTPAGESIZEPF4    0xfU
630 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
631 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
632 
633 #define S_HOSTPAGESIZEPF3    12
634 #define M_HOSTPAGESIZEPF3    0xfU
635 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
636 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
637 
638 #define S_HOSTPAGESIZEPF2    8
639 #define M_HOSTPAGESIZEPF2    0xfU
640 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
641 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
642 
643 #define S_HOSTPAGESIZEPF1    4
644 #define M_HOSTPAGESIZEPF1    0xfU
645 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
646 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
647 
648 #define S_HOSTPAGESIZEPF0    0
649 #define M_HOSTPAGESIZEPF0    0xfU
650 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
651 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
652 
653 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
654 
655 #define S_QUEUESPERPAGEPF7    28
656 #define M_QUEUESPERPAGEPF7    0xfU
657 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
658 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
659 
660 #define S_QUEUESPERPAGEPF6    24
661 #define M_QUEUESPERPAGEPF6    0xfU
662 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
663 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
664 
665 #define S_QUEUESPERPAGEPF5    20
666 #define M_QUEUESPERPAGEPF5    0xfU
667 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
668 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
669 
670 #define S_QUEUESPERPAGEPF4    16
671 #define M_QUEUESPERPAGEPF4    0xfU
672 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
673 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
674 
675 #define S_QUEUESPERPAGEPF3    12
676 #define M_QUEUESPERPAGEPF3    0xfU
677 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
678 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
679 
680 #define S_QUEUESPERPAGEPF2    8
681 #define M_QUEUESPERPAGEPF2    0xfU
682 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
683 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
684 
685 #define S_QUEUESPERPAGEPF1    4
686 #define M_QUEUESPERPAGEPF1    0xfU
687 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
688 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
689 
690 #define S_QUEUESPERPAGEPF0    0
691 #define M_QUEUESPERPAGEPF0    0xfU
692 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
693 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
694 
695 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
696 
697 #define S_QUEUESPERPAGEVFPF7    28
698 #define M_QUEUESPERPAGEVFPF7    0xfU
699 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
700 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
701 
702 #define S_QUEUESPERPAGEVFPF6    24
703 #define M_QUEUESPERPAGEVFPF6    0xfU
704 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
705 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
706 
707 #define S_QUEUESPERPAGEVFPF5    20
708 #define M_QUEUESPERPAGEVFPF5    0xfU
709 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
710 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
711 
712 #define S_QUEUESPERPAGEVFPF4    16
713 #define M_QUEUESPERPAGEVFPF4    0xfU
714 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
715 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
716 
717 #define S_QUEUESPERPAGEVFPF3    12
718 #define M_QUEUESPERPAGEVFPF3    0xfU
719 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
720 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
721 
722 #define S_QUEUESPERPAGEVFPF2    8
723 #define M_QUEUESPERPAGEVFPF2    0xfU
724 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
725 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
726 
727 #define S_QUEUESPERPAGEVFPF1    4
728 #define M_QUEUESPERPAGEVFPF1    0xfU
729 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
730 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
731 
732 #define S_QUEUESPERPAGEVFPF0    0
733 #define M_QUEUESPERPAGEVFPF0    0xfU
734 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
735 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
736 
737 #define A_SGE_USER_MODE_LIMITS 0x1018
738 
739 #define S_OPCODE_MIN    24
740 #define M_OPCODE_MIN    0xffU
741 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
742 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
743 
744 #define S_OPCODE_MAX    16
745 #define M_OPCODE_MAX    0xffU
746 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
747 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
748 
749 #define S_LENGTH_MIN    8
750 #define M_LENGTH_MIN    0xffU
751 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
752 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
753 
754 #define S_LENGTH_MAX    0
755 #define M_LENGTH_MAX    0xffU
756 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
757 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
758 
759 #define A_SGE_WR_ERROR 0x101c
760 
761 #define S_WR_ERROR_OPCODE    0
762 #define M_WR_ERROR_OPCODE    0xffU
763 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
764 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
765 
766 #define A_SGE_INT_CAUSE1 0x1024
767 
768 #define S_PERR_FLM_CREDITFIFO    30
769 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
770 #define F_PERR_FLM_CREDITFIFO    V_PERR_FLM_CREDITFIFO(1U)
771 
772 #define S_PERR_IMSG_HINT_FIFO    29
773 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
774 #define F_PERR_IMSG_HINT_FIFO    V_PERR_IMSG_HINT_FIFO(1U)
775 
776 #define S_PERR_MC_PC    28
777 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
778 #define F_PERR_MC_PC    V_PERR_MC_PC(1U)
779 
780 #define S_PERR_MC_IGR_CTXT    27
781 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
782 #define F_PERR_MC_IGR_CTXT    V_PERR_MC_IGR_CTXT(1U)
783 
784 #define S_PERR_MC_EGR_CTXT    26
785 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
786 #define F_PERR_MC_EGR_CTXT    V_PERR_MC_EGR_CTXT(1U)
787 
788 #define S_PERR_MC_FLM    25
789 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
790 #define F_PERR_MC_FLM    V_PERR_MC_FLM(1U)
791 
792 #define S_PERR_PC_MCTAG    24
793 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
794 #define F_PERR_PC_MCTAG    V_PERR_PC_MCTAG(1U)
795 
796 #define S_PERR_PC_CHPI_RSP1    23
797 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
798 #define F_PERR_PC_CHPI_RSP1    V_PERR_PC_CHPI_RSP1(1U)
799 
800 #define S_PERR_PC_CHPI_RSP0    22
801 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
802 #define F_PERR_PC_CHPI_RSP0    V_PERR_PC_CHPI_RSP0(1U)
803 
804 #define S_PERR_DBP_PC_RSP_FIFO3    21
805 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
806 #define F_PERR_DBP_PC_RSP_FIFO3    V_PERR_DBP_PC_RSP_FIFO3(1U)
807 
808 #define S_PERR_DBP_PC_RSP_FIFO2    20
809 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
810 #define F_PERR_DBP_PC_RSP_FIFO2    V_PERR_DBP_PC_RSP_FIFO2(1U)
811 
812 #define S_PERR_DBP_PC_RSP_FIFO1    19
813 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
814 #define F_PERR_DBP_PC_RSP_FIFO1    V_PERR_DBP_PC_RSP_FIFO1(1U)
815 
816 #define S_PERR_DBP_PC_RSP_FIFO0    18
817 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
818 #define F_PERR_DBP_PC_RSP_FIFO0    V_PERR_DBP_PC_RSP_FIFO0(1U)
819 
820 #define S_PERR_DMARBT    17
821 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
822 #define F_PERR_DMARBT    V_PERR_DMARBT(1U)
823 
824 #define S_PERR_FLM_DBPFIFO    16
825 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
826 #define F_PERR_FLM_DBPFIFO    V_PERR_FLM_DBPFIFO(1U)
827 
828 #define S_PERR_FLM_MCREQ_FIFO    15
829 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
830 #define F_PERR_FLM_MCREQ_FIFO    V_PERR_FLM_MCREQ_FIFO(1U)
831 
832 #define S_PERR_FLM_HINTFIFO    14
833 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
834 #define F_PERR_FLM_HINTFIFO    V_PERR_FLM_HINTFIFO(1U)
835 
836 #define S_PERR_ALIGN_CTL_FIFO3    13
837 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
838 #define F_PERR_ALIGN_CTL_FIFO3    V_PERR_ALIGN_CTL_FIFO3(1U)
839 
840 #define S_PERR_ALIGN_CTL_FIFO2    12
841 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
842 #define F_PERR_ALIGN_CTL_FIFO2    V_PERR_ALIGN_CTL_FIFO2(1U)
843 
844 #define S_PERR_ALIGN_CTL_FIFO1    11
845 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
846 #define F_PERR_ALIGN_CTL_FIFO1    V_PERR_ALIGN_CTL_FIFO1(1U)
847 
848 #define S_PERR_ALIGN_CTL_FIFO0    10
849 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
850 #define F_PERR_ALIGN_CTL_FIFO0    V_PERR_ALIGN_CTL_FIFO0(1U)
851 
852 #define S_PERR_EDMA_FIFO3    9
853 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
854 #define F_PERR_EDMA_FIFO3    V_PERR_EDMA_FIFO3(1U)
855 
856 #define S_PERR_EDMA_FIFO2    8
857 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
858 #define F_PERR_EDMA_FIFO2    V_PERR_EDMA_FIFO2(1U)
859 
860 #define S_PERR_EDMA_FIFO1    7
861 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
862 #define F_PERR_EDMA_FIFO1    V_PERR_EDMA_FIFO1(1U)
863 
864 #define S_PERR_EDMA_FIFO0    6
865 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
866 #define F_PERR_EDMA_FIFO0    V_PERR_EDMA_FIFO0(1U)
867 
868 #define S_PERR_PD_FIFO3    5
869 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
870 #define F_PERR_PD_FIFO3    V_PERR_PD_FIFO3(1U)
871 
872 #define S_PERR_PD_FIFO2    4
873 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
874 #define F_PERR_PD_FIFO2    V_PERR_PD_FIFO2(1U)
875 
876 #define S_PERR_PD_FIFO1    3
877 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
878 #define F_PERR_PD_FIFO1    V_PERR_PD_FIFO1(1U)
879 
880 #define S_PERR_PD_FIFO0    2
881 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
882 #define F_PERR_PD_FIFO0    V_PERR_PD_FIFO0(1U)
883 
884 #define S_PERR_ING_CTXT_MIFRSP    1
885 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
886 #define F_PERR_ING_CTXT_MIFRSP    V_PERR_ING_CTXT_MIFRSP(1U)
887 
888 #define S_PERR_EGR_CTXT_MIFRSP    0
889 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
890 #define F_PERR_EGR_CTXT_MIFRSP    V_PERR_EGR_CTXT_MIFRSP(1U)
891 
892 #define S_PERR_PC_CHPI_RSP2    31
893 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
894 #define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)
895 
896 #define S_PERR_PC_RSP    23
897 #define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
898 #define F_PERR_PC_RSP    V_PERR_PC_RSP(1U)
899 
900 #define S_PERR_PC_REQ    22
901 #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
902 #define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)
903 
904 #define A_SGE_INT_ENABLE1 0x1028
905 #define A_SGE_PERR_ENABLE1 0x102c
906 #define A_SGE_INT_CAUSE2 0x1030
907 
908 #define S_PERR_HINT_DELAY_FIFO1    30
909 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
910 #define F_PERR_HINT_DELAY_FIFO1    V_PERR_HINT_DELAY_FIFO1(1U)
911 
912 #define S_PERR_HINT_DELAY_FIFO0    29
913 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
914 #define F_PERR_HINT_DELAY_FIFO0    V_PERR_HINT_DELAY_FIFO0(1U)
915 
916 #define S_PERR_IMSG_PD_FIFO    28
917 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
918 #define F_PERR_IMSG_PD_FIFO    V_PERR_IMSG_PD_FIFO(1U)
919 
920 #define S_PERR_ULPTX_FIFO1    27
921 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
922 #define F_PERR_ULPTX_FIFO1    V_PERR_ULPTX_FIFO1(1U)
923 
924 #define S_PERR_ULPTX_FIFO0    26
925 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
926 #define F_PERR_ULPTX_FIFO0    V_PERR_ULPTX_FIFO0(1U)
927 
928 #define S_PERR_IDMA2IMSG_FIFO1    25
929 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
930 #define F_PERR_IDMA2IMSG_FIFO1    V_PERR_IDMA2IMSG_FIFO1(1U)
931 
932 #define S_PERR_IDMA2IMSG_FIFO0    24
933 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
934 #define F_PERR_IDMA2IMSG_FIFO0    V_PERR_IDMA2IMSG_FIFO0(1U)
935 
936 #define S_PERR_HEADERSPLIT_FIFO1    23
937 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
938 #define F_PERR_HEADERSPLIT_FIFO1    V_PERR_HEADERSPLIT_FIFO1(1U)
939 
940 #define S_PERR_HEADERSPLIT_FIFO0    22
941 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
942 #define F_PERR_HEADERSPLIT_FIFO0    V_PERR_HEADERSPLIT_FIFO0(1U)
943 
944 #define S_PERR_ESWITCH_FIFO3    21
945 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
946 #define F_PERR_ESWITCH_FIFO3    V_PERR_ESWITCH_FIFO3(1U)
947 
948 #define S_PERR_ESWITCH_FIFO2    20
949 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
950 #define F_PERR_ESWITCH_FIFO2    V_PERR_ESWITCH_FIFO2(1U)
951 
952 #define S_PERR_ESWITCH_FIFO1    19
953 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
954 #define F_PERR_ESWITCH_FIFO1    V_PERR_ESWITCH_FIFO1(1U)
955 
956 #define S_PERR_ESWITCH_FIFO0    18
957 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
958 #define F_PERR_ESWITCH_FIFO0    V_PERR_ESWITCH_FIFO0(1U)
959 
960 #define S_PERR_PC_DBP1    17
961 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
962 #define F_PERR_PC_DBP1    V_PERR_PC_DBP1(1U)
963 
964 #define S_PERR_PC_DBP0    16
965 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
966 #define F_PERR_PC_DBP0    V_PERR_PC_DBP0(1U)
967 
968 #define S_PERR_IMSG_OB_FIFO    15
969 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
970 #define F_PERR_IMSG_OB_FIFO    V_PERR_IMSG_OB_FIFO(1U)
971 
972 #define S_PERR_CONM_SRAM    14
973 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
974 #define F_PERR_CONM_SRAM    V_PERR_CONM_SRAM(1U)
975 
976 #define S_PERR_PC_MC_RSP    13
977 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
978 #define F_PERR_PC_MC_RSP    V_PERR_PC_MC_RSP(1U)
979 
980 #define S_PERR_ISW_IDMA0_FIFO    12
981 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
982 #define F_PERR_ISW_IDMA0_FIFO    V_PERR_ISW_IDMA0_FIFO(1U)
983 
984 #define S_PERR_ISW_IDMA1_FIFO    11
985 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
986 #define F_PERR_ISW_IDMA1_FIFO    V_PERR_ISW_IDMA1_FIFO(1U)
987 
988 #define S_PERR_ISW_DBP_FIFO    10
989 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
990 #define F_PERR_ISW_DBP_FIFO    V_PERR_ISW_DBP_FIFO(1U)
991 
992 #define S_PERR_ISW_GTS_FIFO    9
993 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
994 #define F_PERR_ISW_GTS_FIFO    V_PERR_ISW_GTS_FIFO(1U)
995 
996 #define S_PERR_ITP_EVR    8
997 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
998 #define F_PERR_ITP_EVR    V_PERR_ITP_EVR(1U)
999 
1000 #define S_PERR_FLM_CNTXMEM    7
1001 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
1002 #define F_PERR_FLM_CNTXMEM    V_PERR_FLM_CNTXMEM(1U)
1003 
1004 #define S_PERR_FLM_L1CACHE    6
1005 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
1006 #define F_PERR_FLM_L1CACHE    V_PERR_FLM_L1CACHE(1U)
1007 
1008 #define S_PERR_DBP_HINT_FIFO    5
1009 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
1010 #define F_PERR_DBP_HINT_FIFO    V_PERR_DBP_HINT_FIFO(1U)
1011 
1012 #define S_PERR_DBP_HP_FIFO    4
1013 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
1014 #define F_PERR_DBP_HP_FIFO    V_PERR_DBP_HP_FIFO(1U)
1015 
1016 #define S_PERR_DBP_LP_FIFO    3
1017 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
1018 #define F_PERR_DBP_LP_FIFO    V_PERR_DBP_LP_FIFO(1U)
1019 
1020 #define S_PERR_ING_CTXT_CACHE    2
1021 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
1022 #define F_PERR_ING_CTXT_CACHE    V_PERR_ING_CTXT_CACHE(1U)
1023 
1024 #define S_PERR_EGR_CTXT_CACHE    1
1025 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
1026 #define F_PERR_EGR_CTXT_CACHE    V_PERR_EGR_CTXT_CACHE(1U)
1027 
1028 #define S_PERR_BASE_SIZE    0
1029 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
1030 #define F_PERR_BASE_SIZE    V_PERR_BASE_SIZE(1U)
1031 
1032 #define S_PERR_DBP_HINT_FL_FIFO    24
1033 #define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
1034 #define F_PERR_DBP_HINT_FL_FIFO    V_PERR_DBP_HINT_FL_FIFO(1U)
1035 
1036 #define S_PERR_EGR_DBP_TX_COAL    23
1037 #define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
1038 #define F_PERR_EGR_DBP_TX_COAL    V_PERR_EGR_DBP_TX_COAL(1U)
1039 
1040 #define S_PERR_DBP_FL_FIFO    22
1041 #define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
1042 #define F_PERR_DBP_FL_FIFO    V_PERR_DBP_FL_FIFO(1U)
1043 
1044 #define S_PERR_PC_DBP2    15
1045 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
1046 #define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)
1047 
1048 #define S_DEQ_LL_PERR    21
1049 #define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
1050 #define F_DEQ_LL_PERR    V_DEQ_LL_PERR(1U)
1051 
1052 #define S_ENQ_PERR    20
1053 #define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
1054 #define F_ENQ_PERR    V_ENQ_PERR(1U)
1055 
1056 #define S_DEQ_OUT_PERR    19
1057 #define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
1058 #define F_DEQ_OUT_PERR    V_DEQ_OUT_PERR(1U)
1059 
1060 #define S_BUF_PERR    18
1061 #define V_BUF_PERR(x) ((x) << S_BUF_PERR)
1062 #define F_BUF_PERR    V_BUF_PERR(1U)
1063 
1064 #define S_PERR_DB_FIFO    3
1065 #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
1066 #define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)
1067 
1068 #define A_SGE_INT_ENABLE2 0x1034
1069 #define A_SGE_PERR_ENABLE2 0x1038
1070 #define A_SGE_INT_CAUSE3 0x103c
1071 
1072 #define S_ERR_FLM_DBP    31
1073 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
1074 #define F_ERR_FLM_DBP    V_ERR_FLM_DBP(1U)
1075 
1076 #define S_ERR_FLM_IDMA1    30
1077 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
1078 #define F_ERR_FLM_IDMA1    V_ERR_FLM_IDMA1(1U)
1079 
1080 #define S_ERR_FLM_IDMA0    29
1081 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
1082 #define F_ERR_FLM_IDMA0    V_ERR_FLM_IDMA0(1U)
1083 
1084 #define S_ERR_FLM_HINT    28
1085 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
1086 #define F_ERR_FLM_HINT    V_ERR_FLM_HINT(1U)
1087 
1088 #define S_ERR_PCIE_ERROR3    27
1089 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
1090 #define F_ERR_PCIE_ERROR3    V_ERR_PCIE_ERROR3(1U)
1091 
1092 #define S_ERR_PCIE_ERROR2    26
1093 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
1094 #define F_ERR_PCIE_ERROR2    V_ERR_PCIE_ERROR2(1U)
1095 
1096 #define S_ERR_PCIE_ERROR1    25
1097 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
1098 #define F_ERR_PCIE_ERROR1    V_ERR_PCIE_ERROR1(1U)
1099 
1100 #define S_ERR_PCIE_ERROR0    24
1101 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
1102 #define F_ERR_PCIE_ERROR0    V_ERR_PCIE_ERROR0(1U)
1103 
1104 #define S_ERR_TIMER_ABOVE_MAX_QID    23
1105 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
1106 #define F_ERR_TIMER_ABOVE_MAX_QID    V_ERR_TIMER_ABOVE_MAX_QID(1U)
1107 
1108 #define S_ERR_CPL_EXCEED_IQE_SIZE    22
1109 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
1110 #define F_ERR_CPL_EXCEED_IQE_SIZE    V_ERR_CPL_EXCEED_IQE_SIZE(1U)
1111 
1112 #define S_ERR_INVALID_CIDX_INC    21
1113 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
1114 #define F_ERR_INVALID_CIDX_INC    V_ERR_INVALID_CIDX_INC(1U)
1115 
1116 #define S_ERR_ITP_TIME_PAUSED    20
1117 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
1118 #define F_ERR_ITP_TIME_PAUSED    V_ERR_ITP_TIME_PAUSED(1U)
1119 
1120 #define S_ERR_CPL_OPCODE_0    19
1121 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
1122 #define F_ERR_CPL_OPCODE_0    V_ERR_CPL_OPCODE_0(1U)
1123 
1124 #define S_ERR_DROPPED_DB    18
1125 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
1126 #define F_ERR_DROPPED_DB    V_ERR_DROPPED_DB(1U)
1127 
1128 #define S_ERR_DATA_CPL_ON_HIGH_QID1    17
1129 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
1130 #define F_ERR_DATA_CPL_ON_HIGH_QID1    V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
1131 
1132 #define S_ERR_DATA_CPL_ON_HIGH_QID0    16
1133 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
1134 #define F_ERR_DATA_CPL_ON_HIGH_QID0    V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
1135 
1136 #define S_ERR_BAD_DB_PIDX3    15
1137 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
1138 #define F_ERR_BAD_DB_PIDX3    V_ERR_BAD_DB_PIDX3(1U)
1139 
1140 #define S_ERR_BAD_DB_PIDX2    14
1141 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
1142 #define F_ERR_BAD_DB_PIDX2    V_ERR_BAD_DB_PIDX2(1U)
1143 
1144 #define S_ERR_BAD_DB_PIDX1    13
1145 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
1146 #define F_ERR_BAD_DB_PIDX1    V_ERR_BAD_DB_PIDX1(1U)
1147 
1148 #define S_ERR_BAD_DB_PIDX0    12
1149 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
1150 #define F_ERR_BAD_DB_PIDX0    V_ERR_BAD_DB_PIDX0(1U)
1151 
1152 #define S_ERR_ING_PCIE_CHAN    11
1153 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
1154 #define F_ERR_ING_PCIE_CHAN    V_ERR_ING_PCIE_CHAN(1U)
1155 
1156 #define S_ERR_ING_CTXT_PRIO    10
1157 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
1158 #define F_ERR_ING_CTXT_PRIO    V_ERR_ING_CTXT_PRIO(1U)
1159 
1160 #define S_ERR_EGR_CTXT_PRIO    9
1161 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
1162 #define F_ERR_EGR_CTXT_PRIO    V_ERR_EGR_CTXT_PRIO(1U)
1163 
1164 #define S_DBFIFO_HP_INT    8
1165 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
1166 #define F_DBFIFO_HP_INT    V_DBFIFO_HP_INT(1U)
1167 
1168 #define S_DBFIFO_LP_INT    7
1169 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
1170 #define F_DBFIFO_LP_INT    V_DBFIFO_LP_INT(1U)
1171 
1172 #define S_REG_ADDRESS_ERR    6
1173 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
1174 #define F_REG_ADDRESS_ERR    V_REG_ADDRESS_ERR(1U)
1175 
1176 #define S_INGRESS_SIZE_ERR    5
1177 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
1178 #define F_INGRESS_SIZE_ERR    V_INGRESS_SIZE_ERR(1U)
1179 
1180 #define S_EGRESS_SIZE_ERR    4
1181 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
1182 #define F_EGRESS_SIZE_ERR    V_EGRESS_SIZE_ERR(1U)
1183 
1184 #define S_ERR_INV_CTXT3    3
1185 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
1186 #define F_ERR_INV_CTXT3    V_ERR_INV_CTXT3(1U)
1187 
1188 #define S_ERR_INV_CTXT2    2
1189 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
1190 #define F_ERR_INV_CTXT2    V_ERR_INV_CTXT2(1U)
1191 
1192 #define S_ERR_INV_CTXT1    1
1193 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
1194 #define F_ERR_INV_CTXT1    V_ERR_INV_CTXT1(1U)
1195 
1196 #define S_ERR_INV_CTXT0    0
1197 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
1198 #define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)
1199 
1200 #define S_DBP_TBUF_FULL    8
1201 #define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
1202 #define F_DBP_TBUF_FULL    V_DBP_TBUF_FULL(1U)
1203 
1204 #define S_FATAL_WRE_LEN    7
1205 #define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
1206 #define F_FATAL_WRE_LEN    V_FATAL_WRE_LEN(1U)
1207 
1208 #define A_SGE_INT_ENABLE3 0x1040
1209 #define A_SGE_FL_BUFFER_SIZE0 0x1044
1210 
1211 #define S_SIZE    4
1212 #define M_SIZE    0xfffffffU
1213 #define V_SIZE(x) ((x) << S_SIZE)
1214 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1215 
1216 #define S_T6_SIZE    4
1217 #define M_T6_SIZE    0xfffffU
1218 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1219 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1220 
1221 #define A_SGE_FL_BUFFER_SIZE1 0x1048
1222 
1223 #define S_T6_SIZE    4
1224 #define M_T6_SIZE    0xfffffU
1225 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1226 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1227 
1228 #define A_SGE_FL_BUFFER_SIZE2 0x104c
1229 
1230 #define S_T6_SIZE    4
1231 #define M_T6_SIZE    0xfffffU
1232 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1233 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1234 
1235 #define A_SGE_FL_BUFFER_SIZE3 0x1050
1236 
1237 #define S_T6_SIZE    4
1238 #define M_T6_SIZE    0xfffffU
1239 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1240 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1241 
1242 #define A_SGE_FL_BUFFER_SIZE4 0x1054
1243 
1244 #define S_T6_SIZE    4
1245 #define M_T6_SIZE    0xfffffU
1246 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1247 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1248 
1249 #define A_SGE_FL_BUFFER_SIZE5 0x1058
1250 
1251 #define S_T6_SIZE    4
1252 #define M_T6_SIZE    0xfffffU
1253 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1254 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1255 
1256 #define A_SGE_FL_BUFFER_SIZE6 0x105c
1257 
1258 #define S_T6_SIZE    4
1259 #define M_T6_SIZE    0xfffffU
1260 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1261 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1262 
1263 #define A_SGE_FL_BUFFER_SIZE7 0x1060
1264 
1265 #define S_T6_SIZE    4
1266 #define M_T6_SIZE    0xfffffU
1267 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1268 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1269 
1270 #define A_SGE_FL_BUFFER_SIZE8 0x1064
1271 
1272 #define S_T6_SIZE    4
1273 #define M_T6_SIZE    0xfffffU
1274 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1275 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1276 
1277 #define A_SGE_FL_BUFFER_SIZE9 0x1068
1278 
1279 #define S_T6_SIZE    4
1280 #define M_T6_SIZE    0xfffffU
1281 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1282 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1283 
1284 #define A_SGE_FL_BUFFER_SIZE10 0x106c
1285 
1286 #define S_T6_SIZE    4
1287 #define M_T6_SIZE    0xfffffU
1288 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1289 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1290 
1291 #define A_SGE_FL_BUFFER_SIZE11 0x1070
1292 
1293 #define S_T6_SIZE    4
1294 #define M_T6_SIZE    0xfffffU
1295 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1296 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1297 
1298 #define A_SGE_FL_BUFFER_SIZE12 0x1074
1299 
1300 #define S_T6_SIZE    4
1301 #define M_T6_SIZE    0xfffffU
1302 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1303 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1304 
1305 #define A_SGE_FL_BUFFER_SIZE13 0x1078
1306 
1307 #define S_T6_SIZE    4
1308 #define M_T6_SIZE    0xfffffU
1309 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1310 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1311 
1312 #define A_SGE_FL_BUFFER_SIZE14 0x107c
1313 
1314 #define S_T6_SIZE    4
1315 #define M_T6_SIZE    0xfffffU
1316 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1317 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1318 
1319 #define A_SGE_FL_BUFFER_SIZE15 0x1080
1320 
1321 #define S_T6_SIZE    4
1322 #define M_T6_SIZE    0xfffffU
1323 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1324 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1325 
1326 #define A_SGE_DBQ_CTXT_BADDR 0x1084
1327 
1328 #define S_BASEADDR    3
1329 #define M_BASEADDR    0x1fffffffU
1330 #define V_BASEADDR(x) ((x) << S_BASEADDR)
1331 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
1332 
1333 #define A_SGE_IMSG_CTXT_BADDR 0x1088
1334 #define A_SGE_FLM_CACHE_BADDR 0x108c
1335 #define A_SGE_FLM_CFG 0x1090
1336 
1337 #define S_OPMODE    26
1338 #define M_OPMODE    0x3fU
1339 #define V_OPMODE(x) ((x) << S_OPMODE)
1340 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
1341 
1342 #define S_NULLPTR    20
1343 #define M_NULLPTR    0xfU
1344 #define V_NULLPTR(x) ((x) << S_NULLPTR)
1345 #define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
1346 
1347 #define S_NULLPTREN    19
1348 #define V_NULLPTREN(x) ((x) << S_NULLPTREN)
1349 #define F_NULLPTREN    V_NULLPTREN(1U)
1350 
1351 #define S_NOHDR    18
1352 #define V_NOHDR(x) ((x) << S_NOHDR)
1353 #define F_NOHDR    V_NOHDR(1U)
1354 
1355 #define S_CACHEPTRCNT    16
1356 #define M_CACHEPTRCNT    0x3U
1357 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
1358 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
1359 
1360 #define S_EDRAMPTRCNT    14
1361 #define M_EDRAMPTRCNT    0x3U
1362 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
1363 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
1364 
1365 #define S_HDRSTARTFLQ    11
1366 #define M_HDRSTARTFLQ    0x7U
1367 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
1368 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
1369 
1370 #define S_FETCHTHRESH    6
1371 #define M_FETCHTHRESH    0x1fU
1372 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
1373 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
1374 
1375 #define S_CREDITCNT    4
1376 #define M_CREDITCNT    0x3U
1377 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
1378 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
1379 
1380 #define S_CREDITCNTPACKING    2
1381 #define M_CREDITCNTPACKING    0x3U
1382 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
1383 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
1384 
1385 #define S_NOEDRAM    0
1386 #define V_NOEDRAM(x) ((x) << S_NOEDRAM)
1387 #define F_NOEDRAM    V_NOEDRAM(1U)
1388 
1389 #define A_SGE_CONM_CTRL 0x1094
1390 
1391 #define S_EGRTHRESHOLD    8
1392 #define M_EGRTHRESHOLD    0x3fU
1393 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1394 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1395 
1396 #define S_EGRTHRESHOLDPACKING    14
1397 #define M_EGRTHRESHOLDPACKING    0x3fU
1398 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
1399 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
1400 
1401 #define S_T6_EGRTHRESHOLDPACKING    16
1402 #define M_T6_EGRTHRESHOLDPACKING    0xffU
1403 #define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
1404 #define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
1405 
1406 #define S_T6_EGRTHRESHOLD    8
1407 #define M_T6_EGRTHRESHOLD    0xffU
1408 #define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
1409 #define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
1410 
1411 #define S_INGTHRESHOLD    2
1412 #define M_INGTHRESHOLD    0x3fU
1413 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1414 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1415 
1416 #define A_SGE_TIMESTAMP_LO 0x1098
1417 #define A_SGE_TIMESTAMP_HI 0x109c
1418 
1419 #define S_TSOP    28
1420 #define M_TSOP    0x3U
1421 #define V_TSOP(x) ((x) << S_TSOP)
1422 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1423 
1424 #define S_TSVAL    0
1425 #define M_TSVAL    0xfffffffU
1426 #define V_TSVAL(x) ((x) << S_TSVAL)
1427 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1428 
1429 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1430 
1431 #define S_THRESHOLD_0    24
1432 #define M_THRESHOLD_0    0x3fU
1433 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1434 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1435 
1436 #define S_THRESHOLD_1    16
1437 #define M_THRESHOLD_1    0x3fU
1438 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1439 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1440 
1441 #define S_THRESHOLD_2    8
1442 #define M_THRESHOLD_2    0x3fU
1443 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1444 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1445 
1446 #define S_THRESHOLD_3    0
1447 #define M_THRESHOLD_3    0x3fU
1448 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1449 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1450 
1451 #define A_SGE_DBFIFO_STATUS 0x10a4
1452 
1453 #define S_HP_INT_THRESH    28
1454 #define M_HP_INT_THRESH    0xfU
1455 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1456 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1457 
1458 #define S_HP_COUNT    16
1459 #define M_HP_COUNT    0x7ffU
1460 #define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1461 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1462 
1463 #define S_LP_INT_THRESH    12
1464 #define M_LP_INT_THRESH    0xfU
1465 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1466 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1467 
1468 #define S_LP_COUNT    0
1469 #define M_LP_COUNT    0x7ffU
1470 #define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1471 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1472 
1473 #define S_BAR2VALID    31
1474 #define V_BAR2VALID(x) ((x) << S_BAR2VALID)
1475 #define F_BAR2VALID    V_BAR2VALID(1U)
1476 
1477 #define S_BAR2FULL    30
1478 #define V_BAR2FULL(x) ((x) << S_BAR2FULL)
1479 #define F_BAR2FULL    V_BAR2FULL(1U)
1480 
1481 #define S_LP_INT_THRESH_T5    18
1482 #define M_LP_INT_THRESH_T5    0xfffU
1483 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
1484 #define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
1485 
1486 #define S_LP_COUNT_T5    0
1487 #define M_LP_COUNT_T5    0x3ffffU
1488 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
1489 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
1490 
1491 #define S_VFIFO_CNT    15
1492 #define M_VFIFO_CNT    0x1ffffU
1493 #define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
1494 #define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
1495 
1496 #define S_COAL_CTL_FIFO_CNT    8
1497 #define M_COAL_CTL_FIFO_CNT    0x3fU
1498 #define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
1499 #define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
1500 
1501 #define S_MERGE_FIFO_CNT    0
1502 #define M_MERGE_FIFO_CNT    0x3fU
1503 #define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
1504 #define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
1505 
1506 #define A_SGE_DOORBELL_CONTROL 0x10a8
1507 
1508 #define S_HINTDEPTHCTL    27
1509 #define M_HINTDEPTHCTL    0x1fU
1510 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1511 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1512 
1513 #define S_NOCOALESCE    26
1514 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1515 #define F_NOCOALESCE    V_NOCOALESCE(1U)
1516 
1517 #define S_HP_WEIGHT    24
1518 #define M_HP_WEIGHT    0x3U
1519 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1520 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1521 
1522 #define S_HP_DISABLE    23
1523 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1524 #define F_HP_DISABLE    V_HP_DISABLE(1U)
1525 
1526 #define S_FORCEUSERDBTOLP    22
1527 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1528 #define F_FORCEUSERDBTOLP    V_FORCEUSERDBTOLP(1U)
1529 
1530 #define S_FORCEVFPF0DBTOLP    21
1531 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1532 #define F_FORCEVFPF0DBTOLP    V_FORCEVFPF0DBTOLP(1U)
1533 
1534 #define S_FORCEVFPF1DBTOLP    20
1535 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1536 #define F_FORCEVFPF1DBTOLP    V_FORCEVFPF1DBTOLP(1U)
1537 
1538 #define S_FORCEVFPF2DBTOLP    19
1539 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1540 #define F_FORCEVFPF2DBTOLP    V_FORCEVFPF2DBTOLP(1U)
1541 
1542 #define S_FORCEVFPF3DBTOLP    18
1543 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1544 #define F_FORCEVFPF3DBTOLP    V_FORCEVFPF3DBTOLP(1U)
1545 
1546 #define S_FORCEVFPF4DBTOLP    17
1547 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1548 #define F_FORCEVFPF4DBTOLP    V_FORCEVFPF4DBTOLP(1U)
1549 
1550 #define S_FORCEVFPF5DBTOLP    16
1551 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1552 #define F_FORCEVFPF5DBTOLP    V_FORCEVFPF5DBTOLP(1U)
1553 
1554 #define S_FORCEVFPF6DBTOLP    15
1555 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1556 #define F_FORCEVFPF6DBTOLP    V_FORCEVFPF6DBTOLP(1U)
1557 
1558 #define S_FORCEVFPF7DBTOLP    14
1559 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1560 #define F_FORCEVFPF7DBTOLP    V_FORCEVFPF7DBTOLP(1U)
1561 
1562 #define S_ENABLE_DROP    13
1563 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1564 #define F_ENABLE_DROP    V_ENABLE_DROP(1U)
1565 
1566 #define S_DROP_TIMEOUT    1
1567 #define M_DROP_TIMEOUT    0xfffU
1568 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1569 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1570 
1571 #define S_DROPPED_DB    0
1572 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1573 #define F_DROPPED_DB    V_DROPPED_DB(1U)
1574 
1575 #define S_T6_DROP_TIMEOUT    7
1576 #define M_T6_DROP_TIMEOUT    0x3fU
1577 #define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
1578 #define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
1579 
1580 #define S_INVONDBSYNC    6
1581 #define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
1582 #define F_INVONDBSYNC    V_INVONDBSYNC(1U)
1583 
1584 #define S_INVONGTSSYNC    5
1585 #define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
1586 #define F_INVONGTSSYNC    V_INVONGTSSYNC(1U)
1587 
1588 #define S_DB_DBG_EN    4
1589 #define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
1590 #define F_DB_DBG_EN    V_DB_DBG_EN(1U)
1591 
1592 #define S_GTS_DBG_TIMER_REG    1
1593 #define M_GTS_DBG_TIMER_REG    0x7U
1594 #define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
1595 #define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
1596 
1597 #define S_GTS_DBG_EN    0
1598 #define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
1599 #define F_GTS_DBG_EN    V_GTS_DBG_EN(1U)
1600 
1601 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1602 
1603 #define S_BAR2THROTTLECOUNT    16
1604 #define M_BAR2THROTTLECOUNT    0xffU
1605 #define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
1606 #define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
1607 
1608 #define S_CLRCOALESCEDISABLE    15
1609 #define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
1610 #define F_CLRCOALESCEDISABLE    V_CLRCOALESCEDISABLE(1U)
1611 
1612 #define S_OPENBAR2GATEONCE    14
1613 #define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
1614 #define F_OPENBAR2GATEONCE    V_OPENBAR2GATEONCE(1U)
1615 
1616 #define S_FORCEOPENBAR2GATE    13
1617 #define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
1618 #define F_FORCEOPENBAR2GATE    V_FORCEOPENBAR2GATE(1U)
1619 
1620 #define A_SGE_ITP_CONTROL 0x10b4
1621 
1622 #define S_TSCALE    28
1623 #define M_TSCALE    0xfU
1624 #define V_TSCALE(x) ((x) << S_TSCALE)
1625 #define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
1626 
1627 #define S_CRITICAL_TIME    10
1628 #define M_CRITICAL_TIME    0x7fffU
1629 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1630 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1631 
1632 #define S_LL_EMPTY    4
1633 #define M_LL_EMPTY    0x3fU
1634 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1635 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1636 
1637 #define S_LL_READ_WAIT_DISABLE    0
1638 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1639 #define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)
1640 
1641 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1642 
1643 #define S_TIMERVALUE0    16
1644 #define M_TIMERVALUE0    0xffffU
1645 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1646 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1647 
1648 #define S_TIMERVALUE1    0
1649 #define M_TIMERVALUE1    0xffffU
1650 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1651 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1652 
1653 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1654 
1655 #define S_TIMERVALUE2    16
1656 #define M_TIMERVALUE2    0xffffU
1657 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1658 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1659 
1660 #define S_TIMERVALUE3    0
1661 #define M_TIMERVALUE3    0xffffU
1662 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1663 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1664 
1665 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1666 
1667 #define S_TIMERVALUE4    16
1668 #define M_TIMERVALUE4    0xffffU
1669 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1670 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1671 
1672 #define S_TIMERVALUE5    0
1673 #define M_TIMERVALUE5    0xffffU
1674 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1675 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1676 
1677 #define A_SGE_GK_CONTROL 0x10c4
1678 
1679 #define S_EN_FLM_FIFTH    29
1680 #define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
1681 #define F_EN_FLM_FIFTH    V_EN_FLM_FIFTH(1U)
1682 
1683 #define S_FL_PROG_THRESH    20
1684 #define M_FL_PROG_THRESH    0x1ffU
1685 #define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
1686 #define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
1687 
1688 #define S_COAL_ALL_THREAD    19
1689 #define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
1690 #define F_COAL_ALL_THREAD    V_COAL_ALL_THREAD(1U)
1691 
1692 #define S_EN_PSHB    18
1693 #define V_EN_PSHB(x) ((x) << S_EN_PSHB)
1694 #define F_EN_PSHB    V_EN_PSHB(1U)
1695 
1696 #define S_EN_DB_FIFTH    17
1697 #define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
1698 #define F_EN_DB_FIFTH    V_EN_DB_FIFTH(1U)
1699 
1700 #define S_DB_PROG_THRESH    8
1701 #define M_DB_PROG_THRESH    0x1ffU
1702 #define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
1703 #define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
1704 
1705 #define S_100NS_TIMER    0
1706 #define M_100NS_TIMER    0xffU
1707 #define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
1708 #define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
1709 
1710 #define A_SGE_GK_CONTROL2 0x10c8
1711 
1712 #define S_DBQ_TIMER_TICK    16
1713 #define M_DBQ_TIMER_TICK    0xffffU
1714 #define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
1715 #define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
1716 
1717 #define S_FL_MERGE_CNT_THRESH    8
1718 #define M_FL_MERGE_CNT_THRESH    0xfU
1719 #define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
1720 #define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
1721 
1722 #define S_MERGE_CNT_THRESH    0
1723 #define M_MERGE_CNT_THRESH    0x3fU
1724 #define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
1725 #define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
1726 
1727 #define A_SGE_DEBUG_INDEX 0x10cc
1728 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1729 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1730 #define A_SGE_INT_CAUSE4 0x10dc
1731 
1732 #define S_ERR_BAD_UPFL_INC_CREDIT3    8
1733 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1734 #define F_ERR_BAD_UPFL_INC_CREDIT3    V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1735 
1736 #define S_ERR_BAD_UPFL_INC_CREDIT2    7
1737 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1738 #define F_ERR_BAD_UPFL_INC_CREDIT2    V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1739 
1740 #define S_ERR_BAD_UPFL_INC_CREDIT1    6
1741 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1742 #define F_ERR_BAD_UPFL_INC_CREDIT1    V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1743 
1744 #define S_ERR_BAD_UPFL_INC_CREDIT0    5
1745 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1746 #define F_ERR_BAD_UPFL_INC_CREDIT0    V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1747 
1748 #define S_ERR_PHYSADDR_LEN0_IDMA1    4
1749 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
1750 #define F_ERR_PHYSADDR_LEN0_IDMA1    V_ERR_PHYSADDR_LEN0_IDMA1(1U)
1751 
1752 #define S_ERR_PHYSADDR_LEN0_IDMA0    3
1753 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
1754 #define F_ERR_PHYSADDR_LEN0_IDMA0    V_ERR_PHYSADDR_LEN0_IDMA0(1U)
1755 
1756 #define S_ERR_FLM_INVALID_PKT_DROP1    2
1757 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
1758 #define F_ERR_FLM_INVALID_PKT_DROP1    V_ERR_FLM_INVALID_PKT_DROP1(1U)
1759 
1760 #define S_ERR_FLM_INVALID_PKT_DROP0    1
1761 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
1762 #define F_ERR_FLM_INVALID_PKT_DROP0    V_ERR_FLM_INVALID_PKT_DROP0(1U)
1763 
1764 #define S_ERR_UNEXPECTED_TIMER    0
1765 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
1766 #define F_ERR_UNEXPECTED_TIMER    V_ERR_UNEXPECTED_TIMER(1U)
1767 
1768 #define S_BAR2_EGRESS_LEN_OR_ADDR_ERR    29
1769 #define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
1770 #define F_BAR2_EGRESS_LEN_OR_ADDR_ERR    V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
1771 
1772 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1    28
1773 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
1774 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1    V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
1775 
1776 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0    27
1777 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
1778 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0    V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
1779 
1780 #define S_ERR_WR_LEN_TOO_LARGE3    26
1781 #define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
1782 #define F_ERR_WR_LEN_TOO_LARGE3    V_ERR_WR_LEN_TOO_LARGE3(1U)
1783 
1784 #define S_ERR_WR_LEN_TOO_LARGE2    25
1785 #define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
1786 #define F_ERR_WR_LEN_TOO_LARGE2    V_ERR_WR_LEN_TOO_LARGE2(1U)
1787 
1788 #define S_ERR_WR_LEN_TOO_LARGE1    24
1789 #define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
1790 #define F_ERR_WR_LEN_TOO_LARGE1    V_ERR_WR_LEN_TOO_LARGE1(1U)
1791 
1792 #define S_ERR_WR_LEN_TOO_LARGE0    23
1793 #define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
1794 #define F_ERR_WR_LEN_TOO_LARGE0    V_ERR_WR_LEN_TOO_LARGE0(1U)
1795 
1796 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3    22
1797 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
1798 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3    V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
1799 
1800 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2    21
1801 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
1802 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2    V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
1803 
1804 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1    20
1805 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
1806 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1    V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
1807 
1808 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0    19
1809 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
1810 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0    V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
1811 
1812 #define S_COAL_WITH_HP_DISABLE_ERR    18
1813 #define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
1814 #define F_COAL_WITH_HP_DISABLE_ERR    V_COAL_WITH_HP_DISABLE_ERR(1U)
1815 
1816 #define S_BAR2_EGRESS_COAL0_ERR    17
1817 #define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
1818 #define F_BAR2_EGRESS_COAL0_ERR    V_BAR2_EGRESS_COAL0_ERR(1U)
1819 
1820 #define S_BAR2_EGRESS_SIZE_ERR    16
1821 #define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
1822 #define F_BAR2_EGRESS_SIZE_ERR    V_BAR2_EGRESS_SIZE_ERR(1U)
1823 
1824 #define S_FLM_PC_RSP_ERR    15
1825 #define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
1826 #define F_FLM_PC_RSP_ERR    V_FLM_PC_RSP_ERR(1U)
1827 
1828 #define S_DBFIFO_HP_INT_LOW    14
1829 #define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
1830 #define F_DBFIFO_HP_INT_LOW    V_DBFIFO_HP_INT_LOW(1U)
1831 
1832 #define S_DBFIFO_LP_INT_LOW    13
1833 #define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
1834 #define F_DBFIFO_LP_INT_LOW    V_DBFIFO_LP_INT_LOW(1U)
1835 
1836 #define S_DBFIFO_FL_INT_LOW    12
1837 #define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
1838 #define F_DBFIFO_FL_INT_LOW    V_DBFIFO_FL_INT_LOW(1U)
1839 
1840 #define S_DBFIFO_FL_INT    11
1841 #define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
1842 #define F_DBFIFO_FL_INT    V_DBFIFO_FL_INT(1U)
1843 
1844 #define S_ERR_RX_CPL_PACKET_SIZE1    10
1845 #define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
1846 #define F_ERR_RX_CPL_PACKET_SIZE1    V_ERR_RX_CPL_PACKET_SIZE1(1U)
1847 
1848 #define S_ERR_RX_CPL_PACKET_SIZE0    9
1849 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
1850 #define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)
1851 
1852 #define S_ERR_ISHIFT_UR1    31
1853 #define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
1854 #define F_ERR_ISHIFT_UR1    V_ERR_ISHIFT_UR1(1U)
1855 
1856 #define S_ERR_ISHIFT_UR0    30
1857 #define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
1858 #define F_ERR_ISHIFT_UR0    V_ERR_ISHIFT_UR0(1U)
1859 
1860 #define S_ERR_TH3_MAX_FETCH    14
1861 #define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
1862 #define F_ERR_TH3_MAX_FETCH    V_ERR_TH3_MAX_FETCH(1U)
1863 
1864 #define S_ERR_TH2_MAX_FETCH    13
1865 #define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
1866 #define F_ERR_TH2_MAX_FETCH    V_ERR_TH2_MAX_FETCH(1U)
1867 
1868 #define S_ERR_TH1_MAX_FETCH    12
1869 #define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
1870 #define F_ERR_TH1_MAX_FETCH    V_ERR_TH1_MAX_FETCH(1U)
1871 
1872 #define S_ERR_TH0_MAX_FETCH    11
1873 #define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
1874 #define F_ERR_TH0_MAX_FETCH    V_ERR_TH0_MAX_FETCH(1U)
1875 
1876 #define A_SGE_INT_ENABLE4 0x10e0
1877 #define A_SGE_STAT_TOTAL 0x10e4
1878 #define A_SGE_STAT_MATCH 0x10e8
1879 #define A_SGE_STAT_CFG 0x10ec
1880 
1881 #define S_STATMODE    2
1882 #define M_STATMODE    0x3U
1883 #define V_STATMODE(x) ((x) << S_STATMODE)
1884 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
1885 
1886 #define S_STATSOURCE    0
1887 #define M_STATSOURCE    0x3U
1888 #define V_STATSOURCE(x) ((x) << S_STATSOURCE)
1889 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
1890 
1891 #define S_STATSOURCE_T5    9
1892 #define M_STATSOURCE_T5    0xfU
1893 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
1894 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
1895 
1896 #define S_ITPOPMODE    8
1897 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
1898 #define F_ITPOPMODE    V_ITPOPMODE(1U)
1899 
1900 #define S_EGRCTXTOPMODE    6
1901 #define M_EGRCTXTOPMODE    0x3U
1902 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
1903 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
1904 
1905 #define S_INGCTXTOPMODE    4
1906 #define M_INGCTXTOPMODE    0x3U
1907 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
1908 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
1909 
1910 #define S_T6_STATMODE    0
1911 #define M_T6_STATMODE    0xfU
1912 #define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
1913 #define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
1914 
1915 #define A_SGE_HINT_CFG 0x10f0
1916 
1917 #define S_UPCUTOFFTHRESHLP    12
1918 #define M_UPCUTOFFTHRESHLP    0x7ffU
1919 #define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
1920 #define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
1921 
1922 #define S_HINTSALLOWEDNOHDR    6
1923 #define M_HINTSALLOWEDNOHDR    0x3fU
1924 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
1925 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
1926 
1927 #define S_HINTSALLOWEDHDR    0
1928 #define M_HINTSALLOWEDHDR    0x3fU
1929 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
1930 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
1931 
1932 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
1933 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
1934 #define A_SGE_ERROR_STATS 0x1100
1935 
1936 #define S_UNCAPTURED_ERROR    18
1937 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
1938 #define F_UNCAPTURED_ERROR    V_UNCAPTURED_ERROR(1U)
1939 
1940 #define S_ERROR_QID_VALID    17
1941 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
1942 #define F_ERROR_QID_VALID    V_ERROR_QID_VALID(1U)
1943 
1944 #define S_ERROR_QID    0
1945 #define M_ERROR_QID    0x1ffffU
1946 #define V_ERROR_QID(x) ((x) << S_ERROR_QID)
1947 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
1948 
1949 #define S_CAUSE_REGISTER    24
1950 #define M_CAUSE_REGISTER    0x7U
1951 #define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
1952 #define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
1953 
1954 #define S_CAUSE_BIT    19
1955 #define M_CAUSE_BIT    0x1fU
1956 #define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
1957 #define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
1958 
1959 #define A_SGE_IDMA0_DROP_CNT 0x1104
1960 #define A_SGE_IDMA1_DROP_CNT 0x1108
1961 #define A_SGE_INT_CAUSE5 0x110c
1962 
1963 #define S_ERR_T_RXCRC    31
1964 #define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
1965 #define F_ERR_T_RXCRC    V_ERR_T_RXCRC(1U)
1966 
1967 #define S_PERR_MC_RSPDATA    30
1968 #define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
1969 #define F_PERR_MC_RSPDATA    V_PERR_MC_RSPDATA(1U)
1970 
1971 #define S_PERR_PC_RSPDATA    29
1972 #define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
1973 #define F_PERR_PC_RSPDATA    V_PERR_PC_RSPDATA(1U)
1974 
1975 #define S_PERR_PD_RDRSPDATA    28
1976 #define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
1977 #define F_PERR_PD_RDRSPDATA    V_PERR_PD_RDRSPDATA(1U)
1978 
1979 #define S_PERR_U_RXDATA    27
1980 #define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
1981 #define F_PERR_U_RXDATA    V_PERR_U_RXDATA(1U)
1982 
1983 #define S_PERR_UD_RXDATA    26
1984 #define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
1985 #define F_PERR_UD_RXDATA    V_PERR_UD_RXDATA(1U)
1986 
1987 #define S_PERR_UP_DATA    25
1988 #define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
1989 #define F_PERR_UP_DATA    V_PERR_UP_DATA(1U)
1990 
1991 #define S_PERR_CIM2SGE_RXDATA    24
1992 #define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
1993 #define F_PERR_CIM2SGE_RXDATA    V_PERR_CIM2SGE_RXDATA(1U)
1994 
1995 #define S_PERR_HINT_DELAY_FIFO1_T5    23
1996 #define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
1997 #define F_PERR_HINT_DELAY_FIFO1_T5    V_PERR_HINT_DELAY_FIFO1_T5(1U)
1998 
1999 #define S_PERR_HINT_DELAY_FIFO0_T5    22
2000 #define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
2001 #define F_PERR_HINT_DELAY_FIFO0_T5    V_PERR_HINT_DELAY_FIFO0_T5(1U)
2002 
2003 #define S_PERR_IMSG_PD_FIFO_T5    21
2004 #define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
2005 #define F_PERR_IMSG_PD_FIFO_T5    V_PERR_IMSG_PD_FIFO_T5(1U)
2006 
2007 #define S_PERR_ULPTX_FIFO1_T5    20
2008 #define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
2009 #define F_PERR_ULPTX_FIFO1_T5    V_PERR_ULPTX_FIFO1_T5(1U)
2010 
2011 #define S_PERR_ULPTX_FIFO0_T5    19
2012 #define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
2013 #define F_PERR_ULPTX_FIFO0_T5    V_PERR_ULPTX_FIFO0_T5(1U)
2014 
2015 #define S_PERR_IDMA2IMSG_FIFO1_T5    18
2016 #define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
2017 #define F_PERR_IDMA2IMSG_FIFO1_T5    V_PERR_IDMA2IMSG_FIFO1_T5(1U)
2018 
2019 #define S_PERR_IDMA2IMSG_FIFO0_T5    17
2020 #define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
2021 #define F_PERR_IDMA2IMSG_FIFO0_T5    V_PERR_IDMA2IMSG_FIFO0_T5(1U)
2022 
2023 #define S_PERR_POINTER_DATA_FIFO0    16
2024 #define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
2025 #define F_PERR_POINTER_DATA_FIFO0    V_PERR_POINTER_DATA_FIFO0(1U)
2026 
2027 #define S_PERR_POINTER_DATA_FIFO1    15
2028 #define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
2029 #define F_PERR_POINTER_DATA_FIFO1    V_PERR_POINTER_DATA_FIFO1(1U)
2030 
2031 #define S_PERR_POINTER_HDR_FIFO0    14
2032 #define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
2033 #define F_PERR_POINTER_HDR_FIFO0    V_PERR_POINTER_HDR_FIFO0(1U)
2034 
2035 #define S_PERR_POINTER_HDR_FIFO1    13
2036 #define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
2037 #define F_PERR_POINTER_HDR_FIFO1    V_PERR_POINTER_HDR_FIFO1(1U)
2038 
2039 #define S_PERR_PAYLOAD_FIFO0    12
2040 #define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
2041 #define F_PERR_PAYLOAD_FIFO0    V_PERR_PAYLOAD_FIFO0(1U)
2042 
2043 #define S_PERR_PAYLOAD_FIFO1    11
2044 #define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
2045 #define F_PERR_PAYLOAD_FIFO1    V_PERR_PAYLOAD_FIFO1(1U)
2046 
2047 #define S_PERR_EDMA_INPUT_FIFO3    10
2048 #define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
2049 #define F_PERR_EDMA_INPUT_FIFO3    V_PERR_EDMA_INPUT_FIFO3(1U)
2050 
2051 #define S_PERR_EDMA_INPUT_FIFO2    9
2052 #define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
2053 #define F_PERR_EDMA_INPUT_FIFO2    V_PERR_EDMA_INPUT_FIFO2(1U)
2054 
2055 #define S_PERR_EDMA_INPUT_FIFO1    8
2056 #define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
2057 #define F_PERR_EDMA_INPUT_FIFO1    V_PERR_EDMA_INPUT_FIFO1(1U)
2058 
2059 #define S_PERR_EDMA_INPUT_FIFO0    7
2060 #define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
2061 #define F_PERR_EDMA_INPUT_FIFO0    V_PERR_EDMA_INPUT_FIFO0(1U)
2062 
2063 #define S_PERR_MGT_BAR2_FIFO    6
2064 #define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
2065 #define F_PERR_MGT_BAR2_FIFO    V_PERR_MGT_BAR2_FIFO(1U)
2066 
2067 #define S_PERR_HEADERSPLIT_FIFO1_T5    5
2068 #define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
2069 #define F_PERR_HEADERSPLIT_FIFO1_T5    V_PERR_HEADERSPLIT_FIFO1_T5(1U)
2070 
2071 #define S_PERR_HEADERSPLIT_FIFO0_T5    4
2072 #define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
2073 #define F_PERR_HEADERSPLIT_FIFO0_T5    V_PERR_HEADERSPLIT_FIFO0_T5(1U)
2074 
2075 #define S_PERR_CIM_FIFO1    3
2076 #define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
2077 #define F_PERR_CIM_FIFO1    V_PERR_CIM_FIFO1(1U)
2078 
2079 #define S_PERR_CIM_FIFO0    2
2080 #define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
2081 #define F_PERR_CIM_FIFO0    V_PERR_CIM_FIFO0(1U)
2082 
2083 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1    1
2084 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
2085 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1    V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
2086 
2087 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
2088 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
2089 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
2090 
2091 #define A_SGE_INT_ENABLE5 0x1110
2092 #define A_SGE_PERR_ENABLE5 0x1114
2093 #define A_SGE_DBFIFO_STATUS2 0x1118
2094 
2095 #define S_FL_INT_THRESH    24
2096 #define M_FL_INT_THRESH    0xfU
2097 #define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
2098 #define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
2099 
2100 #define S_FL_COUNT    14
2101 #define M_FL_COUNT    0x3ffU
2102 #define V_FL_COUNT(x) ((x) << S_FL_COUNT)
2103 #define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
2104 
2105 #define S_HP_INT_THRESH_T5    10
2106 #define M_HP_INT_THRESH_T5    0xfU
2107 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
2108 #define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
2109 
2110 #define S_HP_COUNT_T5    0
2111 #define M_HP_COUNT_T5    0x3ffU
2112 #define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
2113 #define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
2114 
2115 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
2116 
2117 #define S_FETCHBURSTMAX0    16
2118 #define M_FETCHBURSTMAX0    0x3ffU
2119 #define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
2120 #define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
2121 
2122 #define S_FETCHBURSTMAX1    0
2123 #define M_FETCHBURSTMAX1    0x3ffU
2124 #define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
2125 #define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
2126 
2127 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
2128 
2129 #define S_FETCHBURSTMAX2    16
2130 #define M_FETCHBURSTMAX2    0x3ffU
2131 #define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
2132 #define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
2133 
2134 #define S_FETCHBURSTMAX3    0
2135 #define M_FETCHBURSTMAX3    0x3ffU
2136 #define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
2137 #define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
2138 
2139 #define A_SGE_CONTROL2 0x1124
2140 
2141 #define S_INGPACKBOUNDARY    16
2142 #define M_INGPACKBOUNDARY    0x7U
2143 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
2144 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
2145 
2146 #define S_VFIFO_ENABLE    10
2147 #define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
2148 #define F_VFIFO_ENABLE    V_VFIFO_ENABLE(1U)
2149 
2150 #define S_FLM_RESCHEDULE_MODE    9
2151 #define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
2152 #define F_FLM_RESCHEDULE_MODE    V_FLM_RESCHEDULE_MODE(1U)
2153 
2154 #define S_HINTDEPTHCTLFL    4
2155 #define M_HINTDEPTHCTLFL    0x1fU
2156 #define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
2157 #define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
2158 
2159 #define S_FORCE_ORDERING    3
2160 #define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
2161 #define F_FORCE_ORDERING    V_FORCE_ORDERING(1U)
2162 
2163 #define S_TX_COALESCE_SIZE    2
2164 #define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
2165 #define F_TX_COALESCE_SIZE    V_TX_COALESCE_SIZE(1U)
2166 
2167 #define S_COAL_STRICT_CIM_PRI    1
2168 #define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
2169 #define F_COAL_STRICT_CIM_PRI    V_COAL_STRICT_CIM_PRI(1U)
2170 
2171 #define S_TX_COALESCE_PRI    0
2172 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
2173 #define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)
2174 
2175 #define S_UPFLCUTOFFDIS    21
2176 #define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
2177 #define F_UPFLCUTOFFDIS    V_UPFLCUTOFFDIS(1U)
2178 
2179 #define S_RXCPLSIZEAUTOCORRECT    20
2180 #define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
2181 #define F_RXCPLSIZEAUTOCORRECT    V_RXCPLSIZEAUTOCORRECT(1U)
2182 
2183 #define S_IDMAARBROUNDROBIN    19
2184 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
2185 #define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)
2186 
2187 #define S_CGEN_EGRESS_CONTEXT    15
2188 #define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
2189 #define F_CGEN_EGRESS_CONTEXT    V_CGEN_EGRESS_CONTEXT(1U)
2190 
2191 #define S_CGEN_INGRESS_CONTEXT    14
2192 #define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
2193 #define F_CGEN_INGRESS_CONTEXT    V_CGEN_INGRESS_CONTEXT(1U)
2194 
2195 #define S_CGEN_IDMA    13
2196 #define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
2197 #define F_CGEN_IDMA    V_CGEN_IDMA(1U)
2198 
2199 #define S_CGEN_DBP    12
2200 #define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
2201 #define F_CGEN_DBP    V_CGEN_DBP(1U)
2202 
2203 #define S_CGEN_EDMA    11
2204 #define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
2205 #define F_CGEN_EDMA    V_CGEN_EDMA(1U)
2206 
2207 #define A_SGE_INT_CAUSE6 0x1128
2208 
2209 #define S_ERR_DB_SYNC    21
2210 #define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
2211 #define F_ERR_DB_SYNC    V_ERR_DB_SYNC(1U)
2212 
2213 #define S_ERR_GTS_SYNC    20
2214 #define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
2215 #define F_ERR_GTS_SYNC    V_ERR_GTS_SYNC(1U)
2216 
2217 #define S_FATAL_LARGE_COAL    19
2218 #define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
2219 #define F_FATAL_LARGE_COAL    V_FATAL_LARGE_COAL(1U)
2220 
2221 #define S_PL_BAR2_FRM_ERR    18
2222 #define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
2223 #define F_PL_BAR2_FRM_ERR    V_PL_BAR2_FRM_ERR(1U)
2224 
2225 #define S_SILENT_DROP_TX_COAL    17
2226 #define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
2227 #define F_SILENT_DROP_TX_COAL    V_SILENT_DROP_TX_COAL(1U)
2228 
2229 #define S_ERR_INV_CTXT4    16
2230 #define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
2231 #define F_ERR_INV_CTXT4    V_ERR_INV_CTXT4(1U)
2232 
2233 #define S_ERR_BAD_DB_PIDX4    15
2234 #define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
2235 #define F_ERR_BAD_DB_PIDX4    V_ERR_BAD_DB_PIDX4(1U)
2236 
2237 #define S_ERR_BAD_UPFL_INC_CREDIT4    14
2238 #define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
2239 #define F_ERR_BAD_UPFL_INC_CREDIT4    V_ERR_BAD_UPFL_INC_CREDIT4(1U)
2240 
2241 #define S_ERR_PC_RSP_LEN3    11
2242 #define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
2243 #define F_ERR_PC_RSP_LEN3    V_ERR_PC_RSP_LEN3(1U)
2244 
2245 #define S_ERR_PC_RSP_LEN2    10
2246 #define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
2247 #define F_ERR_PC_RSP_LEN2    V_ERR_PC_RSP_LEN2(1U)
2248 
2249 #define S_ERR_PC_RSP_LEN1    9
2250 #define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
2251 #define F_ERR_PC_RSP_LEN1    V_ERR_PC_RSP_LEN1(1U)
2252 
2253 #define S_ERR_PC_RSP_LEN0    8
2254 #define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
2255 #define F_ERR_PC_RSP_LEN0    V_ERR_PC_RSP_LEN0(1U)
2256 
2257 #define S_FATAL_ENQ2LL_VLD    7
2258 #define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
2259 #define F_FATAL_ENQ2LL_VLD    V_FATAL_ENQ2LL_VLD(1U)
2260 
2261 #define S_FATAL_LL_EMPTY    6
2262 #define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
2263 #define F_FATAL_LL_EMPTY    V_FATAL_LL_EMPTY(1U)
2264 
2265 #define S_FATAL_OFF_WDENQ    5
2266 #define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
2267 #define F_FATAL_OFF_WDENQ    V_FATAL_OFF_WDENQ(1U)
2268 
2269 #define S_FATAL_DEQ_DRDY    3
2270 #define M_FATAL_DEQ_DRDY    0x3U
2271 #define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
2272 #define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
2273 
2274 #define S_FATAL_OUTP_DRDY    1
2275 #define M_FATAL_OUTP_DRDY    0x3U
2276 #define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
2277 #define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)
2278 
2279 #define S_FATAL_DEQ    0
2280 #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
2281 #define F_FATAL_DEQ    V_FATAL_DEQ(1U)
2282 
2283 #define A_SGE_INT_ENABLE6 0x112c
2284 
2285 #define S_FATAL_TAG_MISMATCH    13
2286 #define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
2287 #define F_FATAL_TAG_MISMATCH    V_FATAL_TAG_MISMATCH(1U)
2288 
2289 #define S_FATAL_ENQ_CTL_RDY    12
2290 #define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
2291 #define F_FATAL_ENQ_CTL_RDY    V_FATAL_ENQ_CTL_RDY(1U)
2292 
2293 #define A_SGE_DBVFIFO_BADDR 0x1138
2294 #define A_SGE_DBVFIFO_SIZE 0x113c
2295 
2296 #define S_DBVFIFO_SIZE    6
2297 #define M_DBVFIFO_SIZE    0xfffU
2298 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
2299 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
2300 
2301 #define S_T6_DBVFIFO_SIZE    0
2302 #define M_T6_DBVFIFO_SIZE    0x1fffU
2303 #define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
2304 #define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)
2305 
2306 #define A_SGE_DBFIFO_STATUS3 0x1140
2307 
2308 #define S_LP_PTRS_EQUAL    21
2309 #define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
2310 #define F_LP_PTRS_EQUAL    V_LP_PTRS_EQUAL(1U)
2311 
2312 #define S_LP_SNAPHOT    20
2313 #define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
2314 #define F_LP_SNAPHOT    V_LP_SNAPHOT(1U)
2315 
2316 #define S_FL_INT_THRESH_LOW    16
2317 #define M_FL_INT_THRESH_LOW    0xfU
2318 #define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
2319 #define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
2320 
2321 #define S_HP_INT_THRESH_LOW    12
2322 #define M_HP_INT_THRESH_LOW    0xfU
2323 #define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
2324 #define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
2325 
2326 #define S_LP_INT_THRESH_LOW    0
2327 #define M_LP_INT_THRESH_LOW    0xfffU
2328 #define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
2329 #define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
2330 
2331 #define A_SGE_CHANGESET 0x1144
2332 #define A_SGE_PC_RSP_ERROR 0x1148
2333 #define A_SGE_TBUF_CONTROL 0x114c
2334 
2335 #define S_DBPTBUFRSV1    9
2336 #define M_DBPTBUFRSV1    0x1ffU
2337 #define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
2338 #define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)
2339 
2340 #define S_DBPTBUFRSV0    0
2341 #define M_DBPTBUFRSV0    0x1ffU
2342 #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
2343 #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
2344 
2345 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
2346 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2347 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
2348 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2349 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2350 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2351 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2352 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2353 #define A_SGE_DBQ_TIMER_DBG 0x11c4
2354 
2355 #define S_DBQ_TIMER_CMD    31
2356 #define V_DBQ_TIMER_CMD(x) ((x) << S_DBQ_TIMER_CMD)
2357 #define F_DBQ_TIMER_CMD    V_DBQ_TIMER_CMD(1U)
2358 
2359 #define S_DBQ_TIMER_INDEX    24
2360 #define M_DBQ_TIMER_INDEX    0x3fU
2361 #define V_DBQ_TIMER_INDEX(x) ((x) << S_DBQ_TIMER_INDEX)
2362 #define G_DBQ_TIMER_INDEX(x) (((x) >> S_DBQ_TIMER_INDEX) & M_DBQ_TIMER_INDEX)
2363 
2364 #define S_DBQ_TIMER_QCNT    0
2365 #define M_DBQ_TIMER_QCNT    0x1ffffU
2366 #define V_DBQ_TIMER_QCNT(x) ((x) << S_DBQ_TIMER_QCNT)
2367 #define G_DBQ_TIMER_QCNT(x) (((x) >> S_DBQ_TIMER_QCNT) & M_DBQ_TIMER_QCNT)
2368 
2369 #define A_SGE_CTXT_CMD 0x11fc
2370 
2371 #define S_BUSY    31
2372 #define V_BUSY(x) ((x) << S_BUSY)
2373 #define F_BUSY    V_BUSY(1U)
2374 
2375 #define S_CTXTOP    28
2376 #define M_CTXTOP    0x3U
2377 #define V_CTXTOP(x) ((x) << S_CTXTOP)
2378 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
2379 
2380 #define S_CTXTTYPE    24
2381 #define M_CTXTTYPE    0x3U
2382 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
2383 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
2384 
2385 #define S_CTXTQID    0
2386 #define M_CTXTQID    0x1ffffU
2387 #define V_CTXTQID(x) ((x) << S_CTXTQID)
2388 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
2389 
2390 #define A_SGE_CTXT_DATA0 0x1200
2391 #define A_SGE_CTXT_DATA1 0x1204
2392 #define A_SGE_CTXT_DATA2 0x1208
2393 #define A_SGE_CTXT_DATA3 0x120c
2394 #define A_SGE_CTXT_DATA4 0x1210
2395 #define A_SGE_CTXT_DATA5 0x1214
2396 #define A_SGE_CTXT_DATA6 0x1218
2397 #define A_SGE_CTXT_DATA7 0x121c
2398 #define A_SGE_CTXT_MASK0 0x1220
2399 #define A_SGE_CTXT_MASK1 0x1224
2400 #define A_SGE_CTXT_MASK2 0x1228
2401 #define A_SGE_CTXT_MASK3 0x122c
2402 #define A_SGE_CTXT_MASK4 0x1230
2403 #define A_SGE_CTXT_MASK5 0x1234
2404 #define A_SGE_CTXT_MASK6 0x1238
2405 #define A_SGE_CTXT_MASK7 0x123c
2406 #define A_SGE_QBASE_MAP0 0x1240
2407 
2408 #define S_EGRESS0_SIZE    24
2409 #define M_EGRESS0_SIZE    0x1fU
2410 #define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
2411 #define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)
2412 
2413 #define S_EGRESS1_SIZE    16
2414 #define M_EGRESS1_SIZE    0x1fU
2415 #define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
2416 #define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)
2417 
2418 #define S_INGRESS0_SIZE    8
2419 #define M_INGRESS0_SIZE    0x1fU
2420 #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
2421 #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
2422 
2423 #define S_INGRESS1_SIZE    0
2424 #define M_INGRESS1_SIZE    0x1fU
2425 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
2426 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
2427 
2428 #define A_SGE_QBASE_MAP1 0x1244
2429 
2430 #define S_EGRESS0_BASE    0
2431 #define M_EGRESS0_BASE    0x1ffffU
2432 #define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
2433 #define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)
2434 
2435 #define A_SGE_QBASE_MAP2 0x1248
2436 
2437 #define S_EGRESS1_BASE    0
2438 #define M_EGRESS1_BASE    0x1ffffU
2439 #define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
2440 #define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)
2441 
2442 #define A_SGE_QBASE_MAP3 0x124c
2443 
2444 #define S_INGRESS1_BASE_256VF    16
2445 #define M_INGRESS1_BASE_256VF    0xffffU
2446 #define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
2447 #define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)
2448 
2449 #define S_INGRESS0_BASE    0
2450 #define M_INGRESS0_BASE    0xffffU
2451 #define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
2452 #define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)
2453 
2454 #define A_SGE_QBASE_INDEX 0x1250
2455 
2456 #define S_QIDX    0
2457 #define M_QIDX    0x1ffU
2458 #define V_QIDX(x) ((x) << S_QIDX)
2459 #define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)
2460 
2461 #define A_SGE_CONM_CTRL2 0x1254
2462 
2463 #define S_FLMTHRESHPACK    8
2464 #define M_FLMTHRESHPACK    0x7fU
2465 #define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
2466 #define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)
2467 
2468 #define S_FLMTHRESH    0
2469 #define M_FLMTHRESH    0x7fU
2470 #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
2471 #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
2472 
2473 #define A_SGE_DEBUG_CONM 0x1258
2474 
2475 #define S_MPS_CH_CNG    16
2476 #define M_MPS_CH_CNG    0xffffU
2477 #define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
2478 #define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)
2479 
2480 #define S_TP_CH_CNG    14
2481 #define M_TP_CH_CNG    0x3U
2482 #define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
2483 #define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)
2484 
2485 #define S_ST_CONG    12
2486 #define M_ST_CONG    0x3U
2487 #define V_ST_CONG(x) ((x) << S_ST_CONG)
2488 #define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)
2489 
2490 #define S_LAST_XOFF    10
2491 #define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
2492 #define F_LAST_XOFF    V_LAST_XOFF(1U)
2493 
2494 #define S_LAST_QID    0
2495 #define M_LAST_QID    0x3ffU
2496 #define V_LAST_QID(x) ((x) << S_LAST_QID)
2497 #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
2498 
2499 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
2500 
2501 #define S_IMSG_GTS_SEL    18
2502 #define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
2503 #define F_IMSG_GTS_SEL    V_IMSG_GTS_SEL(1U)
2504 
2505 #define S_MGT_SEL    17
2506 #define V_MGT_SEL(x) ((x) << S_MGT_SEL)
2507 #define F_MGT_SEL    V_MGT_SEL(1U)
2508 
2509 #define S_DB_GTS_QID    0
2510 #define M_DB_GTS_QID    0x1ffffU
2511 #define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
2512 #define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)
2513 
2514 #define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
2515 #define A_SGE_DBG_QUEUE_STAT0 0x1264
2516 #define A_SGE_DBG_QUEUE_STAT1 0x1268
2517 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c
2518 #define A_SGE_DBG_DB_PKT_CNT 0x1270
2519 #define A_SGE_DBG_GTS_PKT_CNT 0x1274
2520 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
2521 
2522 #define S_CIM_WM    24
2523 #define M_CIM_WM    0x3U
2524 #define V_CIM_WM(x) ((x) << S_CIM_WM)
2525 #define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
2526 
2527 #define S_DEBUG_UP_SOP_CNT    20
2528 #define M_DEBUG_UP_SOP_CNT    0xfU
2529 #define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
2530 #define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
2531 
2532 #define S_DEBUG_UP_EOP_CNT    16
2533 #define M_DEBUG_UP_EOP_CNT    0xfU
2534 #define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
2535 #define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
2536 
2537 #define S_DEBUG_CIM_SOP1_CNT    12
2538 #define M_DEBUG_CIM_SOP1_CNT    0xfU
2539 #define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
2540 #define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
2541 
2542 #define S_DEBUG_CIM_EOP1_CNT    8
2543 #define M_DEBUG_CIM_EOP1_CNT    0xfU
2544 #define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
2545 #define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
2546 
2547 #define S_DEBUG_CIM_SOP0_CNT    4
2548 #define M_DEBUG_CIM_SOP0_CNT    0xfU
2549 #define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
2550 #define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
2551 
2552 #define S_DEBUG_CIM_EOP0_CNT    0
2553 #define M_DEBUG_CIM_EOP0_CNT    0xfU
2554 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
2555 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
2556 
2557 #define S_DEBUG_BAR2_SOP_CNT    28
2558 #define M_DEBUG_BAR2_SOP_CNT    0xfU
2559 #define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
2560 #define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)
2561 
2562 #define S_DEBUG_BAR2_EOP_CNT    24
2563 #define M_DEBUG_BAR2_EOP_CNT    0xfU
2564 #define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
2565 #define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)
2566 
2567 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
2568 
2569 #define S_DEBUG_T_RX_SOP1_CNT    28
2570 #define M_DEBUG_T_RX_SOP1_CNT    0xfU
2571 #define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
2572 #define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
2573 
2574 #define S_DEBUG_T_RX_EOP1_CNT    24
2575 #define M_DEBUG_T_RX_EOP1_CNT    0xfU
2576 #define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
2577 #define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
2578 
2579 #define S_DEBUG_T_RX_SOP0_CNT    20
2580 #define M_DEBUG_T_RX_SOP0_CNT    0xfU
2581 #define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
2582 #define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
2583 
2584 #define S_DEBUG_T_RX_EOP0_CNT    16
2585 #define M_DEBUG_T_RX_EOP0_CNT    0xfU
2586 #define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
2587 #define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
2588 
2589 #define S_DEBUG_U_RX_SOP1_CNT    12
2590 #define M_DEBUG_U_RX_SOP1_CNT    0xfU
2591 #define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
2592 #define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
2593 
2594 #define S_DEBUG_U_RX_EOP1_CNT    8
2595 #define M_DEBUG_U_RX_EOP1_CNT    0xfU
2596 #define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
2597 #define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
2598 
2599 #define S_DEBUG_U_RX_SOP0_CNT    4
2600 #define M_DEBUG_U_RX_SOP0_CNT    0xfU
2601 #define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
2602 #define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
2603 
2604 #define S_DEBUG_U_RX_EOP0_CNT    0
2605 #define M_DEBUG_U_RX_EOP0_CNT    0xfU
2606 #define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
2607 #define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
2608 
2609 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
2610 
2611 #define S_DEBUG_UD_RX_SOP3_CNT    28
2612 #define M_DEBUG_UD_RX_SOP3_CNT    0xfU
2613 #define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
2614 #define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
2615 
2616 #define S_DEBUG_UD_RX_EOP3_CNT    24
2617 #define M_DEBUG_UD_RX_EOP3_CNT    0xfU
2618 #define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
2619 #define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
2620 
2621 #define S_DEBUG_UD_RX_SOP2_CNT    20
2622 #define M_DEBUG_UD_RX_SOP2_CNT    0xfU
2623 #define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
2624 #define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
2625 
2626 #define S_DEBUG_UD_RX_EOP2_CNT    16
2627 #define M_DEBUG_UD_RX_EOP2_CNT    0xfU
2628 #define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
2629 #define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
2630 
2631 #define S_DEBUG_UD_RX_SOP1_CNT    12
2632 #define M_DEBUG_UD_RX_SOP1_CNT    0xfU
2633 #define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
2634 #define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
2635 
2636 #define S_DEBUG_UD_RX_EOP1_CNT    8
2637 #define M_DEBUG_UD_RX_EOP1_CNT    0xfU
2638 #define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
2639 #define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
2640 
2641 #define S_DEBUG_UD_RX_SOP0_CNT    4
2642 #define M_DEBUG_UD_RX_SOP0_CNT    0xfU
2643 #define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
2644 #define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
2645 
2646 #define S_DEBUG_UD_RX_EOP0_CNT    0
2647 #define M_DEBUG_UD_RX_EOP0_CNT    0xfU
2648 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
2649 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
2650 
2651 #define S_DBG_TBUF_USED1    9
2652 #define M_DBG_TBUF_USED1    0x1ffU
2653 #define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
2654 #define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)
2655 
2656 #define S_DBG_TBUF_USED0    0
2657 #define M_DBG_TBUF_USED0    0x1ffU
2658 #define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
2659 #define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)
2660 
2661 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
2662 
2663 #define S_DEBUG_U_TX_SOP3_CNT    28
2664 #define M_DEBUG_U_TX_SOP3_CNT    0xfU
2665 #define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
2666 #define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
2667 
2668 #define S_DEBUG_U_TX_EOP3_CNT    24
2669 #define M_DEBUG_U_TX_EOP3_CNT    0xfU
2670 #define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
2671 #define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
2672 
2673 #define S_DEBUG_U_TX_SOP2_CNT    20
2674 #define M_DEBUG_U_TX_SOP2_CNT    0xfU
2675 #define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
2676 #define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
2677 
2678 #define S_DEBUG_U_TX_EOP2_CNT    16
2679 #define M_DEBUG_U_TX_EOP2_CNT    0xfU
2680 #define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
2681 #define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
2682 
2683 #define S_DEBUG_U_TX_SOP1_CNT    12
2684 #define M_DEBUG_U_TX_SOP1_CNT    0xfU
2685 #define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
2686 #define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
2687 
2688 #define S_DEBUG_U_TX_EOP1_CNT    8
2689 #define M_DEBUG_U_TX_EOP1_CNT    0xfU
2690 #define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
2691 #define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
2692 
2693 #define S_DEBUG_U_TX_SOP0_CNT    4
2694 #define M_DEBUG_U_TX_SOP0_CNT    0xfU
2695 #define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
2696 #define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
2697 
2698 #define S_DEBUG_U_TX_EOP0_CNT    0
2699 #define M_DEBUG_U_TX_EOP0_CNT    0xfU
2700 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
2701 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
2702 
2703 #define A_SGE_DEBUG1_DBP_THREAD 0x128c
2704 
2705 #define S_WR_DEQ_CNT    12
2706 #define M_WR_DEQ_CNT    0xfU
2707 #define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
2708 #define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)
2709 
2710 #define S_WR_ENQ_CNT    8
2711 #define M_WR_ENQ_CNT    0xfU
2712 #define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
2713 #define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)
2714 
2715 #define S_FL_DEQ_CNT    4
2716 #define M_FL_DEQ_CNT    0xfU
2717 #define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
2718 #define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)
2719 
2720 #define S_FL_ENQ_CNT    0
2721 #define M_FL_ENQ_CNT    0xfU
2722 #define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
2723 #define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)
2724 
2725 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
2726 
2727 #define S_DEBUG_PC_RSP_SOP1_CNT    28
2728 #define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
2729 #define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
2730 #define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
2731 
2732 #define S_DEBUG_PC_RSP_EOP1_CNT    24
2733 #define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
2734 #define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
2735 #define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
2736 
2737 #define S_DEBUG_PC_RSP_SOP0_CNT    20
2738 #define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
2739 #define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
2740 #define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
2741 
2742 #define S_DEBUG_PC_RSP_EOP0_CNT    16
2743 #define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
2744 #define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
2745 #define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
2746 
2747 #define S_DEBUG_PC_REQ_SOP1_CNT    12
2748 #define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
2749 #define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
2750 #define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
2751 
2752 #define S_DEBUG_PC_REQ_EOP1_CNT    8
2753 #define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
2754 #define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
2755 #define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
2756 
2757 #define S_DEBUG_PC_REQ_SOP0_CNT    4
2758 #define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
2759 #define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
2760 #define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
2761 
2762 #define S_DEBUG_PC_REQ_EOP0_CNT    0
2763 #define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
2764 #define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
2765 #define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
2766 
2767 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
2768 
2769 #define S_DEBUG_PD_RDREQ_SOP3_CNT    28
2770 #define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
2771 #define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
2772 #define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
2773 
2774 #define S_DEBUG_PD_RDREQ_EOP3_CNT    24
2775 #define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
2776 #define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
2777 #define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
2778 
2779 #define S_DEBUG_PD_RDREQ_SOP2_CNT    20
2780 #define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
2781 #define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
2782 #define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
2783 
2784 #define S_DEBUG_PD_RDREQ_EOP2_CNT    16
2785 #define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
2786 #define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
2787 #define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
2788 
2789 #define S_DEBUG_PD_RDREQ_SOP1_CNT    12
2790 #define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
2791 #define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
2792 #define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
2793 
2794 #define S_DEBUG_PD_RDREQ_EOP1_CNT    8
2795 #define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
2796 #define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
2797 #define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
2798 
2799 #define S_DEBUG_PD_RDREQ_SOP0_CNT    4
2800 #define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
2801 #define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
2802 #define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
2803 
2804 #define S_DEBUG_PD_RDREQ_EOP0_CNT    0
2805 #define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
2806 #define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
2807 #define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
2808 
2809 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
2810 
2811 #define S_DEBUG_PD_RDRSP_SOP3_CNT    28
2812 #define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
2813 #define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
2814 #define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
2815 
2816 #define S_DEBUG_PD_RDRSP_EOP3_CNT    24
2817 #define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
2818 #define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
2819 #define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
2820 
2821 #define S_DEBUG_PD_RDRSP_SOP2_CNT    20
2822 #define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
2823 #define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
2824 #define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
2825 
2826 #define S_DEBUG_PD_RDRSP_EOP2_CNT    16
2827 #define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
2828 #define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
2829 #define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
2830 
2831 #define S_DEBUG_PD_RDRSP_SOP1_CNT    12
2832 #define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
2833 #define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
2834 #define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
2835 
2836 #define S_DEBUG_PD_RDRSP_EOP1_CNT    8
2837 #define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
2838 #define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
2839 #define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
2840 
2841 #define S_DEBUG_PD_RDRSP_SOP0_CNT    4
2842 #define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
2843 #define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
2844 #define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
2845 
2846 #define S_DEBUG_PD_RDRSP_EOP0_CNT    0
2847 #define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
2848 #define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
2849 #define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
2850 
2851 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
2852 
2853 #define S_DEBUG_PD_WRREQ_SOP3_CNT    28
2854 #define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
2855 #define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
2856 #define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
2857 
2858 #define S_DEBUG_PD_WRREQ_EOP3_CNT    24
2859 #define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
2860 #define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
2861 #define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
2862 
2863 #define S_DEBUG_PD_WRREQ_SOP2_CNT    20
2864 #define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
2865 #define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
2866 #define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
2867 
2868 #define S_DEBUG_PD_WRREQ_EOP2_CNT    16
2869 #define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
2870 #define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
2871 #define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
2872 
2873 #define S_DEBUG_PD_WRREQ_SOP1_CNT    12
2874 #define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
2875 #define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
2876 #define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
2877 
2878 #define S_DEBUG_PD_WRREQ_EOP1_CNT    8
2879 #define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
2880 #define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
2881 #define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
2882 
2883 #define S_DEBUG_PD_WRREQ_SOP0_CNT    4
2884 #define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
2885 #define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
2886 #define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
2887 
2888 #define S_DEBUG_PD_WRREQ_EOP0_CNT    0
2889 #define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
2890 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
2891 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
2892 
2893 #define S_DEBUG_PC_RSP_SOP_CNT    28
2894 #define M_DEBUG_PC_RSP_SOP_CNT    0xfU
2895 #define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
2896 #define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)
2897 
2898 #define S_DEBUG_PC_RSP_EOP_CNT    24
2899 #define M_DEBUG_PC_RSP_EOP_CNT    0xfU
2900 #define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
2901 #define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)
2902 
2903 #define S_DEBUG_PC_REQ_SOP_CNT    20
2904 #define M_DEBUG_PC_REQ_SOP_CNT    0xfU
2905 #define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
2906 #define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)
2907 
2908 #define S_DEBUG_PC_REQ_EOP_CNT    16
2909 #define M_DEBUG_PC_REQ_EOP_CNT    0xfU
2910 #define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
2911 #define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)
2912 
2913 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
2914 
2915 #define S_GLOBALENABLE_OFF    29
2916 #define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
2917 #define F_GLOBALENABLE_OFF    V_GLOBALENABLE_OFF(1U)
2918 
2919 #define S_DEBUG_CIM2SGE_RXAFULL_D    27
2920 #define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
2921 #define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
2922 #define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
2923 
2924 #define S_DEBUG_CPLSW_CIM_TXAFULL_D    25
2925 #define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
2926 #define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
2927 #define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
2928 
2929 #define S_DEBUG_UP_FULL    24
2930 #define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
2931 #define F_DEBUG_UP_FULL    V_DEBUG_UP_FULL(1U)
2932 
2933 #define S_DEBUG_M_RD_REQ_OUTSTANDING_PC    23
2934 #define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
2935 #define F_DEBUG_M_RD_REQ_OUTSTANDING_PC    V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
2936 
2937 #define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    22
2938 #define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
2939 #define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
2940 
2941 #define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    21
2942 #define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
2943 #define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
2944 
2945 #define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    20
2946 #define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
2947 #define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
2948 
2949 #define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM    19
2950 #define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
2951 #define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM    V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
2952 
2953 #define S_DEBUG_M_REQVLD    18
2954 #define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
2955 #define F_DEBUG_M_REQVLD    V_DEBUG_M_REQVLD(1U)
2956 
2957 #define S_DEBUG_M_REQRDY    17
2958 #define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
2959 #define F_DEBUG_M_REQRDY    V_DEBUG_M_REQRDY(1U)
2960 
2961 #define S_DEBUG_M_RSPVLD    16
2962 #define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
2963 #define F_DEBUG_M_RSPVLD    V_DEBUG_M_RSPVLD(1U)
2964 
2965 #define S_DEBUG_PD_WRREQ_INT3_CNT    12
2966 #define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
2967 #define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
2968 #define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
2969 
2970 #define S_DEBUG_PD_WRREQ_INT2_CNT    8
2971 #define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
2972 #define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
2973 #define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
2974 
2975 #define S_DEBUG_PD_WRREQ_INT1_CNT    4
2976 #define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
2977 #define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
2978 #define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
2979 
2980 #define S_DEBUG_PD_WRREQ_INT0_CNT    0
2981 #define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
2982 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
2983 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
2984 
2985 #define S_DEBUG_PL_BAR2_REQVLD    31
2986 #define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
2987 #define F_DEBUG_PL_BAR2_REQVLD    V_DEBUG_PL_BAR2_REQVLD(1U)
2988 
2989 #define S_DEBUG_PL_BAR2_REQFULL    30
2990 #define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
2991 #define F_DEBUG_PL_BAR2_REQFULL    V_DEBUG_PL_BAR2_REQFULL(1U)
2992 
2993 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
2994 
2995 #define S_DEBUG_CPLSW_TP_RX_SOP1_CNT    28
2996 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
2997 #define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
2998 #define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
2999 
3000 #define S_DEBUG_CPLSW_TP_RX_EOP1_CNT    24
3001 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
3002 #define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3003 #define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3004 
3005 #define S_DEBUG_CPLSW_TP_RX_SOP0_CNT    20
3006 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
3007 #define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3008 #define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3009 
3010 #define S_DEBUG_CPLSW_TP_RX_EOP0_CNT    16
3011 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
3012 #define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3013 #define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3014 
3015 #define S_DEBUG_CPLSW_CIM_SOP1_CNT    12
3016 #define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
3017 #define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
3018 #define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
3019 
3020 #define S_DEBUG_CPLSW_CIM_EOP1_CNT    8
3021 #define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
3022 #define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
3023 #define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
3024 
3025 #define S_DEBUG_CPLSW_CIM_SOP0_CNT    4
3026 #define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
3027 #define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
3028 #define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
3029 
3030 #define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
3031 #define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
3032 #define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
3033 #define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
3034 
3035 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
3036 
3037 #define S_DEBUG_T_RXAFULL_D    30
3038 #define M_DEBUG_T_RXAFULL_D    0x3U
3039 #define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
3040 #define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
3041 
3042 #define S_DEBUG_PD_RDRSPAFULL_D    26
3043 #define M_DEBUG_PD_RDRSPAFULL_D    0xfU
3044 #define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
3045 #define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
3046 
3047 #define S_DEBUG_PD_RDREQAFULL_D    22
3048 #define M_DEBUG_PD_RDREQAFULL_D    0xfU
3049 #define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
3050 #define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
3051 
3052 #define S_DEBUG_PD_WRREQAFULL_D    18
3053 #define M_DEBUG_PD_WRREQAFULL_D    0xfU
3054 #define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
3055 #define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
3056 
3057 #define S_DEBUG_PC_RSPAFULL_D    15
3058 #define M_DEBUG_PC_RSPAFULL_D    0x7U
3059 #define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
3060 #define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
3061 
3062 #define S_DEBUG_PC_REQAFULL_D    12
3063 #define M_DEBUG_PC_REQAFULL_D    0x7U
3064 #define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
3065 #define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
3066 
3067 #define S_DEBUG_U_TXAFULL_D    8
3068 #define M_DEBUG_U_TXAFULL_D    0xfU
3069 #define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
3070 #define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
3071 
3072 #define S_DEBUG_UD_RXAFULL_D    4
3073 #define M_DEBUG_UD_RXAFULL_D    0xfU
3074 #define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
3075 #define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
3076 
3077 #define S_DEBUG_U_RXAFULL_D    2
3078 #define M_DEBUG_U_RXAFULL_D    0x3U
3079 #define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
3080 #define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
3081 
3082 #define S_DEBUG_CIM_AFULL_D    0
3083 #define M_DEBUG_CIM_AFULL_D    0x3U
3084 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
3085 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
3086 
3087 #define S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    28
3088 #define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
3089 #define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3090 #define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3091 
3092 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    27
3093 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
3094 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)
3095 
3096 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    26
3097 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
3098 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)
3099 
3100 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    25
3101 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
3102 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3103 
3104 #define S_DEBUG_IDMA1_IDMA2IMSG_FULL    24
3105 #define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
3106 #define F_DEBUG_IDMA1_IDMA2IMSG_FULL    V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)
3107 
3108 #define S_DEBUG_IDMA1_IDMA2IMSG_EOP    23
3109 #define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
3110 #define F_DEBUG_IDMA1_IDMA2IMSG_EOP    V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)
3111 
3112 #define S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    22
3113 #define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
3114 #define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)
3115 
3116 #define S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    21
3117 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
3118 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)
3119 
3120 #define S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    17
3121 #define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
3122 #define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3123 #define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3124 
3125 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    16
3126 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
3127 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)
3128 
3129 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    15
3130 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
3131 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)
3132 
3133 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    14
3134 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
3135 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3136 
3137 #define S_DEBUG_IDMA0_IDMA2IMSG_FULL    13
3138 #define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
3139 #define F_DEBUG_IDMA0_IDMA2IMSG_FULL    V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)
3140 
3141 #define S_DEBUG_IDMA0_IDMA2IMSG_EOP    12
3142 #define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
3143 #define F_DEBUG_IDMA0_IDMA2IMSG_EOP    V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)
3144 
3145 #define S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    11
3146 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
3147 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)
3148 
3149 #define S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    10
3150 #define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
3151 #define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)
3152 
3153 #define S_T6_DEBUG_T_RXAFULL_D    8
3154 #define M_T6_DEBUG_T_RXAFULL_D    0x3U
3155 #define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
3156 #define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)
3157 
3158 #define S_T6_DEBUG_PD_WRREQAFULL_D    6
3159 #define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
3160 #define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
3161 #define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)
3162 
3163 #define S_T6_DEBUG_PC_RSPAFULL_D    5
3164 #define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
3165 #define F_T6_DEBUG_PC_RSPAFULL_D    V_T6_DEBUG_PC_RSPAFULL_D(1U)
3166 
3167 #define S_T6_DEBUG_PC_REQAFULL_D    4
3168 #define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
3169 #define F_T6_DEBUG_PC_REQAFULL_D    V_T6_DEBUG_PC_REQAFULL_D(1U)
3170 
3171 #define S_T6_DEBUG_CIM_AFULL_D    0
3172 #define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
3173 #define F_T6_DEBUG_CIM_AFULL_D    V_T6_DEBUG_CIM_AFULL_D(1U)
3174 
3175 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
3176 
3177 #define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    24
3178 #define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
3179 #define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
3180 
3181 #define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    23
3182 #define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
3183 #define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
3184 
3185 #define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    22
3186 #define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
3187 #define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
3188 
3189 #define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    21
3190 #define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
3191 #define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
3192 
3193 #define S_DEBUG_ST_FLM_IDMA1_CACHE    19
3194 #define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
3195 #define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
3196 #define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
3197 
3198 #define S_DEBUG_ST_FLM_IDMA1_CTXT    16
3199 #define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
3200 #define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
3201 #define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
3202 
3203 #define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    8
3204 #define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
3205 #define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
3206 
3207 #define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    7
3208 #define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
3209 #define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
3210 
3211 #define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    6
3212 #define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
3213 #define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
3214 
3215 #define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    5
3216 #define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
3217 #define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
3218 
3219 #define S_DEBUG_ST_FLM_IDMA0_CACHE    3
3220 #define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
3221 #define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
3222 #define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
3223 
3224 #define S_DEBUG_ST_FLM_IDMA0_CTXT    0
3225 #define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
3226 #define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
3227 #define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
3228 
3229 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
3230 
3231 #define S_DEBUG_CPLSW_SOP1_CNT    28
3232 #define M_DEBUG_CPLSW_SOP1_CNT    0xfU
3233 #define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
3234 #define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
3235 
3236 #define S_DEBUG_CPLSW_EOP1_CNT    24
3237 #define M_DEBUG_CPLSW_EOP1_CNT    0xfU
3238 #define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
3239 #define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
3240 
3241 #define S_DEBUG_CPLSW_SOP0_CNT    20
3242 #define M_DEBUG_CPLSW_SOP0_CNT    0xfU
3243 #define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
3244 #define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
3245 
3246 #define S_DEBUG_CPLSW_EOP0_CNT    16
3247 #define M_DEBUG_CPLSW_EOP0_CNT    0xfU
3248 #define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
3249 #define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
3250 
3251 #define S_DEBUG_PC_RSP_SOP2_CNT    12
3252 #define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
3253 #define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
3254 #define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
3255 
3256 #define S_DEBUG_PC_RSP_EOP2_CNT    8
3257 #define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
3258 #define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
3259 #define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
3260 
3261 #define S_DEBUG_PC_REQ_SOP2_CNT    4
3262 #define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
3263 #define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
3264 #define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
3265 
3266 #define S_DEBUG_PC_REQ_EOP2_CNT    0
3267 #define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
3268 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
3269 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
3270 
3271 #define S_DEBUG_IDMA1_ISHIFT_TX_SIZE    8
3272 #define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
3273 #define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3274 #define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3275 
3276 #define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
3277 #define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
3278 #define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3279 #define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3280 
3281 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
3282 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
3283 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
3284 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
3285 
3286 #define S_DEBUG_ST_IDMA1_FLM_REQ    29
3287 #define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
3288 #define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
3289 #define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
3290 
3291 #define S_DEBUG_ST_IDMA0_FLM_REQ    26
3292 #define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
3293 #define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
3294 #define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
3295 
3296 #define S_DEBUG_ST_IMSG_CTXT    23
3297 #define M_DEBUG_ST_IMSG_CTXT    0x7U
3298 #define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
3299 #define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
3300 
3301 #define S_DEBUG_ST_IMSG    18
3302 #define M_DEBUG_ST_IMSG    0x1fU
3303 #define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
3304 #define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
3305 
3306 #define S_DEBUG_ST_IDMA1_IALN    16
3307 #define M_DEBUG_ST_IDMA1_IALN    0x3U
3308 #define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
3309 #define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
3310 
3311 #define S_DEBUG_ST_IDMA1_IDMA_SM    9
3312 #define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
3313 #define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
3314 #define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
3315 
3316 #define S_DEBUG_ST_IDMA0_IALN    7
3317 #define M_DEBUG_ST_IDMA0_IALN    0x3U
3318 #define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
3319 #define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
3320 
3321 #define S_DEBUG_ST_IDMA0_IDMA_SM    0
3322 #define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
3323 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
3324 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
3325 
3326 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
3327 
3328 #define S_DEBUG_ITP_EMPTY    12
3329 #define M_DEBUG_ITP_EMPTY    0x3fU
3330 #define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
3331 #define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
3332 
3333 #define S_DEBUG_ITP_EXPIRED    6
3334 #define M_DEBUG_ITP_EXPIRED    0x3fU
3335 #define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
3336 #define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
3337 
3338 #define S_DEBUG_ITP_PAUSE    5
3339 #define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
3340 #define F_DEBUG_ITP_PAUSE    V_DEBUG_ITP_PAUSE(1U)
3341 
3342 #define S_DEBUG_ITP_DEL_DONE    4
3343 #define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
3344 #define F_DEBUG_ITP_DEL_DONE    V_DEBUG_ITP_DEL_DONE(1U)
3345 
3346 #define S_DEBUG_ITP_ADD_DONE    3
3347 #define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
3348 #define F_DEBUG_ITP_ADD_DONE    V_DEBUG_ITP_ADD_DONE(1U)
3349 
3350 #define S_DEBUG_ITP_EVR_STATE    0
3351 #define M_DEBUG_ITP_EVR_STATE    0x7U
3352 #define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
3353 #define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
3354 
3355 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
3356 
3357 #define S_DEBUG_ST_DBP_THREAD2_CIMFL    25
3358 #define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
3359 #define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
3360 #define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
3361 
3362 #define S_DEBUG_ST_DBP_THREAD2_MAIN    20
3363 #define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
3364 #define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
3365 #define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
3366 
3367 #define S_DEBUG_ST_DBP_THREAD1_CIMFL    15
3368 #define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
3369 #define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
3370 #define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
3371 
3372 #define S_DEBUG_ST_DBP_THREAD1_MAIN    10
3373 #define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
3374 #define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
3375 #define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
3376 
3377 #define S_DEBUG_ST_DBP_THREAD0_CIMFL    5
3378 #define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
3379 #define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
3380 #define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
3381 
3382 #define S_DEBUG_ST_DBP_THREAD0_MAIN    0
3383 #define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
3384 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
3385 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
3386 
3387 #define S_T6_DEBUG_ST_DBP_UPCP_MAIN    14
3388 #define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
3389 #define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
3390 #define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)
3391 
3392 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
3393 
3394 #define S_DEBUG_ST_DBP_UPCP_MAIN    14
3395 #define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
3396 #define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
3397 #define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
3398 
3399 #define S_DEBUG_ST_DBP_DBFIFO_MAIN    13
3400 #define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
3401 #define F_DEBUG_ST_DBP_DBFIFO_MAIN    V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
3402 
3403 #define S_DEBUG_ST_DBP_CTXT    10
3404 #define M_DEBUG_ST_DBP_CTXT    0x7U
3405 #define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
3406 #define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
3407 
3408 #define S_DEBUG_ST_DBP_THREAD3_CIMFL    5
3409 #define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
3410 #define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
3411 #define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
3412 
3413 #define S_DEBUG_ST_DBP_THREAD3_MAIN    0
3414 #define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
3415 #define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
3416 #define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
3417 
3418 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
3419 
3420 #define S_DEBUG_ST_EDMA3_ALIGN_SUB    29
3421 #define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
3422 #define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
3423 #define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
3424 
3425 #define S_DEBUG_ST_EDMA3_ALIGN    27
3426 #define M_DEBUG_ST_EDMA3_ALIGN    0x3U
3427 #define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
3428 #define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
3429 
3430 #define S_DEBUG_ST_EDMA3_REQ    24
3431 #define M_DEBUG_ST_EDMA3_REQ    0x7U
3432 #define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
3433 #define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
3434 
3435 #define S_DEBUG_ST_EDMA2_ALIGN_SUB    21
3436 #define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
3437 #define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
3438 #define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
3439 
3440 #define S_DEBUG_ST_EDMA2_ALIGN    19
3441 #define M_DEBUG_ST_EDMA2_ALIGN    0x3U
3442 #define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
3443 #define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
3444 
3445 #define S_DEBUG_ST_EDMA2_REQ    16
3446 #define M_DEBUG_ST_EDMA2_REQ    0x7U
3447 #define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
3448 #define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
3449 
3450 #define S_DEBUG_ST_EDMA1_ALIGN_SUB    13
3451 #define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
3452 #define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
3453 #define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
3454 
3455 #define S_DEBUG_ST_EDMA1_ALIGN    11
3456 #define M_DEBUG_ST_EDMA1_ALIGN    0x3U
3457 #define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
3458 #define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
3459 
3460 #define S_DEBUG_ST_EDMA1_REQ    8
3461 #define M_DEBUG_ST_EDMA1_REQ    0x7U
3462 #define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
3463 #define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
3464 
3465 #define S_DEBUG_ST_EDMA0_ALIGN_SUB    5
3466 #define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
3467 #define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
3468 #define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
3469 
3470 #define S_DEBUG_ST_EDMA0_ALIGN    3
3471 #define M_DEBUG_ST_EDMA0_ALIGN    0x3U
3472 #define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
3473 #define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
3474 
3475 #define S_DEBUG_ST_EDMA0_REQ    0
3476 #define M_DEBUG_ST_EDMA0_REQ    0x7U
3477 #define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
3478 #define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
3479 
3480 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
3481 
3482 #define S_DEBUG_ST_FLM_DBPTR    30
3483 #define M_DEBUG_ST_FLM_DBPTR    0x3U
3484 #define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
3485 #define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
3486 
3487 #define S_DEBUG_FLM_CACHE_LOCKED_COUNT    23
3488 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
3489 #define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
3490 #define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
3491 
3492 #define S_DEBUG_FLM_CACHE_AGENT    20
3493 #define M_DEBUG_FLM_CACHE_AGENT    0x7U
3494 #define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
3495 #define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
3496 
3497 #define S_DEBUG_ST_FLM_CACHE    16
3498 #define M_DEBUG_ST_FLM_CACHE    0xfU
3499 #define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
3500 #define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
3501 
3502 #define S_DEBUG_FLM_DBPTR_CIDX_STALL    12
3503 #define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
3504 #define F_DEBUG_FLM_DBPTR_CIDX_STALL    V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
3505 
3506 #define S_DEBUG_FLM_DBPTR_QID    0
3507 #define M_DEBUG_FLM_DBPTR_QID    0xfffU
3508 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
3509 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
3510 
3511 #define A_SGE_DEBUG0_DBP_THREAD 0x12d4
3512 
3513 #define S_THREAD_ST_MAIN    25
3514 #define M_THREAD_ST_MAIN    0x3fU
3515 #define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN)
3516 #define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN)
3517 
3518 #define S_THREAD_ST_CIMFL    21
3519 #define M_THREAD_ST_CIMFL    0xfU
3520 #define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL)
3521 #define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL)
3522 
3523 #define S_THREAD_CMDOP    17
3524 #define M_THREAD_CMDOP    0xfU
3525 #define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP)
3526 #define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP)
3527 
3528 #define S_THREAD_QID    0
3529 #define M_THREAD_QID    0x1ffffU
3530 #define V_THREAD_QID(x) ((x) << S_THREAD_QID)
3531 #define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID)
3532 
3533 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
3534 
3535 #define S_DEBUG_DBP_THREAD0_QID    0
3536 #define M_DEBUG_DBP_THREAD0_QID    0x1ffffU
3537 #define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
3538 #define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
3539 
3540 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
3541 
3542 #define S_DEBUG_DBP_THREAD1_QID    0
3543 #define M_DEBUG_DBP_THREAD1_QID    0x1ffffU
3544 #define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
3545 #define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
3546 
3547 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
3548 
3549 #define S_DEBUG_DBP_THREAD2_QID    0
3550 #define M_DEBUG_DBP_THREAD2_QID    0x1ffffU
3551 #define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
3552 #define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
3553 
3554 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
3555 
3556 #define S_DEBUG_DBP_THREAD3_QID    0
3557 #define M_DEBUG_DBP_THREAD3_QID    0x1ffffU
3558 #define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
3559 #define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
3560 
3561 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
3562 
3563 #define S_DEBUG_IMSG_CPL    16
3564 #define M_DEBUG_IMSG_CPL    0xffU
3565 #define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
3566 #define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
3567 
3568 #define S_DEBUG_IMSG_QID    0
3569 #define M_DEBUG_IMSG_QID    0xffffU
3570 #define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
3571 #define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
3572 
3573 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
3574 
3575 #define S_DEBUG_IDMA1_QID    16
3576 #define M_DEBUG_IDMA1_QID    0xffffU
3577 #define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
3578 #define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
3579 
3580 #define S_DEBUG_IDMA0_QID    0
3581 #define M_DEBUG_IDMA0_QID    0xffffU
3582 #define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
3583 #define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
3584 
3585 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
3586 
3587 #define S_DEBUG_IDMA1_FLM_REQ_QID    16
3588 #define M_DEBUG_IDMA1_FLM_REQ_QID    0xffffU
3589 #define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
3590 #define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
3591 
3592 #define S_DEBUG_IDMA0_FLM_REQ_QID    0
3593 #define M_DEBUG_IDMA0_FLM_REQ_QID    0xffffU
3594 #define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
3595 #define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
3596 
3597 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
3598 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
3599 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
3600 #define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300
3601 
3602 #define S_PFIQSPERPAGE    28
3603 #define M_PFIQSPERPAGE    0xfU
3604 #define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE)
3605 #define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE)
3606 
3607 #define S_PFEQSPERPAGE    24
3608 #define M_PFEQSPERPAGE    0xfU
3609 #define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE)
3610 #define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE)
3611 
3612 #define S_PFWCQSPERPAGE    20
3613 #define M_PFWCQSPERPAGE    0xfU
3614 #define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE)
3615 #define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE)
3616 
3617 #define S_PFWCOFFEN    19
3618 #define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN)
3619 #define F_PFWCOFFEN    V_PFWCOFFEN(1U)
3620 
3621 #define S_PFMAXWCSIZE    17
3622 #define M_PFMAXWCSIZE    0x3U
3623 #define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE)
3624 #define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE)
3625 
3626 #define S_PFWCOFFSET    0
3627 #define M_PFWCOFFSET    0x1ffffU
3628 #define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET)
3629 #define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET)
3630 
3631 #define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320
3632 
3633 #define S_VFIQSPERPAGE    28
3634 #define M_VFIQSPERPAGE    0xfU
3635 #define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE)
3636 #define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE)
3637 
3638 #define S_VFEQSPERPAGE    24
3639 #define M_VFEQSPERPAGE    0xfU
3640 #define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE)
3641 #define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE)
3642 
3643 #define S_VFWCQSPERPAGE    20
3644 #define M_VFWCQSPERPAGE    0xfU
3645 #define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE)
3646 #define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE)
3647 
3648 #define S_VFWCOFFEN    19
3649 #define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN)
3650 #define F_VFWCOFFEN    V_VFWCOFFEN(1U)
3651 
3652 #define S_VFMAXWCSIZE    17
3653 #define M_VFMAXWCSIZE    0x3U
3654 #define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE)
3655 #define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE)
3656 
3657 #define S_VFWCOFFSET    0
3658 #define M_VFWCOFFSET    0x1ffffU
3659 #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
3660 #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)
3661 
3662 #define A_SGE_LA_RDPTR_0 0x1800
3663 #define A_SGE_LA_RDDATA_0 0x1804
3664 #define A_SGE_LA_WRPTR_0 0x1808
3665 #define A_SGE_LA_RESERVED_0 0x180c
3666 #define A_SGE_LA_RDPTR_1 0x1810
3667 #define A_SGE_LA_RDDATA_1 0x1814
3668 #define A_SGE_LA_WRPTR_1 0x1818
3669 #define A_SGE_LA_RESERVED_1 0x181c
3670 #define A_SGE_LA_RDPTR_2 0x1820
3671 #define A_SGE_LA_RDDATA_2 0x1824
3672 #define A_SGE_LA_WRPTR_2 0x1828
3673 #define A_SGE_LA_RESERVED_2 0x182c
3674 #define A_SGE_LA_RDPTR_3 0x1830
3675 #define A_SGE_LA_RDDATA_3 0x1834
3676 #define A_SGE_LA_WRPTR_3 0x1838
3677 #define A_SGE_LA_RESERVED_3 0x183c
3678 #define A_SGE_LA_RDPTR_4 0x1840
3679 #define A_SGE_LA_RDDATA_4 0x1844
3680 #define A_SGE_LA_WRPTR_4 0x1848
3681 #define A_SGE_LA_RESERVED_4 0x184c
3682 #define A_SGE_LA_RDPTR_5 0x1850
3683 #define A_SGE_LA_RDDATA_5 0x1854
3684 #define A_SGE_LA_WRPTR_5 0x1858
3685 #define A_SGE_LA_RESERVED_5 0x185c
3686 #define A_SGE_LA_RDPTR_6 0x1860
3687 #define A_SGE_LA_RDDATA_6 0x1864
3688 #define A_SGE_LA_WRPTR_6 0x1868
3689 #define A_SGE_LA_RESERVED_6 0x186c
3690 #define A_SGE_LA_RDPTR_7 0x1870
3691 #define A_SGE_LA_RDDATA_7 0x1874
3692 #define A_SGE_LA_WRPTR_7 0x1878
3693 #define A_SGE_LA_RESERVED_7 0x187c
3694 #define A_SGE_LA_RDPTR_8 0x1880
3695 #define A_SGE_LA_RDDATA_8 0x1884
3696 #define A_SGE_LA_WRPTR_8 0x1888
3697 #define A_SGE_LA_RESERVED_8 0x188c
3698 #define A_SGE_LA_RDPTR_9 0x1890
3699 #define A_SGE_LA_RDDATA_9 0x1894
3700 #define A_SGE_LA_WRPTR_9 0x1898
3701 #define A_SGE_LA_RESERVED_9 0x189c
3702 #define A_SGE_LA_RDPTR_10 0x18a0
3703 #define A_SGE_LA_RDDATA_10 0x18a4
3704 #define A_SGE_LA_WRPTR_10 0x18a8
3705 #define A_SGE_LA_RESERVED_10 0x18ac
3706 #define A_SGE_LA_RDPTR_11 0x18b0
3707 #define A_SGE_LA_RDDATA_11 0x18b4
3708 #define A_SGE_LA_WRPTR_11 0x18b8
3709 #define A_SGE_LA_RESERVED_11 0x18bc
3710 #define A_SGE_LA_RDPTR_12 0x18c0
3711 #define A_SGE_LA_RDDATA_12 0x18c4
3712 #define A_SGE_LA_WRPTR_12 0x18c8
3713 #define A_SGE_LA_RESERVED_12 0x18cc
3714 #define A_SGE_LA_RDPTR_13 0x18d0
3715 #define A_SGE_LA_RDDATA_13 0x18d4
3716 #define A_SGE_LA_WRPTR_13 0x18d8
3717 #define A_SGE_LA_RESERVED_13 0x18dc
3718 #define A_SGE_LA_RDPTR_14 0x18e0
3719 #define A_SGE_LA_RDDATA_14 0x18e4
3720 #define A_SGE_LA_WRPTR_14 0x18e8
3721 #define A_SGE_LA_RESERVED_14 0x18ec
3722 #define A_SGE_LA_RDPTR_15 0x18f0
3723 #define A_SGE_LA_RDDATA_15 0x18f4
3724 #define A_SGE_LA_WRPTR_15 0x18f8
3725 #define A_SGE_LA_RESERVED_15 0x18fc
3726 
3727 /* registers for module PCIE */
3728 #define PCIE_BASE_ADDR 0x3000
3729 
3730 #define A_PCIE_PF_CFG 0x40
3731 
3732 #define S_AIVEC    4
3733 #define M_AIVEC    0x3ffU
3734 #define V_AIVEC(x) ((x) << S_AIVEC)
3735 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
3736 
3737 #define A_PCIE_PF_CLI 0x44
3738 #define A_PCIE_PF_EXPROM_OFST 0x4c
3739 
3740 #define S_OFFSET    10
3741 #define M_OFFSET    0x3fffU
3742 #define V_OFFSET(x) ((x) << S_OFFSET)
3743 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
3744 
3745 #define A_PCIE_INT_CAUSE 0x3004
3746 
3747 #define S_NONFATALERR    30
3748 #define V_NONFATALERR(x) ((x) << S_NONFATALERR)
3749 #define F_NONFATALERR    V_NONFATALERR(1U)
3750 
3751 #define S_UNXSPLCPLERR    29
3752 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
3753 #define F_UNXSPLCPLERR    V_UNXSPLCPLERR(1U)
3754 
3755 #define S_PCIEPINT    28
3756 #define V_PCIEPINT(x) ((x) << S_PCIEPINT)
3757 #define F_PCIEPINT    V_PCIEPINT(1U)
3758 
3759 #define S_PCIESINT    27
3760 #define V_PCIESINT(x) ((x) << S_PCIESINT)
3761 #define F_PCIESINT    V_PCIESINT(1U)
3762 
3763 #define S_RPLPERR    26
3764 #define V_RPLPERR(x) ((x) << S_RPLPERR)
3765 #define F_RPLPERR    V_RPLPERR(1U)
3766 
3767 #define S_RXWRPERR    25
3768 #define V_RXWRPERR(x) ((x) << S_RXWRPERR)
3769 #define F_RXWRPERR    V_RXWRPERR(1U)
3770 
3771 #define S_RXCPLPERR    24
3772 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
3773 #define F_RXCPLPERR    V_RXCPLPERR(1U)
3774 
3775 #define S_PIOTAGPERR    23
3776 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
3777 #define F_PIOTAGPERR    V_PIOTAGPERR(1U)
3778 
3779 #define S_MATAGPERR    22
3780 #define V_MATAGPERR(x) ((x) << S_MATAGPERR)
3781 #define F_MATAGPERR    V_MATAGPERR(1U)
3782 
3783 #define S_INTXCLRPERR    21
3784 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
3785 #define F_INTXCLRPERR    V_INTXCLRPERR(1U)
3786 
3787 #define S_FIDPERR    20
3788 #define V_FIDPERR(x) ((x) << S_FIDPERR)
3789 #define F_FIDPERR    V_FIDPERR(1U)
3790 
3791 #define S_CFGSNPPERR    19
3792 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
3793 #define F_CFGSNPPERR    V_CFGSNPPERR(1U)
3794 
3795 #define S_HRSPPERR    18
3796 #define V_HRSPPERR(x) ((x) << S_HRSPPERR)
3797 #define F_HRSPPERR    V_HRSPPERR(1U)
3798 
3799 #define S_HREQPERR    17
3800 #define V_HREQPERR(x) ((x) << S_HREQPERR)
3801 #define F_HREQPERR    V_HREQPERR(1U)
3802 
3803 #define S_HCNTPERR    16
3804 #define V_HCNTPERR(x) ((x) << S_HCNTPERR)
3805 #define F_HCNTPERR    V_HCNTPERR(1U)
3806 
3807 #define S_DRSPPERR    15
3808 #define V_DRSPPERR(x) ((x) << S_DRSPPERR)
3809 #define F_DRSPPERR    V_DRSPPERR(1U)
3810 
3811 #define S_DREQPERR    14
3812 #define V_DREQPERR(x) ((x) << S_DREQPERR)
3813 #define F_DREQPERR    V_DREQPERR(1U)
3814 
3815 #define S_DCNTPERR    13
3816 #define V_DCNTPERR(x) ((x) << S_DCNTPERR)
3817 #define F_DCNTPERR    V_DCNTPERR(1U)
3818 
3819 #define S_CRSPPERR    12
3820 #define V_CRSPPERR(x) ((x) << S_CRSPPERR)
3821 #define F_CRSPPERR    V_CRSPPERR(1U)
3822 
3823 #define S_CREQPERR    11
3824 #define V_CREQPERR(x) ((x) << S_CREQPERR)
3825 #define F_CREQPERR    V_CREQPERR(1U)
3826 
3827 #define S_CCNTPERR    10
3828 #define V_CCNTPERR(x) ((x) << S_CCNTPERR)
3829 #define F_CCNTPERR    V_CCNTPERR(1U)
3830 
3831 #define S_TARTAGPERR    9
3832 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
3833 #define F_TARTAGPERR    V_TARTAGPERR(1U)
3834 
3835 #define S_PIOREQPERR    8
3836 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
3837 #define F_PIOREQPERR    V_PIOREQPERR(1U)
3838 
3839 #define S_PIOCPLPERR    7
3840 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
3841 #define F_PIOCPLPERR    V_PIOCPLPERR(1U)
3842 
3843 #define S_MSIXDIPERR    6
3844 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
3845 #define F_MSIXDIPERR    V_MSIXDIPERR(1U)
3846 
3847 #define S_MSIXDATAPERR    5
3848 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
3849 #define F_MSIXDATAPERR    V_MSIXDATAPERR(1U)
3850 
3851 #define S_MSIXADDRHPERR    4
3852 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
3853 #define F_MSIXADDRHPERR    V_MSIXADDRHPERR(1U)
3854 
3855 #define S_MSIXADDRLPERR    3
3856 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
3857 #define F_MSIXADDRLPERR    V_MSIXADDRLPERR(1U)
3858 
3859 #define S_MSIDATAPERR    2
3860 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
3861 #define F_MSIDATAPERR    V_MSIDATAPERR(1U)
3862 
3863 #define S_MSIADDRHPERR    1
3864 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
3865 #define F_MSIADDRHPERR    V_MSIADDRHPERR(1U)
3866 
3867 #define S_MSIADDRLPERR    0
3868 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
3869 #define F_MSIADDRLPERR    V_MSIADDRLPERR(1U)
3870 
3871 #define S_IPGRPPERR    31
3872 #define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
3873 #define F_IPGRPPERR    V_IPGRPPERR(1U)
3874 
3875 #define S_READRSPERR    29
3876 #define V_READRSPERR(x) ((x) << S_READRSPERR)
3877 #define F_READRSPERR    V_READRSPERR(1U)
3878 
3879 #define S_TRGT1GRPPERR    28
3880 #define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
3881 #define F_TRGT1GRPPERR    V_TRGT1GRPPERR(1U)
3882 
3883 #define S_IPSOTPERR    27
3884 #define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
3885 #define F_IPSOTPERR    V_IPSOTPERR(1U)
3886 
3887 #define S_IPRETRYPERR    26
3888 #define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
3889 #define F_IPRETRYPERR    V_IPRETRYPERR(1U)
3890 
3891 #define S_IPRXDATAGRPPERR    25
3892 #define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
3893 #define F_IPRXDATAGRPPERR    V_IPRXDATAGRPPERR(1U)
3894 
3895 #define S_IPRXHDRGRPPERR    24
3896 #define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
3897 #define F_IPRXHDRGRPPERR    V_IPRXHDRGRPPERR(1U)
3898 
3899 #define S_PIOTAGQPERR    23
3900 #define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
3901 #define F_PIOTAGQPERR    V_PIOTAGQPERR(1U)
3902 
3903 #define S_MAGRPPERR    22
3904 #define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
3905 #define F_MAGRPPERR    V_MAGRPPERR(1U)
3906 
3907 #define S_VFIDPERR    21
3908 #define V_VFIDPERR(x) ((x) << S_VFIDPERR)
3909 #define F_VFIDPERR    V_VFIDPERR(1U)
3910 
3911 #define S_HREQRDPERR    17
3912 #define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
3913 #define F_HREQRDPERR    V_HREQRDPERR(1U)
3914 
3915 #define S_HREQWRPERR    16
3916 #define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
3917 #define F_HREQWRPERR    V_HREQWRPERR(1U)
3918 
3919 #define S_DREQRDPERR    14
3920 #define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
3921 #define F_DREQRDPERR    V_DREQRDPERR(1U)
3922 
3923 #define S_DREQWRPERR    13
3924 #define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
3925 #define F_DREQWRPERR    V_DREQWRPERR(1U)
3926 
3927 #define S_CREQRDPERR    11
3928 #define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
3929 #define F_CREQRDPERR    V_CREQRDPERR(1U)
3930 
3931 #define S_MSTTAGQPERR    10
3932 #define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
3933 #define F_MSTTAGQPERR    V_MSTTAGQPERR(1U)
3934 
3935 #define S_TGTTAGQPERR    9
3936 #define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
3937 #define F_TGTTAGQPERR    V_TGTTAGQPERR(1U)
3938 
3939 #define S_PIOREQGRPPERR    8
3940 #define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
3941 #define F_PIOREQGRPPERR    V_PIOREQGRPPERR(1U)
3942 
3943 #define S_PIOCPLGRPPERR    7
3944 #define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
3945 #define F_PIOCPLGRPPERR    V_PIOCPLGRPPERR(1U)
3946 
3947 #define S_MSIXSTIPERR    2
3948 #define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
3949 #define F_MSIXSTIPERR    V_MSIXSTIPERR(1U)
3950 
3951 #define S_MSTTIMEOUTPERR    1
3952 #define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
3953 #define F_MSTTIMEOUTPERR    V_MSTTIMEOUTPERR(1U)
3954 
3955 #define S_MSTGRPPERR    0
3956 #define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
3957 #define F_MSTGRPPERR    V_MSTGRPPERR(1U)
3958 
3959 #define A_PCIE_NONFAT_ERR 0x3010
3960 
3961 #define S_RDRSPERR    9
3962 #define V_RDRSPERR(x) ((x) << S_RDRSPERR)
3963 #define F_RDRSPERR    V_RDRSPERR(1U)
3964 
3965 #define S_VPDRSPERR    8
3966 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
3967 #define F_VPDRSPERR    V_VPDRSPERR(1U)
3968 
3969 #define S_POPD    7
3970 #define V_POPD(x) ((x) << S_POPD)
3971 #define F_POPD    V_POPD(1U)
3972 
3973 #define S_POPH    6
3974 #define V_POPH(x) ((x) << S_POPH)
3975 #define F_POPH    V_POPH(1U)
3976 
3977 #define S_POPC    5
3978 #define V_POPC(x) ((x) << S_POPC)
3979 #define F_POPC    V_POPC(1U)
3980 
3981 #define S_MEMREQ    4
3982 #define V_MEMREQ(x) ((x) << S_MEMREQ)
3983 #define F_MEMREQ    V_MEMREQ(1U)
3984 
3985 #define S_PIOREQ    3
3986 #define V_PIOREQ(x) ((x) << S_PIOREQ)
3987 #define F_PIOREQ    V_PIOREQ(1U)
3988 
3989 #define S_TAGDROP    2
3990 #define V_TAGDROP(x) ((x) << S_TAGDROP)
3991 #define F_TAGDROP    V_TAGDROP(1U)
3992 
3993 #define S_TAGCPL    1
3994 #define V_TAGCPL(x) ((x) << S_TAGCPL)
3995 #define F_TAGCPL    V_TAGCPL(1U)
3996 
3997 #define S_CFGSNP    0
3998 #define V_CFGSNP(x) ((x) << S_CFGSNP)
3999 #define F_CFGSNP    V_CFGSNP(1U)
4000 
4001 #define S_MAREQTIMEOUT    29
4002 #define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
4003 #define F_MAREQTIMEOUT    V_MAREQTIMEOUT(1U)
4004 
4005 #define S_TRGT1BARTYPEERR    28
4006 #define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
4007 #define F_TRGT1BARTYPEERR    V_TRGT1BARTYPEERR(1U)
4008 
4009 #define S_MAEXTRARSPERR    27
4010 #define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
4011 #define F_MAEXTRARSPERR    V_MAEXTRARSPERR(1U)
4012 
4013 #define S_MARSPTIMEOUT    26
4014 #define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
4015 #define F_MARSPTIMEOUT    V_MARSPTIMEOUT(1U)
4016 
4017 #define S_INTVFALLMSIDISERR    25
4018 #define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
4019 #define F_INTVFALLMSIDISERR    V_INTVFALLMSIDISERR(1U)
4020 
4021 #define S_INTVFRANGEERR    24
4022 #define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
4023 #define F_INTVFRANGEERR    V_INTVFRANGEERR(1U)
4024 
4025 #define S_INTPLIRSPERR    23
4026 #define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
4027 #define F_INTPLIRSPERR    V_INTPLIRSPERR(1U)
4028 
4029 #define S_MEMREQRDTAGERR    22
4030 #define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
4031 #define F_MEMREQRDTAGERR    V_MEMREQRDTAGERR(1U)
4032 
4033 #define S_CFGINITDONEERR    21
4034 #define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
4035 #define F_CFGINITDONEERR    V_CFGINITDONEERR(1U)
4036 
4037 #define S_BAR2TIMEOUT    20
4038 #define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
4039 #define F_BAR2TIMEOUT    V_BAR2TIMEOUT(1U)
4040 
4041 #define S_VPDTIMEOUT    19
4042 #define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
4043 #define F_VPDTIMEOUT    V_VPDTIMEOUT(1U)
4044 
4045 #define S_MEMRSPRDTAGERR    18
4046 #define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
4047 #define F_MEMRSPRDTAGERR    V_MEMRSPRDTAGERR(1U)
4048 
4049 #define S_MEMRSPWRTAGERR    17
4050 #define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
4051 #define F_MEMRSPWRTAGERR    V_MEMRSPWRTAGERR(1U)
4052 
4053 #define S_PIORSPRDTAGERR    16
4054 #define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
4055 #define F_PIORSPRDTAGERR    V_PIORSPRDTAGERR(1U)
4056 
4057 #define S_PIORSPWRTAGERR    15
4058 #define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
4059 #define F_PIORSPWRTAGERR    V_PIORSPWRTAGERR(1U)
4060 
4061 #define S_DBITIMEOUT    14
4062 #define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
4063 #define F_DBITIMEOUT    V_DBITIMEOUT(1U)
4064 
4065 #define S_PIOUNALINDWR    13
4066 #define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
4067 #define F_PIOUNALINDWR    V_PIOUNALINDWR(1U)
4068 
4069 #define S_BAR2RDERR    12
4070 #define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
4071 #define F_BAR2RDERR    V_BAR2RDERR(1U)
4072 
4073 #define S_MAWREOPERR    11
4074 #define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
4075 #define F_MAWREOPERR    V_MAWREOPERR(1U)
4076 
4077 #define S_MARDEOPERR    10
4078 #define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
4079 #define F_MARDEOPERR    V_MARDEOPERR(1U)
4080 
4081 #define S_BAR2REQ    2
4082 #define V_BAR2REQ(x) ((x) << S_BAR2REQ)
4083 #define F_BAR2REQ    V_BAR2REQ(1U)
4084 
4085 #define S_MARSPUE    30
4086 #define V_MARSPUE(x) ((x) << S_MARSPUE)
4087 #define F_MARSPUE    V_MARSPUE(1U)
4088 
4089 #define S_KDBEOPERR    7
4090 #define V_KDBEOPERR(x) ((x) << S_KDBEOPERR)
4091 #define F_KDBEOPERR    V_KDBEOPERR(1U)
4092 
4093 #define A_PCIE_CFG2 0x3018
4094 
4095 #define S_TOTMAXTAG    0
4096 #define M_TOTMAXTAG    0x7U
4097 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
4098 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
4099 
4100 #define A_PCIE_CFG_SPACE_REQ 0x3060
4101 
4102 #define S_ENABLE    30
4103 #define V_ENABLE(x) ((x) << S_ENABLE)
4104 #define F_ENABLE    V_ENABLE(1U)
4105 
4106 #define S_AI    29
4107 #define V_AI(x) ((x) << S_AI)
4108 #define F_AI    V_AI(1U)
4109 
4110 #define S_LOCALCFG    28
4111 #define V_LOCALCFG(x) ((x) << S_LOCALCFG)
4112 #define F_LOCALCFG    V_LOCALCFG(1U)
4113 
4114 #define S_BUS    20
4115 #define M_BUS    0xffU
4116 #define V_BUS(x) ((x) << S_BUS)
4117 #define G_BUS(x) (((x) >> S_BUS) & M_BUS)
4118 
4119 #define S_DEVICE    15
4120 #define M_DEVICE    0x1fU
4121 #define V_DEVICE(x) ((x) << S_DEVICE)
4122 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
4123 
4124 #define S_FUNCTION    12
4125 #define M_FUNCTION    0x7U
4126 #define V_FUNCTION(x) ((x) << S_FUNCTION)
4127 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
4128 
4129 #define S_EXTREGISTER    8
4130 #define M_EXTREGISTER    0xfU
4131 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
4132 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
4133 
4134 #define S_REGISTER    0
4135 #define M_REGISTER    0xffU
4136 #define V_REGISTER(x) ((x) << S_REGISTER)
4137 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
4138 
4139 #define S_CS2    28
4140 #define V_CS2(x) ((x) << S_CS2)
4141 #define F_CS2    V_CS2(1U)
4142 
4143 #define S_WRBE    24
4144 #define M_WRBE    0xfU
4145 #define V_WRBE(x) ((x) << S_WRBE)
4146 #define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
4147 
4148 #define S_CFG_SPACE_VFVLD    23
4149 #define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
4150 #define F_CFG_SPACE_VFVLD    V_CFG_SPACE_VFVLD(1U)
4151 
4152 #define S_CFG_SPACE_RVF    16
4153 #define M_CFG_SPACE_RVF    0x7fU
4154 #define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
4155 #define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
4156 
4157 #define S_CFG_SPACE_PF    12
4158 #define M_CFG_SPACE_PF    0x7U
4159 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
4160 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
4161 
4162 #define S_T6_ENABLE    31
4163 #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
4164 #define F_T6_ENABLE    V_T6_ENABLE(1U)
4165 
4166 #define S_T6_AI    30
4167 #define V_T6_AI(x) ((x) << S_T6_AI)
4168 #define F_T6_AI    V_T6_AI(1U)
4169 
4170 #define S_T6_CS2    29
4171 #define V_T6_CS2(x) ((x) << S_T6_CS2)
4172 #define F_T6_CS2    V_T6_CS2(1U)
4173 
4174 #define S_T6_WRBE    25
4175 #define M_T6_WRBE    0xfU
4176 #define V_T6_WRBE(x) ((x) << S_T6_WRBE)
4177 #define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE)
4178 
4179 #define S_T6_CFG_SPACE_VFVLD    24
4180 #define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD)
4181 #define F_T6_CFG_SPACE_VFVLD    V_T6_CFG_SPACE_VFVLD(1U)
4182 
4183 #define S_T6_CFG_SPACE_RVF    16
4184 #define M_T6_CFG_SPACE_RVF    0xffU
4185 #define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF)
4186 #define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF)
4187 
4188 #define A_PCIE_CFG_SPACE_DATA 0x3064
4189 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
4190 
4191 #define S_PCIEOFST    10
4192 #define M_PCIEOFST    0x3fffffU
4193 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
4194 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
4195 
4196 #define S_BIR    8
4197 #define M_BIR    0x3U
4198 #define V_BIR(x) ((x) << S_BIR)
4199 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
4200 
4201 #define S_WINDOW    0
4202 #define M_WINDOW    0xffU
4203 #define V_WINDOW(x) ((x) << S_WINDOW)
4204 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
4205 
4206 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
4207 
4208 #define S_MEMOFST    7
4209 #define M_MEMOFST    0x1ffffffU
4210 #define V_MEMOFST(x) ((x) << S_MEMOFST)
4211 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
4212 
4213 #define S_PFNUM    0
4214 #define M_PFNUM    0x7U
4215 #define V_PFNUM(x) ((x) << S_PFNUM)
4216 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
4217 
4218 #define A_PCIE_MA_SYNC 0x30b4
4219 #define A_PCIE_FW 0x30b8
4220 #define A_PCIE_FW_PF 0x30bc
4221 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
4222 
4223 #define S_NUM_LANES    8
4224 #define M_NUM_LANES    0x1fU
4225 #define V_NUM_LANES(x) ((x) << S_NUM_LANES)
4226 #define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
4227 
4228 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
4229 
4230 #define S_RNPP    31
4231 #define V_RNPP(x) ((x) << S_RNPP)
4232 #define F_RNPP    V_RNPP(1U)
4233 
4234 #define S_RPCP    29
4235 #define V_RPCP(x) ((x) << S_RPCP)
4236 #define F_RPCP    V_RPCP(1U)
4237 
4238 #define S_RCIP    27
4239 #define V_RCIP(x) ((x) << S_RCIP)
4240 #define F_RCIP    V_RCIP(1U)
4241 
4242 #define S_RCCP    26
4243 #define V_RCCP(x) ((x) << S_RCCP)
4244 #define F_RCCP    V_RCCP(1U)
4245 
4246 #define S_RFTP    23
4247 #define V_RFTP(x) ((x) << S_RFTP)
4248 #define F_RFTP    V_RFTP(1U)
4249 
4250 #define S_PTRP    20
4251 #define V_PTRP(x) ((x) << S_PTRP)
4252 #define F_PTRP    V_PTRP(1U)
4253 
4254 #define A_PCIE_T5_DMA_STAT2 0x5948
4255 
4256 #define S_COOKIECNT    24
4257 #define M_COOKIECNT    0xfU
4258 #define V_COOKIECNT(x) ((x) << S_COOKIECNT)
4259 #define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
4260 
4261 #define S_RDSEQNUMUPDCNT    20
4262 #define M_RDSEQNUMUPDCNT    0xfU
4263 #define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
4264 #define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
4265 
4266 #define S_SIREQCNT    16
4267 #define M_SIREQCNT    0xfU
4268 #define V_SIREQCNT(x) ((x) << S_SIREQCNT)
4269 #define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
4270 
4271 #define S_WREOPMATCHSOP    12
4272 #define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
4273 #define F_WREOPMATCHSOP    V_WREOPMATCHSOP(1U)
4274 
4275 #define S_WRSOPCNT    8
4276 #define M_WRSOPCNT    0xfU
4277 #define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
4278 #define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
4279 
4280 #define S_RDSOPCNT    0
4281 #define M_RDSOPCNT    0xffU
4282 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
4283 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
4284 
4285 #define A_PCIE_T5_DMA_STAT3 0x594c
4286 
4287 #define S_ATMREQSOPCNT    24
4288 #define M_ATMREQSOPCNT    0xffU
4289 #define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
4290 #define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
4291 
4292 #define S_ATMEOPMATCHSOP    17
4293 #define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
4294 #define F_ATMEOPMATCHSOP    V_ATMEOPMATCHSOP(1U)
4295 
4296 #define S_RSPEOPMATCHSOP    16
4297 #define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
4298 #define F_RSPEOPMATCHSOP    V_RSPEOPMATCHSOP(1U)
4299 
4300 #define S_RSPERRCNT    8
4301 #define M_RSPERRCNT    0xffU
4302 #define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
4303 #define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
4304 
4305 #define S_RSPSOPCNT    0
4306 #define M_RSPSOPCNT    0xffU
4307 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
4308 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
4309 
4310 #define A_PCIE_T5_CMD_STAT2 0x5988
4311 #define A_PCIE_T5_CMD_STAT3 0x598c
4312 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
4313 
4314 #define S_TPCP    30
4315 #define V_TPCP(x) ((x) << S_TPCP)
4316 #define F_TPCP    V_TPCP(1U)
4317 
4318 #define S_TNPP    29
4319 #define V_TNPP(x) ((x) << S_TNPP)
4320 #define F_TNPP    V_TNPP(1U)
4321 
4322 #define S_TFTP    28
4323 #define V_TFTP(x) ((x) << S_TFTP)
4324 #define F_TFTP    V_TFTP(1U)
4325 
4326 #define S_TCAP    27
4327 #define V_TCAP(x) ((x) << S_TCAP)
4328 #define F_TCAP    V_TCAP(1U)
4329 
4330 #define S_TCIP    26
4331 #define V_TCIP(x) ((x) << S_TCIP)
4332 #define F_TCIP    V_TCIP(1U)
4333 
4334 #define S_RCAP    25
4335 #define V_RCAP(x) ((x) << S_RCAP)
4336 #define F_RCAP    V_RCAP(1U)
4337 
4338 #define S_PLUP    23
4339 #define V_PLUP(x) ((x) << S_PLUP)
4340 #define F_PLUP    V_PLUP(1U)
4341 
4342 #define S_PLDN    22
4343 #define V_PLDN(x) ((x) << S_PLDN)
4344 #define F_PLDN    V_PLDN(1U)
4345 
4346 #define S_OTDD    21
4347 #define V_OTDD(x) ((x) << S_OTDD)
4348 #define F_OTDD    V_OTDD(1U)
4349 
4350 #define S_GTRP    20
4351 #define V_GTRP(x) ((x) << S_GTRP)
4352 #define F_GTRP    V_GTRP(1U)
4353 
4354 #define S_RDPE    18
4355 #define V_RDPE(x) ((x) << S_RDPE)
4356 #define F_RDPE    V_RDPE(1U)
4357 
4358 #define S_TDCE    17
4359 #define V_TDCE(x) ((x) << S_TDCE)
4360 #define F_TDCE    V_TDCE(1U)
4361 
4362 #define S_TDUE    16
4363 #define V_TDUE(x) ((x) << S_TDUE)
4364 #define F_TDUE    V_TDUE(1U)
4365 
4366 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
4367 
4368 #define S_PTOM    31
4369 #define V_PTOM(x) ((x) << S_PTOM)
4370 #define F_PTOM    V_PTOM(1U)
4371 
4372 #define S_ALEA    29
4373 #define V_ALEA(x) ((x) << S_ALEA)
4374 #define F_ALEA    V_ALEA(1U)
4375 
4376 #define S_PMC0    23
4377 #define V_PMC0(x) ((x) << S_PMC0)
4378 #define F_PMC0    V_PMC0(1U)
4379 
4380 #define S_PMC1    22
4381 #define V_PMC1(x) ((x) << S_PMC1)
4382 #define F_PMC1    V_PMC1(1U)
4383 
4384 #define S_PMC2    21
4385 #define V_PMC2(x) ((x) << S_PMC2)
4386 #define F_PMC2    V_PMC2(1U)
4387 
4388 #define S_PMC3    20
4389 #define V_PMC3(x) ((x) << S_PMC3)
4390 #define F_PMC3    V_PMC3(1U)
4391 
4392 #define S_PMC4    19
4393 #define V_PMC4(x) ((x) << S_PMC4)
4394 #define F_PMC4    V_PMC4(1U)
4395 
4396 #define S_PMC5    18
4397 #define V_PMC5(x) ((x) << S_PMC5)
4398 #define F_PMC5    V_PMC5(1U)
4399 
4400 #define S_PMC6    17
4401 #define V_PMC6(x) ((x) << S_PMC6)
4402 #define F_PMC6    V_PMC6(1U)
4403 
4404 #define S_PMC7    16
4405 #define V_PMC7(x) ((x) << S_PMC7)
4406 #define F_PMC7    V_PMC7(1U)
4407 
4408 #define A_PCIE_CHANGESET 0x59fc
4409 #define A_PCIE_REVISION 0x5a00
4410 #define A_PCIE_PDEBUG_INDEX 0x5a04
4411 
4412 #define S_PDEBUGSELH    16
4413 #define M_PDEBUGSELH    0x3fU
4414 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
4415 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
4416 
4417 #define S_PDEBUGSELL    0
4418 #define M_PDEBUGSELL    0x3fU
4419 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
4420 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
4421 
4422 #define S_T6_PDEBUGSELH    16
4423 #define M_T6_PDEBUGSELH    0x7fU
4424 #define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH)
4425 #define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH)
4426 
4427 #define S_T6_PDEBUGSELL    0
4428 #define M_T6_PDEBUGSELL    0x7fU
4429 #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
4430 #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)
4431 
4432 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
4433 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
4434 #define A_PCIE_CDEBUG_INDEX 0x5a10
4435 
4436 #define S_CDEBUGSELH    16
4437 #define M_CDEBUGSELH    0xffU
4438 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
4439 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
4440 
4441 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
4442 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
4443 
4444 #define S_CH3    24
4445 #define M_CH3    0xffU
4446 #define V_CH3(x) ((x) << S_CH3)
4447 #define G_CH3(x) (((x) >> S_CH3) & M_CH3)
4448 
4449 #define S_CH2    16
4450 #define M_CH2    0xffU
4451 #define V_CH2(x) ((x) << S_CH2)
4452 #define G_CH2(x) (((x) >> S_CH2) & M_CH2)
4453 
4454 #define S_CH1    8
4455 #define M_CH1    0xffU
4456 #define V_CH1(x) ((x) << S_CH1)
4457 #define G_CH1(x) (((x) >> S_CH1) & M_CH1)
4458 
4459 #define S_CH0    0
4460 #define M_CH0    0xffU
4461 #define V_CH0(x) ((x) << S_CH0)
4462 #define G_CH0(x) (((x) >> S_CH0) & M_CH0)
4463 
4464 #define A_PCIE_DMAW_EOP_CNT 0x5a20
4465 #define A_PCIE_DMAR_REQ_CNT 0x5a24
4466 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
4467 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
4468 #define A_PCIE_DMAI_CNT 0x5a34
4469 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
4470 #define A_PCIE_CMDR_RSP_CNT 0x5a40
4471 
4472 #define S_CH1_EOP    24
4473 #define M_CH1_EOP    0xffU
4474 #define V_CH1_EOP(x) ((x) << S_CH1_EOP)
4475 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
4476 
4477 #define S_CH1_SOP    16
4478 #define M_CH1_SOP    0xffU
4479 #define V_CH1_SOP(x) ((x) << S_CH1_SOP)
4480 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
4481 
4482 #define S_CH0_EOP    8
4483 #define M_CH0_EOP    0xffU
4484 #define V_CH0_EOP(x) ((x) << S_CH0_EOP)
4485 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
4486 
4487 #define S_CH0_SOP    0
4488 #define M_CH0_SOP    0xffU
4489 #define V_CH0_SOP(x) ((x) << S_CH0_SOP)
4490 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
4491 
4492 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
4493 
4494 #define S_KDB_PF_LEN    24
4495 #define M_KDB_PF_LEN    0x1fU
4496 #define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN)
4497 #define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN)
4498 
4499 #define S_KDB_PF_BASEADDR    0
4500 #define M_KDB_PF_BASEADDR    0xfffffU
4501 #define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR)
4502 #define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR)
4503 
4504 #define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14
4505 
4506 #define S_KDB_VF_LEN    24
4507 #define M_KDB_VF_LEN    0x1fU
4508 #define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN)
4509 #define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN)
4510 
4511 #define S_KDB_VF_BASEADDR    0
4512 #define M_KDB_VF_BASEADDR    0xfffffU
4513 #define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR)
4514 #define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR)
4515 
4516 #define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18
4517 
4518 #define S_KDB_VF_MODOFST    0
4519 #define M_KDB_VF_MODOFST    0xfffU
4520 #define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST)
4521 #define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST)
4522 
4523 #define A_PCIE_TGT_SKID_FIFO 0x5e94
4524 
4525 #define S_HDRFREECNT    16
4526 #define M_HDRFREECNT    0xfffU
4527 #define V_HDRFREECNT(x) ((x) << S_HDRFREECNT)
4528 #define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT)
4529 
4530 #define S_DATAFREECNT    0
4531 #define M_DATAFREECNT    0xfffU
4532 #define V_DATAFREECNT(x) ((x) << S_DATAFREECNT)
4533 #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)
4534 
4535 
4536 /* registers for module DBG */
4537 #define DBG_BASE_ADDR 0x6000
4538 
4539 #define A_DBG_GPIO_EN 0x6010
4540 
4541 #define S_GPIO15_OEN    31
4542 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
4543 #define F_GPIO15_OEN    V_GPIO15_OEN(1U)
4544 
4545 #define S_GPIO14_OEN    30
4546 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
4547 #define F_GPIO14_OEN    V_GPIO14_OEN(1U)
4548 
4549 #define S_GPIO13_OEN    29
4550 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
4551 #define F_GPIO13_OEN    V_GPIO13_OEN(1U)
4552 
4553 #define S_GPIO12_OEN    28
4554 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
4555 #define F_GPIO12_OEN    V_GPIO12_OEN(1U)
4556 
4557 #define S_GPIO11_OEN    27
4558 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
4559 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
4560 
4561 #define S_GPIO10_OEN    26
4562 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
4563 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
4564 
4565 #define S_GPIO9_OEN    25
4566 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
4567 #define F_GPIO9_OEN    V_GPIO9_OEN(1U)
4568 
4569 #define S_GPIO8_OEN    24
4570 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
4571 #define F_GPIO8_OEN    V_GPIO8_OEN(1U)
4572 
4573 #define S_GPIO7_OEN    23
4574 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
4575 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
4576 
4577 #define S_GPIO6_OEN    22
4578 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
4579 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
4580 
4581 #define S_GPIO5_OEN    21
4582 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
4583 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
4584 
4585 #define S_GPIO4_OEN    20
4586 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
4587 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
4588 
4589 #define S_GPIO3_OEN    19
4590 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
4591 #define F_GPIO3_OEN    V_GPIO3_OEN(1U)
4592 
4593 #define S_GPIO2_OEN    18
4594 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
4595 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
4596 
4597 #define S_GPIO1_OEN    17
4598 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
4599 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
4600 
4601 #define S_GPIO0_OEN    16
4602 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
4603 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
4604 
4605 #define S_GPIO15_OUT_VAL    15
4606 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
4607 #define F_GPIO15_OUT_VAL    V_GPIO15_OUT_VAL(1U)
4608 
4609 #define S_GPIO14_OUT_VAL    14
4610 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
4611 #define F_GPIO14_OUT_VAL    V_GPIO14_OUT_VAL(1U)
4612 
4613 #define S_GPIO13_OUT_VAL    13
4614 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
4615 #define F_GPIO13_OUT_VAL    V_GPIO13_OUT_VAL(1U)
4616 
4617 #define S_GPIO12_OUT_VAL    12
4618 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
4619 #define F_GPIO12_OUT_VAL    V_GPIO12_OUT_VAL(1U)
4620 
4621 #define S_GPIO11_OUT_VAL    11
4622 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
4623 #define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
4624 
4625 #define S_GPIO10_OUT_VAL    10
4626 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
4627 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
4628 
4629 #define S_GPIO9_OUT_VAL    9
4630 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
4631 #define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
4632 
4633 #define S_GPIO8_OUT_VAL    8
4634 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
4635 #define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
4636 
4637 #define S_GPIO7_OUT_VAL    7
4638 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
4639 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
4640 
4641 #define S_GPIO6_OUT_VAL    6
4642 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
4643 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
4644 
4645 #define S_GPIO5_OUT_VAL    5
4646 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
4647 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
4648 
4649 #define S_GPIO4_OUT_VAL    4
4650 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
4651 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
4652 
4653 #define S_GPIO3_OUT_VAL    3
4654 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
4655 #define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
4656 
4657 #define S_GPIO2_OUT_VAL    2
4658 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
4659 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
4660 
4661 #define S_GPIO1_OUT_VAL    1
4662 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
4663 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
4664 
4665 #define S_GPIO0_OUT_VAL    0
4666 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
4667 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
4668 
4669 #define A_DBG_STATIC_C_PLL_CONF2 0x60d4
4670 
4671 #define S_STATIC_C_PLL_LOCKTUNE    0
4672 #define M_STATIC_C_PLL_LOCKTUNE    0x1fU
4673 #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
4674 #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)
4675 
4676 #define A_DBG_STATIC_C_PLL_CONF3 0x60d8
4677 
4678 #define S_STATIC_C_PLL_LOCKSEL    28
4679 #define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL)
4680 #define F_STATIC_C_PLL_LOCKSEL    V_STATIC_C_PLL_LOCKSEL(1U)
4681 
4682 #define S_STATIC_C_PLL_FFTUNE    12
4683 #define M_STATIC_C_PLL_FFTUNE    0xffffU
4684 #define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE)
4685 #define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE)
4686 
4687 #define A_DBG_STATIC_C_PLL_CONF5 0x60e0
4688 
4689 #define S_STATIC_C_PLL_VCVTUNE    22
4690 #define M_STATIC_C_PLL_VCVTUNE    0x7U
4691 #define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE)
4692 #define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE)
4693 
4694 #define S_STATIC_C_PLL_PREDIV_CNF5    8
4695 #define M_STATIC_C_PLL_PREDIV_CNF5    0x1fU
4696 #define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5)
4697 #define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5)
4698 
4699 #define A_DBG_STATIC_U_PLL_CONF2 0x60e8
4700 
4701 #define S_STATIC_U_PLL_LOCKTUNE    0
4702 #define M_STATIC_U_PLL_LOCKTUNE    0x1fU
4703 #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
4704 #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)
4705 
4706 #define A_DBG_STATIC_U_PLL_CONF3 0x60ec
4707 
4708 #define S_STATIC_U_PLL_LOCKSEL    28
4709 #define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL)
4710 #define F_STATIC_U_PLL_LOCKSEL    V_STATIC_U_PLL_LOCKSEL(1U)
4711 
4712 #define A_DBG_STATIC_KR_PLL_CONF1 0x60f8
4713 
4714 #define S_STATIC_KR_PLL_VBOOSTDIV    27
4715 #define M_STATIC_KR_PLL_VBOOSTDIV    0x7U
4716 #define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV)
4717 #define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV)
4718 
4719 #define S_STATIC_KR_PLL_BGOFFSET    11
4720 #define M_STATIC_KR_PLL_BGOFFSET    0xfU
4721 #define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET)
4722 #define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET)
4723 
4724 #define A_DBG_STATIC_KX_PLL_CONF1 0x6108
4725 
4726 #define S_STATIC_KX_PLL_VBOOSTDIV    27
4727 #define M_STATIC_KX_PLL_VBOOSTDIV    0x7U
4728 #define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV)
4729 #define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV)
4730 
4731 #define S_STATIC_KX_PLL_BGOFFSET    11
4732 #define M_STATIC_KX_PLL_BGOFFSET    0xfU
4733 #define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET)
4734 #define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET)
4735 
4736 
4737 /* registers for module MC */
4738 #define MC_BASE_ADDR 0x6200
4739 
4740 #define A_MC_PAR_CAUSE 0x7510
4741 
4742 #define S_ECC_UE_PAR_CAUSE    3
4743 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
4744 #define F_ECC_UE_PAR_CAUSE    V_ECC_UE_PAR_CAUSE(1U)
4745 
4746 #define S_ECC_CE_PAR_CAUSE    2
4747 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
4748 #define F_ECC_CE_PAR_CAUSE    V_ECC_CE_PAR_CAUSE(1U)
4749 
4750 #define S_FIFOR_PAR_CAUSE    1
4751 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
4752 #define F_FIFOR_PAR_CAUSE    V_FIFOR_PAR_CAUSE(1U)
4753 
4754 #define S_RDATA_FIFOR_PAR_CAUSE    0
4755 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
4756 #define F_RDATA_FIFOR_PAR_CAUSE    V_RDATA_FIFOR_PAR_CAUSE(1U)
4757 
4758 #define A_MC_INT_CAUSE 0x7518
4759 
4760 #define S_ECC_UE_INT_CAUSE    2
4761 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
4762 #define F_ECC_UE_INT_CAUSE    V_ECC_UE_INT_CAUSE(1U)
4763 
4764 #define S_ECC_CE_INT_CAUSE    1
4765 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
4766 #define F_ECC_CE_INT_CAUSE    V_ECC_CE_INT_CAUSE(1U)
4767 
4768 #define S_PERR_INT_CAUSE    0
4769 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
4770 #define F_PERR_INT_CAUSE    V_PERR_INT_CAUSE(1U)
4771 
4772 #define A_MC_ECC_STATUS 0x751c
4773 
4774 #define S_ECC_CECNT    16
4775 #define M_ECC_CECNT    0xffffU
4776 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
4777 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
4778 
4779 #define S_ECC_UECNT    0
4780 #define M_ECC_UECNT    0xffffU
4781 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
4782 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
4783 
4784 #define A_MC_BIST_CMD 0x7600
4785 
4786 #define S_START_BIST    31
4787 #define V_START_BIST(x) ((x) << S_START_BIST)
4788 #define F_START_BIST    V_START_BIST(1U)
4789 
4790 #define S_BIST_CMD_GAP    8
4791 #define M_BIST_CMD_GAP    0xffU
4792 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
4793 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
4794 
4795 #define S_BIST_OPCODE    0
4796 #define M_BIST_OPCODE    0x3U
4797 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
4798 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
4799 
4800 #define A_MC_BIST_CMD_ADDR 0x7604
4801 #define A_MC_BIST_CMD_LEN 0x7608
4802 #define A_MC_BIST_DATA_PATTERN 0x760c
4803 
4804 #define S_BIST_DATA_TYPE    0
4805 #define M_BIST_DATA_TYPE    0xfU
4806 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
4807 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
4808 
4809 #define A_MC_BIST_STATUS_RDATA 0x7688
4810 
4811 /* registers for module MA */
4812 #define MA_BASE_ADDR 0x7700
4813 
4814 #define A_MA_EDRAM0_BAR 0x77c0
4815 
4816 #define S_EDRAM0_BASE    16
4817 #define M_EDRAM0_BASE    0xfffU
4818 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
4819 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
4820 
4821 #define S_EDRAM0_SIZE    0
4822 #define M_EDRAM0_SIZE    0xfffU
4823 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
4824 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
4825 
4826 #define A_MA_EDRAM1_BAR 0x77c4
4827 
4828 #define S_EDRAM1_BASE    16
4829 #define M_EDRAM1_BASE    0xfffU
4830 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
4831 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
4832 
4833 #define S_EDRAM1_SIZE    0
4834 #define M_EDRAM1_SIZE    0xfffU
4835 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
4836 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
4837 
4838 #define A_MA_EXT_MEMORY_BAR 0x77c8
4839 
4840 #define S_EXT_MEM_BASE    16
4841 #define M_EXT_MEM_BASE    0xfffU
4842 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
4843 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
4844 
4845 #define S_EXT_MEM_SIZE    0
4846 #define M_EXT_MEM_SIZE    0xfffU
4847 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
4848 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
4849 
4850 #define A_MA_EXT_MEMORY0_BAR 0x77c8
4851 
4852 #define S_EXT_MEM0_BASE    16
4853 #define M_EXT_MEM0_BASE    0xfffU
4854 #define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
4855 #define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
4856 
4857 #define S_EXT_MEM0_SIZE    0
4858 #define M_EXT_MEM0_SIZE    0xfffU
4859 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
4860 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
4861 
4862 #define A_MA_TARGET_MEM_ENABLE 0x77d8
4863 
4864 #define S_HMA_ENABLE    3
4865 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
4866 #define F_HMA_ENABLE    V_HMA_ENABLE(1U)
4867 
4868 #define S_EXT_MEM_ENABLE    2
4869 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
4870 #define F_EXT_MEM_ENABLE    V_EXT_MEM_ENABLE(1U)
4871 
4872 #define S_EDRAM1_ENABLE    1
4873 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
4874 #define F_EDRAM1_ENABLE    V_EDRAM1_ENABLE(1U)
4875 
4876 #define S_EDRAM0_ENABLE    0
4877 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
4878 #define F_EDRAM0_ENABLE    V_EDRAM0_ENABLE(1U)
4879 
4880 #define S_HMA_MUX    5
4881 #define V_HMA_MUX(x) ((x) << S_HMA_MUX)
4882 #define F_HMA_MUX    V_HMA_MUX(1U)
4883 
4884 #define S_EXT_MEM1_ENABLE    4
4885 #define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
4886 #define F_EXT_MEM1_ENABLE    V_EXT_MEM1_ENABLE(1U)
4887 
4888 #define S_EXT_MEM0_ENABLE    2
4889 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
4890 #define F_EXT_MEM0_ENABLE    V_EXT_MEM0_ENABLE(1U)
4891 
4892 #define S_MC_SPLIT    6
4893 #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
4894 #define F_MC_SPLIT    V_MC_SPLIT(1U)
4895 
4896 #define A_MA_INT_CAUSE 0x77e0
4897 
4898 #define S_MEM_PERR_INT_CAUSE    1
4899 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
4900 #define F_MEM_PERR_INT_CAUSE    V_MEM_PERR_INT_CAUSE(1U)
4901 
4902 #define S_MEM_WRAP_INT_CAUSE    0
4903 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
4904 #define F_MEM_WRAP_INT_CAUSE    V_MEM_WRAP_INT_CAUSE(1U)
4905 
4906 #define A_MA_INT_WRAP_STATUS 0x77e4
4907 
4908 #define S_MEM_WRAP_ADDRESS    4
4909 #define M_MEM_WRAP_ADDRESS    0xfffffffU
4910 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
4911 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
4912 
4913 #define S_MEM_WRAP_CLIENT_NUM    0
4914 #define M_MEM_WRAP_CLIENT_NUM    0xfU
4915 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
4916 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
4917 
4918 #define A_MA_PARITY_ERROR_STATUS 0x77f4
4919 
4920 #define S_TP_DMARBT_PAR_ERROR    31
4921 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
4922 #define F_TP_DMARBT_PAR_ERROR    V_TP_DMARBT_PAR_ERROR(1U)
4923 
4924 #define S_LOGIC_FIFO_PAR_ERROR    30
4925 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
4926 #define F_LOGIC_FIFO_PAR_ERROR    V_LOGIC_FIFO_PAR_ERROR(1U)
4927 
4928 #define S_ARB3_PAR_WRQUEUE_ERROR    29
4929 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
4930 #define F_ARB3_PAR_WRQUEUE_ERROR    V_ARB3_PAR_WRQUEUE_ERROR(1U)
4931 
4932 #define S_ARB2_PAR_WRQUEUE_ERROR    28
4933 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
4934 #define F_ARB2_PAR_WRQUEUE_ERROR    V_ARB2_PAR_WRQUEUE_ERROR(1U)
4935 
4936 #define S_ARB1_PAR_WRQUEUE_ERROR    27
4937 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
4938 #define F_ARB1_PAR_WRQUEUE_ERROR    V_ARB1_PAR_WRQUEUE_ERROR(1U)
4939 
4940 #define S_ARB0_PAR_WRQUEUE_ERROR    26
4941 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
4942 #define F_ARB0_PAR_WRQUEUE_ERROR    V_ARB0_PAR_WRQUEUE_ERROR(1U)
4943 
4944 #define S_ARB3_PAR_RDQUEUE_ERROR    25
4945 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
4946 #define F_ARB3_PAR_RDQUEUE_ERROR    V_ARB3_PAR_RDQUEUE_ERROR(1U)
4947 
4948 #define S_ARB2_PAR_RDQUEUE_ERROR    24
4949 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
4950 #define F_ARB2_PAR_RDQUEUE_ERROR    V_ARB2_PAR_RDQUEUE_ERROR(1U)
4951 
4952 #define S_ARB1_PAR_RDQUEUE_ERROR    23
4953 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
4954 #define F_ARB1_PAR_RDQUEUE_ERROR    V_ARB1_PAR_RDQUEUE_ERROR(1U)
4955 
4956 #define S_ARB0_PAR_RDQUEUE_ERROR    22
4957 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
4958 #define F_ARB0_PAR_RDQUEUE_ERROR    V_ARB0_PAR_RDQUEUE_ERROR(1U)
4959 
4960 #define S_CL10_PAR_WRQUEUE_ERROR    21
4961 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
4962 #define F_CL10_PAR_WRQUEUE_ERROR    V_CL10_PAR_WRQUEUE_ERROR(1U)
4963 
4964 #define S_CL9_PAR_WRQUEUE_ERROR    20
4965 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
4966 #define F_CL9_PAR_WRQUEUE_ERROR    V_CL9_PAR_WRQUEUE_ERROR(1U)
4967 
4968 #define S_CL8_PAR_WRQUEUE_ERROR    19
4969 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
4970 #define F_CL8_PAR_WRQUEUE_ERROR    V_CL8_PAR_WRQUEUE_ERROR(1U)
4971 
4972 #define S_CL7_PAR_WRQUEUE_ERROR    18
4973 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
4974 #define F_CL7_PAR_WRQUEUE_ERROR    V_CL7_PAR_WRQUEUE_ERROR(1U)
4975 
4976 #define S_CL6_PAR_WRQUEUE_ERROR    17
4977 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
4978 #define F_CL6_PAR_WRQUEUE_ERROR    V_CL6_PAR_WRQUEUE_ERROR(1U)
4979 
4980 #define S_CL5_PAR_WRQUEUE_ERROR    16
4981 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
4982 #define F_CL5_PAR_WRQUEUE_ERROR    V_CL5_PAR_WRQUEUE_ERROR(1U)
4983 
4984 #define S_CL4_PAR_WRQUEUE_ERROR    15
4985 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
4986 #define F_CL4_PAR_WRQUEUE_ERROR    V_CL4_PAR_WRQUEUE_ERROR(1U)
4987 
4988 #define S_CL3_PAR_WRQUEUE_ERROR    14
4989 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
4990 #define F_CL3_PAR_WRQUEUE_ERROR    V_CL3_PAR_WRQUEUE_ERROR(1U)
4991 
4992 #define S_CL2_PAR_WRQUEUE_ERROR    13
4993 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
4994 #define F_CL2_PAR_WRQUEUE_ERROR    V_CL2_PAR_WRQUEUE_ERROR(1U)
4995 
4996 #define S_CL1_PAR_WRQUEUE_ERROR    12
4997 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
4998 #define F_CL1_PAR_WRQUEUE_ERROR    V_CL1_PAR_WRQUEUE_ERROR(1U)
4999 
5000 #define S_CL0_PAR_WRQUEUE_ERROR    11
5001 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
5002 #define F_CL0_PAR_WRQUEUE_ERROR    V_CL0_PAR_WRQUEUE_ERROR(1U)
5003 
5004 #define S_CL10_PAR_RDQUEUE_ERROR    10
5005 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
5006 #define F_CL10_PAR_RDQUEUE_ERROR    V_CL10_PAR_RDQUEUE_ERROR(1U)
5007 
5008 #define S_CL9_PAR_RDQUEUE_ERROR    9
5009 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
5010 #define F_CL9_PAR_RDQUEUE_ERROR    V_CL9_PAR_RDQUEUE_ERROR(1U)
5011 
5012 #define S_CL8_PAR_RDQUEUE_ERROR    8
5013 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
5014 #define F_CL8_PAR_RDQUEUE_ERROR    V_CL8_PAR_RDQUEUE_ERROR(1U)
5015 
5016 #define S_CL7_PAR_RDQUEUE_ERROR    7
5017 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
5018 #define F_CL7_PAR_RDQUEUE_ERROR    V_CL7_PAR_RDQUEUE_ERROR(1U)
5019 
5020 #define S_CL6_PAR_RDQUEUE_ERROR    6
5021 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
5022 #define F_CL6_PAR_RDQUEUE_ERROR    V_CL6_PAR_RDQUEUE_ERROR(1U)
5023 
5024 #define S_CL5_PAR_RDQUEUE_ERROR    5
5025 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
5026 #define F_CL5_PAR_RDQUEUE_ERROR    V_CL5_PAR_RDQUEUE_ERROR(1U)
5027 
5028 #define S_CL4_PAR_RDQUEUE_ERROR    4
5029 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
5030 #define F_CL4_PAR_RDQUEUE_ERROR    V_CL4_PAR_RDQUEUE_ERROR(1U)
5031 
5032 #define S_CL3_PAR_RDQUEUE_ERROR    3
5033 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
5034 #define F_CL3_PAR_RDQUEUE_ERROR    V_CL3_PAR_RDQUEUE_ERROR(1U)
5035 
5036 #define S_CL2_PAR_RDQUEUE_ERROR    2
5037 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
5038 #define F_CL2_PAR_RDQUEUE_ERROR    V_CL2_PAR_RDQUEUE_ERROR(1U)
5039 
5040 #define S_CL1_PAR_RDQUEUE_ERROR    1
5041 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
5042 #define F_CL1_PAR_RDQUEUE_ERROR    V_CL1_PAR_RDQUEUE_ERROR(1U)
5043 
5044 #define S_CL0_PAR_RDQUEUE_ERROR    0
5045 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
5046 #define F_CL0_PAR_RDQUEUE_ERROR    V_CL0_PAR_RDQUEUE_ERROR(1U)
5047 
5048 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
5049 #define A_MA_PARITY_ERROR_STATUS2 0x7804
5050 
5051 #define S_ARB4_PAR_WRQUEUE_ERROR    1
5052 #define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
5053 #define F_ARB4_PAR_WRQUEUE_ERROR    V_ARB4_PAR_WRQUEUE_ERROR(1U)
5054 
5055 #define S_ARB4_PAR_RDQUEUE_ERROR    0
5056 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
5057 #define F_ARB4_PAR_RDQUEUE_ERROR    V_ARB4_PAR_RDQUEUE_ERROR(1U)
5058 
5059 #define A_MA_EXT_MEMORY1_BAR 0x7808
5060 
5061 #define S_EXT_MEM1_BASE    16
5062 #define M_EXT_MEM1_BASE    0xfffU
5063 #define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
5064 #define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
5065 
5066 #define S_EXT_MEM1_SIZE    0
5067 #define M_EXT_MEM1_SIZE    0xfffU
5068 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
5069 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
5070 
5071 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
5072 
5073 #define S_DEBUG_OR    15
5074 #define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
5075 #define F_DEBUG_OR    V_DEBUG_OR(1U)
5076 
5077 #define S_DEBUG_HI    14
5078 #define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
5079 #define F_DEBUG_HI    V_DEBUG_HI(1U)
5080 
5081 #define S_DEBUG_RPT    13
5082 #define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
5083 #define F_DEBUG_RPT    V_DEBUG_RPT(1U)
5084 
5085 #define S_DEBUGPAGE    10
5086 #define M_DEBUGPAGE    0x7U
5087 #define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
5088 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
5089 
5090 
5091 /* registers for module EDC_0 */
5092 #define EDC_0_BASE_ADDR 0x7900
5093 
5094 #define A_EDC_BIST_CMD 0x7904
5095 #define A_EDC_BIST_CMD_ADDR 0x7908
5096 #define A_EDC_BIST_CMD_LEN 0x790c
5097 #define A_EDC_BIST_DATA_PATTERN 0x7910
5098 #define A_EDC_BIST_STATUS_RDATA 0x7928
5099 #define A_EDC_INT_CAUSE 0x7978
5100 
5101 #define S_ECC_UE_PAR    5
5102 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
5103 #define F_ECC_UE_PAR    V_ECC_UE_PAR(1U)
5104 
5105 #define S_ECC_CE_PAR    4
5106 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
5107 #define F_ECC_CE_PAR    V_ECC_CE_PAR(1U)
5108 
5109 #define S_PERR_PAR_CAUSE    3
5110 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
5111 #define F_PERR_PAR_CAUSE    V_PERR_PAR_CAUSE(1U)
5112 
5113 #define A_EDC_ECC_STATUS 0x797c
5114 
5115 /* registers for module EDC_1 */
5116 #define EDC_1_BASE_ADDR 0x7980
5117 
5118 /* registers for module HMA */
5119 #define HMA_BASE_ADDR 0x7a00
5120 
5121 /* registers for module CIM */
5122 #define CIM_BASE_ADDR 0x7b00
5123 
5124 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
5125 
5126 #define S_VFMBGENERIC    4
5127 #define M_VFMBGENERIC    0xfU
5128 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
5129 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
5130 
5131 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
5132 
5133 #define S_MBVFREADY    0
5134 #define V_MBVFREADY(x) ((x) << S_MBVFREADY)
5135 #define F_MBVFREADY    V_MBVFREADY(1U)
5136 
5137 #define A_CIM_PF_MAILBOX_DATA 0x240
5138 #define A_CIM_PF_MAILBOX_CTRL 0x280
5139 
5140 #define S_MBGENERIC    4
5141 #define M_MBGENERIC    0xfffffffU
5142 #define V_MBGENERIC(x) ((x) << S_MBGENERIC)
5143 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
5144 
5145 #define S_MBMSGVALID    3
5146 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
5147 #define F_MBMSGVALID    V_MBMSGVALID(1U)
5148 
5149 #define S_MBINTREQ    2
5150 #define V_MBINTREQ(x) ((x) << S_MBINTREQ)
5151 #define F_MBINTREQ    V_MBINTREQ(1U)
5152 
5153 #define S_MBOWNER    0
5154 #define M_MBOWNER    0x3U
5155 #define V_MBOWNER(x) ((x) << S_MBOWNER)
5156 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
5157 
5158 #define A_CIM_PF_HOST_INT_ENABLE 0x288
5159 
5160 #define S_MBMSGRDYINTEN    19
5161 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
5162 #define F_MBMSGRDYINTEN    V_MBMSGRDYINTEN(1U)
5163 
5164 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
5165 
5166 #define S_MBMSGRDYINT    19
5167 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
5168 #define F_MBMSGRDYINT    V_MBMSGRDYINT(1U)
5169 
5170 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
5171 #define A_CIM_BOOT_CFG 0x7b00
5172 
5173 #define S_BOOTADDR    8
5174 #define M_BOOTADDR    0xffffffU
5175 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
5176 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
5177 
5178 #define S_UPGEN    2
5179 #define M_UPGEN    0x3fU
5180 #define V_UPGEN(x) ((x) << S_UPGEN)
5181 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
5182 
5183 #define S_BOOTSDRAM    1
5184 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
5185 #define F_BOOTSDRAM    V_BOOTSDRAM(1U)
5186 
5187 #define S_UPCRST    0
5188 #define V_UPCRST(x) ((x) << S_UPCRST)
5189 #define F_UPCRST    V_UPCRST(1U)
5190 
5191 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
5192 
5193 #define S_SDRAMBASEADDR    6
5194 #define M_SDRAMBASEADDR    0x3ffffffU
5195 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
5196 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
5197 
5198 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
5199 
5200 #define S_SDRAMADDRSIZE    4
5201 #define M_SDRAMADDRSIZE    0xfffffffU
5202 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
5203 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
5204 
5205 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
5206 
5207 #define S_EXTMEM2BASEADDR    6
5208 #define M_EXTMEM2BASEADDR    0x3ffffffU
5209 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
5210 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
5211 
5212 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
5213 
5214 #define S_EXTMEM2ADDRSIZE    4
5215 #define M_EXTMEM2ADDRSIZE    0xfffffffU
5216 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
5217 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
5218 
5219 #define A_CIM_HOST_INT_CAUSE 0x7b2c
5220 
5221 #define S_TIEQOUTPARERRINT    20
5222 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
5223 #define F_TIEQOUTPARERRINT    V_TIEQOUTPARERRINT(1U)
5224 
5225 #define S_TIEQINPARERRINT    19
5226 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
5227 #define F_TIEQINPARERRINT    V_TIEQINPARERRINT(1U)
5228 
5229 #define S_MBHOSTPARERR    18
5230 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
5231 #define F_MBHOSTPARERR    V_MBHOSTPARERR(1U)
5232 
5233 #define S_MBUPPARERR    17
5234 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
5235 #define F_MBUPPARERR    V_MBUPPARERR(1U)
5236 
5237 #define S_IBQTP0PARERR    16
5238 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
5239 #define F_IBQTP0PARERR    V_IBQTP0PARERR(1U)
5240 
5241 #define S_IBQTP1PARERR    15
5242 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
5243 #define F_IBQTP1PARERR    V_IBQTP1PARERR(1U)
5244 
5245 #define S_IBQULPPARERR    14
5246 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
5247 #define F_IBQULPPARERR    V_IBQULPPARERR(1U)
5248 
5249 #define S_IBQSGELOPARERR    13
5250 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
5251 #define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
5252 
5253 #define S_IBQSGEHIPARERR    12
5254 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
5255 #define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
5256 
5257 #define S_IBQNCSIPARERR    11
5258 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
5259 #define F_IBQNCSIPARERR    V_IBQNCSIPARERR(1U)
5260 
5261 #define S_OBQULP0PARERR    10
5262 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
5263 #define F_OBQULP0PARERR    V_OBQULP0PARERR(1U)
5264 
5265 #define S_OBQULP1PARERR    9
5266 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
5267 #define F_OBQULP1PARERR    V_OBQULP1PARERR(1U)
5268 
5269 #define S_OBQULP2PARERR    8
5270 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
5271 #define F_OBQULP2PARERR    V_OBQULP2PARERR(1U)
5272 
5273 #define S_OBQULP3PARERR    7
5274 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
5275 #define F_OBQULP3PARERR    V_OBQULP3PARERR(1U)
5276 
5277 #define S_OBQSGEPARERR    6
5278 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
5279 #define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
5280 
5281 #define S_OBQNCSIPARERR    5
5282 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
5283 #define F_OBQNCSIPARERR    V_OBQNCSIPARERR(1U)
5284 
5285 #define S_TIMER1INT    3
5286 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
5287 #define F_TIMER1INT    V_TIMER1INT(1U)
5288 
5289 #define S_TIMER0INT    2
5290 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
5291 #define F_TIMER0INT    V_TIMER0INT(1U)
5292 
5293 #define S_PREFDROPINT    1
5294 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
5295 #define F_PREFDROPINT    V_PREFDROPINT(1U)
5296 
5297 #define S_UPACCNONZERO    0
5298 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
5299 #define F_UPACCNONZERO    V_UPACCNONZERO(1U)
5300 
5301 #define S_MA_CIM_INTFPERR    28
5302 #define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
5303 #define F_MA_CIM_INTFPERR    V_MA_CIM_INTFPERR(1U)
5304 
5305 #define S_PLCIM_MSTRSPDATAPARERR    27
5306 #define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
5307 #define F_PLCIM_MSTRSPDATAPARERR    V_PLCIM_MSTRSPDATAPARERR(1U)
5308 
5309 #define S_NCSI2CIMINTFPARERR    26
5310 #define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
5311 #define F_NCSI2CIMINTFPARERR    V_NCSI2CIMINTFPARERR(1U)
5312 
5313 #define S_SGE2CIMINTFPARERR    25
5314 #define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
5315 #define F_SGE2CIMINTFPARERR    V_SGE2CIMINTFPARERR(1U)
5316 
5317 #define S_ULP2CIMINTFPARERR    24
5318 #define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
5319 #define F_ULP2CIMINTFPARERR    V_ULP2CIMINTFPARERR(1U)
5320 
5321 #define S_TP2CIMINTFPARERR    23
5322 #define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
5323 #define F_TP2CIMINTFPARERR    V_TP2CIMINTFPARERR(1U)
5324 
5325 #define S_OBQSGERX1PARERR    22
5326 #define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
5327 #define F_OBQSGERX1PARERR    V_OBQSGERX1PARERR(1U)
5328 
5329 #define S_OBQSGERX0PARERR    21
5330 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
5331 #define F_OBQSGERX0PARERR    V_OBQSGERX0PARERR(1U)
5332 
5333 #define S_PCIE2CIMINTFPARERR    29
5334 #define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR)
5335 #define F_PCIE2CIMINTFPARERR    V_PCIE2CIMINTFPARERR(1U)
5336 
5337 #define S_IBQPCIEPARERR    12
5338 #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
5339 #define F_IBQPCIEPARERR    V_IBQPCIEPARERR(1U)
5340 
5341 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
5342 
5343 #define S_EEPROMWRINT    30
5344 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
5345 #define F_EEPROMWRINT    V_EEPROMWRINT(1U)
5346 
5347 #define S_TIMEOUTMAINT    29
5348 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
5349 #define F_TIMEOUTMAINT    V_TIMEOUTMAINT(1U)
5350 
5351 #define S_TIMEOUTINT    28
5352 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
5353 #define F_TIMEOUTINT    V_TIMEOUTINT(1U)
5354 
5355 #define S_RSPOVRLOOKUPINT    27
5356 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
5357 #define F_RSPOVRLOOKUPINT    V_RSPOVRLOOKUPINT(1U)
5358 
5359 #define S_REQOVRLOOKUPINT    26
5360 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
5361 #define F_REQOVRLOOKUPINT    V_REQOVRLOOKUPINT(1U)
5362 
5363 #define S_BLKWRPLINT    25
5364 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
5365 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
5366 
5367 #define S_BLKRDPLINT    24
5368 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
5369 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
5370 
5371 #define S_SGLWRPLINT    23
5372 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
5373 #define F_SGLWRPLINT    V_SGLWRPLINT(1U)
5374 
5375 #define S_SGLRDPLINT    22
5376 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
5377 #define F_SGLRDPLINT    V_SGLRDPLINT(1U)
5378 
5379 #define S_BLKWRCTLINT    21
5380 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
5381 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
5382 
5383 #define S_BLKRDCTLINT    20
5384 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
5385 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
5386 
5387 #define S_SGLWRCTLINT    19
5388 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
5389 #define F_SGLWRCTLINT    V_SGLWRCTLINT(1U)
5390 
5391 #define S_SGLRDCTLINT    18
5392 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
5393 #define F_SGLRDCTLINT    V_SGLRDCTLINT(1U)
5394 
5395 #define S_BLKWREEPROMINT    17
5396 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
5397 #define F_BLKWREEPROMINT    V_BLKWREEPROMINT(1U)
5398 
5399 #define S_BLKRDEEPROMINT    16
5400 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
5401 #define F_BLKRDEEPROMINT    V_BLKRDEEPROMINT(1U)
5402 
5403 #define S_SGLWREEPROMINT    15
5404 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
5405 #define F_SGLWREEPROMINT    V_SGLWREEPROMINT(1U)
5406 
5407 #define S_SGLRDEEPROMINT    14
5408 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
5409 #define F_SGLRDEEPROMINT    V_SGLRDEEPROMINT(1U)
5410 
5411 #define S_BLKWRFLASHINT    13
5412 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
5413 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
5414 
5415 #define S_BLKRDFLASHINT    12
5416 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
5417 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
5418 
5419 #define S_SGLWRFLASHINT    11
5420 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
5421 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
5422 
5423 #define S_SGLRDFLASHINT    10
5424 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
5425 #define F_SGLRDFLASHINT    V_SGLRDFLASHINT(1U)
5426 
5427 #define S_BLKWRBOOTINT    9
5428 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
5429 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
5430 
5431 #define S_BLKRDBOOTINT    8
5432 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
5433 #define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
5434 
5435 #define S_SGLWRBOOTINT    7
5436 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
5437 #define F_SGLWRBOOTINT    V_SGLWRBOOTINT(1U)
5438 
5439 #define S_SGLRDBOOTINT    6
5440 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
5441 #define F_SGLRDBOOTINT    V_SGLRDBOOTINT(1U)
5442 
5443 #define S_ILLWRBEINT    5
5444 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
5445 #define F_ILLWRBEINT    V_ILLWRBEINT(1U)
5446 
5447 #define S_ILLRDBEINT    4
5448 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
5449 #define F_ILLRDBEINT    V_ILLRDBEINT(1U)
5450 
5451 #define S_ILLRDINT    3
5452 #define V_ILLRDINT(x) ((x) << S_ILLRDINT)
5453 #define F_ILLRDINT    V_ILLRDINT(1U)
5454 
5455 #define S_ILLWRINT    2
5456 #define V_ILLWRINT(x) ((x) << S_ILLWRINT)
5457 #define F_ILLWRINT    V_ILLWRINT(1U)
5458 
5459 #define S_ILLTRANSINT    1
5460 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
5461 #define F_ILLTRANSINT    V_ILLTRANSINT(1U)
5462 
5463 #define S_RSVDSPACEINT    0
5464 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
5465 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
5466 
5467 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
5468 
5469 #define S_OBQSELECT    4
5470 #define V_OBQSELECT(x) ((x) << S_OBQSELECT)
5471 #define F_OBQSELECT    V_OBQSELECT(1U)
5472 
5473 #define S_IBQSELECT    3
5474 #define V_IBQSELECT(x) ((x) << S_IBQSELECT)
5475 #define F_IBQSELECT    V_IBQSELECT(1U)
5476 
5477 #define S_QUENUMSELECT    0
5478 #define M_QUENUMSELECT    0x7U
5479 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
5480 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
5481 
5482 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
5483 
5484 #define S_CIMQSIZE    24
5485 #define M_CIMQSIZE    0x3fU
5486 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
5487 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
5488 
5489 #define S_CIMQBASE    16
5490 #define M_CIMQBASE    0x3fU
5491 #define V_CIMQBASE(x) ((x) << S_CIMQBASE)
5492 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
5493 
5494 #define S_CIMQDBG8BEN    9
5495 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
5496 #define F_CIMQDBG8BEN    V_CIMQDBG8BEN(1U)
5497 
5498 #define S_QUEFULLTHRSH    0
5499 #define M_QUEFULLTHRSH    0x1ffU
5500 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
5501 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
5502 
5503 #define S_CIMQ1KEN    30
5504 #define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN)
5505 #define F_CIMQ1KEN    V_CIMQ1KEN(1U)
5506 
5507 #define A_CIM_HOST_ACC_CTRL 0x7b50
5508 
5509 #define S_HOSTBUSY    17
5510 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
5511 #define F_HOSTBUSY    V_HOSTBUSY(1U)
5512 
5513 #define S_HOSTWRITE    16
5514 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
5515 #define F_HOSTWRITE    V_HOSTWRITE(1U)
5516 
5517 #define S_HOSTADDR    0
5518 #define M_HOSTADDR    0xffffU
5519 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
5520 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
5521 
5522 #define A_CIM_HOST_ACC_DATA 0x7b54
5523 #define A_CIM_IBQ_DBG_CFG 0x7b60
5524 
5525 #define S_IBQDBGADDR    16
5526 #define M_IBQDBGADDR    0xfffU
5527 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
5528 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
5529 
5530 #define S_IBQDBGWR    2
5531 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
5532 #define F_IBQDBGWR    V_IBQDBGWR(1U)
5533 
5534 #define S_IBQDBGBUSY    1
5535 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
5536 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
5537 
5538 #define S_IBQDBGEN    0
5539 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
5540 #define F_IBQDBGEN    V_IBQDBGEN(1U)
5541 
5542 #define A_CIM_OBQ_DBG_CFG 0x7b64
5543 
5544 #define S_OBQDBGADDR    16
5545 #define M_OBQDBGADDR    0xfffU
5546 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
5547 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
5548 
5549 #define S_OBQDBGWR    2
5550 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
5551 #define F_OBQDBGWR    V_OBQDBGWR(1U)
5552 
5553 #define S_OBQDBGBUSY    1
5554 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
5555 #define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
5556 
5557 #define S_OBQDBGEN    0
5558 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
5559 #define F_OBQDBGEN    V_OBQDBGEN(1U)
5560 
5561 #define A_CIM_IBQ_DBG_DATA 0x7b68
5562 #define A_CIM_OBQ_DBG_DATA 0x7b6c
5563 #define A_CIM_DEBUGCFG 0x7b70
5564 
5565 #define S_POLADBGRDPTR    23
5566 #define M_POLADBGRDPTR    0x1ffU
5567 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
5568 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
5569 
5570 #define S_PILADBGRDPTR    14
5571 #define M_PILADBGRDPTR    0x1ffU
5572 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
5573 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
5574 
5575 #define S_LAMASKTRIG    13
5576 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
5577 #define F_LAMASKTRIG    V_LAMASKTRIG(1U)
5578 
5579 #define S_LADBGEN    12
5580 #define V_LADBGEN(x) ((x) << S_LADBGEN)
5581 #define F_LADBGEN    V_LADBGEN(1U)
5582 
5583 #define S_LAFILLONCE    11
5584 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
5585 #define F_LAFILLONCE    V_LAFILLONCE(1U)
5586 
5587 #define S_LAMASKSTOP    10
5588 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
5589 #define F_LAMASKSTOP    V_LAMASKSTOP(1U)
5590 
5591 #define S_DEBUGSELH    5
5592 #define M_DEBUGSELH    0x1fU
5593 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
5594 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
5595 
5596 #define S_DEBUGSELL    0
5597 #define M_DEBUGSELL    0x1fU
5598 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
5599 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
5600 
5601 #define A_CIM_DEBUGSTS 0x7b74
5602 
5603 #define S_LARESET    31
5604 #define V_LARESET(x) ((x) << S_LARESET)
5605 #define F_LARESET    V_LARESET(1U)
5606 
5607 #define S_POLADBGWRPTR    16
5608 #define M_POLADBGWRPTR    0x1ffU
5609 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
5610 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
5611 
5612 #define S_PILADBGWRPTR    0
5613 #define M_PILADBGWRPTR    0x1ffU
5614 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
5615 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
5616 
5617 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
5618 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
5619 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
5620 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
5621 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
5622 
5623 #define S_DADDRILLEGAL    2
5624 #define M_DADDRILLEGAL    0x3fffffffU
5625 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
5626 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
5627 
5628 #define S_DADDRILLEGALTYPE    0
5629 #define M_DADDRILLEGALTYPE    0x3U
5630 #define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE)
5631 #define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE)
5632 
5633 #define A_CIM_UP_OPERATION_FREQ 0x7c38
5634 
5635 /* registers for module TP */
5636 #define TP_BASE_ADDR 0x7d00
5637 
5638 #define A_TP_IN_CONFIG 0x7d00
5639 
5640 #define S_NICMODE    14
5641 #define V_NICMODE(x) ((x) << S_NICMODE)
5642 #define F_NICMODE    V_NICMODE(1U)
5643 
5644 #define S_ECHECKSUMCHECKTCP    13
5645 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
5646 #define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
5647 
5648 #define S_ECHECKSUMCHECKIP    12
5649 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
5650 #define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
5651 
5652 #define A_TP_OUT_CONFIG 0x7d04
5653 
5654 #define S_IPIDSPLITMODE    16
5655 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
5656 #define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
5657 
5658 #define S_VLANEXTENABLEPORT3    15
5659 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
5660 #define F_VLANEXTENABLEPORT3    V_VLANEXTENABLEPORT3(1U)
5661 
5662 #define S_VLANEXTENABLEPORT2    14
5663 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
5664 #define F_VLANEXTENABLEPORT2    V_VLANEXTENABLEPORT2(1U)
5665 
5666 #define S_VLANEXTENABLEPORT1    13
5667 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
5668 #define F_VLANEXTENABLEPORT1    V_VLANEXTENABLEPORT1(1U)
5669 
5670 #define S_VLANEXTENABLEPORT0    12
5671 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
5672 #define F_VLANEXTENABLEPORT0    V_VLANEXTENABLEPORT0(1U)
5673 
5674 #define S_CRXPKTENC    3
5675 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
5676 #define F_CRXPKTENC    V_CRXPKTENC(1U)
5677 
5678 #define S_CRXPKTXT    1
5679 #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
5680 #define F_CRXPKTXT    V_CRXPKTXT(1U)
5681 
5682 #define A_TP_GLOBAL_CONFIG 0x7d08
5683 
5684 #define S_SYNCOOKIEPARAMS    26
5685 #define M_SYNCOOKIEPARAMS    0x3fU
5686 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
5687 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
5688 
5689 #define S_RXFLOWCONTROLDISABLE    25
5690 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
5691 #define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
5692 
5693 #define S_TXPACINGENABLE    24
5694 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
5695 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
5696 
5697 #define S_ATTACKFILTERENABLE    23
5698 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
5699 #define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
5700 
5701 #define S_SYNCOOKIENOOPTIONS    22
5702 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
5703 #define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
5704 
5705 #define S_PROTECTEDMODE    21
5706 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
5707 #define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
5708 
5709 #define S_PINGDROP    20
5710 #define V_PINGDROP(x) ((x) << S_PINGDROP)
5711 #define F_PINGDROP    V_PINGDROP(1U)
5712 
5713 #define S_FRAGMENTDROP    19
5714 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
5715 #define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
5716 
5717 #define S_FIVETUPLELOOKUP    17
5718 #define M_FIVETUPLELOOKUP    0x3U
5719 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
5720 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
5721 
5722 #define S_OFDMPSSTATS    16
5723 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
5724 #define F_OFDMPSSTATS    V_OFDMPSSTATS(1U)
5725 
5726 #define S_DONTFRAGMENT    15
5727 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
5728 #define F_DONTFRAGMENT    V_DONTFRAGMENT(1U)
5729 
5730 #define S_IPIDENTSPLIT    14
5731 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
5732 #define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
5733 
5734 #define S_IPCHECKSUMOFFLOAD    13
5735 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
5736 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
5737 
5738 #define S_UDPCHECKSUMOFFLOAD    12
5739 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
5740 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
5741 
5742 #define S_TCPCHECKSUMOFFLOAD    11
5743 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
5744 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
5745 
5746 #define S_RSSLOOPBACKENABLE    10
5747 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
5748 #define F_RSSLOOPBACKENABLE    V_RSSLOOPBACKENABLE(1U)
5749 
5750 #define S_TCAMSERVERUSE    8
5751 #define M_TCAMSERVERUSE    0x3U
5752 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
5753 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
5754 
5755 #define S_IPTTL    0
5756 #define M_IPTTL    0xffU
5757 #define V_IPTTL(x) ((x) << S_IPTTL)
5758 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
5759 
5760 #define S_RSSSYNSTEERENABLE    12
5761 #define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
5762 #define F_RSSSYNSTEERENABLE    V_RSSSYNSTEERENABLE(1U)
5763 
5764 #define S_ISSFROMCPLENABLE    11
5765 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
5766 #define F_ISSFROMCPLENABLE    V_ISSFROMCPLENABLE(1U)
5767 
5768 #define S_ACTIVEFILTERCOUNTS    22
5769 #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
5770 #define F_ACTIVEFILTERCOUNTS    V_ACTIVEFILTERCOUNTS(1U)
5771 
5772 #define A_TP_CMM_TCB_BASE 0x7d10
5773 #define A_TP_CMM_MM_BASE 0x7d14
5774 #define A_TP_CMM_TIMER_BASE 0x7d18
5775 #define A_TP_PMM_TX_BASE 0x7d20
5776 #define A_TP_PMM_RX_BASE 0x7d28
5777 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
5778 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
5779 
5780 #define S_PMRXNUMCHN    31
5781 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
5782 #define F_PMRXNUMCHN    V_PMRXNUMCHN(1U)
5783 
5784 #define S_PMRXMAXPAGE    0
5785 #define M_PMRXMAXPAGE    0x1fffffU
5786 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
5787 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
5788 
5789 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
5790 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
5791 
5792 #define S_PMTXNUMCHN    30
5793 #define M_PMTXNUMCHN    0x3U
5794 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
5795 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
5796 
5797 #define S_PMTXMAXPAGE    0
5798 #define M_PMTXMAXPAGE    0x1fffffU
5799 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
5800 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
5801 
5802 #define A_TP_DACK_CONFIG 0x7d44
5803 
5804 #define S_AUTOSTATE3    30
5805 #define M_AUTOSTATE3    0x3U
5806 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
5807 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
5808 
5809 #define S_AUTOSTATE2    28
5810 #define M_AUTOSTATE2    0x3U
5811 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
5812 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
5813 
5814 #define S_AUTOSTATE1    26
5815 #define M_AUTOSTATE1    0x3U
5816 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
5817 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
5818 
5819 #define S_BYTETHRESHOLD    8
5820 #define M_BYTETHRESHOLD    0x3ffffU
5821 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
5822 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
5823 
5824 #define S_MSSTHRESHOLD    4
5825 #define M_MSSTHRESHOLD    0x7U
5826 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
5827 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
5828 
5829 #define S_AUTOENABLE    1
5830 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
5831 #define F_AUTOENABLE    V_AUTOENABLE(1U)
5832 
5833 #define S_MODE    0
5834 #define V_MODE(x) ((x) << S_MODE)
5835 #define F_MODE    V_MODE(1U)
5836 
5837 #define A_TP_PARA_REG0 0x7d60
5838 
5839 #define S_DUPACKTHRESH    20
5840 #define M_DUPACKTHRESH    0xfU
5841 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
5842 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
5843 
5844 #define A_TP_PARA_REG2 0x7d68
5845 
5846 #define S_MAXRXDATA    16
5847 #define M_MAXRXDATA    0xffffU
5848 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
5849 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
5850 
5851 #define S_RXCOALESCESIZE    0
5852 #define M_RXCOALESCESIZE    0xffffU
5853 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
5854 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
5855 
5856 #define A_TP_PARA_REG3 0x7d6c
5857 
5858 #define S_TUNNELCNGDROP3    23
5859 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
5860 #define F_TUNNELCNGDROP3    V_TUNNELCNGDROP3(1U)
5861 
5862 #define S_TUNNELCNGDROP2    22
5863 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
5864 #define F_TUNNELCNGDROP2    V_TUNNELCNGDROP2(1U)
5865 
5866 #define S_TUNNELCNGDROP1    21
5867 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
5868 #define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
5869 
5870 #define S_TUNNELCNGDROP0    20
5871 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
5872 #define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
5873 
5874 #define S_RXURGTUNNEL    6
5875 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
5876 #define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
5877 
5878 #define A_TP_PARA_REG5 0x7d74
5879 
5880 #define S_INDICATESIZE    16
5881 #define M_INDICATESIZE    0xffffU
5882 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
5883 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
5884 
5885 #define S_REARMDDPOFFSET    4
5886 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
5887 #define F_REARMDDPOFFSET    V_REARMDDPOFFSET(1U)
5888 
5889 #define S_RESETDDPOFFSET    3
5890 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
5891 #define F_RESETDDPOFFSET    V_RESETDDPOFFSET(1U)
5892 
5893 #define A_TP_TIMER_RESOLUTION 0x7d90
5894 
5895 #define S_TIMERRESOLUTION    16
5896 #define M_TIMERRESOLUTION    0xffU
5897 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
5898 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
5899 
5900 #define S_TIMESTAMPRESOLUTION    8
5901 #define M_TIMESTAMPRESOLUTION    0xffU
5902 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
5903 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
5904 
5905 #define S_DELAYEDACKRESOLUTION    0
5906 #define M_DELAYEDACKRESOLUTION    0xffU
5907 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
5908 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
5909 
5910 #define A_TP_MSL 0x7d94
5911 
5912 #define S_MSL    0
5913 #define M_MSL    0x3fffffffU
5914 #define V_MSL(x) ((x) << S_MSL)
5915 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
5916 
5917 #define A_TP_RXT_MIN 0x7d98
5918 
5919 #define S_RXTMIN    0
5920 #define M_RXTMIN    0x3fffffffU
5921 #define V_RXTMIN(x) ((x) << S_RXTMIN)
5922 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
5923 
5924 #define A_TP_RXT_MAX 0x7d9c
5925 
5926 #define S_RXTMAX    0
5927 #define M_RXTMAX    0x3fffffffU
5928 #define V_RXTMAX(x) ((x) << S_RXTMAX)
5929 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
5930 
5931 #define A_TP_PERS_MIN 0x7da0
5932 
5933 #define S_PERSMIN    0
5934 #define M_PERSMIN    0x3fffffffU
5935 #define V_PERSMIN(x) ((x) << S_PERSMIN)
5936 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
5937 
5938 #define A_TP_PERS_MAX 0x7da4
5939 
5940 #define S_PERSMAX    0
5941 #define M_PERSMAX    0x3fffffffU
5942 #define V_PERSMAX(x) ((x) << S_PERSMAX)
5943 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
5944 
5945 #define A_TP_KEEP_IDLE 0x7da8
5946 
5947 #define S_KEEPALIVEIDLE    0
5948 #define M_KEEPALIVEIDLE    0x3fffffffU
5949 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
5950 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
5951 
5952 #define A_TP_KEEP_INTVL 0x7dac
5953 
5954 #define S_KEEPALIVEINTVL    0
5955 #define M_KEEPALIVEINTVL    0x3fffffffU
5956 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
5957 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
5958 
5959 #define A_TP_INIT_SRTT 0x7db0
5960 
5961 #define S_MAXRTT    16
5962 #define M_MAXRTT    0xffffU
5963 #define V_MAXRTT(x) ((x) << S_MAXRTT)
5964 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
5965 
5966 #define S_INITSRTT    0
5967 #define M_INITSRTT    0xffffU
5968 #define V_INITSRTT(x) ((x) << S_INITSRTT)
5969 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
5970 
5971 #define A_TP_DACK_TIMER 0x7db4
5972 
5973 #define S_DACKTIME    0
5974 #define M_DACKTIME    0xfffU
5975 #define V_DACKTIME(x) ((x) << S_DACKTIME)
5976 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
5977 
5978 #define A_TP_FINWAIT2_TIMER 0x7db8
5979 
5980 #define S_FINWAIT2TIME    0
5981 #define M_FINWAIT2TIME    0x3fffffffU
5982 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
5983 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
5984 
5985 #define A_TP_SHIFT_CNT 0x7dc0
5986 
5987 #define S_SYNSHIFTMAX    24
5988 #define M_SYNSHIFTMAX    0xffU
5989 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
5990 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
5991 
5992 #define S_RXTSHIFTMAXR1    20
5993 #define M_RXTSHIFTMAXR1    0xfU
5994 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
5995 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
5996 
5997 #define S_RXTSHIFTMAXR2    16
5998 #define M_RXTSHIFTMAXR2    0xfU
5999 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
6000 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
6001 
6002 #define S_PERSHIFTBACKOFFMAX    12
6003 #define M_PERSHIFTBACKOFFMAX    0xfU
6004 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
6005 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
6006 
6007 #define S_PERSHIFTMAX    8
6008 #define M_PERSHIFTMAX    0xfU
6009 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
6010 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
6011 
6012 #define S_KEEPALIVEMAXR1    4
6013 #define M_KEEPALIVEMAXR1    0xfU
6014 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
6015 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
6016 
6017 #define S_KEEPALIVEMAXR2    0
6018 #define M_KEEPALIVEMAXR2    0xfU
6019 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
6020 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
6021 
6022 #define S_T6_SYNSHIFTMAX    24
6023 #define M_T6_SYNSHIFTMAX    0xfU
6024 #define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX)
6025 #define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX)
6026 
6027 #define A_TP_TIME_LO 0x7dc8
6028 #define A_TP_TIME_HI 0x7dcc
6029 #define A_TP_PACE_TABLE 0x7dd8
6030 #define A_TP_CCTRL_TABLE 0x7ddc
6031 
6032 #define S_ROWINDEX    16
6033 #define M_ROWINDEX    0xffffU
6034 #define V_ROWINDEX(x) ((x) << S_ROWINDEX)
6035 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
6036 
6037 #define S_ROWVALUE    0
6038 #define M_ROWVALUE    0xffffU
6039 #define V_ROWVALUE(x) ((x) << S_ROWVALUE)
6040 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
6041 
6042 #define A_TP_MTU_TABLE 0x7de4
6043 
6044 #define S_MTUINDEX    24
6045 #define M_MTUINDEX    0xffU
6046 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
6047 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
6048 
6049 #define S_MTUWIDTH    16
6050 #define M_MTUWIDTH    0xfU
6051 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
6052 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
6053 
6054 #define S_MTUVALUE    0
6055 #define M_MTUVALUE    0x3fffU
6056 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
6057 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
6058 
6059 #define A_TP_RSS_LKP_TABLE 0x7dec
6060 
6061 #define S_LKPTBLROWVLD    31
6062 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
6063 #define F_LKPTBLROWVLD    V_LKPTBLROWVLD(1U)
6064 
6065 #define S_LKPTBLROWIDX    20
6066 #define M_LKPTBLROWIDX    0x3ffU
6067 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
6068 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
6069 
6070 #define S_LKPTBLQUEUE1    10
6071 #define M_LKPTBLQUEUE1    0x3ffU
6072 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
6073 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
6074 
6075 #define S_LKPTBLQUEUE0    0
6076 #define M_LKPTBLQUEUE0    0x3ffU
6077 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
6078 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
6079 
6080 #define S_T6_LKPTBLROWIDX    20
6081 #define M_T6_LKPTBLROWIDX    0x7ffU
6082 #define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX)
6083 #define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX)
6084 
6085 #define A_TP_RSS_CONFIG 0x7df0
6086 
6087 #define S_TNL4TUPENIPV6    31
6088 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
6089 #define F_TNL4TUPENIPV6    V_TNL4TUPENIPV6(1U)
6090 
6091 #define S_TNL2TUPENIPV6    30
6092 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
6093 #define F_TNL2TUPENIPV6    V_TNL2TUPENIPV6(1U)
6094 
6095 #define S_TNL4TUPENIPV4    29
6096 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
6097 #define F_TNL4TUPENIPV4    V_TNL4TUPENIPV4(1U)
6098 
6099 #define S_TNL2TUPENIPV4    28
6100 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
6101 #define F_TNL2TUPENIPV4    V_TNL2TUPENIPV4(1U)
6102 
6103 #define S_TNLTCPSEL    27
6104 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
6105 #define F_TNLTCPSEL    V_TNLTCPSEL(1U)
6106 
6107 #define S_TNLIP6SEL    26
6108 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
6109 #define F_TNLIP6SEL    V_TNLIP6SEL(1U)
6110 
6111 #define S_TNLVRTSEL    25
6112 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
6113 #define F_TNLVRTSEL    V_TNLVRTSEL(1U)
6114 
6115 #define S_TNLMAPEN    24
6116 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
6117 #define F_TNLMAPEN    V_TNLMAPEN(1U)
6118 
6119 #define S_OFDHASHSAVE    19
6120 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
6121 #define F_OFDHASHSAVE    V_OFDHASHSAVE(1U)
6122 
6123 #define S_OFDVRTSEL    18
6124 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
6125 #define F_OFDVRTSEL    V_OFDVRTSEL(1U)
6126 
6127 #define S_OFDMAPEN    17
6128 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
6129 #define F_OFDMAPEN    V_OFDMAPEN(1U)
6130 
6131 #define S_OFDLKPEN    16
6132 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
6133 #define F_OFDLKPEN    V_OFDLKPEN(1U)
6134 
6135 #define S_SYN4TUPENIPV6    15
6136 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
6137 #define F_SYN4TUPENIPV6    V_SYN4TUPENIPV6(1U)
6138 
6139 #define S_SYN2TUPENIPV6    14
6140 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
6141 #define F_SYN2TUPENIPV6    V_SYN2TUPENIPV6(1U)
6142 
6143 #define S_SYN4TUPENIPV4    13
6144 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
6145 #define F_SYN4TUPENIPV4    V_SYN4TUPENIPV4(1U)
6146 
6147 #define S_SYN2TUPENIPV4    12
6148 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
6149 #define F_SYN2TUPENIPV4    V_SYN2TUPENIPV4(1U)
6150 
6151 #define S_SYNIP6SEL    11
6152 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
6153 #define F_SYNIP6SEL    V_SYNIP6SEL(1U)
6154 
6155 #define S_SYNVRTSEL    10
6156 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
6157 #define F_SYNVRTSEL    V_SYNVRTSEL(1U)
6158 
6159 #define S_SYNMAPEN    9
6160 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
6161 #define F_SYNMAPEN    V_SYNMAPEN(1U)
6162 
6163 #define S_SYNLKPEN    8
6164 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
6165 #define F_SYNLKPEN    V_SYNLKPEN(1U)
6166 
6167 #define S_CHANNELENABLE    7
6168 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
6169 #define F_CHANNELENABLE    V_CHANNELENABLE(1U)
6170 
6171 #define S_PORTENABLE    6
6172 #define V_PORTENABLE(x) ((x) << S_PORTENABLE)
6173 #define F_PORTENABLE    V_PORTENABLE(1U)
6174 
6175 #define S_TNLALLLOOKUP    5
6176 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
6177 #define F_TNLALLLOOKUP    V_TNLALLLOOKUP(1U)
6178 
6179 #define S_VIRTENABLE    4
6180 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
6181 #define F_VIRTENABLE    V_VIRTENABLE(1U)
6182 
6183 #define S_CONGESTIONENABLE    3
6184 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
6185 #define F_CONGESTIONENABLE    V_CONGESTIONENABLE(1U)
6186 
6187 #define S_HASHTOEPLITZ    2
6188 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
6189 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
6190 
6191 #define S_UDPENABLE    1
6192 #define V_UDPENABLE(x) ((x) << S_UDPENABLE)
6193 #define F_UDPENABLE    V_UDPENABLE(1U)
6194 
6195 #define S_DISABLE    0
6196 #define V_DISABLE(x) ((x) << S_DISABLE)
6197 #define F_DISABLE    V_DISABLE(1U)
6198 
6199 #define S_TNLFCOEMODE    23
6200 #define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
6201 #define F_TNLFCOEMODE    V_TNLFCOEMODE(1U)
6202 
6203 #define S_TNLFCOEEN    21
6204 #define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
6205 #define F_TNLFCOEEN    V_TNLFCOEEN(1U)
6206 
6207 #define S_HASHXOR    20
6208 #define V_HASHXOR(x) ((x) << S_HASHXOR)
6209 #define F_HASHXOR    V_HASHXOR(1U)
6210 
6211 #define S_TNLFCOESID    22
6212 #define V_TNLFCOESID(x) ((x) << S_TNLFCOESID)
6213 #define F_TNLFCOESID    V_TNLFCOESID(1U)
6214 
6215 #define A_TP_RSS_CONFIG_TNL 0x7df4
6216 
6217 #define S_MASKSIZE    28
6218 #define M_MASKSIZE    0xfU
6219 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
6220 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
6221 
6222 #define S_MASKFILTER    16
6223 #define M_MASKFILTER    0x7ffU
6224 #define V_MASKFILTER(x) ((x) << S_MASKFILTER)
6225 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
6226 
6227 #define S_USEWIRECH    0
6228 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
6229 #define F_USEWIRECH    V_USEWIRECH(1U)
6230 
6231 #define S_HASHALL    2
6232 #define V_HASHALL(x) ((x) << S_HASHALL)
6233 #define F_HASHALL    V_HASHALL(1U)
6234 
6235 #define S_HASHETH    1
6236 #define V_HASHETH(x) ((x) << S_HASHETH)
6237 #define F_HASHETH    V_HASHETH(1U)
6238 
6239 #define A_TP_RSS_CONFIG_OFD 0x7df8
6240 
6241 #define S_RRCPLMAPEN    20
6242 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
6243 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
6244 
6245 #define S_RRCPLQUEWIDTH    16
6246 #define M_RRCPLQUEWIDTH    0xfU
6247 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
6248 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
6249 
6250 #define S_FRMWRQUEMASK    12
6251 #define M_FRMWRQUEMASK    0xfU
6252 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
6253 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
6254 
6255 #define A_TP_RSS_CONFIG_SYN 0x7dfc
6256 #define A_TP_RSS_CONFIG_VRT 0x7e00
6257 
6258 #define S_VFRDRG    25
6259 #define V_VFRDRG(x) ((x) << S_VFRDRG)
6260 #define F_VFRDRG    V_VFRDRG(1U)
6261 
6262 #define S_VFRDEN    24
6263 #define V_VFRDEN(x) ((x) << S_VFRDEN)
6264 #define F_VFRDEN    V_VFRDEN(1U)
6265 
6266 #define S_VFPERREN    23
6267 #define V_VFPERREN(x) ((x) << S_VFPERREN)
6268 #define F_VFPERREN    V_VFPERREN(1U)
6269 
6270 #define S_KEYPERREN    22
6271 #define V_KEYPERREN(x) ((x) << S_KEYPERREN)
6272 #define F_KEYPERREN    V_KEYPERREN(1U)
6273 
6274 #define S_DISABLEVLAN    21
6275 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
6276 #define F_DISABLEVLAN    V_DISABLEVLAN(1U)
6277 
6278 #define S_ENABLEUP0    20
6279 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
6280 #define F_ENABLEUP0    V_ENABLEUP0(1U)
6281 
6282 #define S_HASHDELAY    16
6283 #define M_HASHDELAY    0xfU
6284 #define V_HASHDELAY(x) ((x) << S_HASHDELAY)
6285 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
6286 
6287 #define S_VFWRADDR    8
6288 #define M_VFWRADDR    0x7fU
6289 #define V_VFWRADDR(x) ((x) << S_VFWRADDR)
6290 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
6291 
6292 #define S_KEYMODE    6
6293 #define M_KEYMODE    0x3U
6294 #define V_KEYMODE(x) ((x) << S_KEYMODE)
6295 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
6296 
6297 #define S_VFWREN    5
6298 #define V_VFWREN(x) ((x) << S_VFWREN)
6299 #define F_VFWREN    V_VFWREN(1U)
6300 
6301 #define S_KEYWREN    4
6302 #define V_KEYWREN(x) ((x) << S_KEYWREN)
6303 #define F_KEYWREN    V_KEYWREN(1U)
6304 
6305 #define S_KEYWRADDR    0
6306 #define M_KEYWRADDR    0xfU
6307 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
6308 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
6309 
6310 #define S_VFVLANEN    21
6311 #define V_VFVLANEN(x) ((x) << S_VFVLANEN)
6312 #define F_VFVLANEN    V_VFVLANEN(1U)
6313 
6314 #define S_VFFWEN    20
6315 #define V_VFFWEN(x) ((x) << S_VFFWEN)
6316 #define F_VFFWEN    V_VFFWEN(1U)
6317 
6318 #define S_KEYWRADDRX    30
6319 #define M_KEYWRADDRX    0x3U
6320 #define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
6321 #define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX)
6322 
6323 #define S_KEYEXTEND    26
6324 #define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
6325 #define F_KEYEXTEND    V_KEYEXTEND(1U)
6326 
6327 #define S_T6_VFWRADDR    8
6328 #define M_T6_VFWRADDR    0xffU
6329 #define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
6330 #define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR)
6331 
6332 #define A_TP_RSS_CONFIG_CNG 0x7e04
6333 
6334 #define S_CHNCOUNT3    31
6335 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
6336 #define F_CHNCOUNT3    V_CHNCOUNT3(1U)
6337 
6338 #define S_CHNCOUNT2    30
6339 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
6340 #define F_CHNCOUNT2    V_CHNCOUNT2(1U)
6341 
6342 #define S_CHNCOUNT1    29
6343 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
6344 #define F_CHNCOUNT1    V_CHNCOUNT1(1U)
6345 
6346 #define S_CHNCOUNT0    28
6347 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
6348 #define F_CHNCOUNT0    V_CHNCOUNT0(1U)
6349 
6350 #define S_CHNUNDFLOW3    27
6351 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
6352 #define F_CHNUNDFLOW3    V_CHNUNDFLOW3(1U)
6353 
6354 #define S_CHNUNDFLOW2    26
6355 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
6356 #define F_CHNUNDFLOW2    V_CHNUNDFLOW2(1U)
6357 
6358 #define S_CHNUNDFLOW1    25
6359 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
6360 #define F_CHNUNDFLOW1    V_CHNUNDFLOW1(1U)
6361 
6362 #define S_CHNUNDFLOW0    24
6363 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
6364 #define F_CHNUNDFLOW0    V_CHNUNDFLOW0(1U)
6365 
6366 #define S_CHNOVRFLOW3    23
6367 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
6368 #define F_CHNOVRFLOW3    V_CHNOVRFLOW3(1U)
6369 
6370 #define S_CHNOVRFLOW2    22
6371 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
6372 #define F_CHNOVRFLOW2    V_CHNOVRFLOW2(1U)
6373 
6374 #define S_CHNOVRFLOW1    21
6375 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
6376 #define F_CHNOVRFLOW1    V_CHNOVRFLOW1(1U)
6377 
6378 #define S_CHNOVRFLOW0    20
6379 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
6380 #define F_CHNOVRFLOW0    V_CHNOVRFLOW0(1U)
6381 
6382 #define S_RSTCHN3    19
6383 #define V_RSTCHN3(x) ((x) << S_RSTCHN3)
6384 #define F_RSTCHN3    V_RSTCHN3(1U)
6385 
6386 #define S_RSTCHN2    18
6387 #define V_RSTCHN2(x) ((x) << S_RSTCHN2)
6388 #define F_RSTCHN2    V_RSTCHN2(1U)
6389 
6390 #define S_RSTCHN1    17
6391 #define V_RSTCHN1(x) ((x) << S_RSTCHN1)
6392 #define F_RSTCHN1    V_RSTCHN1(1U)
6393 
6394 #define S_RSTCHN0    16
6395 #define V_RSTCHN0(x) ((x) << S_RSTCHN0)
6396 #define F_RSTCHN0    V_RSTCHN0(1U)
6397 
6398 #define S_UPDVLD    15
6399 #define V_UPDVLD(x) ((x) << S_UPDVLD)
6400 #define F_UPDVLD    V_UPDVLD(1U)
6401 
6402 #define S_XOFF    14
6403 #define V_XOFF(x) ((x) << S_XOFF)
6404 #define F_XOFF    V_XOFF(1U)
6405 
6406 #define S_UPDCHN3    13
6407 #define V_UPDCHN3(x) ((x) << S_UPDCHN3)
6408 #define F_UPDCHN3    V_UPDCHN3(1U)
6409 
6410 #define S_UPDCHN2    12
6411 #define V_UPDCHN2(x) ((x) << S_UPDCHN2)
6412 #define F_UPDCHN2    V_UPDCHN2(1U)
6413 
6414 #define S_UPDCHN1    11
6415 #define V_UPDCHN1(x) ((x) << S_UPDCHN1)
6416 #define F_UPDCHN1    V_UPDCHN1(1U)
6417 
6418 #define S_UPDCHN0    10
6419 #define V_UPDCHN0(x) ((x) << S_UPDCHN0)
6420 #define F_UPDCHN0    V_UPDCHN0(1U)
6421 
6422 #define S_QUEUE    0
6423 #define M_QUEUE    0x3ffU
6424 #define V_QUEUE(x) ((x) << S_QUEUE)
6425 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
6426 
6427 #define A_TP_TM_PIO_ADDR 0x7e18
6428 #define A_TP_TM_PIO_DATA 0x7e1c
6429 #define A_TP_MOD_CONFIG 0x7e24
6430 
6431 #define S_RXCHANNELWEIGHT1    24
6432 #define M_RXCHANNELWEIGHT1    0xffU
6433 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
6434 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
6435 
6436 #define S_RXCHANNELWEIGHT0    16
6437 #define M_RXCHANNELWEIGHT0    0xffU
6438 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
6439 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
6440 
6441 #define S_TIMERMODE    8
6442 #define M_TIMERMODE    0xffU
6443 #define V_TIMERMODE(x) ((x) << S_TIMERMODE)
6444 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
6445 
6446 #define S_TXCHANNELXOFFEN    0
6447 #define M_TXCHANNELXOFFEN    0xfU
6448 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
6449 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
6450 
6451 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
6452 
6453 #define S_RX_MOD_WEIGHT    24
6454 #define M_RX_MOD_WEIGHT    0xffU
6455 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
6456 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
6457 
6458 #define S_TX_MOD_WEIGHT    16
6459 #define M_TX_MOD_WEIGHT    0xffU
6460 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
6461 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
6462 
6463 #define S_TX_MOD_QUEUE_REQ_MAP    0
6464 #define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
6465 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
6466 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
6467 
6468 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
6469 
6470 #define S_TX_MODQ_WEIGHT7    24
6471 #define M_TX_MODQ_WEIGHT7    0xffU
6472 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
6473 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
6474 
6475 #define S_TX_MODQ_WEIGHT6    16
6476 #define M_TX_MODQ_WEIGHT6    0xffU
6477 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
6478 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
6479 
6480 #define S_TX_MODQ_WEIGHT5    8
6481 #define M_TX_MODQ_WEIGHT5    0xffU
6482 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
6483 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
6484 
6485 #define S_TX_MODQ_WEIGHT4    0
6486 #define M_TX_MODQ_WEIGHT4    0xffU
6487 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
6488 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
6489 
6490 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
6491 
6492 #define S_TX_MODQ_WEIGHT3    24
6493 #define M_TX_MODQ_WEIGHT3    0xffU
6494 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
6495 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
6496 
6497 #define S_TX_MODQ_WEIGHT2    16
6498 #define M_TX_MODQ_WEIGHT2    0xffU
6499 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
6500 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
6501 
6502 #define S_TX_MODQ_WEIGHT1    8
6503 #define M_TX_MODQ_WEIGHT1    0xffU
6504 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
6505 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
6506 
6507 #define S_TX_MODQ_WEIGHT0    0
6508 #define M_TX_MODQ_WEIGHT0    0xffU
6509 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
6510 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
6511 
6512 #define A_TP_PIO_ADDR 0x7e40
6513 #define A_TP_PIO_DATA 0x7e44
6514 #define A_TP_MIB_INDEX 0x7e50
6515 #define A_TP_MIB_DATA 0x7e54
6516 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
6517 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
6518 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
6519 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
6520 
6521 #define S_CMMAXPSTRUCT    0
6522 #define M_CMMAXPSTRUCT    0x1fffffU
6523 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
6524 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
6525 
6526 #define A_TP_INT_ENABLE 0x7e70
6527 
6528 #define S_FLMTXFLSTEMPTY    30
6529 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
6530 #define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
6531 
6532 #define A_TP_INT_CAUSE 0x7e74
6533 #define A_TP_PER_ENABLE 0x7e78
6534 #define A_TP_FLM_FREE_PS_CNT 0x7e80
6535 
6536 #define S_FREEPSTRUCTCOUNT    0
6537 #define M_FREEPSTRUCTCOUNT    0x1fffffU
6538 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
6539 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
6540 
6541 #define A_TP_FLM_FREE_RX_CNT 0x7e84
6542 
6543 #define S_FREERXPAGECHN    28
6544 #define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
6545 #define F_FREERXPAGECHN    V_FREERXPAGECHN(1U)
6546 
6547 #define S_FREERXPAGECOUNT    0
6548 #define M_FREERXPAGECOUNT    0x1fffffU
6549 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
6550 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
6551 
6552 #define A_TP_FLM_FREE_TX_CNT 0x7e88
6553 
6554 #define S_FREETXPAGECHN    28
6555 #define M_FREETXPAGECHN    0x3U
6556 #define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
6557 #define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
6558 
6559 #define S_FREETXPAGECOUNT    0
6560 #define M_FREETXPAGECOUNT    0x1fffffU
6561 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
6562 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
6563 
6564 #define A_TP_TX_ORATE 0x7ebc
6565 
6566 #define S_OFDRATE3    24
6567 #define M_OFDRATE3    0xffU
6568 #define V_OFDRATE3(x) ((x) << S_OFDRATE3)
6569 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
6570 
6571 #define S_OFDRATE2    16
6572 #define M_OFDRATE2    0xffU
6573 #define V_OFDRATE2(x) ((x) << S_OFDRATE2)
6574 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
6575 
6576 #define S_OFDRATE1    8
6577 #define M_OFDRATE1    0xffU
6578 #define V_OFDRATE1(x) ((x) << S_OFDRATE1)
6579 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
6580 
6581 #define S_OFDRATE0    0
6582 #define M_OFDRATE0    0xffU
6583 #define V_OFDRATE0(x) ((x) << S_OFDRATE0)
6584 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
6585 
6586 #define A_TP_TX_TRATE 0x7ed0
6587 
6588 #define S_TNLRATE3    24
6589 #define M_TNLRATE3    0xffU
6590 #define V_TNLRATE3(x) ((x) << S_TNLRATE3)
6591 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
6592 
6593 #define S_TNLRATE2    16
6594 #define M_TNLRATE2    0xffU
6595 #define V_TNLRATE2(x) ((x) << S_TNLRATE2)
6596 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
6597 
6598 #define S_TNLRATE1    8
6599 #define M_TNLRATE1    0xffU
6600 #define V_TNLRATE1(x) ((x) << S_TNLRATE1)
6601 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
6602 
6603 #define S_TNLRATE0    0
6604 #define M_TNLRATE0    0xffU
6605 #define V_TNLRATE0(x) ((x) << S_TNLRATE0)
6606 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
6607 
6608 #define A_TP_DBG_LA_CONFIG 0x7ed4
6609 
6610 #define S_DBGLAOPCENABLE    24
6611 #define M_DBGLAOPCENABLE    0xffU
6612 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
6613 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
6614 
6615 #define S_DBGLAWHLF    23
6616 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
6617 #define F_DBGLAWHLF    V_DBGLAWHLF(1U)
6618 
6619 #define S_DBGLAWPTR    16
6620 #define M_DBGLAWPTR    0x7fU
6621 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
6622 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
6623 
6624 #define S_DBGLAMODE    14
6625 #define M_DBGLAMODE    0x3U
6626 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
6627 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
6628 
6629 #define S_DBGLAFATALFREEZE    13
6630 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
6631 #define F_DBGLAFATALFREEZE    V_DBGLAFATALFREEZE(1U)
6632 
6633 #define S_DBGLAENABLE    12
6634 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
6635 #define F_DBGLAENABLE    V_DBGLAENABLE(1U)
6636 
6637 #define S_DBGLARPTR    0
6638 #define M_DBGLARPTR    0x7fU
6639 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
6640 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
6641 
6642 #define A_TP_DBG_LA_DATAL 0x7ed8
6643 #define A_TP_DBG_LA_DATAH 0x7edc
6644 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
6645 
6646 #define S_TXTIMERSEPQ1    16
6647 #define M_TXTIMERSEPQ1    0xffffU
6648 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
6649 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
6650 
6651 #define S_TXTIMERSEPQ0    0
6652 #define M_TXTIMERSEPQ0    0xffffU
6653 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
6654 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
6655 
6656 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
6657 
6658 #define S_TXRATEINCQ1    24
6659 #define M_TXRATEINCQ1    0xffU
6660 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
6661 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
6662 
6663 #define S_TXRATETCKQ1    16
6664 #define M_TXRATETCKQ1    0xffU
6665 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
6666 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
6667 
6668 #define S_TXRATEINCQ0    8
6669 #define M_TXRATEINCQ0    0xffU
6670 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
6671 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
6672 
6673 #define S_TXRATETCKQ0    0
6674 #define M_TXRATETCKQ0    0xffU
6675 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
6676 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
6677 
6678 #define A_TP_RSS_PF0_CONFIG 0x30
6679 
6680 #define S_MAPENABLE    31
6681 #define V_MAPENABLE(x) ((x) << S_MAPENABLE)
6682 #define F_MAPENABLE    V_MAPENABLE(1U)
6683 
6684 #define S_CHNENABLE    30
6685 #define V_CHNENABLE(x) ((x) << S_CHNENABLE)
6686 #define F_CHNENABLE    V_CHNENABLE(1U)
6687 
6688 #define S_PRTENABLE    29
6689 #define V_PRTENABLE(x) ((x) << S_PRTENABLE)
6690 #define F_PRTENABLE    V_PRTENABLE(1U)
6691 
6692 #define S_UDPFOURTUPEN    28
6693 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
6694 #define F_UDPFOURTUPEN    V_UDPFOURTUPEN(1U)
6695 
6696 #define S_IP6FOURTUPEN    27
6697 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
6698 #define F_IP6FOURTUPEN    V_IP6FOURTUPEN(1U)
6699 
6700 #define S_IP6TWOTUPEN    26
6701 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
6702 #define F_IP6TWOTUPEN    V_IP6TWOTUPEN(1U)
6703 
6704 #define S_IP4FOURTUPEN    25
6705 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
6706 #define F_IP4FOURTUPEN    V_IP4FOURTUPEN(1U)
6707 
6708 #define S_IP4TWOTUPEN    24
6709 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
6710 #define F_IP4TWOTUPEN    V_IP4TWOTUPEN(1U)
6711 
6712 #define S_IVFWIDTH    20
6713 #define M_IVFWIDTH    0xfU
6714 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
6715 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
6716 
6717 #define S_CH1DEFAULTQUEUE    10
6718 #define M_CH1DEFAULTQUEUE    0x3ffU
6719 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
6720 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
6721 
6722 #define S_CH0DEFAULTQUEUE    0
6723 #define M_CH0DEFAULTQUEUE    0x3ffU
6724 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
6725 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
6726 
6727 #define S_PRIENABLE    30
6728 #define V_PRIENABLE(x) ((x) << S_PRIENABLE)
6729 #define F_PRIENABLE    V_PRIENABLE(1U)
6730 
6731 #define S_T6_CHNENABLE    29
6732 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
6733 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
6734 
6735 #define A_TP_RSS_PF_MAP 0x38
6736 
6737 #define S_LKPIDXSIZE    24
6738 #define M_LKPIDXSIZE    0x3U
6739 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
6740 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
6741 
6742 #define S_PF7LKPIDX    21
6743 #define M_PF7LKPIDX    0x7U
6744 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
6745 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
6746 
6747 #define S_PF6LKPIDX    18
6748 #define M_PF6LKPIDX    0x7U
6749 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
6750 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
6751 
6752 #define S_PF5LKPIDX    15
6753 #define M_PF5LKPIDX    0x7U
6754 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
6755 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
6756 
6757 #define S_PF4LKPIDX    12
6758 #define M_PF4LKPIDX    0x7U
6759 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
6760 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
6761 
6762 #define S_PF3LKPIDX    9
6763 #define M_PF3LKPIDX    0x7U
6764 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
6765 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
6766 
6767 #define S_PF2LKPIDX    6
6768 #define M_PF2LKPIDX    0x7U
6769 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
6770 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
6771 
6772 #define S_PF1LKPIDX    3
6773 #define M_PF1LKPIDX    0x7U
6774 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
6775 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
6776 
6777 #define S_PF0LKPIDX    0
6778 #define M_PF0LKPIDX    0x7U
6779 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
6780 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
6781 
6782 #define A_TP_RSS_PF_MSK 0x39
6783 
6784 #define S_PF7MSKSIZE    28
6785 #define M_PF7MSKSIZE    0xfU
6786 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
6787 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
6788 
6789 #define S_PF6MSKSIZE    24
6790 #define M_PF6MSKSIZE    0xfU
6791 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
6792 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
6793 
6794 #define S_PF5MSKSIZE    20
6795 #define M_PF5MSKSIZE    0xfU
6796 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
6797 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
6798 
6799 #define S_PF4MSKSIZE    16
6800 #define M_PF4MSKSIZE    0xfU
6801 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
6802 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
6803 
6804 #define S_PF3MSKSIZE    12
6805 #define M_PF3MSKSIZE    0xfU
6806 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
6807 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
6808 
6809 #define S_PF2MSKSIZE    8
6810 #define M_PF2MSKSIZE    0xfU
6811 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
6812 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
6813 
6814 #define S_PF1MSKSIZE    4
6815 #define M_PF1MSKSIZE    0xfU
6816 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
6817 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
6818 
6819 #define S_PF0MSKSIZE    0
6820 #define M_PF0MSKSIZE    0xfU
6821 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
6822 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
6823 
6824 #define A_TP_RSS_VFL_CONFIG 0x3a
6825 #define A_TP_RSS_VFH_CONFIG 0x3b
6826 
6827 #define S_ENABLEUDPHASH    31
6828 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
6829 #define F_ENABLEUDPHASH    V_ENABLEUDPHASH(1U)
6830 
6831 #define S_VFUPEN    30
6832 #define V_VFUPEN(x) ((x) << S_VFUPEN)
6833 #define F_VFUPEN    V_VFUPEN(1U)
6834 
6835 #define S_VFVLNEX    28
6836 #define V_VFVLNEX(x) ((x) << S_VFVLNEX)
6837 #define F_VFVLNEX    V_VFVLNEX(1U)
6838 
6839 #define S_VFPRTEN    27
6840 #define V_VFPRTEN(x) ((x) << S_VFPRTEN)
6841 #define F_VFPRTEN    V_VFPRTEN(1U)
6842 
6843 #define S_VFCHNEN    26
6844 #define V_VFCHNEN(x) ((x) << S_VFCHNEN)
6845 #define F_VFCHNEN    V_VFCHNEN(1U)
6846 
6847 #define S_DEFAULTQUEUE    16
6848 #define M_DEFAULTQUEUE    0x3ffU
6849 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
6850 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
6851 
6852 #define S_VFLKPIDX    8
6853 #define M_VFLKPIDX    0xffU
6854 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
6855 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
6856 
6857 #define S_VFIP6FOURTUPEN    7
6858 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
6859 #define F_VFIP6FOURTUPEN    V_VFIP6FOURTUPEN(1U)
6860 
6861 #define S_VFIP6TWOTUPEN    6
6862 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
6863 #define F_VFIP6TWOTUPEN    V_VFIP6TWOTUPEN(1U)
6864 
6865 #define S_VFIP4FOURTUPEN    5
6866 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
6867 #define F_VFIP4FOURTUPEN    V_VFIP4FOURTUPEN(1U)
6868 
6869 #define S_VFIP4TWOTUPEN    4
6870 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
6871 #define F_VFIP4TWOTUPEN    V_VFIP4TWOTUPEN(1U)
6872 
6873 #define S_KEYINDEX    0
6874 #define M_KEYINDEX    0xfU
6875 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
6876 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
6877 
6878 #define A_TP_RSS_SECRET_KEY0 0x40
6879 #define A_TP_DBG_ESIDE_PKT0 0x130
6880 
6881 #define S_ETXSOPCNT    28
6882 #define M_ETXSOPCNT    0xfU
6883 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
6884 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
6885 
6886 #define S_ETXEOPCNT    24
6887 #define M_ETXEOPCNT    0xfU
6888 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
6889 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
6890 
6891 #define S_ETXPLDSOPCNT    20
6892 #define M_ETXPLDSOPCNT    0xfU
6893 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
6894 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
6895 
6896 #define S_ETXPLDEOPCNT    16
6897 #define M_ETXPLDEOPCNT    0xfU
6898 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
6899 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
6900 
6901 #define S_ERXSOPCNT    12
6902 #define M_ERXSOPCNT    0xfU
6903 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
6904 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
6905 
6906 #define S_ERXEOPCNT    8
6907 #define M_ERXEOPCNT    0xfU
6908 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
6909 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
6910 
6911 #define S_ERXPLDSOPCNT    4
6912 #define M_ERXPLDSOPCNT    0xfU
6913 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
6914 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
6915 
6916 #define S_ERXPLDEOPCNT    0
6917 #define M_ERXPLDEOPCNT    0xfU
6918 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
6919 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
6920 
6921 #define A_TP_DBG_ESIDE_PKT1 0x131
6922 #define A_TP_DBG_ESIDE_PKT2 0x132
6923 #define A_TP_DBG_ESIDE_PKT3 0x133
6924 #define A_TP_VLAN_PRI_MAP 0x140
6925 
6926 #define S_FRAGMENTATION    9
6927 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
6928 #define F_FRAGMENTATION    V_FRAGMENTATION(1U)
6929 
6930 #define S_MPSHITTYPE    8
6931 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
6932 #define F_MPSHITTYPE    V_MPSHITTYPE(1U)
6933 
6934 #define S_MACMATCH    7
6935 #define V_MACMATCH(x) ((x) << S_MACMATCH)
6936 #define F_MACMATCH    V_MACMATCH(1U)
6937 
6938 #define S_ETHERTYPE    6
6939 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
6940 #define F_ETHERTYPE    V_ETHERTYPE(1U)
6941 
6942 #define S_PROTOCOL    5
6943 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
6944 #define F_PROTOCOL    V_PROTOCOL(1U)
6945 
6946 #define S_TOS    4
6947 #define V_TOS(x) ((x) << S_TOS)
6948 #define F_TOS    V_TOS(1U)
6949 
6950 #define S_VLAN    3
6951 #define V_VLAN(x) ((x) << S_VLAN)
6952 #define F_VLAN    V_VLAN(1U)
6953 
6954 #define S_VNIC_ID    2
6955 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
6956 #define F_VNIC_ID    V_VNIC_ID(1U)
6957 
6958 #define S_PORT    1
6959 #define V_PORT(x) ((x) << S_PORT)
6960 #define F_PORT    V_PORT(1U)
6961 
6962 #define S_FCOE    0
6963 #define V_FCOE(x) ((x) << S_FCOE)
6964 #define F_FCOE    V_FCOE(1U)
6965 
6966 #define S_FILTERMODE    15
6967 #define V_FILTERMODE(x) ((x) << S_FILTERMODE)
6968 #define F_FILTERMODE    V_FILTERMODE(1U)
6969 
6970 #define S_FCOEMASK    14
6971 #define V_FCOEMASK(x) ((x) << S_FCOEMASK)
6972 #define F_FCOEMASK    V_FCOEMASK(1U)
6973 
6974 #define S_SRVRSRAM    13
6975 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
6976 #define F_SRVRSRAM    V_SRVRSRAM(1U)
6977 
6978 #define A_TP_INGRESS_CONFIG 0x141
6979 
6980 #define S_OPAQUE_TYPE    16
6981 #define M_OPAQUE_TYPE    0xffffU
6982 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
6983 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
6984 
6985 #define S_OPAQUE_RM    15
6986 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
6987 #define F_OPAQUE_RM    V_OPAQUE_RM(1U)
6988 
6989 #define S_OPAQUE_HDR_SIZE    14
6990 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
6991 #define F_OPAQUE_HDR_SIZE    V_OPAQUE_HDR_SIZE(1U)
6992 
6993 #define S_OPAQUE_RM_MAC_IN_MAC    13
6994 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
6995 #define F_OPAQUE_RM_MAC_IN_MAC    V_OPAQUE_RM_MAC_IN_MAC(1U)
6996 
6997 #define S_FCOE_TARGET    12
6998 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
6999 #define F_FCOE_TARGET    V_FCOE_TARGET(1U)
7000 
7001 #define S_VNIC    11
7002 #define V_VNIC(x) ((x) << S_VNIC)
7003 #define F_VNIC    V_VNIC(1U)
7004 
7005 #define S_CSUM_HAS_PSEUDO_HDR    10
7006 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
7007 #define F_CSUM_HAS_PSEUDO_HDR    V_CSUM_HAS_PSEUDO_HDR(1U)
7008 
7009 #define S_RM_OVLAN    9
7010 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
7011 #define F_RM_OVLAN    V_RM_OVLAN(1U)
7012 
7013 #define S_LOOKUPEVERYPKT    8
7014 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
7015 #define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
7016 
7017 #define S_IPV6_EXT_HDR_SKIP    0
7018 #define M_IPV6_EXT_HDR_SKIP    0xffU
7019 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
7020 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
7021 
7022 #define S_FRAG_LEN_MOD8_COMPAT    12
7023 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
7024 #define F_FRAG_LEN_MOD8_COMPAT    V_FRAG_LEN_MOD8_COMPAT(1U)
7025 
7026 #define S_USE_ENC_IDX    13
7027 #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
7028 #define F_USE_ENC_IDX    V_USE_ENC_IDX(1U)
7029 
7030 #define A_TP_ESIDE_CONFIG 0x160
7031 
7032 #define S_VNI_EN    26
7033 #define V_VNI_EN(x) ((x) << S_VNI_EN)
7034 #define F_VNI_EN    V_VNI_EN(1U)
7035 
7036 #define S_ENC_RX_EN    25
7037 #define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN)
7038 #define F_ENC_RX_EN    V_ENC_RX_EN(1U)
7039 
7040 #define S_TNL_LKP_INNER_SEL    24
7041 #define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL)
7042 #define F_TNL_LKP_INNER_SEL    V_TNL_LKP_INNER_SEL(1U)
7043 
7044 #define S_ROCEV2UDPPORT    0
7045 #define M_ROCEV2UDPPORT    0xffffU
7046 #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
7047 #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)
7048 
7049 #define A_TP_DBG_CSIDE_RX0 0x230
7050 
7051 #define S_CRXSOPCNT    28
7052 #define M_CRXSOPCNT    0xfU
7053 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
7054 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
7055 
7056 #define S_CRXEOPCNT    24
7057 #define M_CRXEOPCNT    0xfU
7058 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
7059 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
7060 
7061 #define S_CRXPLDSOPCNT    20
7062 #define M_CRXPLDSOPCNT    0xfU
7063 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
7064 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
7065 
7066 #define S_CRXPLDEOPCNT    16
7067 #define M_CRXPLDEOPCNT    0xfU
7068 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
7069 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
7070 
7071 #define S_CRXARBSOPCNT    12
7072 #define M_CRXARBSOPCNT    0xfU
7073 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
7074 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
7075 
7076 #define S_CRXARBEOPCNT    8
7077 #define M_CRXARBEOPCNT    0xfU
7078 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
7079 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
7080 
7081 #define S_CRXCPLSOPCNT    4
7082 #define M_CRXCPLSOPCNT    0xfU
7083 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
7084 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
7085 
7086 #define S_CRXCPLEOPCNT    0
7087 #define M_CRXCPLEOPCNT    0xfU
7088 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
7089 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
7090 
7091 #define A_TP_DBG_CSIDE_RX1 0x231
7092 #define A_TP_DBG_CSIDE_RX2 0x232
7093 #define A_TP_DBG_CSIDE_RX3 0x233
7094 #define A_TP_DBG_CSIDE_TX0 0x234
7095 
7096 #define S_TXSOPCNT    28
7097 #define M_TXSOPCNT    0xfU
7098 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
7099 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
7100 
7101 #define S_TXEOPCNT    24
7102 #define M_TXEOPCNT    0xfU
7103 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
7104 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
7105 
7106 #define S_TXPLDSOPCNT    20
7107 #define M_TXPLDSOPCNT    0xfU
7108 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
7109 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
7110 
7111 #define S_TXPLDEOPCNT    16
7112 #define M_TXPLDEOPCNT    0xfU
7113 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
7114 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
7115 
7116 #define S_TXARBSOPCNT    12
7117 #define M_TXARBSOPCNT    0xfU
7118 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
7119 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
7120 
7121 #define S_TXARBEOPCNT    8
7122 #define M_TXARBEOPCNT    0xfU
7123 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
7124 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
7125 
7126 #define S_TXCPLSOPCNT    4
7127 #define M_TXCPLSOPCNT    0xfU
7128 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
7129 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
7130 
7131 #define S_TXCPLEOPCNT    0
7132 #define M_TXCPLEOPCNT    0xfU
7133 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
7134 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
7135 
7136 #define A_TP_DBG_CSIDE_TX1 0x235
7137 #define A_TP_DBG_CSIDE_TX2 0x236
7138 #define A_TP_DBG_CSIDE_TX3 0x237
7139 #define A_TP_MIB_MAC_IN_ERR_0 0x0
7140 #define A_TP_MIB_MAC_IN_ERR_1 0x1
7141 #define A_TP_MIB_MAC_IN_ERR_2 0x2
7142 #define A_TP_MIB_MAC_IN_ERR_3 0x3
7143 #define A_TP_MIB_HDR_IN_ERR_0 0x4
7144 #define A_TP_MIB_HDR_IN_ERR_1 0x5
7145 #define A_TP_MIB_HDR_IN_ERR_2 0x6
7146 #define A_TP_MIB_HDR_IN_ERR_3 0x7
7147 #define A_TP_MIB_TCP_IN_ERR_0 0x8
7148 #define A_TP_MIB_TCP_IN_ERR_1 0x9
7149 #define A_TP_MIB_TCP_IN_ERR_2 0xa
7150 #define A_TP_MIB_TCP_IN_ERR_3 0xb
7151 #define A_TP_MIB_TCP_OUT_RST 0xc
7152 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
7153 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
7154 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
7155 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
7156 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
7157 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
7158 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
7159 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
7160 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
7161 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
7162 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
7163 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
7164 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
7165 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
7166 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
7167 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
7168 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
7169 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
7170 #define A_TP_MIB_TNL_IN_PKT_0 0x24
7171 #define A_TP_MIB_TNL_IN_PKT_1 0x25
7172 #define A_TP_MIB_TNL_IN_PKT_2 0x26
7173 #define A_TP_MIB_TNL_IN_PKT_3 0x27
7174 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
7175 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
7176 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
7177 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
7178 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
7179 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
7180 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
7181 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
7182 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
7183 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
7184 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
7185 #define A_TP_MIB_OFD_ARP_DROP 0x36
7186 #define A_TP_MIB_OFD_DFR_DROP 0x37
7187 #define A_TP_MIB_CPL_IN_REQ_0 0x38
7188 #define A_TP_MIB_CPL_IN_REQ_1 0x39
7189 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
7190 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
7191 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
7192 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
7193 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
7194 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
7195 #define A_TP_MIB_TNL_LPBK_0 0x40
7196 #define A_TP_MIB_TNL_LPBK_1 0x41
7197 #define A_TP_MIB_TNL_LPBK_2 0x42
7198 #define A_TP_MIB_TNL_LPBK_3 0x43
7199 #define A_TP_MIB_TNL_DROP_0 0x44
7200 #define A_TP_MIB_TNL_DROP_1 0x45
7201 #define A_TP_MIB_TNL_DROP_2 0x46
7202 #define A_TP_MIB_TNL_DROP_3 0x47
7203 #define A_TP_MIB_FCOE_DDP_0 0x48
7204 #define A_TP_MIB_FCOE_DDP_1 0x49
7205 #define A_TP_MIB_FCOE_DDP_2 0x4a
7206 #define A_TP_MIB_FCOE_DDP_3 0x4b
7207 #define A_TP_MIB_FCOE_DROP_0 0x4c
7208 #define A_TP_MIB_FCOE_DROP_1 0x4d
7209 #define A_TP_MIB_FCOE_DROP_2 0x4e
7210 #define A_TP_MIB_FCOE_DROP_3 0x4f
7211 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
7212 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
7213 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
7214 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
7215 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
7216 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
7217 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
7218 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
7219 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
7220 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
7221 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
7222 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
7223 #define A_TP_MIB_USM_PKTS 0x5c
7224 #define A_TP_MIB_USM_DROP 0x5d
7225 #define A_TP_MIB_USM_BYTES_HI 0x5e
7226 #define A_TP_MIB_USM_BYTES_LO 0x5f
7227 #define A_TP_MIB_TID_DEL 0x60
7228 #define A_TP_MIB_TID_INV 0x61
7229 #define A_TP_MIB_TID_ACT 0x62
7230 #define A_TP_MIB_TID_PAS 0x63
7231 #define A_TP_MIB_RQE_DFR_PKT 0x64
7232 #define A_TP_MIB_RQE_DFR_MOD 0x65
7233 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
7234 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
7235 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
7236 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
7237 #define A_TP_MIB_ENG_LINE_0 0x6c
7238 #define A_TP_MIB_ENG_LINE_1 0x6d
7239 #define A_TP_MIB_ENG_LINE_2 0x6e
7240 #define A_TP_MIB_ENG_LINE_3 0x6f
7241 #define A_TP_MIB_TNL_ERR_0 0x70
7242 #define A_TP_MIB_TNL_ERR_1 0x71
7243 #define A_TP_MIB_TNL_ERR_2 0x72
7244 #define A_TP_MIB_TNL_ERR_3 0x73
7245 
7246 /* registers for module ULP_TX */
7247 #define ULP_TX_BASE_ADDR 0x8dc0
7248 
7249 #define A_ULP_TX_INT_CAUSE 0x8dcc
7250 
7251 #define S_PBL_BOUND_ERR_CH3    31
7252 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
7253 #define F_PBL_BOUND_ERR_CH3    V_PBL_BOUND_ERR_CH3(1U)
7254 
7255 #define S_PBL_BOUND_ERR_CH2    30
7256 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
7257 #define F_PBL_BOUND_ERR_CH2    V_PBL_BOUND_ERR_CH2(1U)
7258 
7259 #define S_PBL_BOUND_ERR_CH1    29
7260 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
7261 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
7262 
7263 #define S_PBL_BOUND_ERR_CH0    28
7264 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
7265 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
7266 
7267 #define S_SGE2ULP_FIFO_PERR_SET3    27
7268 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
7269 #define F_SGE2ULP_FIFO_PERR_SET3    V_SGE2ULP_FIFO_PERR_SET3(1U)
7270 
7271 #define S_SGE2ULP_FIFO_PERR_SET2    26
7272 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
7273 #define F_SGE2ULP_FIFO_PERR_SET2    V_SGE2ULP_FIFO_PERR_SET2(1U)
7274 
7275 #define S_SGE2ULP_FIFO_PERR_SET1    25
7276 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
7277 #define F_SGE2ULP_FIFO_PERR_SET1    V_SGE2ULP_FIFO_PERR_SET1(1U)
7278 
7279 #define S_SGE2ULP_FIFO_PERR_SET0    24
7280 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
7281 #define F_SGE2ULP_FIFO_PERR_SET0    V_SGE2ULP_FIFO_PERR_SET0(1U)
7282 
7283 #define S_CIM2ULP_FIFO_PERR_SET3    23
7284 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
7285 #define F_CIM2ULP_FIFO_PERR_SET3    V_CIM2ULP_FIFO_PERR_SET3(1U)
7286 
7287 #define S_CIM2ULP_FIFO_PERR_SET2    22
7288 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
7289 #define F_CIM2ULP_FIFO_PERR_SET2    V_CIM2ULP_FIFO_PERR_SET2(1U)
7290 
7291 #define S_CIM2ULP_FIFO_PERR_SET1    21
7292 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
7293 #define F_CIM2ULP_FIFO_PERR_SET1    V_CIM2ULP_FIFO_PERR_SET1(1U)
7294 
7295 #define S_CIM2ULP_FIFO_PERR_SET0    20
7296 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
7297 #define F_CIM2ULP_FIFO_PERR_SET0    V_CIM2ULP_FIFO_PERR_SET0(1U)
7298 
7299 #define S_CQE_FIFO_PERR_SET3    19
7300 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
7301 #define F_CQE_FIFO_PERR_SET3    V_CQE_FIFO_PERR_SET3(1U)
7302 
7303 #define S_CQE_FIFO_PERR_SET2    18
7304 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
7305 #define F_CQE_FIFO_PERR_SET2    V_CQE_FIFO_PERR_SET2(1U)
7306 
7307 #define S_CQE_FIFO_PERR_SET1    17
7308 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
7309 #define F_CQE_FIFO_PERR_SET1    V_CQE_FIFO_PERR_SET1(1U)
7310 
7311 #define S_CQE_FIFO_PERR_SET0    16
7312 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
7313 #define F_CQE_FIFO_PERR_SET0    V_CQE_FIFO_PERR_SET0(1U)
7314 
7315 #define S_PBL_FIFO_PERR_SET3    15
7316 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
7317 #define F_PBL_FIFO_PERR_SET3    V_PBL_FIFO_PERR_SET3(1U)
7318 
7319 #define S_PBL_FIFO_PERR_SET2    14
7320 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
7321 #define F_PBL_FIFO_PERR_SET2    V_PBL_FIFO_PERR_SET2(1U)
7322 
7323 #define S_PBL_FIFO_PERR_SET1    13
7324 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
7325 #define F_PBL_FIFO_PERR_SET1    V_PBL_FIFO_PERR_SET1(1U)
7326 
7327 #define S_PBL_FIFO_PERR_SET0    12
7328 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
7329 #define F_PBL_FIFO_PERR_SET0    V_PBL_FIFO_PERR_SET0(1U)
7330 
7331 #define S_CMD_FIFO_PERR_SET3    11
7332 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
7333 #define F_CMD_FIFO_PERR_SET3    V_CMD_FIFO_PERR_SET3(1U)
7334 
7335 #define S_CMD_FIFO_PERR_SET2    10
7336 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
7337 #define F_CMD_FIFO_PERR_SET2    V_CMD_FIFO_PERR_SET2(1U)
7338 
7339 #define S_CMD_FIFO_PERR_SET1    9
7340 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
7341 #define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)
7342 
7343 #define S_CMD_FIFO_PERR_SET0    8
7344 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
7345 #define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)
7346 
7347 #define S_LSO_HDR_SRAM_PERR_SET3    7
7348 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
7349 #define F_LSO_HDR_SRAM_PERR_SET3    V_LSO_HDR_SRAM_PERR_SET3(1U)
7350 
7351 #define S_LSO_HDR_SRAM_PERR_SET2    6
7352 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
7353 #define F_LSO_HDR_SRAM_PERR_SET2    V_LSO_HDR_SRAM_PERR_SET2(1U)
7354 
7355 #define S_LSO_HDR_SRAM_PERR_SET1    5
7356 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
7357 #define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)
7358 
7359 #define S_LSO_HDR_SRAM_PERR_SET0    4
7360 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
7361 #define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)
7362 
7363 #define S_IMM_DATA_PERR_SET_CH3    3
7364 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
7365 #define F_IMM_DATA_PERR_SET_CH3    V_IMM_DATA_PERR_SET_CH3(1U)
7366 
7367 #define S_IMM_DATA_PERR_SET_CH2    2
7368 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
7369 #define F_IMM_DATA_PERR_SET_CH2    V_IMM_DATA_PERR_SET_CH2(1U)
7370 
7371 #define S_IMM_DATA_PERR_SET_CH1    1
7372 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
7373 #define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)
7374 
7375 #define S_IMM_DATA_PERR_SET_CH0    0
7376 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
7377 #define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
7378 
7379 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
7380 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
7381 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
7382 #define A_ULP_TX_PBL_ULIMIT 0x8de0
7383 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
7384 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
7385 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
7386 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
7387 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
7388 #define A_ULP_TX_FPGA_CMD_1 0x8e40
7389 #define A_ULP_TX_FPGA_CMD_2 0x8e44
7390 #define A_ULP_TX_FPGA_CMD_3 0x8e48
7391 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
7392 #define A_ULP_TX_FPGA_CMD_5 0x8e50
7393 #define A_ULP_TX_FPGA_CMD_6 0x8e54
7394 #define A_ULP_TX_FPGA_CMD_7 0x8e58
7395 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
7396 #define A_ULP_TX_FPGA_CMD_9 0x8e60
7397 #define A_ULP_TX_FPGA_CMD_10 0x8e64
7398 #define A_ULP_TX_FPGA_CMD_11 0x8e68
7399 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
7400 #define A_ULP_TX_FPGA_CMD_13 0x8e70
7401 #define A_ULP_TX_FPGA_CMD_14 0x8e74
7402 #define A_ULP_TX_FPGA_CMD_15 0x8e78
7403 #define A_ULP_TX_INT_CAUSE_2 0x8e80
7404 
7405 #define S_SMARBT2ULP_DATA_PERR_SET    12
7406 #define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
7407 #define F_SMARBT2ULP_DATA_PERR_SET    V_SMARBT2ULP_DATA_PERR_SET(1U)
7408 
7409 #define S_ULP2TP_DATA_PERR_SET    11
7410 #define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
7411 #define F_ULP2TP_DATA_PERR_SET    V_ULP2TP_DATA_PERR_SET(1U)
7412 
7413 #define S_MA2ULP_DATA_PERR_SET    10
7414 #define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
7415 #define F_MA2ULP_DATA_PERR_SET    V_MA2ULP_DATA_PERR_SET(1U)
7416 
7417 #define S_SGE2ULP_DATA_PERR_SET    9
7418 #define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
7419 #define F_SGE2ULP_DATA_PERR_SET    V_SGE2ULP_DATA_PERR_SET(1U)
7420 
7421 #define S_CIM2ULP_DATA_PERR_SET    8
7422 #define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
7423 #define F_CIM2ULP_DATA_PERR_SET    V_CIM2ULP_DATA_PERR_SET(1U)
7424 
7425 #define S_FSO_HDR_SRAM_PERR_SET3    7
7426 #define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
7427 #define F_FSO_HDR_SRAM_PERR_SET3    V_FSO_HDR_SRAM_PERR_SET3(1U)
7428 
7429 #define S_FSO_HDR_SRAM_PERR_SET2    6
7430 #define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
7431 #define F_FSO_HDR_SRAM_PERR_SET2    V_FSO_HDR_SRAM_PERR_SET2(1U)
7432 
7433 #define S_FSO_HDR_SRAM_PERR_SET1    5
7434 #define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
7435 #define F_FSO_HDR_SRAM_PERR_SET1    V_FSO_HDR_SRAM_PERR_SET1(1U)
7436 
7437 #define S_FSO_HDR_SRAM_PERR_SET0    4
7438 #define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
7439 #define F_FSO_HDR_SRAM_PERR_SET0    V_FSO_HDR_SRAM_PERR_SET0(1U)
7440 
7441 #define S_T10_PI_SRAM_PERR_SET3    3
7442 #define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
7443 #define F_T10_PI_SRAM_PERR_SET3    V_T10_PI_SRAM_PERR_SET3(1U)
7444 
7445 #define S_T10_PI_SRAM_PERR_SET2    2
7446 #define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
7447 #define F_T10_PI_SRAM_PERR_SET2    V_T10_PI_SRAM_PERR_SET2(1U)
7448 
7449 #define S_T10_PI_SRAM_PERR_SET1    1
7450 #define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
7451 #define F_T10_PI_SRAM_PERR_SET1    V_T10_PI_SRAM_PERR_SET1(1U)
7452 
7453 #define S_T10_PI_SRAM_PERR_SET0    0
7454 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
7455 #define F_T10_PI_SRAM_PERR_SET0    V_T10_PI_SRAM_PERR_SET0(1U)
7456 
7457 #define S_EDMA_IN_FIFO_PERR_SET3    31
7458 #define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3)
7459 #define F_EDMA_IN_FIFO_PERR_SET3    V_EDMA_IN_FIFO_PERR_SET3(1U)
7460 
7461 #define S_EDMA_IN_FIFO_PERR_SET2    30
7462 #define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2)
7463 #define F_EDMA_IN_FIFO_PERR_SET2    V_EDMA_IN_FIFO_PERR_SET2(1U)
7464 
7465 #define S_EDMA_IN_FIFO_PERR_SET1    29
7466 #define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1)
7467 #define F_EDMA_IN_FIFO_PERR_SET1    V_EDMA_IN_FIFO_PERR_SET1(1U)
7468 
7469 #define S_EDMA_IN_FIFO_PERR_SET0    28
7470 #define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0)
7471 #define F_EDMA_IN_FIFO_PERR_SET0    V_EDMA_IN_FIFO_PERR_SET0(1U)
7472 
7473 #define S_ALIGN_CTL_FIFO_PERR_SET3    27
7474 #define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3)
7475 #define F_ALIGN_CTL_FIFO_PERR_SET3    V_ALIGN_CTL_FIFO_PERR_SET3(1U)
7476 
7477 #define S_ALIGN_CTL_FIFO_PERR_SET2    26
7478 #define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2)
7479 #define F_ALIGN_CTL_FIFO_PERR_SET2    V_ALIGN_CTL_FIFO_PERR_SET2(1U)
7480 
7481 #define S_ALIGN_CTL_FIFO_PERR_SET1    25
7482 #define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1)
7483 #define F_ALIGN_CTL_FIFO_PERR_SET1    V_ALIGN_CTL_FIFO_PERR_SET1(1U)
7484 
7485 #define S_ALIGN_CTL_FIFO_PERR_SET0    24
7486 #define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0)
7487 #define F_ALIGN_CTL_FIFO_PERR_SET0    V_ALIGN_CTL_FIFO_PERR_SET0(1U)
7488 
7489 #define S_SGE_FIFO_PERR_SET3    23
7490 #define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3)
7491 #define F_SGE_FIFO_PERR_SET3    V_SGE_FIFO_PERR_SET3(1U)
7492 
7493 #define S_SGE_FIFO_PERR_SET2    22
7494 #define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2)
7495 #define F_SGE_FIFO_PERR_SET2    V_SGE_FIFO_PERR_SET2(1U)
7496 
7497 #define S_SGE_FIFO_PERR_SET1    21
7498 #define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1)
7499 #define F_SGE_FIFO_PERR_SET1    V_SGE_FIFO_PERR_SET1(1U)
7500 
7501 #define S_SGE_FIFO_PERR_SET0    20
7502 #define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0)
7503 #define F_SGE_FIFO_PERR_SET0    V_SGE_FIFO_PERR_SET0(1U)
7504 
7505 #define S_STAG_FIFO_PERR_SET3    19
7506 #define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3)
7507 #define F_STAG_FIFO_PERR_SET3    V_STAG_FIFO_PERR_SET3(1U)
7508 
7509 #define S_STAG_FIFO_PERR_SET2    18
7510 #define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2)
7511 #define F_STAG_FIFO_PERR_SET2    V_STAG_FIFO_PERR_SET2(1U)
7512 
7513 #define S_STAG_FIFO_PERR_SET1    17
7514 #define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1)
7515 #define F_STAG_FIFO_PERR_SET1    V_STAG_FIFO_PERR_SET1(1U)
7516 
7517 #define S_STAG_FIFO_PERR_SET0    16
7518 #define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0)
7519 #define F_STAG_FIFO_PERR_SET0    V_STAG_FIFO_PERR_SET0(1U)
7520 
7521 #define S_MAP_FIFO_PERR_SET3    15
7522 #define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3)
7523 #define F_MAP_FIFO_PERR_SET3    V_MAP_FIFO_PERR_SET3(1U)
7524 
7525 #define S_MAP_FIFO_PERR_SET2    14
7526 #define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2)
7527 #define F_MAP_FIFO_PERR_SET2    V_MAP_FIFO_PERR_SET2(1U)
7528 
7529 #define S_MAP_FIFO_PERR_SET1    13
7530 #define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1)
7531 #define F_MAP_FIFO_PERR_SET1    V_MAP_FIFO_PERR_SET1(1U)
7532 
7533 #define S_MAP_FIFO_PERR_SET0    12
7534 #define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0)
7535 #define F_MAP_FIFO_PERR_SET0    V_MAP_FIFO_PERR_SET0(1U)
7536 
7537 #define S_DMA_FIFO_PERR_SET3    11
7538 #define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3)
7539 #define F_DMA_FIFO_PERR_SET3    V_DMA_FIFO_PERR_SET3(1U)
7540 
7541 #define S_DMA_FIFO_PERR_SET2    10
7542 #define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2)
7543 #define F_DMA_FIFO_PERR_SET2    V_DMA_FIFO_PERR_SET2(1U)
7544 
7545 #define S_DMA_FIFO_PERR_SET1    9
7546 #define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1)
7547 #define F_DMA_FIFO_PERR_SET1    V_DMA_FIFO_PERR_SET1(1U)
7548 
7549 #define S_DMA_FIFO_PERR_SET0    8
7550 #define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0)
7551 #define F_DMA_FIFO_PERR_SET0    V_DMA_FIFO_PERR_SET0(1U)
7552 
7553 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
7554 
7555 #define S_SOP_CNT_ULP2TP    28
7556 #define M_SOP_CNT_ULP2TP    0xfU
7557 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
7558 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
7559 
7560 #define S_EOP_CNT_ULP2TP    24
7561 #define M_EOP_CNT_ULP2TP    0xfU
7562 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
7563 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
7564 
7565 #define S_SOP_CNT_LSO_IN    20
7566 #define M_SOP_CNT_LSO_IN    0xfU
7567 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
7568 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
7569 
7570 #define S_EOP_CNT_LSO_IN    16
7571 #define M_EOP_CNT_LSO_IN    0xfU
7572 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
7573 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
7574 
7575 #define S_SOP_CNT_ALG_IN    12
7576 #define M_SOP_CNT_ALG_IN    0xfU
7577 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
7578 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
7579 
7580 #define S_EOP_CNT_ALG_IN    8
7581 #define M_EOP_CNT_ALG_IN    0xfU
7582 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
7583 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
7584 
7585 #define S_SOP_CNT_CIM2ULP    4
7586 #define M_SOP_CNT_CIM2ULP    0xfU
7587 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
7588 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
7589 
7590 #define S_EOP_CNT_CIM2ULP    0
7591 #define M_EOP_CNT_CIM2ULP    0xfU
7592 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
7593 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
7594 
7595 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
7596 #define A_ULP_TX_SE_CNT_CH1 0x8eac
7597 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
7598 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
7599 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
7600 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
7601 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
7602 #define A_ULP_TX_CSU_REVISION 0x8ebc
7603 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
7604 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
7605 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
7606 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
7607 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
7608 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
7609 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
7610 #define A_ULP_TX_LA_RESERVED_1 0x8edc
7611 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
7612 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
7613 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
7614 #define A_ULP_TX_LA_RESERVED_2 0x8eec
7615 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
7616 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
7617 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
7618 #define A_ULP_TX_LA_RESERVED_3 0x8efc
7619 #define A_ULP_TX_LA_RDPTR_4 0x8f00
7620 #define A_ULP_TX_LA_RDDATA_4 0x8f04
7621 #define A_ULP_TX_LA_WRPTR_4 0x8f08
7622 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
7623 #define A_ULP_TX_LA_RDPTR_5 0x8f10
7624 #define A_ULP_TX_LA_RDDATA_5 0x8f14
7625 #define A_ULP_TX_LA_WRPTR_5 0x8f18
7626 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
7627 #define A_ULP_TX_LA_RDPTR_6 0x8f20
7628 #define A_ULP_TX_LA_RDDATA_6 0x8f24
7629 #define A_ULP_TX_LA_WRPTR_6 0x8f28
7630 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
7631 #define A_ULP_TX_LA_RDPTR_7 0x8f30
7632 #define A_ULP_TX_LA_RDDATA_7 0x8f34
7633 #define A_ULP_TX_LA_WRPTR_7 0x8f38
7634 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
7635 #define A_ULP_TX_LA_RDPTR_8 0x8f40
7636 #define A_ULP_TX_LA_RDDATA_8 0x8f44
7637 #define A_ULP_TX_LA_WRPTR_8 0x8f48
7638 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
7639 #define A_ULP_TX_LA_RDPTR_9 0x8f50
7640 #define A_ULP_TX_LA_RDDATA_9 0x8f54
7641 #define A_ULP_TX_LA_WRPTR_9 0x8f58
7642 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
7643 #define A_ULP_TX_LA_RDPTR_10 0x8f60
7644 #define A_ULP_TX_LA_RDDATA_10 0x8f64
7645 #define A_ULP_TX_LA_WRPTR_10 0x8f68
7646 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
7647 #define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
7648 
7649 #define S_LA_WR0    0
7650 #define V_LA_WR0(x) ((x) << S_LA_WR0)
7651 #define F_LA_WR0    V_LA_WR0(1U)
7652 
7653 #define A_ULP_TX_ASIC_DEBUG_0 0x8f74
7654 #define A_ULP_TX_ASIC_DEBUG_1 0x8f78
7655 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
7656 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
7657 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
7658 #define A_ULP_TX_TLS_CH0_PERR_CAUSE 0xc
7659 
7660 #define S_GLUE_PERR    3
7661 #define V_GLUE_PERR(x) ((x) << S_GLUE_PERR)
7662 #define F_GLUE_PERR    V_GLUE_PERR(1U)
7663 
7664 #define S_DSGL_PERR    2
7665 #define V_DSGL_PERR(x) ((x) << S_DSGL_PERR)
7666 #define F_DSGL_PERR    V_DSGL_PERR(1U)
7667 
7668 #define S_SGE_PERR    1
7669 #define V_SGE_PERR(x) ((x) << S_SGE_PERR)
7670 #define F_SGE_PERR    V_SGE_PERR(1U)
7671 
7672 #define A_ULP_TX_TLS_CH1_PERR_CAUSE 0x4c
7673 
7674 /* registers for module PM_RX */
7675 #define PM_RX_BASE_ADDR 0x8fc0
7676 
7677 #define A_PM_RX_STAT_CONFIG 0x8fc8
7678 #define A_PM_RX_STAT_COUNT 0x8fcc
7679 #define A_PM_RX_STAT_LSB 0x8fd0
7680 #define A_PM_RX_DBG_CTRL 0x8fd0
7681 
7682 #define S_OSPIWRBUSY_T5    21
7683 #define M_OSPIWRBUSY_T5    0x3U
7684 #define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
7685 #define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
7686 
7687 #define S_ISPIWRBUSY    17
7688 #define M_ISPIWRBUSY    0xfU
7689 #define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
7690 #define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
7691 
7692 #define S_PMDBGADDR    0
7693 #define M_PMDBGADDR    0x1ffffU
7694 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
7695 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
7696 
7697 #define A_PM_RX_STAT_MSB 0x8fd4
7698 #define A_PM_RX_DBG_DATA 0x8fd4
7699 #define A_PM_RX_INT_CAUSE 0x8fdc
7700 
7701 #define S_ZERO_E_CMD_ERROR    22
7702 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
7703 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
7704 
7705 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    21
7706 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
7707 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
7708 
7709 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    20
7710 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
7711 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
7712 
7713 #define S_IESPI2_FIFO2X_RX_FRAMING_ERROR    19
7714 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
7715 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR    V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
7716 
7717 #define S_IESPI3_FIFO2X_RX_FRAMING_ERROR    18
7718 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
7719 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR    V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
7720 
7721 #define S_IESPI0_RX_FRAMING_ERROR    17
7722 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
7723 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
7724 
7725 #define S_IESPI1_RX_FRAMING_ERROR    16
7726 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
7727 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
7728 
7729 #define S_IESPI2_RX_FRAMING_ERROR    15
7730 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
7731 #define F_IESPI2_RX_FRAMING_ERROR    V_IESPI2_RX_FRAMING_ERROR(1U)
7732 
7733 #define S_IESPI3_RX_FRAMING_ERROR    14
7734 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
7735 #define F_IESPI3_RX_FRAMING_ERROR    V_IESPI3_RX_FRAMING_ERROR(1U)
7736 
7737 #define S_IESPI0_TX_FRAMING_ERROR    13
7738 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
7739 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
7740 
7741 #define S_IESPI1_TX_FRAMING_ERROR    12
7742 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
7743 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
7744 
7745 #define S_IESPI2_TX_FRAMING_ERROR    11
7746 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
7747 #define F_IESPI2_TX_FRAMING_ERROR    V_IESPI2_TX_FRAMING_ERROR(1U)
7748 
7749 #define S_IESPI3_TX_FRAMING_ERROR    10
7750 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
7751 #define F_IESPI3_TX_FRAMING_ERROR    V_IESPI3_TX_FRAMING_ERROR(1U)
7752 
7753 #define S_OCSPI0_RX_FRAMING_ERROR    9
7754 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
7755 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
7756 
7757 #define S_OCSPI1_RX_FRAMING_ERROR    8
7758 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
7759 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
7760 
7761 #define S_OCSPI0_TX_FRAMING_ERROR    7
7762 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
7763 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
7764 
7765 #define S_OCSPI1_TX_FRAMING_ERROR    6
7766 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
7767 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
7768 
7769 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    5
7770 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
7771 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
7772 
7773 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    4
7774 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
7775 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
7776 
7777 #define S_OCSPI_PAR_ERROR    3
7778 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
7779 #define F_OCSPI_PAR_ERROR    V_OCSPI_PAR_ERROR(1U)
7780 
7781 #define S_DB_OPTIONS_PAR_ERROR    2
7782 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
7783 #define F_DB_OPTIONS_PAR_ERROR    V_DB_OPTIONS_PAR_ERROR(1U)
7784 
7785 #define S_IESPI_PAR_ERROR    1
7786 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
7787 #define F_IESPI_PAR_ERROR    V_IESPI_PAR_ERROR(1U)
7788 
7789 #define S_E_PCMD_PAR_ERROR    0
7790 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
7791 #define F_E_PCMD_PAR_ERROR    V_E_PCMD_PAR_ERROR(1U)
7792 
7793 #define S_OSPI_OVERFLOW1    28
7794 #define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
7795 #define F_OSPI_OVERFLOW1    V_OSPI_OVERFLOW1(1U)
7796 
7797 #define S_OSPI_OVERFLOW0    27
7798 #define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
7799 #define F_OSPI_OVERFLOW0    V_OSPI_OVERFLOW0(1U)
7800 
7801 #define S_MA_INTF_SDC_ERR    26
7802 #define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
7803 #define F_MA_INTF_SDC_ERR    V_MA_INTF_SDC_ERR(1U)
7804 
7805 #define S_BUNDLE_LEN_PARERR    25
7806 #define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
7807 #define F_BUNDLE_LEN_PARERR    V_BUNDLE_LEN_PARERR(1U)
7808 
7809 #define S_BUNDLE_LEN_OVFL    24
7810 #define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
7811 #define F_BUNDLE_LEN_OVFL    V_BUNDLE_LEN_OVFL(1U)
7812 
7813 #define S_SDC_ERR    23
7814 #define V_SDC_ERR(x) ((x) << S_SDC_ERR)
7815 #define F_SDC_ERR    V_SDC_ERR(1U)
7816 
7817 #define A_PM_RX_DBG_STAT_MSB 0x10013
7818 #define A_PM_RX_DBG_STAT_LSB 0x10014
7819 
7820 /* registers for module PM_TX */
7821 #define PM_TX_BASE_ADDR 0x8fe0
7822 
7823 #define A_PM_TX_STAT_CONFIG 0x8fe8
7824 #define A_PM_TX_STAT_COUNT 0x8fec
7825 #define A_PM_TX_STAT_LSB 0x8ff0
7826 #define A_PM_TX_DBG_CTRL 0x8ff0
7827 
7828 #define S_OSPIWRBUSY    21
7829 #define M_OSPIWRBUSY    0xfU
7830 #define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
7831 #define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
7832 
7833 #define A_PM_TX_STAT_MSB 0x8ff4
7834 #define A_PM_TX_DBG_DATA 0x8ff4
7835 #define A_PM_TX_INT_CAUSE 0x8ffc
7836 
7837 #define S_PCMD_LEN_OVFL0    31
7838 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
7839 #define F_PCMD_LEN_OVFL0    V_PCMD_LEN_OVFL0(1U)
7840 
7841 #define S_PCMD_LEN_OVFL1    30
7842 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
7843 #define F_PCMD_LEN_OVFL1    V_PCMD_LEN_OVFL1(1U)
7844 
7845 #define S_PCMD_LEN_OVFL2    29
7846 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
7847 #define F_PCMD_LEN_OVFL2    V_PCMD_LEN_OVFL2(1U)
7848 
7849 #define S_ZERO_C_CMD_ERROR    28
7850 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
7851 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
7852 
7853 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    27
7854 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
7855 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
7856 
7857 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    26
7858 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
7859 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
7860 
7861 #define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR    25
7862 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
7863 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
7864 
7865 #define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR    24
7866 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
7867 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
7868 
7869 #define S_ICSPI0_RX_FRAMING_ERROR    23
7870 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
7871 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
7872 
7873 #define S_ICSPI1_RX_FRAMING_ERROR    22
7874 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
7875 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
7876 
7877 #define S_ICSPI2_RX_FRAMING_ERROR    21
7878 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
7879 #define F_ICSPI2_RX_FRAMING_ERROR    V_ICSPI2_RX_FRAMING_ERROR(1U)
7880 
7881 #define S_ICSPI3_RX_FRAMING_ERROR    20
7882 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
7883 #define F_ICSPI3_RX_FRAMING_ERROR    V_ICSPI3_RX_FRAMING_ERROR(1U)
7884 
7885 #define S_ICSPI0_TX_FRAMING_ERROR    19
7886 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
7887 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
7888 
7889 #define S_ICSPI1_TX_FRAMING_ERROR    18
7890 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
7891 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
7892 
7893 #define S_ICSPI2_TX_FRAMING_ERROR    17
7894 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
7895 #define F_ICSPI2_TX_FRAMING_ERROR    V_ICSPI2_TX_FRAMING_ERROR(1U)
7896 
7897 #define S_ICSPI3_TX_FRAMING_ERROR    16
7898 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
7899 #define F_ICSPI3_TX_FRAMING_ERROR    V_ICSPI3_TX_FRAMING_ERROR(1U)
7900 
7901 #define S_OESPI0_RX_FRAMING_ERROR    15
7902 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
7903 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
7904 
7905 #define S_OESPI1_RX_FRAMING_ERROR    14
7906 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
7907 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
7908 
7909 #define S_OESPI2_RX_FRAMING_ERROR    13
7910 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
7911 #define F_OESPI2_RX_FRAMING_ERROR    V_OESPI2_RX_FRAMING_ERROR(1U)
7912 
7913 #define S_OESPI3_RX_FRAMING_ERROR    12
7914 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
7915 #define F_OESPI3_RX_FRAMING_ERROR    V_OESPI3_RX_FRAMING_ERROR(1U)
7916 
7917 #define S_OESPI0_TX_FRAMING_ERROR    11
7918 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
7919 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
7920 
7921 #define S_OESPI1_TX_FRAMING_ERROR    10
7922 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
7923 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
7924 
7925 #define S_OESPI2_TX_FRAMING_ERROR    9
7926 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
7927 #define F_OESPI2_TX_FRAMING_ERROR    V_OESPI2_TX_FRAMING_ERROR(1U)
7928 
7929 #define S_OESPI3_TX_FRAMING_ERROR    8
7930 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
7931 #define F_OESPI3_TX_FRAMING_ERROR    V_OESPI3_TX_FRAMING_ERROR(1U)
7932 
7933 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
7934 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
7935 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
7936 
7937 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
7938 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
7939 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
7940 
7941 #define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR    5
7942 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
7943 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
7944 
7945 #define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR    4
7946 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
7947 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
7948 
7949 #define S_OESPI_PAR_ERROR    3
7950 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
7951 #define F_OESPI_PAR_ERROR    V_OESPI_PAR_ERROR(1U)
7952 
7953 #define S_ICSPI_PAR_ERROR    1
7954 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
7955 #define F_ICSPI_PAR_ERROR    V_ICSPI_PAR_ERROR(1U)
7956 
7957 #define S_C_PCMD_PAR_ERROR    0
7958 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
7959 #define F_C_PCMD_PAR_ERROR    V_C_PCMD_PAR_ERROR(1U)
7960 
7961 #define S_OSPI_OR_BUNDLE_LEN_PAR_ERR    3
7962 #define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
7963 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR    V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
7964 
7965 #define A_PM_TX_DBG_STAT_MSB 0x1001a
7966 #define A_PM_TX_DBG_STAT_LSB 0x1001b
7967 
7968 /* registers for module MPS */
7969 #define MPS_BASE_ADDR 0x9000
7970 
7971 #define A_MPS_VF_CTL 0x0
7972 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
7973 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
7974 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
7975 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
7976 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
7977 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
7978 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
7979 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
7980 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
7981 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
7982 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
7983 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
7984 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
7985 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
7986 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
7987 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
7988 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
7989 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
7990 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
7991 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
7992 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
7993 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
7994 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
7995 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
7996 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
7997 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
7998 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
7999 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
8000 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
8001 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
8002 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
8003 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
8004 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
8005 
8006 #define S_VALID    20
8007 #define V_VALID(x) ((x) << S_VALID)
8008 #define F_VALID    V_VALID(1U)
8009 
8010 #define S_HASHPORTMAP    16
8011 #define M_HASHPORTMAP    0xfU
8012 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
8013 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
8014 
8015 #define S_MULTILISTEN    15
8016 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
8017 #define F_MULTILISTEN    V_MULTILISTEN(1U)
8018 
8019 #define S_PRIORITY    12
8020 #define M_PRIORITY    0x7U
8021 #define V_PRIORITY(x) ((x) << S_PRIORITY)
8022 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
8023 
8024 #define S_REPLICATE    11
8025 #define V_REPLICATE(x) ((x) << S_REPLICATE)
8026 #define F_REPLICATE    V_REPLICATE(1U)
8027 
8028 #define S_PF    8
8029 #define M_PF    0x7U
8030 #define V_PF(x) ((x) << S_PF)
8031 #define G_PF(x) (((x) >> S_PF) & M_PF)
8032 
8033 #define S_VF_VALID    7
8034 #define V_VF_VALID(x) ((x) << S_VF_VALID)
8035 #define F_VF_VALID    V_VF_VALID(1U)
8036 
8037 #define S_VF    0
8038 #define M_VF    0x7fU
8039 #define V_VF(x) ((x) << S_VF)
8040 #define G_VF(x) (((x) >> S_VF) & M_VF)
8041 
8042 #define S_DISENCAPOUTERRPLCT    23
8043 #define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT)
8044 #define F_DISENCAPOUTERRPLCT    V_DISENCAPOUTERRPLCT(1U)
8045 
8046 #define S_DISENCAP    22
8047 #define V_DISENCAP(x) ((x) << S_DISENCAP)
8048 #define F_DISENCAP    V_DISENCAP(1U)
8049 
8050 #define S_T6_VALID    21
8051 #define V_T6_VALID(x) ((x) << S_T6_VALID)
8052 #define F_T6_VALID    V_T6_VALID(1U)
8053 
8054 #define S_T6_HASHPORTMAP    17
8055 #define M_T6_HASHPORTMAP    0xfU
8056 #define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP)
8057 #define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP)
8058 
8059 #define S_T6_MULTILISTEN    16
8060 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
8061 #define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
8062 
8063 #define S_T6_PRIORITY    13
8064 #define M_T6_PRIORITY    0x7U
8065 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
8066 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
8067 
8068 #define S_T6_REPLICATE    12
8069 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
8070 #define F_T6_REPLICATE    V_T6_REPLICATE(1U)
8071 
8072 #define S_T6_PF    9
8073 #define M_T6_PF    0x7U
8074 #define V_T6_PF(x) ((x) << S_T6_PF)
8075 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
8076 
8077 #define S_T6_VF_VALID    8
8078 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
8079 #define F_T6_VF_VALID    V_T6_VF_VALID(1U)
8080 
8081 #define S_T6_VF    0
8082 #define M_T6_VF    0xffU
8083 #define V_T6_VF(x) ((x) << S_T6_VF)
8084 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
8085 
8086 #define A_MPS_PF_CTL 0x2c0
8087 
8088 #define S_TXEN    1
8089 #define V_TXEN(x) ((x) << S_TXEN)
8090 #define F_TXEN    V_TXEN(1U)
8091 
8092 #define S_RXEN    0
8093 #define V_RXEN(x) ((x) << S_RXEN)
8094 #define F_RXEN    V_RXEN(1U)
8095 
8096 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
8097 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
8098 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
8099 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
8100 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
8101 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
8102 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
8103 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
8104 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
8105 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
8106 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
8107 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
8108 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
8109 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
8110 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
8111 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
8112 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
8113 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
8114 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
8115 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
8116 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
8117 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
8118 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
8119 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
8120 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
8121 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
8122 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
8123 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
8124 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
8125 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
8126 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
8127 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
8128 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
8129 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
8130 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
8131 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
8132 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
8133 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
8134 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
8135 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
8136 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
8137 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
8138 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
8139 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
8140 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
8141 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
8142 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
8143 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
8144 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
8145 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
8146 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
8147 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
8148 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
8149 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
8150 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
8151 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
8152 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
8153 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
8154 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
8155 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
8156 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
8157 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
8158 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
8159 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
8160 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
8161 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
8162 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
8163 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
8164 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
8165 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
8166 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
8167 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
8168 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
8169 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
8170 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
8171 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
8172 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
8173 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
8174 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
8175 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
8176 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
8177 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
8178 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
8179 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
8180 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
8181 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
8182 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
8183 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
8184 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
8185 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
8186 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
8187 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
8188 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
8189 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
8190 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
8191 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
8192 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
8193 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
8194 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
8195 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
8196 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
8197 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
8198 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
8199 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
8200 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
8201 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
8202 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
8203 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
8204 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
8205 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
8206 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
8207 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
8208 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
8209 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
8210 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
8211 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
8212 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
8213 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
8214 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
8215 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
8216 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
8217 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
8218 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
8219 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
8220 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
8221 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
8222 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
8223 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
8224 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
8225 #define A_MPS_CMN_CTL 0x9000
8226 
8227 #define S_DETECT8023    3
8228 #define V_DETECT8023(x) ((x) << S_DETECT8023)
8229 #define F_DETECT8023    V_DETECT8023(1U)
8230 
8231 #define S_VFDIRECTACCESS    2
8232 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
8233 #define F_VFDIRECTACCESS    V_VFDIRECTACCESS(1U)
8234 
8235 #define S_NUMPORTS    0
8236 #define M_NUMPORTS    0x3U
8237 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
8238 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
8239 
8240 #define S_LPBKCRDTCTRL    4
8241 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
8242 #define F_LPBKCRDTCTRL    V_LPBKCRDTCTRL(1U)
8243 
8244 #define A_MPS_INT_CAUSE 0x9008
8245 
8246 #define S_STATINT    5
8247 #define V_STATINT(x) ((x) << S_STATINT)
8248 #define F_STATINT    V_STATINT(1U)
8249 
8250 #define S_TXINT    4
8251 #define V_TXINT(x) ((x) << S_TXINT)
8252 #define F_TXINT    V_TXINT(1U)
8253 
8254 #define S_RXINT    3
8255 #define V_RXINT(x) ((x) << S_RXINT)
8256 #define F_RXINT    V_RXINT(1U)
8257 
8258 #define S_TRCINT    2
8259 #define V_TRCINT(x) ((x) << S_TRCINT)
8260 #define F_TRCINT    V_TRCINT(1U)
8261 
8262 #define S_CLSINT    1
8263 #define V_CLSINT(x) ((x) << S_CLSINT)
8264 #define F_CLSINT    V_CLSINT(1U)
8265 
8266 #define S_PLINT    0
8267 #define V_PLINT(x) ((x) << S_PLINT)
8268 #define F_PLINT    V_PLINT(1U)
8269 
8270 #define A_MPS_TX_INT_CAUSE 0x9408
8271 
8272 #define S_PORTERR    16
8273 #define V_PORTERR(x) ((x) << S_PORTERR)
8274 #define F_PORTERR    V_PORTERR(1U)
8275 
8276 #define S_FRMERR    15
8277 #define V_FRMERR(x) ((x) << S_FRMERR)
8278 #define F_FRMERR    V_FRMERR(1U)
8279 
8280 #define S_SECNTERR    14
8281 #define V_SECNTERR(x) ((x) << S_SECNTERR)
8282 #define F_SECNTERR    V_SECNTERR(1U)
8283 
8284 #define S_BUBBLE    13
8285 #define V_BUBBLE(x) ((x) << S_BUBBLE)
8286 #define F_BUBBLE    V_BUBBLE(1U)
8287 
8288 #define S_TXDESCFIFO    9
8289 #define M_TXDESCFIFO    0xfU
8290 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
8291 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
8292 
8293 #define S_TXDATAFIFO    5
8294 #define M_TXDATAFIFO    0xfU
8295 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
8296 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
8297 
8298 #define S_NCSIFIFO    4
8299 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
8300 #define F_NCSIFIFO    V_NCSIFIFO(1U)
8301 
8302 #define S_TPFIFO    0
8303 #define M_TPFIFO    0xfU
8304 #define V_TPFIFO(x) ((x) << S_TPFIFO)
8305 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
8306 
8307 #define A_MPS_TX_SE_CNT_TP01 0x9418
8308 #define A_MPS_TX_SE_CNT_TP23 0x941c
8309 #define A_MPS_TX_SE_CNT_MAC01 0x9420
8310 #define A_MPS_TX_SE_CNT_MAC23 0x9424
8311 #define A_MPS_STAT_CTL 0x9600
8312 
8313 #define S_COUNTPAUSESTATRX    4
8314 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
8315 #define F_COUNTPAUSESTATRX    V_COUNTPAUSESTATRX(1U)
8316 
8317 #define S_COUNTPAUSESTATTX    2
8318 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
8319 #define F_COUNTPAUSESTATTX    V_COUNTPAUSESTATTX(1U)
8320 
8321 #define S_STATSTOPCTRL    10
8322 #define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
8323 #define F_STATSTOPCTRL    V_STATSTOPCTRL(1U)
8324 
8325 #define S_STOPSTAT    9
8326 #define V_STOPSTAT(x) ((x) << S_STOPSTAT)
8327 #define F_STOPSTAT    V_STOPSTAT(1U)
8328 
8329 #define S_STATWRITECTRL    8
8330 #define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
8331 #define F_STATWRITECTRL    V_STATWRITECTRL(1U)
8332 
8333 #define S_COUNTLBPF    7
8334 #define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
8335 #define F_COUNTLBPF    V_COUNTLBPF(1U)
8336 
8337 #define S_COUNTLBVF    6
8338 #define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
8339 #define F_COUNTLBVF    V_COUNTLBVF(1U)
8340 
8341 #define S_COUNTPAUSEMCRX    5
8342 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
8343 #define F_COUNTPAUSEMCRX    V_COUNTPAUSEMCRX(1U)
8344 
8345 #define S_COUNTPAUSEMCTX    3
8346 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
8347 #define F_COUNTPAUSEMCTX    V_COUNTPAUSEMCTX(1U)
8348 
8349 #define A_MPS_STAT_INT_CAUSE 0x960c
8350 
8351 #define S_PLREADSYNCERR    0
8352 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
8353 #define F_PLREADSYNCERR    V_PLREADSYNCERR(1U)
8354 
8355 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
8356 
8357 #define S_RXBG    20
8358 #define V_RXBG(x) ((x) << S_RXBG)
8359 #define F_RXBG    V_RXBG(1U)
8360 
8361 #define S_RXVF    18
8362 #define M_RXVF    0x3U
8363 #define V_RXVF(x) ((x) << S_RXVF)
8364 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
8365 
8366 #define S_TXVF    16
8367 #define M_TXVF    0x3U
8368 #define V_TXVF(x) ((x) << S_TXVF)
8369 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
8370 
8371 #define S_RXPF    13
8372 #define M_RXPF    0x7U
8373 #define V_RXPF(x) ((x) << S_RXPF)
8374 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
8375 
8376 #define S_TXPF    11
8377 #define M_TXPF    0x3U
8378 #define V_TXPF(x) ((x) << S_TXPF)
8379 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
8380 
8381 #define S_RXPORT    7
8382 #define M_RXPORT    0xfU
8383 #define V_RXPORT(x) ((x) << S_RXPORT)
8384 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
8385 
8386 #define S_LBPORT    4
8387 #define M_LBPORT    0x7U
8388 #define V_LBPORT(x) ((x) << S_LBPORT)
8389 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
8390 
8391 #define S_TXPORT    0
8392 #define M_TXPORT    0xfU
8393 #define V_TXPORT(x) ((x) << S_TXPORT)
8394 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
8395 
8396 #define S_T5_RXBG    27
8397 #define M_T5_RXBG    0x3U
8398 #define V_T5_RXBG(x) ((x) << S_T5_RXBG)
8399 #define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
8400 
8401 #define S_T5_RXPF    22
8402 #define M_T5_RXPF    0x1fU
8403 #define V_T5_RXPF(x) ((x) << S_T5_RXPF)
8404 #define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
8405 
8406 #define S_T5_TXPF    18
8407 #define M_T5_TXPF    0xfU
8408 #define V_T5_TXPF(x) ((x) << S_T5_TXPF)
8409 #define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
8410 
8411 #define S_T5_RXPORT    11
8412 #define M_T5_RXPORT    0x7fU
8413 #define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
8414 #define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
8415 
8416 #define S_T5_LBPORT    6
8417 #define M_T5_LBPORT    0x1fU
8418 #define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
8419 #define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
8420 
8421 #define S_T5_TXPORT    0
8422 #define M_T5_TXPORT    0x3fU
8423 #define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
8424 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
8425 
8426 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
8427 
8428 #define S_TX    12
8429 #define M_TX    0xffU
8430 #define V_TX(x) ((x) << S_TX)
8431 #define G_TX(x) (((x) >> S_TX) & M_TX)
8432 
8433 #define S_TXPAUSEFIFO    8
8434 #define M_TXPAUSEFIFO    0xfU
8435 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
8436 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
8437 
8438 #define S_DROP    0
8439 #define M_DROP    0xffU
8440 #define V_DROP(x) ((x) << S_DROP)
8441 #define G_DROP(x) (((x) >> S_DROP) & M_DROP)
8442 
8443 #define S_TXCH    20
8444 #define M_TXCH    0xfU
8445 #define V_TXCH(x) ((x) << S_TXCH)
8446 #define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
8447 
8448 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
8449 
8450 #define S_PAUSEFIFO    20
8451 #define M_PAUSEFIFO    0xfU
8452 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
8453 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
8454 
8455 #define S_LPBK    16
8456 #define M_LPBK    0xfU
8457 #define V_LPBK(x) ((x) << S_LPBK)
8458 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
8459 
8460 #define S_NQ    8
8461 #define M_NQ    0xffU
8462 #define V_NQ(x) ((x) << S_NQ)
8463 #define G_NQ(x) (((x) >> S_NQ) & M_NQ)
8464 
8465 #define S_PV    4
8466 #define M_PV    0xfU
8467 #define V_PV(x) ((x) << S_PV)
8468 #define G_PV(x) (((x) >> S_PV) & M_PV)
8469 
8470 #define S_MAC    0
8471 #define M_MAC    0xfU
8472 #define V_MAC(x) ((x) << S_MAC)
8473 #define G_MAC(x) (((x) >> S_MAC) & M_MAC)
8474 
8475 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
8476 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
8477 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
8478 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
8479 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
8480 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
8481 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
8482 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
8483 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
8484 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
8485 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
8486 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
8487 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
8488 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
8489 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
8490 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
8491 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
8492 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
8493 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
8494 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
8495 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
8496 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
8497 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
8498 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
8499 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
8500 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
8501 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
8502 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
8503 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
8504 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
8505 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
8506 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
8507 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
8508 
8509 #define S_T5_RXVF    5
8510 #define M_T5_RXVF    0x7U
8511 #define V_T5_RXVF(x) ((x) << S_T5_RXVF)
8512 #define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
8513 
8514 #define S_T5_TXVF    0
8515 #define M_T5_TXVF    0x1fU
8516 #define V_T5_TXVF(x) ((x) << S_T5_TXVF)
8517 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
8518 
8519 #define A_MPS_TRC_CFG 0x9800
8520 
8521 #define S_TRCFIFOEMPTY    4
8522 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
8523 #define F_TRCFIFOEMPTY    V_TRCFIFOEMPTY(1U)
8524 
8525 #define S_TRCIGNOREDROPINPUT    3
8526 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
8527 #define F_TRCIGNOREDROPINPUT    V_TRCIGNOREDROPINPUT(1U)
8528 
8529 #define S_TRCKEEPDUPLICATES    2
8530 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
8531 #define F_TRCKEEPDUPLICATES    V_TRCKEEPDUPLICATES(1U)
8532 
8533 #define S_TRCEN    1
8534 #define V_TRCEN(x) ((x) << S_TRCEN)
8535 #define F_TRCEN    V_TRCEN(1U)
8536 
8537 #define S_TRCMULTIFILTER    0
8538 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
8539 #define F_TRCMULTIFILTER    V_TRCMULTIFILTER(1U)
8540 
8541 #define S_TRCMULTIRSSFILTER    5
8542 #define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
8543 #define F_TRCMULTIRSSFILTER    V_TRCMULTIRSSFILTER(1U)
8544 
8545 #define A_MPS_TRC_RSS_CONTROL 0x9808
8546 
8547 #define S_RSSCONTROL    16
8548 #define M_RSSCONTROL    0xffU
8549 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
8550 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
8551 
8552 #define S_QUEUENUMBER    0
8553 #define M_QUEUENUMBER    0xffffU
8554 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
8555 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
8556 
8557 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
8558 
8559 #define S_TFINVERTMATCH    24
8560 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
8561 #define F_TFINVERTMATCH    V_TFINVERTMATCH(1U)
8562 
8563 #define S_TFPKTTOOLARGE    23
8564 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
8565 #define F_TFPKTTOOLARGE    V_TFPKTTOOLARGE(1U)
8566 
8567 #define S_TFEN    22
8568 #define V_TFEN(x) ((x) << S_TFEN)
8569 #define F_TFEN    V_TFEN(1U)
8570 
8571 #define S_TFPORT    18
8572 #define M_TFPORT    0xfU
8573 #define V_TFPORT(x) ((x) << S_TFPORT)
8574 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
8575 
8576 #define S_TFDROP    17
8577 #define V_TFDROP(x) ((x) << S_TFDROP)
8578 #define F_TFDROP    V_TFDROP(1U)
8579 
8580 #define S_TFSOPEOPERR    16
8581 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
8582 #define F_TFSOPEOPERR    V_TFSOPEOPERR(1U)
8583 
8584 #define S_TFLENGTH    8
8585 #define M_TFLENGTH    0x1fU
8586 #define V_TFLENGTH(x) ((x) << S_TFLENGTH)
8587 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
8588 
8589 #define S_TFOFFSET    0
8590 #define M_TFOFFSET    0x1fU
8591 #define V_TFOFFSET(x) ((x) << S_TFOFFSET)
8592 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
8593 
8594 #define S_TFINSERTACTLEN    27
8595 #define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
8596 #define F_TFINSERTACTLEN    V_TFINSERTACTLEN(1U)
8597 
8598 #define S_TFINSERTTIMER    26
8599 #define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
8600 #define F_TFINSERTTIMER    V_TFINSERTTIMER(1U)
8601 
8602 #define S_T5_TFINVERTMATCH    25
8603 #define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
8604 #define F_T5_TFINVERTMATCH    V_T5_TFINVERTMATCH(1U)
8605 
8606 #define S_T5_TFPKTTOOLARGE    24
8607 #define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
8608 #define F_T5_TFPKTTOOLARGE    V_T5_TFPKTTOOLARGE(1U)
8609 
8610 #define S_T5_TFEN    23
8611 #define V_T5_TFEN(x) ((x) << S_T5_TFEN)
8612 #define F_T5_TFEN    V_T5_TFEN(1U)
8613 
8614 #define S_T5_TFPORT    18
8615 #define M_T5_TFPORT    0x1fU
8616 #define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
8617 #define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
8618 
8619 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
8620 
8621 #define S_TFMINPKTSIZE    16
8622 #define M_TFMINPKTSIZE    0x1ffU
8623 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
8624 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
8625 
8626 #define S_TFCAPTUREMAX    0
8627 #define M_TFCAPTUREMAX    0x3fffU
8628 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
8629 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
8630 
8631 #define A_MPS_TRC_INT_CAUSE 0x985c
8632 
8633 #define S_TRCPLERRENB    9
8634 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
8635 #define F_TRCPLERRENB    V_TRCPLERRENB(1U)
8636 
8637 #define S_MISCPERR    8
8638 #define V_MISCPERR(x) ((x) << S_MISCPERR)
8639 #define F_MISCPERR    V_MISCPERR(1U)
8640 
8641 #define S_PKTFIFO    4
8642 #define M_PKTFIFO    0xfU
8643 #define V_PKTFIFO(x) ((x) << S_PKTFIFO)
8644 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
8645 
8646 #define S_FILTMEM    0
8647 #define M_FILTMEM    0xfU
8648 #define V_FILTMEM(x) ((x) << S_FILTMEM)
8649 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
8650 
8651 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
8652 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
8653 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
8654 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
8655 #define A_MPS_CLS_PERR_ENABLE 0xd020
8656 
8657 #define S_HASHSRAM    2
8658 #define V_HASHSRAM(x) ((x) << S_HASHSRAM)
8659 #define F_HASHSRAM    V_HASHSRAM(1U)
8660 
8661 #define S_MATCHTCAM    1
8662 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
8663 #define F_MATCHTCAM    V_MATCHTCAM(1U)
8664 
8665 #define S_MATCHSRAM    0
8666 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
8667 #define F_MATCHSRAM    V_MATCHSRAM(1U)
8668 
8669 #define A_MPS_CLS_INT_ENABLE 0xd024
8670 
8671 #define S_PLERRENB    3
8672 #define V_PLERRENB(x) ((x) << S_PLERRENB)
8673 #define F_PLERRENB    V_PLERRENB(1U)
8674 
8675 #define A_MPS_CLS_INT_CAUSE 0xd028
8676 #define A_MPS_CLS_SRAM_L 0xe000
8677 
8678 #define S_MULTILISTEN3    28
8679 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
8680 #define F_MULTILISTEN3    V_MULTILISTEN3(1U)
8681 
8682 #define S_MULTILISTEN2    27
8683 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
8684 #define F_MULTILISTEN2    V_MULTILISTEN2(1U)
8685 
8686 #define S_MULTILISTEN1    26
8687 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
8688 #define F_MULTILISTEN1    V_MULTILISTEN1(1U)
8689 
8690 #define S_MULTILISTEN0    25
8691 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
8692 #define F_MULTILISTEN0    V_MULTILISTEN0(1U)
8693 
8694 #define S_SRAM_PRIO3    22
8695 #define M_SRAM_PRIO3    0x7U
8696 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
8697 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
8698 
8699 #define S_SRAM_PRIO2    19
8700 #define M_SRAM_PRIO2    0x7U
8701 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
8702 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
8703 
8704 #define S_SRAM_PRIO1    16
8705 #define M_SRAM_PRIO1    0x7U
8706 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
8707 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
8708 
8709 #define S_SRAM_PRIO0    13
8710 #define M_SRAM_PRIO0    0x7U
8711 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
8712 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
8713 
8714 #define S_SRAM_VLD    12
8715 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
8716 #define F_SRAM_VLD    V_SRAM_VLD(1U)
8717 
8718 #define A_MPS_T5_CLS_SRAM_L 0xe000
8719 
8720 #define S_T6_DISENCAPOUTERRPLCT    31
8721 #define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT)
8722 #define F_T6_DISENCAPOUTERRPLCT    V_T6_DISENCAPOUTERRPLCT(1U)
8723 
8724 #define S_T6_DISENCAP    30
8725 #define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP)
8726 #define F_T6_DISENCAP    V_T6_DISENCAP(1U)
8727 
8728 #define S_T6_MULTILISTEN3    29
8729 #define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3)
8730 #define F_T6_MULTILISTEN3    V_T6_MULTILISTEN3(1U)
8731 
8732 #define S_T6_MULTILISTEN2    28
8733 #define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2)
8734 #define F_T6_MULTILISTEN2    V_T6_MULTILISTEN2(1U)
8735 
8736 #define S_T6_MULTILISTEN1    27
8737 #define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1)
8738 #define F_T6_MULTILISTEN1    V_T6_MULTILISTEN1(1U)
8739 
8740 #define S_T6_MULTILISTEN0    26
8741 #define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0)
8742 #define F_T6_MULTILISTEN0    V_T6_MULTILISTEN0(1U)
8743 
8744 #define S_T6_SRAM_PRIO3    23
8745 #define M_T6_SRAM_PRIO3    0x7U
8746 #define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3)
8747 #define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3)
8748 
8749 #define S_T6_SRAM_PRIO2    20
8750 #define M_T6_SRAM_PRIO2    0x7U
8751 #define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2)
8752 #define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2)
8753 
8754 #define S_T6_SRAM_PRIO1    17
8755 #define M_T6_SRAM_PRIO1    0x7U
8756 #define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1)
8757 #define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1)
8758 
8759 #define S_T6_SRAM_PRIO0    14
8760 #define M_T6_SRAM_PRIO0    0x7U
8761 #define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0)
8762 #define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0)
8763 
8764 #define S_T6_SRAM_VLD    13
8765 #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
8766 #define F_T6_SRAM_VLD    V_T6_SRAM_VLD(1U)
8767 
8768 #define S_T6_REPLICATE    12
8769 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
8770 #define F_T6_REPLICATE    V_T6_REPLICATE(1U)
8771 
8772 #define S_T6_PF    9
8773 #define M_T6_PF    0x7U
8774 #define V_T6_PF(x) ((x) << S_T6_PF)
8775 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
8776 
8777 #define S_T6_VF_VALID    8
8778 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
8779 #define F_T6_VF_VALID    V_T6_VF_VALID(1U)
8780 
8781 #define S_T6_VF    0
8782 #define M_T6_VF    0xffU
8783 #define V_T6_VF(x) ((x) << S_T6_VF)
8784 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
8785 
8786 #define A_MPS_CLS_SRAM_H 0xe004
8787 
8788 #define S_MACPARITY1    9
8789 #define V_MACPARITY1(x) ((x) << S_MACPARITY1)
8790 #define F_MACPARITY1    V_MACPARITY1(1U)
8791 
8792 #define S_MACPARITY0    8
8793 #define V_MACPARITY0(x) ((x) << S_MACPARITY0)
8794 #define F_MACPARITY0    V_MACPARITY0(1U)
8795 
8796 #define S_MACPARITYMASKSIZE    4
8797 #define M_MACPARITYMASKSIZE    0xfU
8798 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
8799 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
8800 
8801 #define S_PORTMAP    0
8802 #define M_PORTMAP    0xfU
8803 #define V_PORTMAP(x) ((x) << S_PORTMAP)
8804 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
8805 
8806 #define A_MPS_T5_CLS_SRAM_H 0xe004
8807 
8808 #define S_MACPARITY2    10
8809 #define V_MACPARITY2(x) ((x) << S_MACPARITY2)
8810 #define F_MACPARITY2    V_MACPARITY2(1U)
8811 
8812 #define A_MPS_CLS_TCAM_Y_L 0xf000
8813 #define A_MPS_CLS_TCAM_DATA0 0xf000
8814 #define A_MPS_CLS_TCAM_DATA1 0xf004
8815 
8816 #define S_VIDL    16
8817 #define M_VIDL    0xffffU
8818 #define V_VIDL(x) ((x) << S_VIDL)
8819 #define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL)
8820 
8821 #define S_DMACH    0
8822 #define M_DMACH    0xffffU
8823 #define V_DMACH(x) ((x) << S_DMACH)
8824 #define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH)
8825 
8826 #define A_MPS_CLS_TCAM_X_L 0xf008
8827 #define A_MPS_CLS_TCAM_DATA2_CTL 0xf008
8828 
8829 #define S_CTLCMDTYPE    31
8830 #define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE)
8831 #define F_CTLCMDTYPE    V_CTLCMDTYPE(1U)
8832 
8833 #define S_CTLREQID    30
8834 #define V_CTLREQID(x) ((x) << S_CTLREQID)
8835 #define F_CTLREQID    V_CTLREQID(1U)
8836 
8837 #define S_CTLTCAMSEL    25
8838 #define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL)
8839 #define F_CTLTCAMSEL    V_CTLTCAMSEL(1U)
8840 
8841 #define S_CTLTCAMINDEX    17
8842 #define M_CTLTCAMINDEX    0xffU
8843 #define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX)
8844 #define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX)
8845 
8846 #define S_CTLXYBITSEL    16
8847 #define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL)
8848 #define F_CTLXYBITSEL    V_CTLXYBITSEL(1U)
8849 
8850 #define S_DATAPORTNUM    12
8851 #define M_DATAPORTNUM    0xfU
8852 #define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM)
8853 #define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM)
8854 
8855 #define S_DATALKPTYPE    10
8856 #define M_DATALKPTYPE    0x3U
8857 #define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE)
8858 #define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE)
8859 
8860 #define S_DATADIPHIT    8
8861 #define V_DATADIPHIT(x) ((x) << S_DATADIPHIT)
8862 #define F_DATADIPHIT    V_DATADIPHIT(1U)
8863 
8864 #define S_DATAVIDH2    7
8865 #define V_DATAVIDH2(x) ((x) << S_DATAVIDH2)
8866 #define F_DATAVIDH2    V_DATAVIDH2(1U)
8867 
8868 #define S_DATAVIDH1    0
8869 #define M_DATAVIDH1    0x7fU
8870 #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
8871 #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)
8872 
8873 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
8874 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
8875 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
8876 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
8877 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
8878 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
8879 #define A_MPS_RX_PG_RSV0 0x11010
8880 
8881 #define S_CLR_INTR    31
8882 #define V_CLR_INTR(x) ((x) << S_CLR_INTR)
8883 #define F_CLR_INTR    V_CLR_INTR(1U)
8884 
8885 #define S_SET_INTR    30
8886 #define V_SET_INTR(x) ((x) << S_SET_INTR)
8887 #define F_SET_INTR    V_SET_INTR(1U)
8888 
8889 #define S_USED    16
8890 #define M_USED    0x7ffU
8891 #define V_USED(x) ((x) << S_USED)
8892 #define G_USED(x) (((x) >> S_USED) & M_USED)
8893 
8894 #define S_ALLOC    0
8895 #define M_ALLOC    0x7ffU
8896 #define V_ALLOC(x) ((x) << S_ALLOC)
8897 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
8898 
8899 #define S_T5_USED    16
8900 #define M_T5_USED    0xfffU
8901 #define V_T5_USED(x) ((x) << S_T5_USED)
8902 #define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
8903 
8904 #define S_T5_ALLOC    0
8905 #define M_T5_ALLOC    0xfffU
8906 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
8907 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
8908 
8909 #define A_MPS_RX_PG_RSV1 0x11014
8910 #define A_MPS_RX_PG_RSV2 0x11018
8911 #define A_MPS_RX_PG_RSV3 0x1101c
8912 #define A_MPS_RX_PG_RSV4 0x11020
8913 #define A_MPS_RX_PG_RSV5 0x11024
8914 #define A_MPS_RX_PG_RSV6 0x11028
8915 #define A_MPS_RX_PG_RSV7 0x1102c
8916 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
8917 
8918 #define S_FF    23
8919 #define V_FF(x) ((x) << S_FF)
8920 #define F_FF    V_FF(1U)
8921 
8922 #define S_PGMO    22
8923 #define V_PGMO(x) ((x) << S_PGMO)
8924 #define F_PGMO    V_PGMO(1U)
8925 
8926 #define S_PGME    21
8927 #define V_PGME(x) ((x) << S_PGME)
8928 #define F_PGME    V_PGME(1U)
8929 
8930 #define S_CHMN    20
8931 #define V_CHMN(x) ((x) << S_CHMN)
8932 #define F_CHMN    V_CHMN(1U)
8933 
8934 #define S_RPLC    19
8935 #define V_RPLC(x) ((x) << S_RPLC)
8936 #define F_RPLC    V_RPLC(1U)
8937 
8938 #define S_ATRB    18
8939 #define V_ATRB(x) ((x) << S_ATRB)
8940 #define F_ATRB    V_ATRB(1U)
8941 
8942 #define S_PSMX    17
8943 #define V_PSMX(x) ((x) << S_PSMX)
8944 #define F_PSMX    V_PSMX(1U)
8945 
8946 #define S_PGLL    16
8947 #define V_PGLL(x) ((x) << S_PGLL)
8948 #define F_PGLL    V_PGLL(1U)
8949 
8950 #define S_PGFL    15
8951 #define V_PGFL(x) ((x) << S_PGFL)
8952 #define F_PGFL    V_PGFL(1U)
8953 
8954 #define S_PKTQ    14
8955 #define V_PKTQ(x) ((x) << S_PKTQ)
8956 #define F_PKTQ    V_PKTQ(1U)
8957 
8958 #define S_PKFL    13
8959 #define V_PKFL(x) ((x) << S_PKFL)
8960 #define F_PKFL    V_PKFL(1U)
8961 
8962 #define S_PPM3    12
8963 #define V_PPM3(x) ((x) << S_PPM3)
8964 #define F_PPM3    V_PPM3(1U)
8965 
8966 #define S_PPM2    11
8967 #define V_PPM2(x) ((x) << S_PPM2)
8968 #define F_PPM2    V_PPM2(1U)
8969 
8970 #define S_PPM1    10
8971 #define V_PPM1(x) ((x) << S_PPM1)
8972 #define F_PPM1    V_PPM1(1U)
8973 
8974 #define S_PPM0    9
8975 #define V_PPM0(x) ((x) << S_PPM0)
8976 #define F_PPM0    V_PPM0(1U)
8977 
8978 #define S_SPMX    8
8979 #define V_SPMX(x) ((x) << S_SPMX)
8980 #define F_SPMX    V_SPMX(1U)
8981 
8982 #define S_CDL3    7
8983 #define V_CDL3(x) ((x) << S_CDL3)
8984 #define F_CDL3    V_CDL3(1U)
8985 
8986 #define S_CDL2    6
8987 #define V_CDL2(x) ((x) << S_CDL2)
8988 #define F_CDL2    V_CDL2(1U)
8989 
8990 #define S_CDL1    5
8991 #define V_CDL1(x) ((x) << S_CDL1)
8992 #define F_CDL1    V_CDL1(1U)
8993 
8994 #define S_CDL0    4
8995 #define V_CDL0(x) ((x) << S_CDL0)
8996 #define F_CDL0    V_CDL0(1U)
8997 
8998 #define S_CDM3    3
8999 #define V_CDM3(x) ((x) << S_CDM3)
9000 #define F_CDM3    V_CDM3(1U)
9001 
9002 #define S_CDM2    2
9003 #define V_CDM2(x) ((x) << S_CDM2)
9004 #define F_CDM2    V_CDM2(1U)
9005 
9006 #define S_CDM1    1
9007 #define V_CDM1(x) ((x) << S_CDM1)
9008 #define F_CDM1    V_CDM1(1U)
9009 
9010 #define S_CDM0    0
9011 #define V_CDM0(x) ((x) << S_CDM0)
9012 #define F_CDM0    V_CDM0(1U)
9013 
9014 #define A_MPS_RX_SE_CNT_IN0 0x11148
9015 
9016 #define S_SOP_CNT_PM    24
9017 #define M_SOP_CNT_PM    0xffU
9018 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
9019 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
9020 
9021 #define S_EOP_CNT_PM    16
9022 #define M_EOP_CNT_PM    0xffU
9023 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
9024 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
9025 
9026 #define S_SOP_CNT_IN    8
9027 #define M_SOP_CNT_IN    0xffU
9028 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
9029 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
9030 
9031 #define S_EOP_CNT_IN    0
9032 #define M_EOP_CNT_IN    0xffU
9033 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
9034 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
9035 
9036 #define A_MPS_RX_SE_CNT_IN1 0x1114c
9037 #define A_MPS_RX_SE_CNT_IN2 0x11150
9038 #define A_MPS_RX_SE_CNT_IN3 0x11154
9039 #define A_MPS_RX_SE_CNT_IN4 0x11158
9040 #define A_MPS_RX_SE_CNT_IN5 0x1115c
9041 #define A_MPS_RX_SE_CNT_IN6 0x11160
9042 #define A_MPS_RX_SE_CNT_IN7 0x11164
9043 #define A_MPS_RX_SE_CNT_OUT01 0x11168
9044 
9045 #define S_SOP_CNT_1    24
9046 #define M_SOP_CNT_1    0xffU
9047 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
9048 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
9049 
9050 #define S_EOP_CNT_1    16
9051 #define M_EOP_CNT_1    0xffU
9052 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
9053 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
9054 
9055 #define S_SOP_CNT_0    8
9056 #define M_SOP_CNT_0    0xffU
9057 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
9058 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
9059 
9060 #define S_EOP_CNT_0    0
9061 #define M_EOP_CNT_0    0xffU
9062 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
9063 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
9064 
9065 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
9066 
9067 #define S_SOP_CNT_3    24
9068 #define M_SOP_CNT_3    0xffU
9069 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
9070 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
9071 
9072 #define S_EOP_CNT_3    16
9073 #define M_EOP_CNT_3    0xffU
9074 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
9075 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
9076 
9077 #define S_SOP_CNT_2    8
9078 #define M_SOP_CNT_2    0xffU
9079 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
9080 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
9081 
9082 #define S_EOP_CNT_2    0
9083 #define M_EOP_CNT_2    0xffU
9084 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
9085 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
9086 
9087 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
9088 
9089 #define S_LPBK_CNT0    16
9090 #define M_LPBK_CNT0    0xffffU
9091 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
9092 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
9093 
9094 #define S_MAC_CNT0    0
9095 #define M_MAC_CNT0    0xffffU
9096 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
9097 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
9098 
9099 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
9100 
9101 #define S_LPBK_CNT1    16
9102 #define M_LPBK_CNT1    0xffffU
9103 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
9104 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
9105 
9106 #define S_MAC_CNT1    0
9107 #define M_MAC_CNT1    0xffffU
9108 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
9109 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
9110 
9111 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
9112 
9113 #define S_LPBK_CNT2    16
9114 #define M_LPBK_CNT2    0xffffU
9115 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
9116 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
9117 
9118 #define S_MAC_CNT2    0
9119 #define M_MAC_CNT2    0xffffU
9120 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
9121 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
9122 
9123 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
9124 
9125 #define S_LPBK_CNT3    16
9126 #define M_LPBK_CNT3    0xffffU
9127 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
9128 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
9129 
9130 #define S_MAC_CNT3    0
9131 #define M_MAC_CNT3    0xffffU
9132 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
9133 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
9134 
9135 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
9136 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
9137 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
9138 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
9139 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
9140 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
9141 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
9142 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
9143 #define A_MPS_RX_MAC_BG_PG_CNT0 0x11208
9144 
9145 #define S_MAC_USED    16
9146 #define M_MAC_USED    0x7ffU
9147 #define V_MAC_USED(x) ((x) << S_MAC_USED)
9148 #define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED)
9149 
9150 #define S_MAC_ALLOC    0
9151 #define M_MAC_ALLOC    0x7ffU
9152 #define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC)
9153 #define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC)
9154 
9155 #define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
9156 #define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
9157 #define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
9158 #define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218
9159 
9160 #define S_LPBK_USED    16
9161 #define M_LPBK_USED    0x7ffU
9162 #define V_LPBK_USED(x) ((x) << S_LPBK_USED)
9163 #define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED)
9164 
9165 #define S_LPBK_ALLOC    0
9166 #define M_LPBK_ALLOC    0x7ffU
9167 #define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC)
9168 #define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC)
9169 
9170 #define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
9171 #define A_MPS_RX_GRE_PROT_TYPE 0x11230
9172 
9173 #define S_NVGRE_EN    9
9174 #define V_NVGRE_EN(x) ((x) << S_NVGRE_EN)
9175 #define F_NVGRE_EN    V_NVGRE_EN(1U)
9176 
9177 #define S_GRE_EN    8
9178 #define V_GRE_EN(x) ((x) << S_GRE_EN)
9179 #define F_GRE_EN    V_GRE_EN(1U)
9180 
9181 #define S_GRE    0
9182 #define M_GRE    0xffU
9183 #define V_GRE(x) ((x) << S_GRE)
9184 #define G_GRE(x) (((x) >> S_GRE) & M_GRE)
9185 
9186 #define A_MPS_RX_VXLAN_TYPE 0x11234
9187 
9188 #define S_VXLAN_EN    16
9189 #define V_VXLAN_EN(x) ((x) << S_VXLAN_EN)
9190 #define F_VXLAN_EN    V_VXLAN_EN(1U)
9191 
9192 #define S_VXLAN    0
9193 #define M_VXLAN    0xffffU
9194 #define V_VXLAN(x) ((x) << S_VXLAN)
9195 #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)
9196 
9197 #define A_MPS_RX_GENEVE_TYPE 0x11238
9198 
9199 #define S_GENEVE_EN    16
9200 #define V_GENEVE_EN(x) ((x) << S_GENEVE_EN)
9201 #define F_GENEVE_EN    V_GENEVE_EN(1U)
9202 
9203 #define S_GENEVE    0
9204 #define M_GENEVE    0xffffU
9205 #define V_GENEVE(x) ((x) << S_GENEVE)
9206 #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)
9207 
9208 #define A_MPS_RX_ENCAP_NVGRE 0x11240
9209 
9210 #define S_ETYPE_EN    16
9211 #define V_ETYPE_EN(x) ((x) << S_ETYPE_EN)
9212 #define F_ETYPE_EN    V_ETYPE_EN(1U)
9213 
9214 #define S_ETYPE    0
9215 #define M_ETYPE    0xffffU
9216 #define V_ETYPE(x) ((x) << S_ETYPE)
9217 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
9218 
9219 #define A_MPS_RX_ENCAP_GENEVE 0x11244
9220 
9221 /* registers for module CPL_SWITCH */
9222 #define CPL_SWITCH_BASE_ADDR 0x19040
9223 
9224 #define A_CPL_INTR_ENABLE 0x19050
9225 
9226 #define S_CIM_OP_MAP_PERR    5
9227 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
9228 #define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
9229 
9230 #define S_CIM_OVFL_ERROR    4
9231 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
9232 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
9233 
9234 #define S_TP_FRAMING_ERROR    3
9235 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
9236 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
9237 
9238 #define S_SGE_FRAMING_ERROR    2
9239 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
9240 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
9241 
9242 #define S_CIM_FRAMING_ERROR    1
9243 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
9244 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
9245 
9246 #define S_ZERO_SWITCH_ERROR    0
9247 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
9248 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
9249 
9250 #define S_PERR_CPL_128TO128_1    7
9251 #define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
9252 #define F_PERR_CPL_128TO128_1    V_PERR_CPL_128TO128_1(1U)
9253 
9254 #define S_PERR_CPL_128TO128_0    6
9255 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
9256 #define F_PERR_CPL_128TO128_0    V_PERR_CPL_128TO128_0(1U)
9257 
9258 #define A_CPL_INTR_CAUSE 0x19054
9259 
9260 /* registers for module SMB */
9261 #define SMB_BASE_ADDR 0x19060
9262 
9263 #define A_SMB_INT_ENABLE 0x1908c
9264 
9265 #define S_MSTTXFIFOPAREN    21
9266 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
9267 #define F_MSTTXFIFOPAREN    V_MSTTXFIFOPAREN(1U)
9268 
9269 #define S_MSTRXFIFOPAREN    20
9270 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
9271 #define F_MSTRXFIFOPAREN    V_MSTRXFIFOPAREN(1U)
9272 
9273 #define S_SLVFIFOPAREN    19
9274 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
9275 #define F_SLVFIFOPAREN    V_SLVFIFOPAREN(1U)
9276 
9277 #define A_SMB_INT_CAUSE 0x19090
9278 
9279 #define S_MSTTXFIFOPARINT    21
9280 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
9281 #define F_MSTTXFIFOPARINT    V_MSTTXFIFOPARINT(1U)
9282 
9283 #define S_MSTRXFIFOPARINT    20
9284 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
9285 #define F_MSTRXFIFOPARINT    V_MSTRXFIFOPARINT(1U)
9286 
9287 #define S_SLVFIFOPARINT    19
9288 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
9289 #define F_SLVFIFOPARINT    V_SLVFIFOPARINT(1U)
9290 
9291 
9292 /* registers for module I2CM */
9293 #define I2CM_BASE_ADDR 0x190f0
9294 
9295 #define A_I2CM_CFG 0x190f0
9296 
9297 #define S_I2C_CLKDIV16B    0
9298 #define M_I2C_CLKDIV16B    0xffffU
9299 #define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
9300 #define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
9301 
9302 
9303 /* registers for module MI */
9304 #define MI_BASE_ADDR 0x19100
9305 
9306 
9307 /* registers for module UART */
9308 #define UART_BASE_ADDR 0x19110
9309 
9310 
9311 /* registers for module PMU */
9312 #define PMU_BASE_ADDR 0x19120
9313 
9314 
9315 /* registers for module ULP_RX */
9316 #define ULP_RX_BASE_ADDR 0x19150
9317 
9318 #define A_ULP_RX_CTL 0x19150
9319 
9320 #define S_PCMD1THRESHOLD    24
9321 #define M_PCMD1THRESHOLD    0xffU
9322 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
9323 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
9324 
9325 #define S_PCMD0THRESHOLD    16
9326 #define M_PCMD0THRESHOLD    0xffU
9327 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
9328 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
9329 
9330 #define S_DISABLE_0B_STAG_ERR    14
9331 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
9332 #define F_DISABLE_0B_STAG_ERR    V_DISABLE_0B_STAG_ERR(1U)
9333 
9334 #define S_RDMA_0B_WR_OPCODE    10
9335 #define M_RDMA_0B_WR_OPCODE    0xfU
9336 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
9337 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
9338 
9339 #define S_RDMA_0B_WR_PASS    9
9340 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
9341 #define F_RDMA_0B_WR_PASS    V_RDMA_0B_WR_PASS(1U)
9342 
9343 #define S_STAG_RQE    8
9344 #define V_STAG_RQE(x) ((x) << S_STAG_RQE)
9345 #define F_STAG_RQE    V_STAG_RQE(1U)
9346 
9347 #define S_RDMA_STATE_EN    7
9348 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
9349 #define F_RDMA_STATE_EN    V_RDMA_STATE_EN(1U)
9350 
9351 #define S_CRC1_EN    6
9352 #define V_CRC1_EN(x) ((x) << S_CRC1_EN)
9353 #define F_CRC1_EN    V_CRC1_EN(1U)
9354 
9355 #define S_RDMA_0B_WR_CQE    5
9356 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
9357 #define F_RDMA_0B_WR_CQE    V_RDMA_0B_WR_CQE(1U)
9358 
9359 #define S_PCIE_ATRB_EN    4
9360 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
9361 #define F_PCIE_ATRB_EN    V_PCIE_ATRB_EN(1U)
9362 
9363 #define S_RDMA_PERMISSIVE_MODE    3
9364 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
9365 #define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
9366 
9367 #define S_PAGEPODME    2
9368 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
9369 #define F_PAGEPODME    V_PAGEPODME(1U)
9370 
9371 #define S_ISCSITAGTCB    1
9372 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
9373 #define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
9374 
9375 #define S_TDDPTAGTCB    0
9376 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
9377 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
9378 
9379 #define A_ULP_RX_INT_CAUSE 0x19158
9380 
9381 #define S_CAUSE_CTX_1    24
9382 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
9383 #define F_CAUSE_CTX_1    V_CAUSE_CTX_1(1U)
9384 
9385 #define S_CAUSE_CTX_0    23
9386 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
9387 #define F_CAUSE_CTX_0    V_CAUSE_CTX_0(1U)
9388 
9389 #define S_CAUSE_FF    22
9390 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
9391 #define F_CAUSE_FF    V_CAUSE_FF(1U)
9392 
9393 #define S_CAUSE_APF_1    21
9394 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
9395 #define F_CAUSE_APF_1    V_CAUSE_APF_1(1U)
9396 
9397 #define S_CAUSE_APF_0    20
9398 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
9399 #define F_CAUSE_APF_0    V_CAUSE_APF_0(1U)
9400 
9401 #define S_CAUSE_AF_1    19
9402 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
9403 #define F_CAUSE_AF_1    V_CAUSE_AF_1(1U)
9404 
9405 #define S_CAUSE_AF_0    18
9406 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
9407 #define F_CAUSE_AF_0    V_CAUSE_AF_0(1U)
9408 
9409 #define S_CAUSE_DDPDF_1    17
9410 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
9411 #define F_CAUSE_DDPDF_1    V_CAUSE_DDPDF_1(1U)
9412 
9413 #define S_CAUSE_DDPMF_1    16
9414 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
9415 #define F_CAUSE_DDPMF_1    V_CAUSE_DDPMF_1(1U)
9416 
9417 #define S_CAUSE_MEMRF_1    15
9418 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
9419 #define F_CAUSE_MEMRF_1    V_CAUSE_MEMRF_1(1U)
9420 
9421 #define S_CAUSE_PRSDF_1    14
9422 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
9423 #define F_CAUSE_PRSDF_1    V_CAUSE_PRSDF_1(1U)
9424 
9425 #define S_CAUSE_DDPDF_0    13
9426 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
9427 #define F_CAUSE_DDPDF_0    V_CAUSE_DDPDF_0(1U)
9428 
9429 #define S_CAUSE_DDPMF_0    12
9430 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
9431 #define F_CAUSE_DDPMF_0    V_CAUSE_DDPMF_0(1U)
9432 
9433 #define S_CAUSE_MEMRF_0    11
9434 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
9435 #define F_CAUSE_MEMRF_0    V_CAUSE_MEMRF_0(1U)
9436 
9437 #define S_CAUSE_PRSDF_0    10
9438 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
9439 #define F_CAUSE_PRSDF_0    V_CAUSE_PRSDF_0(1U)
9440 
9441 #define S_CAUSE_PCMDF_1    9
9442 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
9443 #define F_CAUSE_PCMDF_1    V_CAUSE_PCMDF_1(1U)
9444 
9445 #define S_CAUSE_TPTCF_1    8
9446 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
9447 #define F_CAUSE_TPTCF_1    V_CAUSE_TPTCF_1(1U)
9448 
9449 #define S_CAUSE_DDPCF_1    7
9450 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
9451 #define F_CAUSE_DDPCF_1    V_CAUSE_DDPCF_1(1U)
9452 
9453 #define S_CAUSE_MPARF_1    6
9454 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
9455 #define F_CAUSE_MPARF_1    V_CAUSE_MPARF_1(1U)
9456 
9457 #define S_CAUSE_MPARC_1    5
9458 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
9459 #define F_CAUSE_MPARC_1    V_CAUSE_MPARC_1(1U)
9460 
9461 #define S_CAUSE_PCMDF_0    4
9462 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
9463 #define F_CAUSE_PCMDF_0    V_CAUSE_PCMDF_0(1U)
9464 
9465 #define S_CAUSE_TPTCF_0    3
9466 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
9467 #define F_CAUSE_TPTCF_0    V_CAUSE_TPTCF_0(1U)
9468 
9469 #define S_CAUSE_DDPCF_0    2
9470 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
9471 #define F_CAUSE_DDPCF_0    V_CAUSE_DDPCF_0(1U)
9472 
9473 #define S_CAUSE_MPARF_0    1
9474 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
9475 #define F_CAUSE_MPARF_0    V_CAUSE_MPARF_0(1U)
9476 
9477 #define S_CAUSE_MPARC_0    0
9478 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
9479 #define F_CAUSE_MPARC_0    V_CAUSE_MPARC_0(1U)
9480 
9481 #define S_SE_CNT_MISMATCH_1    26
9482 #define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
9483 #define F_SE_CNT_MISMATCH_1    V_SE_CNT_MISMATCH_1(1U)
9484 
9485 #define S_SE_CNT_MISMATCH_0    25
9486 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
9487 #define F_SE_CNT_MISMATCH_0    V_SE_CNT_MISMATCH_0(1U)
9488 
9489 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
9490 
9491 #define S_ISCSILLIMIT    6
9492 #define M_ISCSILLIMIT    0x3ffffffU
9493 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
9494 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
9495 
9496 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
9497 
9498 #define S_ISCSIULIMIT    6
9499 #define M_ISCSIULIMIT    0x3ffffffU
9500 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
9501 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
9502 
9503 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
9504 
9505 #define S_ISCSITAGMASK    6
9506 #define M_ISCSITAGMASK    0x3ffffffU
9507 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
9508 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
9509 
9510 #define A_ULP_RX_ISCSI_PSZ 0x19168
9511 
9512 #define S_HPZ3    24
9513 #define M_HPZ3    0xfU
9514 #define V_HPZ3(x) ((x) << S_HPZ3)
9515 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
9516 
9517 #define S_HPZ2    16
9518 #define M_HPZ2    0xfU
9519 #define V_HPZ2(x) ((x) << S_HPZ2)
9520 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
9521 
9522 #define S_HPZ1    8
9523 #define M_HPZ1    0xfU
9524 #define V_HPZ1(x) ((x) << S_HPZ1)
9525 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
9526 
9527 #define S_HPZ0    0
9528 #define M_HPZ0    0xfU
9529 #define V_HPZ0(x) ((x) << S_HPZ0)
9530 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
9531 
9532 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
9533 
9534 #define S_TDDPLLIMIT    6
9535 #define M_TDDPLLIMIT    0x3ffffffU
9536 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
9537 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
9538 
9539 #define A_ULP_RX_TDDP_ULIMIT 0x19170
9540 
9541 #define S_TDDPULIMIT    6
9542 #define M_TDDPULIMIT    0x3ffffffU
9543 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
9544 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
9545 
9546 #define A_ULP_RX_TDDP_TAGMASK 0x19174
9547 
9548 #define S_TDDPTAGMASK    6
9549 #define M_TDDPTAGMASK    0x3ffffffU
9550 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
9551 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
9552 
9553 #define A_ULP_RX_TDDP_PSZ 0x19178
9554 #define A_ULP_RX_STAG_LLIMIT 0x1917c
9555 #define A_ULP_RX_STAG_ULIMIT 0x19180
9556 #define A_ULP_RX_RQ_LLIMIT 0x19184
9557 #define A_ULP_RX_RQ_ULIMIT 0x19188
9558 #define A_ULP_RX_PBL_LLIMIT 0x1918c
9559 #define A_ULP_RX_PBL_ULIMIT 0x19190
9560 #define A_ULP_RX_CTX_BASE 0x19194
9561 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
9562 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
9563 #define A_ULP_RX_SE_CNT_CH0 0x191d8
9564 
9565 #define S_SOP_CNT_OUT0    28
9566 #define M_SOP_CNT_OUT0    0xfU
9567 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
9568 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
9569 
9570 #define S_EOP_CNT_OUT0    24
9571 #define M_EOP_CNT_OUT0    0xfU
9572 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
9573 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
9574 
9575 #define S_SOP_CNT_AL0    20
9576 #define M_SOP_CNT_AL0    0xfU
9577 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
9578 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
9579 
9580 #define S_EOP_CNT_AL0    16
9581 #define M_EOP_CNT_AL0    0xfU
9582 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
9583 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
9584 
9585 #define S_SOP_CNT_MR0    12
9586 #define M_SOP_CNT_MR0    0xfU
9587 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
9588 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
9589 
9590 #define S_EOP_CNT_MR0    8
9591 #define M_EOP_CNT_MR0    0xfU
9592 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
9593 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
9594 
9595 #define S_SOP_CNT_IN0    4
9596 #define M_SOP_CNT_IN0    0xfU
9597 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
9598 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
9599 
9600 #define S_EOP_CNT_IN0    0
9601 #define M_EOP_CNT_IN0    0xfU
9602 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
9603 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
9604 
9605 #define A_ULP_RX_SE_CNT_CH1 0x191dc
9606 
9607 #define S_SOP_CNT_OUT1    28
9608 #define M_SOP_CNT_OUT1    0xfU
9609 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
9610 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
9611 
9612 #define S_EOP_CNT_OUT1    24
9613 #define M_EOP_CNT_OUT1    0xfU
9614 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
9615 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
9616 
9617 #define S_SOP_CNT_AL1    20
9618 #define M_SOP_CNT_AL1    0xfU
9619 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
9620 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
9621 
9622 #define S_EOP_CNT_AL1    16
9623 #define M_EOP_CNT_AL1    0xfU
9624 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
9625 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
9626 
9627 #define S_SOP_CNT_MR1    12
9628 #define M_SOP_CNT_MR1    0xfU
9629 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
9630 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
9631 
9632 #define S_EOP_CNT_MR1    8
9633 #define M_EOP_CNT_MR1    0xfU
9634 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
9635 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
9636 
9637 #define S_SOP_CNT_IN1    4
9638 #define M_SOP_CNT_IN1    0xfU
9639 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
9640 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
9641 
9642 #define S_EOP_CNT_IN1    0
9643 #define M_EOP_CNT_IN1    0xfU
9644 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
9645 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
9646 
9647 #define A_ULP_RX_LA_CTL 0x1923c
9648 
9649 #define S_TRC_SEL    0
9650 #define V_TRC_SEL(x) ((x) << S_TRC_SEL)
9651 #define F_TRC_SEL    V_TRC_SEL(1U)
9652 
9653 #define A_ULP_RX_LA_RDPTR 0x19240
9654 
9655 #define S_RD_PTR    0
9656 #define M_RD_PTR    0x1ffU
9657 #define V_RD_PTR(x) ((x) << S_RD_PTR)
9658 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
9659 
9660 #define A_ULP_RX_LA_RDDATA 0x19244
9661 #define A_ULP_RX_LA_WRPTR 0x19248
9662 
9663 #define S_WR_PTR    0
9664 #define M_WR_PTR    0x1ffU
9665 #define V_WR_PTR(x) ((x) << S_WR_PTR)
9666 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
9667 
9668 #define A_ULP_RX_LA_RESERVED 0x1924c
9669 #define A_ULP_RX_INT_CAUSE_2 0x19270
9670 
9671 #define S_ULPRX2MA_INTFPERR    8
9672 #define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
9673 #define F_ULPRX2MA_INTFPERR    V_ULPRX2MA_INTFPERR(1U)
9674 
9675 #define S_ALN_SDC_ERR_1    7
9676 #define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
9677 #define F_ALN_SDC_ERR_1    V_ALN_SDC_ERR_1(1U)
9678 
9679 #define S_ALN_SDC_ERR_0    6
9680 #define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
9681 #define F_ALN_SDC_ERR_0    V_ALN_SDC_ERR_0(1U)
9682 
9683 #define S_PF_UNTAGGED_TPT_1    5
9684 #define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
9685 #define F_PF_UNTAGGED_TPT_1    V_PF_UNTAGGED_TPT_1(1U)
9686 
9687 #define S_PF_UNTAGGED_TPT_0    4
9688 #define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
9689 #define F_PF_UNTAGGED_TPT_0    V_PF_UNTAGGED_TPT_0(1U)
9690 
9691 #define S_PF_PBL_1    3
9692 #define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
9693 #define F_PF_PBL_1    V_PF_PBL_1(1U)
9694 
9695 #define S_PF_PBL_0    2
9696 #define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
9697 #define F_PF_PBL_0    V_PF_PBL_0(1U)
9698 
9699 #define S_DDP_HINT_1    1
9700 #define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
9701 #define F_DDP_HINT_1    V_DDP_HINT_1(1U)
9702 
9703 #define S_DDP_HINT_0    0
9704 #define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
9705 #define F_DDP_HINT_0    V_DDP_HINT_0(1U)
9706 
9707 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
9708 
9709 #define S_TLSPPLLIMIT    6
9710 #define M_TLSPPLLIMIT    0x3ffffffU
9711 #define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT)
9712 #define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT)
9713 
9714 #define A_ULP_RX_TLS_PP_ULIMIT 0x192a8
9715 
9716 #define S_TLSPPULIMIT    6
9717 #define M_TLSPPULIMIT    0x3ffffffU
9718 #define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT)
9719 #define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT)
9720 
9721 #define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac
9722 
9723 #define S_TLSKEYLLIMIT    8
9724 #define M_TLSKEYLLIMIT    0xffffffU
9725 #define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT)
9726 #define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT)
9727 
9728 #define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0
9729 
9730 #define S_TLSKEYULIMIT    8
9731 #define M_TLSKEYULIMIT    0xffffffU
9732 #define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT)
9733 #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)
9734 
9735 
9736 /* registers for module SF */
9737 #define SF_BASE_ADDR 0x193f8
9738 
9739 #define A_SF_DATA 0x193f8
9740 #define A_SF_OP 0x193fc
9741 
9742 #define S_SF_LOCK    4
9743 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
9744 #define F_SF_LOCK    V_SF_LOCK(1U)
9745 
9746 #define S_CONT    3
9747 #define V_CONT(x) ((x) << S_CONT)
9748 #define F_CONT    V_CONT(1U)
9749 
9750 #define S_BYTECNT    1
9751 #define M_BYTECNT    0x3U
9752 #define V_BYTECNT(x) ((x) << S_BYTECNT)
9753 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
9754 
9755 #define S_OP    0
9756 #define V_OP(x) ((x) << S_OP)
9757 #define F_OP    V_OP(1U)
9758 
9759 /* registers for module PL */
9760 #define PL_BASE_ADDR 0x19400
9761 
9762 #define A_PL_VF_WHOAMI 0x0
9763 
9764 #define S_PORTXMAP    24
9765 #define M_PORTXMAP    0x7U
9766 #define V_PORTXMAP(x) ((x) << S_PORTXMAP)
9767 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
9768 
9769 #define S_SOURCEBUS    16
9770 #define M_SOURCEBUS    0x3U
9771 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
9772 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
9773 
9774 #define S_SOURCEPF    8
9775 #define M_SOURCEPF    0x7U
9776 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
9777 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
9778 
9779 #define S_ISVF    7
9780 #define V_ISVF(x) ((x) << S_ISVF)
9781 #define F_ISVF    V_ISVF(1U)
9782 
9783 #define S_VFID    0
9784 #define M_VFID    0x7fU
9785 #define V_VFID(x) ((x) << S_VFID)
9786 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
9787 
9788 #define S_T6_SOURCEPF    9
9789 #define M_T6_SOURCEPF    0x7U
9790 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
9791 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
9792 
9793 #define S_T6_ISVF    8
9794 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
9795 #define F_T6_ISVF    V_T6_ISVF(1U)
9796 
9797 #define S_T6_VFID    0
9798 #define M_T6_VFID    0xffU
9799 #define V_T6_VFID(x) ((x) << S_T6_VFID)
9800 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
9801 
9802 #define A_PL_VF_REV 0x4
9803 
9804 #define S_CHIPID    4
9805 #define M_CHIPID    0xfU
9806 #define V_CHIPID(x) ((x) << S_CHIPID)
9807 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
9808 
9809 #define A_PL_VF_REVISION 0x8
9810 #define A_PL_PF_INT_CAUSE 0x3c0
9811 #define A_PL_PF_INT_ENABLE 0x3c4
9812 
9813 #define S_PFSW    3
9814 #define V_PFSW(x) ((x) << S_PFSW)
9815 #define F_PFSW    V_PFSW(1U)
9816 
9817 #define S_PFSGE    2
9818 #define V_PFSGE(x) ((x) << S_PFSGE)
9819 #define F_PFSGE    V_PFSGE(1U)
9820 
9821 #define S_PFCIM    1
9822 #define V_PFCIM(x) ((x) << S_PFCIM)
9823 #define F_PFCIM    V_PFCIM(1U)
9824 
9825 #define S_PFMPS    0
9826 #define V_PFMPS(x) ((x) << S_PFMPS)
9827 #define F_PFMPS    V_PFMPS(1U)
9828 
9829 #define A_PL_PF_CTL 0x3c8
9830 
9831 #define S_SWINT    0
9832 #define V_SWINT(x) ((x) << S_SWINT)
9833 #define F_SWINT    V_SWINT(1U)
9834 
9835 #define A_PL_WHOAMI 0x19400
9836 
9837 #define S_T6_SOURCEPF    9
9838 #define M_T6_SOURCEPF    0x7U
9839 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
9840 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
9841 
9842 #define S_T6_ISVF    8
9843 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
9844 #define F_T6_ISVF    V_T6_ISVF(1U)
9845 
9846 #define S_T6_VFID    0
9847 #define M_T6_VFID    0xffU
9848 #define V_T6_VFID(x) ((x) << S_T6_VFID)
9849 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
9850 
9851 #define A_PL_PERR_CAUSE 0x19404
9852 
9853 #define S_UART    28
9854 #define V_UART(x) ((x) << S_UART)
9855 #define F_UART    V_UART(1U)
9856 
9857 #define S_ULP_TX    27
9858 #define V_ULP_TX(x) ((x) << S_ULP_TX)
9859 #define F_ULP_TX    V_ULP_TX(1U)
9860 
9861 #define S_SGE    26
9862 #define V_SGE(x) ((x) << S_SGE)
9863 #define F_SGE    V_SGE(1U)
9864 
9865 #define S_HMA    25
9866 #define V_HMA(x) ((x) << S_HMA)
9867 #define F_HMA    V_HMA(1U)
9868 
9869 #define S_CPL_SWITCH    24
9870 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
9871 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
9872 
9873 #define S_ULP_RX    23
9874 #define V_ULP_RX(x) ((x) << S_ULP_RX)
9875 #define F_ULP_RX    V_ULP_RX(1U)
9876 
9877 #define S_PM_RX    22
9878 #define V_PM_RX(x) ((x) << S_PM_RX)
9879 #define F_PM_RX    V_PM_RX(1U)
9880 
9881 #define S_PM_TX    21
9882 #define V_PM_TX(x) ((x) << S_PM_TX)
9883 #define F_PM_TX    V_PM_TX(1U)
9884 
9885 #define S_MA    20
9886 #define V_MA(x) ((x) << S_MA)
9887 #define F_MA    V_MA(1U)
9888 
9889 #define S_TP    19
9890 #define V_TP(x) ((x) << S_TP)
9891 #define F_TP    V_TP(1U)
9892 
9893 #define S_LE    18
9894 #define V_LE(x) ((x) << S_LE)
9895 #define F_LE    V_LE(1U)
9896 
9897 #define S_EDC1    17
9898 #define V_EDC1(x) ((x) << S_EDC1)
9899 #define F_EDC1    V_EDC1(1U)
9900 
9901 #define S_EDC0    16
9902 #define V_EDC0(x) ((x) << S_EDC0)
9903 #define F_EDC0    V_EDC0(1U)
9904 
9905 #define S_MC    15
9906 #define V_MC(x) ((x) << S_MC)
9907 #define F_MC    V_MC(1U)
9908 
9909 #define S_PCIE    14
9910 #define V_PCIE(x) ((x) << S_PCIE)
9911 #define F_PCIE    V_PCIE(1U)
9912 
9913 #define S_PMU    13
9914 #define V_PMU(x) ((x) << S_PMU)
9915 #define F_PMU    V_PMU(1U)
9916 
9917 #define S_XGMAC_KR1    12
9918 #define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
9919 #define F_XGMAC_KR1    V_XGMAC_KR1(1U)
9920 
9921 #define S_XGMAC_KR0    11
9922 #define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
9923 #define F_XGMAC_KR0    V_XGMAC_KR0(1U)
9924 
9925 #define S_XGMAC1    10
9926 #define V_XGMAC1(x) ((x) << S_XGMAC1)
9927 #define F_XGMAC1    V_XGMAC1(1U)
9928 
9929 #define S_XGMAC0    9
9930 #define V_XGMAC0(x) ((x) << S_XGMAC0)
9931 #define F_XGMAC0    V_XGMAC0(1U)
9932 
9933 #define S_SMB    8
9934 #define V_SMB(x) ((x) << S_SMB)
9935 #define F_SMB    V_SMB(1U)
9936 
9937 #define S_SF    7
9938 #define V_SF(x) ((x) << S_SF)
9939 #define F_SF    V_SF(1U)
9940 
9941 #define S_PL    6
9942 #define V_PL(x) ((x) << S_PL)
9943 #define F_PL    V_PL(1U)
9944 
9945 #define S_NCSI    5
9946 #define V_NCSI(x) ((x) << S_NCSI)
9947 #define F_NCSI    V_NCSI(1U)
9948 
9949 #define S_MPS    4
9950 #define V_MPS(x) ((x) << S_MPS)
9951 #define F_MPS    V_MPS(1U)
9952 
9953 #define S_MI    3
9954 #define V_MI(x) ((x) << S_MI)
9955 #define F_MI    V_MI(1U)
9956 
9957 #define S_DBG    2
9958 #define V_DBG(x) ((x) << S_DBG)
9959 #define F_DBG    V_DBG(1U)
9960 
9961 #define S_I2CM    1
9962 #define V_I2CM(x) ((x) << S_I2CM)
9963 #define F_I2CM    V_I2CM(1U)
9964 
9965 #define S_CIM    0
9966 #define V_CIM(x) ((x) << S_CIM)
9967 #define F_CIM    V_CIM(1U)
9968 
9969 #define A_PL_INT_CAUSE 0x1940c
9970 
9971 #define S_MC1    31
9972 #define V_MC1(x) ((x) << S_MC1)
9973 #define F_MC1    V_MC1(1U)
9974 
9975 #define S_MAC3    12
9976 #define V_MAC3(x) ((x) << S_MAC3)
9977 #define F_MAC3    V_MAC3(1U)
9978 
9979 #define S_MAC2    11
9980 #define V_MAC2(x) ((x) << S_MAC2)
9981 #define F_MAC2    V_MAC2(1U)
9982 
9983 #define S_FLR    30
9984 #define V_FLR(x) ((x) << S_FLR)
9985 #define F_FLR    V_FLR(1U)
9986 
9987 #define S_SW_CIM    29
9988 #define V_SW_CIM(x) ((x) << S_SW_CIM)
9989 #define F_SW_CIM    V_SW_CIM(1U)
9990 
9991 #define S_MC0    15
9992 #define V_MC0(x) ((x) << S_MC0)
9993 #define F_MC0    V_MC0(1U)
9994 
9995 #define S_MAC1    10
9996 #define V_MAC1(x) ((x) << S_MAC1)
9997 #define F_MAC1    V_MAC1(1U)
9998 
9999 #define S_MAC0    9
10000 #define V_MAC0(x) ((x) << S_MAC0)
10001 #define F_MAC0    V_MAC0(1U)
10002 
10003 #define A_PL_INT_ENABLE 0x19410
10004 #define A_PL_INT_MAP0 0x19414
10005 
10006 #define S_MAPNCSI    16
10007 #define M_MAPNCSI    0x1ffU
10008 #define V_MAPNCSI(x) ((x) << S_MAPNCSI)
10009 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
10010 
10011 #define S_MAPDEFAULT    0
10012 #define M_MAPDEFAULT    0x1ffU
10013 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
10014 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
10015 
10016 #define A_PL_RST 0x19428
10017 
10018 #define S_FATALPERREN    3
10019 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
10020 #define F_FATALPERREN    V_FATALPERREN(1U)
10021 
10022 #define S_SWINTCIM    2
10023 #define V_SWINTCIM(x) ((x) << S_SWINTCIM)
10024 #define F_SWINTCIM    V_SWINTCIM(1U)
10025 
10026 #define S_PIORST    1
10027 #define V_PIORST(x) ((x) << S_PIORST)
10028 #define F_PIORST    V_PIORST(1U)
10029 
10030 #define S_PIORSTMODE    0
10031 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
10032 #define F_PIORSTMODE    V_PIORSTMODE(1U)
10033 
10034 #define S_AUTOPCIEPAUSE    4
10035 #define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
10036 #define F_AUTOPCIEPAUSE    V_AUTOPCIEPAUSE(1U)
10037 
10038 #define A_PL_PL_INT_CAUSE 0x19430
10039 
10040 #define S_PF_ENABLEERR    5
10041 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
10042 #define F_PF_ENABLEERR    V_PF_ENABLEERR(1U)
10043 
10044 #define S_FATALPERR    4
10045 #define V_FATALPERR(x) ((x) << S_FATALPERR)
10046 #define F_FATALPERR    V_FATALPERR(1U)
10047 
10048 #define S_INVALIDACCESS    3
10049 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
10050 #define F_INVALIDACCESS    V_INVALIDACCESS(1U)
10051 
10052 #define S_TIMEOUT    2
10053 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
10054 #define F_TIMEOUT    V_TIMEOUT(1U)
10055 
10056 #define S_PLERR    1
10057 #define V_PLERR(x) ((x) << S_PLERR)
10058 #define F_PLERR    V_PLERR(1U)
10059 
10060 #define S_PERRVFID    0
10061 #define V_PERRVFID(x) ((x) << S_PERRVFID)
10062 #define F_PERRVFID    V_PERRVFID(1U)
10063 
10064 #define S_PL_BUSPERR    6
10065 #define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
10066 #define F_PL_BUSPERR    V_PL_BUSPERR(1U)
10067 
10068 #define A_PL_PL_INT_ENABLE 0x19434
10069 #define A_PL_PL_PERR_ENABLE 0x19438
10070 #define A_PL_REV 0x1943c
10071 
10072 #define S_REV    0
10073 #define M_REV    0xfU
10074 #define V_REV(x) ((x) << S_REV)
10075 #define G_REV(x) (((x) >> S_REV) & M_REV)
10076 
10077 #define A_PL_TIMEOUT_STATUS1 0x194f8
10078 
10079 #define S_PL_TORID    0
10080 #define M_PL_TORID    0xffffU
10081 #define V_PL_TORID(x) ((x) << S_PL_TORID)
10082 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
10083 
10084 #define S_PL_TOVFID    0
10085 #define M_PL_TOVFID    0xffU
10086 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
10087 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
10088 
10089 #define S_T6_PL_TOVFID    0
10090 #define M_T6_PL_TOVFID    0x1ffU
10091 #define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID)
10092 #define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID)
10093 
10094 
10095 /* registers for module LE */
10096 #define LE_BASE_ADDR 0x19c00
10097 
10098 #define A_LE_DB_CONFIG 0x19c04
10099 
10100 #define S_TCAMCMDOVLAPEN    21
10101 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
10102 #define F_TCAMCMDOVLAPEN    V_TCAMCMDOVLAPEN(1U)
10103 
10104 #define S_HASHEN    20
10105 #define V_HASHEN(x) ((x) << S_HASHEN)
10106 #define F_HASHEN    V_HASHEN(1U)
10107 
10108 #define S_ASBOTHSRCHEN    18
10109 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
10110 #define F_ASBOTHSRCHEN    V_ASBOTHSRCHEN(1U)
10111 
10112 #define S_ASLIPCOMPEN    17
10113 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
10114 #define F_ASLIPCOMPEN    V_ASLIPCOMPEN(1U)
10115 
10116 #define S_BUILD    16
10117 #define V_BUILD(x) ((x) << S_BUILD)
10118 #define F_BUILD    V_BUILD(1U)
10119 
10120 #define S_FILTEREN    11
10121 #define V_FILTEREN(x) ((x) << S_FILTEREN)
10122 #define F_FILTEREN    V_FILTEREN(1U)
10123 
10124 #define S_SYNMODE    7
10125 #define M_SYNMODE    0x3U
10126 #define V_SYNMODE(x) ((x) << S_SYNMODE)
10127 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
10128 
10129 #define S_LEBUSEN    5
10130 #define V_LEBUSEN(x) ((x) << S_LEBUSEN)
10131 #define F_LEBUSEN    V_LEBUSEN(1U)
10132 
10133 #define S_ELOOKDUMEN    4
10134 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
10135 #define F_ELOOKDUMEN    V_ELOOKDUMEN(1U)
10136 
10137 #define S_IPV4ONLYEN    3
10138 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
10139 #define F_IPV4ONLYEN    V_IPV4ONLYEN(1U)
10140 
10141 #define S_MOSTCMDOEN    2
10142 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
10143 #define F_MOSTCMDOEN    V_MOSTCMDOEN(1U)
10144 
10145 #define S_DELACTSYNOEN    1
10146 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
10147 #define F_DELACTSYNOEN    V_DELACTSYNOEN(1U)
10148 
10149 #define S_CMDOVERLAPDIS    0
10150 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
10151 #define F_CMDOVERLAPDIS    V_CMDOVERLAPDIS(1U)
10152 
10153 #define S_MASKCMDOLAPDIS    26
10154 #define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
10155 #define F_MASKCMDOLAPDIS    V_MASKCMDOLAPDIS(1U)
10156 
10157 #define S_IPV4HASHSIZEEN    25
10158 #define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
10159 #define F_IPV4HASHSIZEEN    V_IPV4HASHSIZEEN(1U)
10160 
10161 #define S_PROTOCOLMASKEN    24
10162 #define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
10163 #define F_PROTOCOLMASKEN    V_PROTOCOLMASKEN(1U)
10164 
10165 #define S_TUPLESIZEEN    23
10166 #define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
10167 #define F_TUPLESIZEEN    V_TUPLESIZEEN(1U)
10168 
10169 #define S_SRVRSRAMEN    22
10170 #define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
10171 #define F_SRVRSRAMEN    V_SRVRSRAMEN(1U)
10172 
10173 #define S_ASBOTHSRCHENPR    19
10174 #define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
10175 #define F_ASBOTHSRCHENPR    V_ASBOTHSRCHENPR(1U)
10176 
10177 #define S_POCLIPTID0    15
10178 #define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
10179 #define F_POCLIPTID0    V_POCLIPTID0(1U)
10180 
10181 #define S_TCAMARBOFF    14
10182 #define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
10183 #define F_TCAMARBOFF    V_TCAMARBOFF(1U)
10184 
10185 #define S_ACCNTFULLEN    13
10186 #define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
10187 #define F_ACCNTFULLEN    V_ACCNTFULLEN(1U)
10188 
10189 #define S_FILTERRWNOCLIP    12
10190 #define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
10191 #define F_FILTERRWNOCLIP    V_FILTERRWNOCLIP(1U)
10192 
10193 #define S_CRCHASH    10
10194 #define V_CRCHASH(x) ((x) << S_CRCHASH)
10195 #define F_CRCHASH    V_CRCHASH(1U)
10196 
10197 #define S_COMPTID    9
10198 #define V_COMPTID(x) ((x) << S_COMPTID)
10199 #define F_COMPTID    V_COMPTID(1U)
10200 
10201 #define S_SINGLETHREAD    6
10202 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
10203 #define F_SINGLETHREAD    V_SINGLETHREAD(1U)
10204 
10205 #define S_CHK_FUL_TUP_ZERO    27
10206 #define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO)
10207 #define F_CHK_FUL_TUP_ZERO    V_CHK_FUL_TUP_ZERO(1U)
10208 
10209 #define S_PRI_HASH    26
10210 #define V_PRI_HASH(x) ((x) << S_PRI_HASH)
10211 #define F_PRI_HASH    V_PRI_HASH(1U)
10212 
10213 #define S_EXTN_HASH_IPV4    25
10214 #define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4)
10215 #define F_EXTN_HASH_IPV4    V_EXTN_HASH_IPV4(1U)
10216 
10217 #define S_ASLIPCOMPEN_IPV4    18
10218 #define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4)
10219 #define F_ASLIPCOMPEN_IPV4    V_ASLIPCOMPEN_IPV4(1U)
10220 
10221 #define S_IGNR_TUP_ZERO    9
10222 #define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO)
10223 #define F_IGNR_TUP_ZERO    V_IGNR_TUP_ZERO(1U)
10224 
10225 #define S_IGNR_LIP_ZERO    8
10226 #define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO)
10227 #define F_IGNR_LIP_ZERO    V_IGNR_LIP_ZERO(1U)
10228 
10229 #define S_CLCAM_INIT_BUSY    7
10230 #define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY)
10231 #define F_CLCAM_INIT_BUSY    V_CLCAM_INIT_BUSY(1U)
10232 
10233 #define S_CLCAM_INIT    6
10234 #define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT)
10235 #define F_CLCAM_INIT    V_CLCAM_INIT(1U)
10236 
10237 #define S_MTCAM_INIT_BUSY    5
10238 #define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY)
10239 #define F_MTCAM_INIT_BUSY    V_MTCAM_INIT_BUSY(1U)
10240 
10241 #define S_MTCAM_INIT    4
10242 #define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT)
10243 #define F_MTCAM_INIT    V_MTCAM_INIT(1U)
10244 
10245 #define S_REGION_EN    0
10246 #define M_REGION_EN    0xfU
10247 #define V_REGION_EN(x) ((x) << S_REGION_EN)
10248 #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)
10249 
10250 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
10251 
10252 #define S_RTINDX    7
10253 #define M_RTINDX    0x3fU
10254 #define V_RTINDX(x) ((x) << S_RTINDX)
10255 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
10256 
10257 #define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10
10258 
10259 #define S_ATINDX    0
10260 #define M_ATINDX    0xfffffU
10261 #define V_ATINDX(x) ((x) << S_ATINDX)
10262 #define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX)
10263 
10264 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
10265 
10266 #define S_FTINDX    7
10267 #define M_FTINDX    0x3fU
10268 #define V_FTINDX(x) ((x) << S_FTINDX)
10269 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
10270 
10271 #define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14
10272 
10273 #define S_NFTINDX    0
10274 #define M_NFTINDX    0xfffffU
10275 #define V_NFTINDX(x) ((x) << S_NFTINDX)
10276 #define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX)
10277 
10278 #define A_LE_DB_SERVER_INDEX 0x19c18
10279 
10280 #define S_SRINDX    7
10281 #define M_SRINDX    0x3fU
10282 #define V_SRINDX(x) ((x) << S_SRINDX)
10283 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
10284 
10285 #define A_LE_DB_SRVR_START_INDEX 0x19c18
10286 
10287 #define S_T6_SRINDX    0
10288 #define M_T6_SRINDX    0xfffffU
10289 #define V_T6_SRINDX(x) ((x) << S_T6_SRINDX)
10290 #define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX)
10291 
10292 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
10293 
10294 #define S_CLIPTINDX    7
10295 #define M_CLIPTINDX    0x3fU
10296 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
10297 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
10298 
10299 #define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c
10300 
10301 #define S_HFTINDX    0
10302 #define M_HFTINDX    0xfffffU
10303 #define V_HFTINDX(x) ((x) << S_HFTINDX)
10304 #define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX)
10305 
10306 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
10307 
10308 #define S_ACTCNTIPV4    0
10309 #define M_ACTCNTIPV4    0xfffffU
10310 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
10311 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
10312 
10313 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
10314 
10315 #define S_ACTCNTIPV6    0
10316 #define M_ACTCNTIPV6    0xfffffU
10317 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
10318 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
10319 
10320 #define A_LE_DB_HASH_CONFIG 0x19c28
10321 
10322 #define S_HASHTIDSIZE    16
10323 #define M_HASHTIDSIZE    0x3fU
10324 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
10325 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
10326 
10327 #define S_HASHSIZE    0
10328 #define M_HASHSIZE    0x3fU
10329 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
10330 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
10331 
10332 #define A_LE_DB_HASH_TID_BASE 0x19c30
10333 #define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30
10334 
10335 #define S_HASHTBLADDR    4
10336 #define M_HASHTBLADDR    0xfffffffU
10337 #define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR)
10338 #define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR)
10339 
10340 #define A_LE_DB_INT_ENABLE 0x19c38
10341 
10342 #define S_CLIPSUBERR    29
10343 #define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR)
10344 #define F_CLIPSUBERR    V_CLIPSUBERR(1U)
10345 
10346 #define S_CLCAMFIFOERR    28
10347 #define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR)
10348 #define F_CLCAMFIFOERR    V_CLCAMFIFOERR(1U)
10349 
10350 #define S_HASHTBLMEMCRCERR    27
10351 #define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR)
10352 #define F_HASHTBLMEMCRCERR    V_HASHTBLMEMCRCERR(1U)
10353 
10354 #define S_CTCAMINVLDENT    26
10355 #define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT)
10356 #define F_CTCAMINVLDENT    V_CTCAMINVLDENT(1U)
10357 
10358 #define S_TCAMINVLDENT    25
10359 #define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT)
10360 #define F_TCAMINVLDENT    V_TCAMINVLDENT(1U)
10361 
10362 #define S_TOTCNTERR    24
10363 #define V_TOTCNTERR(x) ((x) << S_TOTCNTERR)
10364 #define F_TOTCNTERR    V_TOTCNTERR(1U)
10365 
10366 #define S_CMDPRSRINTERR    23
10367 #define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR)
10368 #define F_CMDPRSRINTERR    V_CMDPRSRINTERR(1U)
10369 
10370 #define S_CMDTIDERR    22
10371 #define V_CMDTIDERR(x) ((x) << S_CMDTIDERR)
10372 #define F_CMDTIDERR    V_CMDTIDERR(1U)
10373 
10374 #define S_T6_ACTRGNFULL    21
10375 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
10376 #define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
10377 
10378 #define S_T6_ACTCNTIPV6TZERO    20
10379 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
10380 #define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
10381 
10382 #define S_T6_ACTCNTIPV4TZERO    19
10383 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
10384 #define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
10385 
10386 #define S_T6_ACTCNTIPV6ZERO    18
10387 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
10388 #define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
10389 
10390 #define S_T6_ACTCNTIPV4ZERO    17
10391 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
10392 #define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
10393 
10394 #define S_MAIFWRINTPERR    16
10395 #define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR)
10396 #define F_MAIFWRINTPERR    V_MAIFWRINTPERR(1U)
10397 
10398 #define S_HASHTBLMEMACCERR    15
10399 #define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR)
10400 #define F_HASHTBLMEMACCERR    V_HASHTBLMEMACCERR(1U)
10401 
10402 #define S_TCAMCRCERR    14
10403 #define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR)
10404 #define F_TCAMCRCERR    V_TCAMCRCERR(1U)
10405 
10406 #define S_TCAMINTPERR    13
10407 #define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR)
10408 #define F_TCAMINTPERR    V_TCAMINTPERR(1U)
10409 
10410 #define S_VFSRAMPERR    12
10411 #define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR)
10412 #define F_VFSRAMPERR    V_VFSRAMPERR(1U)
10413 
10414 #define S_SRVSRAMPERR    11
10415 #define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR)
10416 #define F_SRVSRAMPERR    V_SRVSRAMPERR(1U)
10417 
10418 #define S_SSRAMINTPERR    10
10419 #define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR)
10420 #define F_SSRAMINTPERR    V_SSRAMINTPERR(1U)
10421 
10422 #define S_CLCAMINTPERR    9
10423 #define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR)
10424 #define F_CLCAMINTPERR    V_CLCAMINTPERR(1U)
10425 
10426 #define S_CLCAMCRCPARERR    8
10427 #define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR)
10428 #define F_CLCAMCRCPARERR    V_CLCAMCRCPARERR(1U)
10429 
10430 #define S_HASHTBLACCFAIL    7
10431 #define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL)
10432 #define F_HASHTBLACCFAIL    V_HASHTBLACCFAIL(1U)
10433 
10434 #define S_TCAMACCFAIL    6
10435 #define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL)
10436 #define F_TCAMACCFAIL    V_TCAMACCFAIL(1U)
10437 
10438 #define S_SRVSRAMACCFAIL    5
10439 #define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL)
10440 #define F_SRVSRAMACCFAIL    V_SRVSRAMACCFAIL(1U)
10441 
10442 #define S_CLIPTCAMACCFAIL    4
10443 #define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL)
10444 #define F_CLIPTCAMACCFAIL    V_CLIPTCAMACCFAIL(1U)
10445 
10446 #define S_T6_UNKNOWNCMD    3
10447 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
10448 #define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
10449 
10450 #define S_T6_LIP0    2
10451 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
10452 #define F_T6_LIP0    V_T6_LIP0(1U)
10453 
10454 #define S_T6_LIPMISS    1
10455 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
10456 #define F_T6_LIPMISS    V_T6_LIPMISS(1U)
10457 
10458 #define S_PIPELINEERR    0
10459 #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
10460 #define F_PIPELINEERR    V_PIPELINEERR(1U)
10461 
10462 #define A_LE_DB_INT_CAUSE 0x19c3c
10463 
10464 #define S_REQQPARERR    16
10465 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
10466 #define F_REQQPARERR    V_REQQPARERR(1U)
10467 
10468 #define S_UNKNOWNCMD    15
10469 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
10470 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
10471 
10472 #define S_DROPFILTERHIT    13
10473 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
10474 #define F_DROPFILTERHIT    V_DROPFILTERHIT(1U)
10475 
10476 #define S_FILTERHIT    12
10477 #define V_FILTERHIT(x) ((x) << S_FILTERHIT)
10478 #define F_FILTERHIT    V_FILTERHIT(1U)
10479 
10480 #define S_SYNCOOKIEOFF    11
10481 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
10482 #define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
10483 
10484 #define S_SYNCOOKIEBAD    10
10485 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
10486 #define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
10487 
10488 #define S_SYNCOOKIE    9
10489 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
10490 #define F_SYNCOOKIE    V_SYNCOOKIE(1U)
10491 
10492 #define S_NFASRCHFAIL    8
10493 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
10494 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
10495 
10496 #define S_ACTRGNFULL    7
10497 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
10498 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
10499 
10500 #define S_PARITYERR    6
10501 #define V_PARITYERR(x) ((x) << S_PARITYERR)
10502 #define F_PARITYERR    V_PARITYERR(1U)
10503 
10504 #define S_LIPMISS    5
10505 #define V_LIPMISS(x) ((x) << S_LIPMISS)
10506 #define F_LIPMISS    V_LIPMISS(1U)
10507 
10508 #define S_LIP0    4
10509 #define V_LIP0(x) ((x) << S_LIP0)
10510 #define F_LIP0    V_LIP0(1U)
10511 
10512 #define S_MISS    3
10513 #define V_MISS(x) ((x) << S_MISS)
10514 #define F_MISS    V_MISS(1U)
10515 
10516 #define S_ROUTINGHIT    2
10517 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
10518 #define F_ROUTINGHIT    V_ROUTINGHIT(1U)
10519 
10520 #define S_ACTIVEHIT    1
10521 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
10522 #define F_ACTIVEHIT    V_ACTIVEHIT(1U)
10523 
10524 #define S_SERVERHIT    0
10525 #define V_SERVERHIT(x) ((x) << S_SERVERHIT)
10526 #define F_SERVERHIT    V_SERVERHIT(1U)
10527 
10528 #define S_ACTCNTIPV6TZERO    21
10529 #define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
10530 #define F_ACTCNTIPV6TZERO    V_ACTCNTIPV6TZERO(1U)
10531 
10532 #define S_ACTCNTIPV4TZERO    20
10533 #define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
10534 #define F_ACTCNTIPV4TZERO    V_ACTCNTIPV4TZERO(1U)
10535 
10536 #define S_ACTCNTIPV6ZERO    19
10537 #define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
10538 #define F_ACTCNTIPV6ZERO    V_ACTCNTIPV6ZERO(1U)
10539 
10540 #define S_ACTCNTIPV4ZERO    18
10541 #define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
10542 #define F_ACTCNTIPV4ZERO    V_ACTCNTIPV4ZERO(1U)
10543 
10544 #define S_MARSPPARERR    17
10545 #define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
10546 #define F_MARSPPARERR    V_MARSPPARERR(1U)
10547 
10548 #define S_VFPARERR    14
10549 #define V_VFPARERR(x) ((x) << S_VFPARERR)
10550 #define F_VFPARERR    V_VFPARERR(1U)
10551 
10552 #define S_T6_ACTRGNFULL    21
10553 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
10554 #define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
10555 
10556 #define S_T6_ACTCNTIPV6TZERO    20
10557 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
10558 #define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
10559 
10560 #define S_T6_ACTCNTIPV4TZERO    19
10561 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
10562 #define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
10563 
10564 #define S_T6_ACTCNTIPV6ZERO    18
10565 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
10566 #define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
10567 
10568 #define S_T6_ACTCNTIPV4ZERO    17
10569 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
10570 #define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
10571 
10572 #define S_T6_UNKNOWNCMD    3
10573 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
10574 #define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
10575 
10576 #define S_T6_LIP0    2
10577 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
10578 #define F_T6_LIP0    V_T6_LIP0(1U)
10579 
10580 #define S_T6_LIPMISS    1
10581 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
10582 #define F_T6_LIPMISS    V_T6_LIPMISS(1U)
10583 
10584 #define A_LE_DB_RSP_CODE_0 0x19c74
10585 
10586 #define S_SUCCESS    25
10587 #define M_SUCCESS    0x1fU
10588 #define V_SUCCESS(x) ((x) << S_SUCCESS)
10589 #define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS)
10590 
10591 #define S_TCAM_ACTV_SUCC    20
10592 #define M_TCAM_ACTV_SUCC    0x1fU
10593 #define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC)
10594 #define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC)
10595 
10596 #define S_HASH_ACTV_SUCC    15
10597 #define M_HASH_ACTV_SUCC    0x1fU
10598 #define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC)
10599 #define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC)
10600 
10601 #define S_TCAM_SRVR_HIT    10
10602 #define M_TCAM_SRVR_HIT    0x1fU
10603 #define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT)
10604 #define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT)
10605 
10606 #define S_SRAM_SRVR_HIT    5
10607 #define M_SRAM_SRVR_HIT    0x1fU
10608 #define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT)
10609 #define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT)
10610 
10611 #define S_TCAM_ACTV_HIT    0
10612 #define M_TCAM_ACTV_HIT    0x1fU
10613 #define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT)
10614 #define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT)
10615 
10616 #define A_LE_DB_RSP_CODE_1 0x19c78
10617 
10618 #define S_HASH_ACTV_HIT    25
10619 #define M_HASH_ACTV_HIT    0x1fU
10620 #define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT)
10621 #define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT)
10622 
10623 #define S_T6_MISS    20
10624 #define M_T6_MISS    0x1fU
10625 #define V_T6_MISS(x) ((x) << S_T6_MISS)
10626 #define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS)
10627 
10628 #define S_NORM_FILT_HIT    15
10629 #define M_NORM_FILT_HIT    0x1fU
10630 #define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT)
10631 #define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT)
10632 
10633 #define S_HPRI_FILT_HIT    10
10634 #define M_HPRI_FILT_HIT    0x1fU
10635 #define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT)
10636 #define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT)
10637 
10638 #define S_ACTV_OPEN_ERR    5
10639 #define M_ACTV_OPEN_ERR    0x1fU
10640 #define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR)
10641 #define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR)
10642 
10643 #define S_ACTV_FULL_ERR    0
10644 #define M_ACTV_FULL_ERR    0x1fU
10645 #define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR)
10646 #define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR)
10647 
10648 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
10649 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
10650 #define A_LE_ACT_CNT_THRSH 0x19c9c
10651 
10652 #define S_ACT_CNT_THRSH    0
10653 #define M_ACT_CNT_THRSH    0x1fffffU
10654 #define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
10655 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
10656 
10657 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
10658 
10659 #define S_RSPCNTLE    16
10660 #define M_RSPCNTLE    0xffffU
10661 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
10662 #define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
10663 
10664 #define S_REQCNTLE    0
10665 #define M_REQCNTLE    0xffffU
10666 #define V_REQCNTLE(x) ((x) << S_REQCNTLE)
10667 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
10668 
10669 #define A_LE_DB_DBGI_CONFIG 0x19cf0
10670 
10671 #define S_DBGICMDPERR    31
10672 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
10673 #define F_DBGICMDPERR    V_DBGICMDPERR(1U)
10674 
10675 #define S_DBGICMDRANGE    22
10676 #define M_DBGICMDRANGE    0x7U
10677 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
10678 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
10679 
10680 #define S_DBGICMDMSKTYPE    21
10681 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
10682 #define F_DBGICMDMSKTYPE    V_DBGICMDMSKTYPE(1U)
10683 
10684 #define S_DBGICMDSEARCH    20
10685 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
10686 #define F_DBGICMDSEARCH    V_DBGICMDSEARCH(1U)
10687 
10688 #define S_DBGICMDREAD    19
10689 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
10690 #define F_DBGICMDREAD    V_DBGICMDREAD(1U)
10691 
10692 #define S_DBGICMDLEARN    18
10693 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
10694 #define F_DBGICMDLEARN    V_DBGICMDLEARN(1U)
10695 
10696 #define S_DBGICMDERASE    17
10697 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
10698 #define F_DBGICMDERASE    V_DBGICMDERASE(1U)
10699 
10700 #define S_DBGICMDIPV6    16
10701 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
10702 #define F_DBGICMDIPV6    V_DBGICMDIPV6(1U)
10703 
10704 #define S_DBGICMDTYPE    13
10705 #define M_DBGICMDTYPE    0x7U
10706 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
10707 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
10708 
10709 #define S_DBGICMDACKERR    12
10710 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
10711 #define F_DBGICMDACKERR    V_DBGICMDACKERR(1U)
10712 
10713 #define S_DBGICMDBUSY    3
10714 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
10715 #define F_DBGICMDBUSY    V_DBGICMDBUSY(1U)
10716 
10717 #define S_DBGICMDSTRT    2
10718 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
10719 #define F_DBGICMDSTRT    V_DBGICMDSTRT(1U)
10720 
10721 #define S_DBGICMDMODE    0
10722 #define M_DBGICMDMODE    0x3U
10723 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
10724 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
10725 
10726 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
10727 
10728 #define S_DBGICMD    20
10729 #define M_DBGICMD    0xfU
10730 #define V_DBGICMD(x) ((x) << S_DBGICMD)
10731 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
10732 
10733 #define S_DBGITINDEX    0
10734 #define M_DBGITINDEX    0xfffffU
10735 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
10736 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
10737 
10738 #define A_LE_DB_DBGI_REQ_CMD 0x19cf4
10739 
10740 #define S_DBGITID    0
10741 #define M_DBGITID    0xfffffU
10742 #define V_DBGITID(x) ((x) << S_DBGITID)
10743 #define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID)
10744 
10745 #define A_LE_PERR_ENABLE 0x19cf8
10746 
10747 #define S_BKCHKPERIOD    22
10748 #define M_BKCHKPERIOD    0x3ffU
10749 #define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD)
10750 #define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD)
10751 
10752 #define S_TCAMBKCHKEN    21
10753 #define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN)
10754 #define F_TCAMBKCHKEN    V_TCAMBKCHKEN(1U)
10755 
10756 #define S_T6_CLCAMFIFOERR    2
10757 #define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR)
10758 #define F_T6_CLCAMFIFOERR    V_T6_CLCAMFIFOERR(1U)
10759 
10760 #define S_T6_HASHTBLMEMCRCERR    1
10761 #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
10762 #define F_T6_HASHTBLMEMCRCERR    V_T6_HASHTBLMEMCRCERR(1U)
10763 
10764 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
10765 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
10766 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
10767 
10768 #define S_DBGIRSPINDEX    12
10769 #define M_DBGIRSPINDEX    0xfffffU
10770 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
10771 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
10772 
10773 #define S_DBGIRSPMSG    8
10774 #define M_DBGIRSPMSG    0xfU
10775 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
10776 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
10777 
10778 #define S_DBGIRSPMSGVLD    7
10779 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
10780 #define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
10781 
10782 #define S_DBGIRSPMHIT    2
10783 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
10784 #define F_DBGIRSPMHIT    V_DBGIRSPMHIT(1U)
10785 
10786 #define S_DBGIRSPHIT    1
10787 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
10788 #define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
10789 
10790 #define S_DBGIRSPVALID    0
10791 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
10792 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
10793 
10794 #define S_DBGIRSPTID    12
10795 #define M_DBGIRSPTID    0xfffffU
10796 #define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID)
10797 #define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID)
10798 
10799 #define S_DBGIRSPLEARN    2
10800 #define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN)
10801 #define F_DBGIRSPLEARN    V_DBGIRSPLEARN(1U)
10802 
10803 #define A_LE_DBG_SEL 0x19d98
10804 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
10805 #define A_LE_DB_TCAM_TID_BASE 0x19df0
10806 
10807 #define S_TCAM_TID_BASE    0
10808 #define M_TCAM_TID_BASE    0xfffffU
10809 #define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE)
10810 #define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE)
10811 
10812 #define A_LE_DB_CLCAM_TID_BASE 0x19df4
10813 
10814 #define S_CLCAM_TID_BASE    0
10815 #define M_CLCAM_TID_BASE    0xfffffU
10816 #define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE)
10817 #define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE)
10818 
10819 #define A_LE_DB_TID_HASHBASE 0x19df8
10820 
10821 #define S_HASHBASE_ADDR    2
10822 #define M_HASHBASE_ADDR    0xfffffU
10823 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
10824 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
10825 
10826 #define A_T6_LE_DB_HASH_TID_BASE 0x19df8
10827 
10828 #define S_HASH_TID_BASE    0
10829 #define M_HASH_TID_BASE    0xfffffU
10830 #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
10831 #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)
10832 
10833 #define A_LE_DB_SSRAM_TID_BASE 0x19dfc
10834 
10835 #define S_SSRAM_TID_BASE    0
10836 #define M_SSRAM_TID_BASE    0xfffffU
10837 #define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE)
10838 #define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE)
10839 
10840 #define A_LE_DEBUG_LA_CONFIG 0x19f20
10841 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
10842 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
10843 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
10844 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
10845 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
10846 #define A_LE_SRVR_SRAM_INIT 0x19f34
10847 
10848 #define S_SRVRSRAMBASE    2
10849 #define M_SRVRSRAMBASE    0xfffffU
10850 #define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
10851 #define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
10852 
10853 #define S_SRVRINITBUSY    1
10854 #define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
10855 #define F_SRVRINITBUSY    V_SRVRINITBUSY(1U)
10856 
10857 #define S_SRVRINIT    0
10858 #define V_SRVRINIT(x) ((x) << S_SRVRINIT)
10859 #define F_SRVRINIT    V_SRVRINIT(1U)
10860 
10861 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
10862 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
10863 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
10864 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
10865 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
10866 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
10867 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
10868 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
10869 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
10870 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
10871 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
10872 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
10873 
10874 /* registers for module NCSI */
10875 #define NCSI_BASE_ADDR 0x1a000
10876 
10877 #define A_NCSI_LA_RESERVED 0x1a0cc
10878 #define A_NCSI_INT_ENABLE 0x1a0d4
10879 
10880 #define S_CIM_DM_PRTY_ERR    8
10881 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
10882 #define F_CIM_DM_PRTY_ERR    V_CIM_DM_PRTY_ERR(1U)
10883 
10884 #define S_MPS_DM_PRTY_ERR    7
10885 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
10886 #define F_MPS_DM_PRTY_ERR    V_MPS_DM_PRTY_ERR(1U)
10887 
10888 #define S_TOKEN    6
10889 #define V_TOKEN(x) ((x) << S_TOKEN)
10890 #define F_TOKEN    V_TOKEN(1U)
10891 
10892 #define S_ARB_DONE    5
10893 #define V_ARB_DONE(x) ((x) << S_ARB_DONE)
10894 #define F_ARB_DONE    V_ARB_DONE(1U)
10895 
10896 #define S_ARB_STARTED    4
10897 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
10898 #define F_ARB_STARTED    V_ARB_STARTED(1U)
10899 
10900 #define S_WOL    3
10901 #define V_WOL(x) ((x) << S_WOL)
10902 #define F_WOL    V_WOL(1U)
10903 
10904 #define S_MACINT    2
10905 #define V_MACINT(x) ((x) << S_MACINT)
10906 #define F_MACINT    V_MACINT(1U)
10907 
10908 #define S_TXFIFO_PRTY_ERR    1
10909 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
10910 #define F_TXFIFO_PRTY_ERR    V_TXFIFO_PRTY_ERR(1U)
10911 
10912 #define S_RXFIFO_PRTY_ERR    0
10913 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
10914 #define F_RXFIFO_PRTY_ERR    V_RXFIFO_PRTY_ERR(1U)
10915 
10916 #define A_NCSI_INT_CAUSE 0x1a0d8
10917 #define A_NCSI_PERR_ENABLE 0x1a0f8
10918 
10919 /* registers for module XGMAC */
10920 #define XGMAC_BASE_ADDR 0x0
10921 
10922 #define A_XGMAC_PORT_CFG 0x1000
10923 
10924 #define S_SIGNAL_DET    14
10925 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
10926 #define F_SIGNAL_DET    V_SIGNAL_DET(1U)
10927 
10928 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
10929 
10930 #define S_EXT_LOS    28
10931 #define V_EXT_LOS(x) ((x) << S_EXT_LOS)
10932 #define F_EXT_LOS    V_EXT_LOS(1U)
10933 
10934 #define S_INCMPTBL_LINK    27
10935 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
10936 #define F_INCMPTBL_LINK    V_INCMPTBL_LINK(1U)
10937 
10938 #define S_PATDETWAKE    26
10939 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
10940 #define F_PATDETWAKE    V_PATDETWAKE(1U)
10941 
10942 #define S_MAGICWAKE    25
10943 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
10944 #define F_MAGICWAKE    V_MAGICWAKE(1U)
10945 
10946 #define S_SIGDETCHG    24
10947 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
10948 #define F_SIGDETCHG    V_SIGDETCHG(1U)
10949 
10950 #define S_PCSR_FEC_CORR    23
10951 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
10952 #define F_PCSR_FEC_CORR    V_PCSR_FEC_CORR(1U)
10953 
10954 #define S_AE_TRAIN_LOCAL    22
10955 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
10956 #define F_AE_TRAIN_LOCAL    V_AE_TRAIN_LOCAL(1U)
10957 
10958 #define S_HSSPLL_LOCK    21
10959 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
10960 #define F_HSSPLL_LOCK    V_HSSPLL_LOCK(1U)
10961 
10962 #define S_HSSPRT_READY    20
10963 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
10964 #define F_HSSPRT_READY    V_HSSPRT_READY(1U)
10965 
10966 #define S_AUTONEG_DONE    19
10967 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
10968 #define F_AUTONEG_DONE    V_AUTONEG_DONE(1U)
10969 
10970 #define S_PCSR_HI_BER    18
10971 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
10972 #define F_PCSR_HI_BER    V_PCSR_HI_BER(1U)
10973 
10974 #define S_PCSR_FEC_ERROR    17
10975 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
10976 #define F_PCSR_FEC_ERROR    V_PCSR_FEC_ERROR(1U)
10977 
10978 #define S_PCSR_LINK_FAIL    16
10979 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
10980 #define F_PCSR_LINK_FAIL    V_PCSR_LINK_FAIL(1U)
10981 
10982 #define S_XAUI_DEC_ERROR    15
10983 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
10984 #define F_XAUI_DEC_ERROR    V_XAUI_DEC_ERROR(1U)
10985 
10986 #define S_XAUI_LINK_FAIL    14
10987 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
10988 #define F_XAUI_LINK_FAIL    V_XAUI_LINK_FAIL(1U)
10989 
10990 #define S_PCS_CTC_ERROR    13
10991 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
10992 #define F_PCS_CTC_ERROR    V_PCS_CTC_ERROR(1U)
10993 
10994 #define S_PCS_LINK_GOOD    12
10995 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
10996 #define F_PCS_LINK_GOOD    V_PCS_LINK_GOOD(1U)
10997 
10998 #define S_PCS_LINK_FAIL    11
10999 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
11000 #define F_PCS_LINK_FAIL    V_PCS_LINK_FAIL(1U)
11001 
11002 #define S_RXFIFOOVERFLOW    10
11003 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
11004 #define F_RXFIFOOVERFLOW    V_RXFIFOOVERFLOW(1U)
11005 
11006 #define S_HSSPRBSERR    9
11007 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
11008 #define F_HSSPRBSERR    V_HSSPRBSERR(1U)
11009 
11010 #define S_HSSEYEQUAL    8
11011 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
11012 #define F_HSSEYEQUAL    V_HSSEYEQUAL(1U)
11013 
11014 #define S_REMOTEFAULT    7
11015 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
11016 #define F_REMOTEFAULT    V_REMOTEFAULT(1U)
11017 
11018 #define S_LOCALFAULT    6
11019 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
11020 #define F_LOCALFAULT    V_LOCALFAULT(1U)
11021 
11022 #define S_MAC_LINK_DOWN    5
11023 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
11024 #define F_MAC_LINK_DOWN    V_MAC_LINK_DOWN(1U)
11025 
11026 #define S_MAC_LINK_UP    4
11027 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
11028 #define F_MAC_LINK_UP    V_MAC_LINK_UP(1U)
11029 
11030 #define S_BEAN_INT    3
11031 #define V_BEAN_INT(x) ((x) << S_BEAN_INT)
11032 #define F_BEAN_INT    V_BEAN_INT(1U)
11033 
11034 #define S_XGM_INT    2
11035 #define V_XGM_INT(x) ((x) << S_XGM_INT)
11036 #define F_XGM_INT    V_XGM_INT(1U)
11037 
11038 
11039 /* registers for module UP */
11040 #define UP_BASE_ADDR 0x0
11041 
11042 #define A_UP_IBQ_0_RDADDR 0x10
11043 
11044 #define S_QUEID    13
11045 #define M_QUEID    0x7ffffU
11046 #define V_QUEID(x) ((x) << S_QUEID)
11047 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
11048 
11049 #define S_IBQRDADDR    0
11050 #define M_IBQRDADDR    0x1fffU
11051 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
11052 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
11053 
11054 #define A_UP_IBQ_0_WRADDR 0x14
11055 
11056 #define S_IBQWRADDR    0
11057 #define M_IBQWRADDR    0x1fffU
11058 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
11059 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
11060 
11061 #define A_UP_IBQ_0_STATUS 0x18
11062 
11063 #define S_QUEERRFRAME    31
11064 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
11065 #define F_QUEERRFRAME    V_QUEERRFRAME(1U)
11066 
11067 #define S_QUEREMFLITS    0
11068 #define M_QUEREMFLITS    0x7ffU
11069 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
11070 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
11071 
11072 #define A_UP_IBQ_0_PKTCNT 0x1c
11073 
11074 #define S_QUEEOPCNT    16
11075 #define M_QUEEOPCNT    0xfffU
11076 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
11077 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
11078 
11079 #define S_QUESOPCNT    0
11080 #define M_QUESOPCNT    0xfffU
11081 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
11082 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
11083 
11084 #define A_UP_OBQ_0_RDADDR 0x70
11085 
11086 #define S_OBQID    15
11087 #define M_OBQID    0x1ffffU
11088 #define V_OBQID(x) ((x) << S_OBQID)
11089 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
11090 
11091 #define S_QUERDADDR    0
11092 #define M_QUERDADDR    0x7fffU
11093 #define V_QUERDADDR(x) ((x) << S_QUERDADDR)
11094 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
11095 
11096 #define A_UP_OBQ_0_REALADDR 0x104
11097 
11098 #define S_QUEMEMADDR    3
11099 #define M_QUEMEMADDR    0x7ffU
11100 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
11101 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
11102 
11103 #define A_UP_UP_DBG_LA_CFG 0x140
11104 
11105 #define S_UPDBGLACAPTBUB    31
11106 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
11107 #define F_UPDBGLACAPTBUB    V_UPDBGLACAPTBUB(1U)
11108 
11109 #define S_UPDBGLACAPTPCONLY    30
11110 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
11111 #define F_UPDBGLACAPTPCONLY    V_UPDBGLACAPTPCONLY(1U)
11112 
11113 #define S_UPDBGLAMASKSTOP    29
11114 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
11115 #define F_UPDBGLAMASKSTOP    V_UPDBGLAMASKSTOP(1U)
11116 
11117 #define S_UPDBGLAMASKTRIG    28
11118 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
11119 #define F_UPDBGLAMASKTRIG    V_UPDBGLAMASKTRIG(1U)
11120 
11121 #define S_UPDBGLAWRPTR    16
11122 #define M_UPDBGLAWRPTR    0xfffU
11123 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
11124 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
11125 
11126 #define S_UPDBGLARDPTR    2
11127 #define M_UPDBGLARDPTR    0xfffU
11128 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
11129 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
11130 
11131 #define S_UPDBGLARDEN    1
11132 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
11133 #define F_UPDBGLARDEN    V_UPDBGLARDEN(1U)
11134 
11135 #define S_UPDBGLAEN    0
11136 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
11137 #define F_UPDBGLAEN    V_UPDBGLAEN(1U)
11138 
11139 #define S_UPDBGLABUSY    14
11140 #define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
11141 #define F_UPDBGLABUSY    V_UPDBGLABUSY(1U)
11142 
11143 #define A_UP_UP_DBG_LA_DATA 0x144
11144 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280
11145 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284
11146 #define A_UP_IBQ_0_SHADOW_STATUS 0x288
11147 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
11148 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290
11149 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294
11150 #define A_UP_IBQ_1_SHADOW_STATUS 0x298
11151 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
11152 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
11153 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
11154 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
11155 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
11156 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
11157 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
11158 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
11159 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
11160 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
11161 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
11162 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
11163 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
11164 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
11165 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
11166 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
11167 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
11168 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
11169 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
11170 
11171 #define S_QUEWRADDR    0
11172 #define M_QUEWRADDR    0x7fffU
11173 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
11174 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
11175 
11176 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
11177 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
11178 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
11179 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
11180 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
11181 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
11182 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300
11183 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304
11184 #define A_UP_OBQ_2_SHADOW_STATUS 0x308
11185 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
11186 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310
11187 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314
11188 #define A_UP_OBQ_3_SHADOW_STATUS 0x318
11189 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
11190 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320
11191 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324
11192 #define A_UP_OBQ_4_SHADOW_STATUS 0x328
11193 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
11194 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330
11195 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334
11196 #define A_UP_OBQ_5_SHADOW_STATUS 0x338
11197 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
11198 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340
11199 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344
11200 #define A_UP_OBQ_6_SHADOW_STATUS 0x348
11201 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
11202 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350
11203 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354
11204 #define A_UP_OBQ_7_SHADOW_STATUS 0x358
11205 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
11206 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360
11207 
11208 #define S_QUESIZE    26
11209 #define M_QUESIZE    0x3fU
11210 #define V_QUESIZE(x) ((x) << S_QUESIZE)
11211 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
11212 
11213 #define S_QUEBASE    8
11214 #define M_QUEBASE    0x3fU
11215 #define V_QUEBASE(x) ((x) << S_QUEBASE)
11216 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
11217 
11218 #define S_QUEDBG8BEN    7
11219 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
11220 #define F_QUEDBG8BEN    V_QUEDBG8BEN(1U)
11221 
11222 #define S_QUEBAREADDR    0
11223 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
11224 #define F_QUEBAREADDR    V_QUEBAREADDR(1U)
11225 
11226 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364
11227 
11228 #define S_QUERDADDRWRAP    31
11229 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
11230 #define F_QUERDADDRWRAP    V_QUERDADDRWRAP(1U)
11231 
11232 #define S_QUEWRADDRWRAP    30
11233 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
11234 #define F_QUEWRADDRWRAP    V_QUEWRADDRWRAP(1U)
11235 
11236 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368
11237 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
11238 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370
11239 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374
11240 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378
11241 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
11242 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380
11243 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384
11244 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388
11245 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
11246 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390
11247 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394
11248 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398
11249 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
11250 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
11251 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
11252 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
11253 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
11254 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
11255 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
11256 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
11257 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
11258 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
11259 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
11260 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
11261 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
11262 
11263 /* registers for module CIM_CTL */
11264 #define CIM_CTL_BASE_ADDR 0x0
11265 
11266 
11267 /* registers for module MAC */
11268 #define MAC_BASE_ADDR 0x0
11269 
11270 #define A_MAC_PORT_CFG 0x800
11271 
11272 #define S_MAC_CLK_SEL    29
11273 #define M_MAC_CLK_SEL    0x7U
11274 #define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
11275 #define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
11276 
11277 #define S_SINKTX    27
11278 #define V_SINKTX(x) ((x) << S_SINKTX)
11279 #define F_SINKTX    V_SINKTX(1U)
11280 
11281 #define S_SINKTXONLINKDOWN    26
11282 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
11283 #define F_SINKTXONLINKDOWN    V_SINKTXONLINKDOWN(1U)
11284 
11285 #define S_LOOPNOFWD    24
11286 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
11287 #define F_LOOPNOFWD    V_LOOPNOFWD(1U)
11288 
11289 #define S_SMUX_RX_LOOP    19
11290 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
11291 #define F_SMUX_RX_LOOP    V_SMUX_RX_LOOP(1U)
11292 
11293 #define S_RX_LANE_SWAP    18
11294 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
11295 #define F_RX_LANE_SWAP    V_RX_LANE_SWAP(1U)
11296 
11297 #define S_TX_LANE_SWAP    17
11298 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
11299 #define F_TX_LANE_SWAP    V_TX_LANE_SWAP(1U)
11300 
11301 #define S_SMUXTXSEL    9
11302 #define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
11303 #define F_SMUXTXSEL    V_SMUXTXSEL(1U)
11304 
11305 #define S_SMUXRXSEL    8
11306 #define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
11307 #define F_SMUXRXSEL    V_SMUXRXSEL(1U)
11308 
11309 #define S_PORTSPEED    4
11310 #define M_PORTSPEED    0x3U
11311 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
11312 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
11313 
11314 #define S_RX_BYTE_SWAP    3
11315 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
11316 #define F_RX_BYTE_SWAP    V_RX_BYTE_SWAP(1U)
11317 
11318 #define S_TX_BYTE_SWAP    2
11319 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
11320 #define F_TX_BYTE_SWAP    V_TX_BYTE_SWAP(1U)
11321 
11322 #define S_PORT_SEL    0
11323 #define V_PORT_SEL(x) ((x) << S_PORT_SEL)
11324 #define F_PORT_SEL    V_PORT_SEL(1U)
11325 
11326 #define S_ENA_ERR_RSP    28
11327 #define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP)
11328 #define F_ENA_ERR_RSP    V_ENA_ERR_RSP(1U)
11329 
11330 #define S_DEBUG_CLR    25
11331 #define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR)
11332 #define F_DEBUG_CLR    V_DEBUG_CLR(1U)
11333 
11334 #define S_PLL_SEL    23
11335 #define V_PLL_SEL(x) ((x) << S_PLL_SEL)
11336 #define F_PLL_SEL    V_PLL_SEL(1U)
11337 
11338 #define S_PORT_MAP    20
11339 #define M_PORT_MAP    0x7U
11340 #define V_PORT_MAP(x) ((x) << S_PORT_MAP)
11341 #define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP)
11342 
11343 #define S_AEC_PAT_DATA    15
11344 #define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA)
11345 #define F_AEC_PAT_DATA    V_AEC_PAT_DATA(1U)
11346 
11347 #define S_MACCLK_SEL    13
11348 #define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL)
11349 #define F_MACCLK_SEL    V_MACCLK_SEL(1U)
11350 
11351 #define S_XGMII_SEL    12
11352 #define V_XGMII_SEL(x) ((x) << S_XGMII_SEL)
11353 #define F_XGMII_SEL    V_XGMII_SEL(1U)
11354 
11355 #define S_DEBUG_PORT_SEL    10
11356 #define M_DEBUG_PORT_SEL    0x3U
11357 #define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL)
11358 #define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL)
11359 
11360 #define S_ENABLE_25G    7
11361 #define V_ENABLE_25G(x) ((x) << S_ENABLE_25G)
11362 #define F_ENABLE_25G    V_ENABLE_25G(1U)
11363 
11364 #define S_ENABLE_50G    6
11365 #define V_ENABLE_50G(x) ((x) << S_ENABLE_50G)
11366 #define F_ENABLE_50G    V_ENABLE_50G(1U)
11367 
11368 #define S_DEBUG_TX_RX_SEL    1
11369 #define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL)
11370 #define F_DEBUG_TX_RX_SEL    V_DEBUG_TX_RX_SEL(1U)
11371 
11372 #define A_MAC_PORT_RESET_CTRL 0x804
11373 
11374 #define S_TWGDSK_HSSC16B    31
11375 #define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
11376 #define F_TWGDSK_HSSC16B    V_TWGDSK_HSSC16B(1U)
11377 
11378 #define S_EEE_RESET    30
11379 #define V_EEE_RESET(x) ((x) << S_EEE_RESET)
11380 #define F_EEE_RESET    V_EEE_RESET(1U)
11381 
11382 #define S_PTP_TIMER    29
11383 #define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
11384 #define F_PTP_TIMER    V_PTP_TIMER(1U)
11385 
11386 #define S_MTIPREFRESET    28
11387 #define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
11388 #define F_MTIPREFRESET    V_MTIPREFRESET(1U)
11389 
11390 #define S_MAC100G40G_RESET    27
11391 #define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET)
11392 #define F_MAC100G40G_RESET    V_MAC100G40G_RESET(1U)
11393 
11394 #define S_MAC10G1G_RESET    26
11395 #define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET)
11396 #define F_MAC10G1G_RESET    V_MAC10G1G_RESET(1U)
11397 
11398 #define S_MTIPREGRESET    25
11399 #define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
11400 #define F_MTIPREGRESET    V_MTIPREGRESET(1U)
11401 
11402 #define S_PCS1G_RESET    24
11403 #define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET)
11404 #define F_PCS1G_RESET    V_PCS1G_RESET(1U)
11405 
11406 #define S_AEC3RESET    23
11407 #define V_AEC3RESET(x) ((x) << S_AEC3RESET)
11408 #define F_AEC3RESET    V_AEC3RESET(1U)
11409 
11410 #define S_AEC2RESET    22
11411 #define V_AEC2RESET(x) ((x) << S_AEC2RESET)
11412 #define F_AEC2RESET    V_AEC2RESET(1U)
11413 
11414 #define S_AEC1RESET    21
11415 #define V_AEC1RESET(x) ((x) << S_AEC1RESET)
11416 #define F_AEC1RESET    V_AEC1RESET(1U)
11417 
11418 #define S_AEC0RESET    20
11419 #define V_AEC0RESET(x) ((x) << S_AEC0RESET)
11420 #define F_AEC0RESET    V_AEC0RESET(1U)
11421 
11422 #define S_AET3RESET    19
11423 #define V_AET3RESET(x) ((x) << S_AET3RESET)
11424 #define F_AET3RESET    V_AET3RESET(1U)
11425 
11426 #define S_AET2RESET    18
11427 #define V_AET2RESET(x) ((x) << S_AET2RESET)
11428 #define F_AET2RESET    V_AET2RESET(1U)
11429 
11430 #define S_AET1RESET    17
11431 #define V_AET1RESET(x) ((x) << S_AET1RESET)
11432 #define F_AET1RESET    V_AET1RESET(1U)
11433 
11434 #define S_AET0RESET    16
11435 #define V_AET0RESET(x) ((x) << S_AET0RESET)
11436 #define F_AET0RESET    V_AET0RESET(1U)
11437 
11438 #define S_PCS10G_RESET    15
11439 #define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET)
11440 #define F_PCS10G_RESET    V_PCS10G_RESET(1U)
11441 
11442 #define S_PCS40G_RESET    14
11443 #define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET)
11444 #define F_PCS40G_RESET    V_PCS40G_RESET(1U)
11445 
11446 #define S_PCS100G_RESET    13
11447 #define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET)
11448 #define F_PCS100G_RESET    V_PCS100G_RESET(1U)
11449 
11450 #define S_TXIF_RESET    12
11451 #define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
11452 #define F_TXIF_RESET    V_TXIF_RESET(1U)
11453 
11454 #define S_RXIF_RESET    11
11455 #define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
11456 #define F_RXIF_RESET    V_RXIF_RESET(1U)
11457 
11458 #define S_AUXEXT_RESET    10
11459 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
11460 #define F_AUXEXT_RESET    V_AUXEXT_RESET(1U)
11461 
11462 #define S_MTIPSD3TXRST    9
11463 #define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
11464 #define F_MTIPSD3TXRST    V_MTIPSD3TXRST(1U)
11465 
11466 #define S_MTIPSD2TXRST    8
11467 #define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
11468 #define F_MTIPSD2TXRST    V_MTIPSD2TXRST(1U)
11469 
11470 #define S_MTIPSD1TXRST    7
11471 #define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
11472 #define F_MTIPSD1TXRST    V_MTIPSD1TXRST(1U)
11473 
11474 #define S_MTIPSD0TXRST    6
11475 #define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
11476 #define F_MTIPSD0TXRST    V_MTIPSD0TXRST(1U)
11477 
11478 #define S_MTIPSD3RXRST    5
11479 #define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
11480 #define F_MTIPSD3RXRST    V_MTIPSD3RXRST(1U)
11481 
11482 #define S_MTIPSD2RXRST    4
11483 #define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
11484 #define F_MTIPSD2RXRST    V_MTIPSD2RXRST(1U)
11485 
11486 #define S_MTIPSD1RXRST    3
11487 #define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
11488 #define F_MTIPSD1RXRST    V_MTIPSD1RXRST(1U)
11489 
11490 #define S_WOL_RESET    2
11491 #define V_WOL_RESET(x) ((x) << S_WOL_RESET)
11492 #define F_WOL_RESET    V_WOL_RESET(1U)
11493 
11494 #define S_MTIPSD0RXRST    1
11495 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
11496 #define F_MTIPSD0RXRST    V_MTIPSD0RXRST(1U)
11497 
11498 #define S_HSS_RESET    0
11499 #define V_HSS_RESET(x) ((x) << S_HSS_RESET)
11500 #define F_HSS_RESET    V_HSS_RESET(1U)
11501 
11502 #define A_MAC_PORT_PKT_COUNT 0x81c
11503 
11504 #define S_TX_SOP_COUNT    24
11505 #define M_TX_SOP_COUNT    0xffU
11506 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
11507 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
11508 
11509 #define S_TX_EOP_COUNT    16
11510 #define M_TX_EOP_COUNT    0xffU
11511 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
11512 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
11513 
11514 #define S_RX_SOP_COUNT    8
11515 #define M_RX_SOP_COUNT    0xffU
11516 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
11517 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
11518 
11519 #define S_RX_EOP_COUNT    0
11520 #define M_RX_EOP_COUNT    0xffU
11521 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
11522 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
11523 
11524 #define A_MAC_PORT_MTIP_RESET_CTRL 0x82c
11525 
11526 #define S_AN_RESET_SD_TX_CLK    31
11527 #define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK)
11528 #define F_AN_RESET_SD_TX_CLK    V_AN_RESET_SD_TX_CLK(1U)
11529 
11530 #define S_AN_RESET_SD_RX_CLK    30
11531 #define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK)
11532 #define F_AN_RESET_SD_RX_CLK    V_AN_RESET_SD_RX_CLK(1U)
11533 
11534 #define S_SGMII_RESET_TX_CLK    29
11535 #define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK)
11536 #define F_SGMII_RESET_TX_CLK    V_SGMII_RESET_TX_CLK(1U)
11537 
11538 #define S_SGMII_RESET_RX_CLK    28
11539 #define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK)
11540 #define F_SGMII_RESET_RX_CLK    V_SGMII_RESET_RX_CLK(1U)
11541 
11542 #define S_SGMII_RESET_REF_CLK    27
11543 #define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK)
11544 #define F_SGMII_RESET_REF_CLK    V_SGMII_RESET_REF_CLK(1U)
11545 
11546 #define S_PCS10G_RESET_XFI_RXCLK    26
11547 #define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK)
11548 #define F_PCS10G_RESET_XFI_RXCLK    V_PCS10G_RESET_XFI_RXCLK(1U)
11549 
11550 #define S_PCS10G_RESET_XFI_TXCLK    25
11551 #define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK)
11552 #define F_PCS10G_RESET_XFI_TXCLK    V_PCS10G_RESET_XFI_TXCLK(1U)
11553 
11554 #define S_PCS10G_RESET_SD_TX_CLK    24
11555 #define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK)
11556 #define F_PCS10G_RESET_SD_TX_CLK    V_PCS10G_RESET_SD_TX_CLK(1U)
11557 
11558 #define S_PCS10G_RESET_SD_RX_CLK    23
11559 #define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK)
11560 #define F_PCS10G_RESET_SD_RX_CLK    V_PCS10G_RESET_SD_RX_CLK(1U)
11561 
11562 #define S_PCS40G_RESET_RXCLK    22
11563 #define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK)
11564 #define F_PCS40G_RESET_RXCLK    V_PCS40G_RESET_RXCLK(1U)
11565 
11566 #define S_PCS40G_RESET_SD_TX_CLK    21
11567 #define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK)
11568 #define F_PCS40G_RESET_SD_TX_CLK    V_PCS40G_RESET_SD_TX_CLK(1U)
11569 
11570 #define S_PCS40G_RESET_SD0_RX_CLK    20
11571 #define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK)
11572 #define F_PCS40G_RESET_SD0_RX_CLK    V_PCS40G_RESET_SD0_RX_CLK(1U)
11573 
11574 #define S_PCS40G_RESET_SD1_RX_CLK    19
11575 #define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK)
11576 #define F_PCS40G_RESET_SD1_RX_CLK    V_PCS40G_RESET_SD1_RX_CLK(1U)
11577 
11578 #define S_PCS40G_RESET_SD2_RX_CLK    18
11579 #define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK)
11580 #define F_PCS40G_RESET_SD2_RX_CLK    V_PCS40G_RESET_SD2_RX_CLK(1U)
11581 
11582 #define S_PCS40G_RESET_SD3_RX_CLK    17
11583 #define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK)
11584 #define F_PCS40G_RESET_SD3_RX_CLK    V_PCS40G_RESET_SD3_RX_CLK(1U)
11585 
11586 #define S_PCS100G_RESET_CGMII_RXCLK    16
11587 #define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK)
11588 #define F_PCS100G_RESET_CGMII_RXCLK    V_PCS100G_RESET_CGMII_RXCLK(1U)
11589 
11590 #define S_PCS100G_RESET_CGMII_TXCLK    15
11591 #define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK)
11592 #define F_PCS100G_RESET_CGMII_TXCLK    V_PCS100G_RESET_CGMII_TXCLK(1U)
11593 
11594 #define S_PCS100G_RESET_TX_CLK    14
11595 #define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK)
11596 #define F_PCS100G_RESET_TX_CLK    V_PCS100G_RESET_TX_CLK(1U)
11597 
11598 #define S_PCS100G_RESET_SD0_RX_CLK    13
11599 #define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK)
11600 #define F_PCS100G_RESET_SD0_RX_CLK    V_PCS100G_RESET_SD0_RX_CLK(1U)
11601 
11602 #define S_PCS100G_RESET_SD1_RX_CLK    12
11603 #define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK)
11604 #define F_PCS100G_RESET_SD1_RX_CLK    V_PCS100G_RESET_SD1_RX_CLK(1U)
11605 
11606 #define S_PCS100G_RESET_SD2_RX_CLK    11
11607 #define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK)
11608 #define F_PCS100G_RESET_SD2_RX_CLK    V_PCS100G_RESET_SD2_RX_CLK(1U)
11609 
11610 #define S_PCS100G_RESET_SD3_RX_CLK    10
11611 #define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK)
11612 #define F_PCS100G_RESET_SD3_RX_CLK    V_PCS100G_RESET_SD3_RX_CLK(1U)
11613 
11614 #define S_MAC40G100G_RESET_TXCLK    9
11615 #define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK)
11616 #define F_MAC40G100G_RESET_TXCLK    V_MAC40G100G_RESET_TXCLK(1U)
11617 
11618 #define S_MAC40G100G_RESET_RXCLK    8
11619 #define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK)
11620 #define F_MAC40G100G_RESET_RXCLK    V_MAC40G100G_RESET_RXCLK(1U)
11621 
11622 #define S_MAC40G100G_RESET_FF_TX_CLK    7
11623 #define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK)
11624 #define F_MAC40G100G_RESET_FF_TX_CLK    V_MAC40G100G_RESET_FF_TX_CLK(1U)
11625 
11626 #define S_MAC40G100G_RESET_FF_RX_CLK    6
11627 #define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK)
11628 #define F_MAC40G100G_RESET_FF_RX_CLK    V_MAC40G100G_RESET_FF_RX_CLK(1U)
11629 
11630 #define S_MAC40G100G_RESET_TS_CLK    5
11631 #define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK)
11632 #define F_MAC40G100G_RESET_TS_CLK    V_MAC40G100G_RESET_TS_CLK(1U)
11633 
11634 #define S_MAC1G10G_RESET_RXCLK    4
11635 #define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK)
11636 #define F_MAC1G10G_RESET_RXCLK    V_MAC1G10G_RESET_RXCLK(1U)
11637 
11638 #define S_MAC1G10G_RESET_TXCLK    3
11639 #define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK)
11640 #define F_MAC1G10G_RESET_TXCLK    V_MAC1G10G_RESET_TXCLK(1U)
11641 
11642 #define S_MAC1G10G_RESET_FF_RX_CLK    2
11643 #define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK)
11644 #define F_MAC1G10G_RESET_FF_RX_CLK    V_MAC1G10G_RESET_FF_RX_CLK(1U)
11645 
11646 #define S_MAC1G10G_RESET_FF_TX_CLK    1
11647 #define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK)
11648 #define F_MAC1G10G_RESET_FF_TX_CLK    V_MAC1G10G_RESET_FF_TX_CLK(1U)
11649 
11650 #define S_XGMII_CLK_RESET    0
11651 #define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET)
11652 #define F_XGMII_CLK_RESET    V_XGMII_CLK_RESET(1U)
11653 
11654 #define A_MAC_PORT_MTIP_GATE_CTRL 0x830
11655 
11656 #define S_AN_GATE_SD_TX_CLK    31
11657 #define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK)
11658 #define F_AN_GATE_SD_TX_CLK    V_AN_GATE_SD_TX_CLK(1U)
11659 
11660 #define S_AN_GATE_SD_RX_CLK    30
11661 #define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK)
11662 #define F_AN_GATE_SD_RX_CLK    V_AN_GATE_SD_RX_CLK(1U)
11663 
11664 #define S_SGMII_GATE_TX_CLK    29
11665 #define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK)
11666 #define F_SGMII_GATE_TX_CLK    V_SGMII_GATE_TX_CLK(1U)
11667 
11668 #define S_SGMII_GATE_RX_CLK    28
11669 #define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK)
11670 #define F_SGMII_GATE_RX_CLK    V_SGMII_GATE_RX_CLK(1U)
11671 
11672 #define S_SGMII_GATE_REF_CLK    27
11673 #define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK)
11674 #define F_SGMII_GATE_REF_CLK    V_SGMII_GATE_REF_CLK(1U)
11675 
11676 #define S_PCS10G_GATE_XFI_RXCLK    26
11677 #define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK)
11678 #define F_PCS10G_GATE_XFI_RXCLK    V_PCS10G_GATE_XFI_RXCLK(1U)
11679 
11680 #define S_PCS10G_GATE_XFI_TXCLK    25
11681 #define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK)
11682 #define F_PCS10G_GATE_XFI_TXCLK    V_PCS10G_GATE_XFI_TXCLK(1U)
11683 
11684 #define S_PCS10G_GATE_SD_TX_CLK    24
11685 #define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK)
11686 #define F_PCS10G_GATE_SD_TX_CLK    V_PCS10G_GATE_SD_TX_CLK(1U)
11687 
11688 #define S_PCS10G_GATE_SD_RX_CLK    23
11689 #define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK)
11690 #define F_PCS10G_GATE_SD_RX_CLK    V_PCS10G_GATE_SD_RX_CLK(1U)
11691 
11692 #define S_PCS40G_GATE_RXCLK    22
11693 #define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK)
11694 #define F_PCS40G_GATE_RXCLK    V_PCS40G_GATE_RXCLK(1U)
11695 
11696 #define S_PCS40G_GATE_SD_TX_CLK    21
11697 #define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK)
11698 #define F_PCS40G_GATE_SD_TX_CLK    V_PCS40G_GATE_SD_TX_CLK(1U)
11699 
11700 #define S_PCS40G_GATE_SD_RX_CLK    20
11701 #define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK)
11702 #define F_PCS40G_GATE_SD_RX_CLK    V_PCS40G_GATE_SD_RX_CLK(1U)
11703 
11704 #define S_PCS100G_GATE_CGMII_RXCLK    19
11705 #define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK)
11706 #define F_PCS100G_GATE_CGMII_RXCLK    V_PCS100G_GATE_CGMII_RXCLK(1U)
11707 
11708 #define S_PCS100G_GATE_CGMII_TXCLK    18
11709 #define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK)
11710 #define F_PCS100G_GATE_CGMII_TXCLK    V_PCS100G_GATE_CGMII_TXCLK(1U)
11711 
11712 #define S_PCS100G_GATE_TX_CLK    17
11713 #define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK)
11714 #define F_PCS100G_GATE_TX_CLK    V_PCS100G_GATE_TX_CLK(1U)
11715 
11716 #define S_PCS100G_GATE_SD_RX_CLK    16
11717 #define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK)
11718 #define F_PCS100G_GATE_SD_RX_CLK    V_PCS100G_GATE_SD_RX_CLK(1U)
11719 
11720 #define S_MAC40G100G_GATE_TXCLK    15
11721 #define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK)
11722 #define F_MAC40G100G_GATE_TXCLK    V_MAC40G100G_GATE_TXCLK(1U)
11723 
11724 #define S_MAC40G100G_GATE_RXCLK    14
11725 #define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK)
11726 #define F_MAC40G100G_GATE_RXCLK    V_MAC40G100G_GATE_RXCLK(1U)
11727 
11728 #define S_MAC40G100G_GATE_FF_TX_CLK    13
11729 #define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK)
11730 #define F_MAC40G100G_GATE_FF_TX_CLK    V_MAC40G100G_GATE_FF_TX_CLK(1U)
11731 
11732 #define S_MAC40G100G_GATE_FF_RX_CLK    12
11733 #define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK)
11734 #define F_MAC40G100G_GATE_FF_RX_CLK    V_MAC40G100G_GATE_FF_RX_CLK(1U)
11735 
11736 #define S_MAC40G100G_TS_CLK    11
11737 #define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK)
11738 #define F_MAC40G100G_TS_CLK    V_MAC40G100G_TS_CLK(1U)
11739 
11740 #define S_MAC1G10G_GATE_RXCLK    10
11741 #define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK)
11742 #define F_MAC1G10G_GATE_RXCLK    V_MAC1G10G_GATE_RXCLK(1U)
11743 
11744 #define S_MAC1G10G_GATE_TXCLK    9
11745 #define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK)
11746 #define F_MAC1G10G_GATE_TXCLK    V_MAC1G10G_GATE_TXCLK(1U)
11747 
11748 #define S_MAC1G10G_GATE_FF_RX_CLK    8
11749 #define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK)
11750 #define F_MAC1G10G_GATE_FF_RX_CLK    V_MAC1G10G_GATE_FF_RX_CLK(1U)
11751 
11752 #define S_MAC1G10G_GATE_FF_TX_CLK    7
11753 #define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK)
11754 #define F_MAC1G10G_GATE_FF_TX_CLK    V_MAC1G10G_GATE_FF_TX_CLK(1U)
11755 
11756 #define S_AEC_RX    6
11757 #define V_AEC_RX(x) ((x) << S_AEC_RX)
11758 #define F_AEC_RX    V_AEC_RX(1U)
11759 
11760 #define S_AEC_TX    5
11761 #define V_AEC_TX(x) ((x) << S_AEC_TX)
11762 #define F_AEC_TX    V_AEC_TX(1U)
11763 
11764 #define S_PCS100G_CLK_ENABLE    4
11765 #define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE)
11766 #define F_PCS100G_CLK_ENABLE    V_PCS100G_CLK_ENABLE(1U)
11767 
11768 #define S_PCS40G_CLK_ENABLE    3
11769 #define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE)
11770 #define F_PCS40G_CLK_ENABLE    V_PCS40G_CLK_ENABLE(1U)
11771 
11772 #define S_PCS10G_CLK_ENABLE    2
11773 #define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE)
11774 #define F_PCS10G_CLK_ENABLE    V_PCS10G_CLK_ENABLE(1U)
11775 
11776 #define S_PCS1G_CLK_ENABLE    1
11777 #define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE)
11778 #define F_PCS1G_CLK_ENABLE    V_PCS1G_CLK_ENABLE(1U)
11779 
11780 #define S_AN_CLK_ENABLE    0
11781 #define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE)
11782 #define F_AN_CLK_ENABLE    V_AN_CLK_ENABLE(1U)
11783 
11784 #define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888
11785 
11786 #define S_PERR_RX_FEC100G_DLY    29
11787 #define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY)
11788 #define F_PERR_RX_FEC100G_DLY    V_PERR_RX_FEC100G_DLY(1U)
11789 
11790 #define S_PERR_RX_FEC100G    28
11791 #define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G)
11792 #define F_PERR_RX_FEC100G    V_PERR_RX_FEC100G(1U)
11793 
11794 #define S_PERR_RX3_FEC100G_DK    27
11795 #define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK)
11796 #define F_PERR_RX3_FEC100G_DK    V_PERR_RX3_FEC100G_DK(1U)
11797 
11798 #define S_PERR_RX2_FEC100G_DK    26
11799 #define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK)
11800 #define F_PERR_RX2_FEC100G_DK    V_PERR_RX2_FEC100G_DK(1U)
11801 
11802 #define S_PERR_RX1_FEC100G_DK    25
11803 #define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK)
11804 #define F_PERR_RX1_FEC100G_DK    V_PERR_RX1_FEC100G_DK(1U)
11805 
11806 #define S_PERR_RX0_FEC100G_DK    24
11807 #define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK)
11808 #define F_PERR_RX0_FEC100G_DK    V_PERR_RX0_FEC100G_DK(1U)
11809 
11810 #define S_PERR_TX3_PCS100G    23
11811 #define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G)
11812 #define F_PERR_TX3_PCS100G    V_PERR_TX3_PCS100G(1U)
11813 
11814 #define S_PERR_TX2_PCS100G    22
11815 #define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G)
11816 #define F_PERR_TX2_PCS100G    V_PERR_TX2_PCS100G(1U)
11817 
11818 #define S_PERR_TX1_PCS100G    21
11819 #define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G)
11820 #define F_PERR_TX1_PCS100G    V_PERR_TX1_PCS100G(1U)
11821 
11822 #define S_PERR_TX0_PCS100G    20
11823 #define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G)
11824 #define F_PERR_TX0_PCS100G    V_PERR_TX0_PCS100G(1U)
11825 
11826 #define S_PERR_RX19_PCS100G    19
11827 #define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G)
11828 #define F_PERR_RX19_PCS100G    V_PERR_RX19_PCS100G(1U)
11829 
11830 #define S_PERR_RX18_PCS100G    18
11831 #define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G)
11832 #define F_PERR_RX18_PCS100G    V_PERR_RX18_PCS100G(1U)
11833 
11834 #define S_PERR_RX17_PCS100G    17
11835 #define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G)
11836 #define F_PERR_RX17_PCS100G    V_PERR_RX17_PCS100G(1U)
11837 
11838 #define S_PERR_RX16_PCS100G    16
11839 #define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G)
11840 #define F_PERR_RX16_PCS100G    V_PERR_RX16_PCS100G(1U)
11841 
11842 #define S_PERR_RX15_PCS100G    15
11843 #define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G)
11844 #define F_PERR_RX15_PCS100G    V_PERR_RX15_PCS100G(1U)
11845 
11846 #define S_PERR_RX14_PCS100G    14
11847 #define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G)
11848 #define F_PERR_RX14_PCS100G    V_PERR_RX14_PCS100G(1U)
11849 
11850 #define S_PERR_RX13_PCS100G    13
11851 #define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G)
11852 #define F_PERR_RX13_PCS100G    V_PERR_RX13_PCS100G(1U)
11853 
11854 #define S_PERR_RX12_PCS100G    12
11855 #define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G)
11856 #define F_PERR_RX12_PCS100G    V_PERR_RX12_PCS100G(1U)
11857 
11858 #define S_PERR_RX11_PCS100G    11
11859 #define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G)
11860 #define F_PERR_RX11_PCS100G    V_PERR_RX11_PCS100G(1U)
11861 
11862 #define S_PERR_RX10_PCS100G    10
11863 #define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G)
11864 #define F_PERR_RX10_PCS100G    V_PERR_RX10_PCS100G(1U)
11865 
11866 #define S_PERR_RX9_PCS100G    9
11867 #define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G)
11868 #define F_PERR_RX9_PCS100G    V_PERR_RX9_PCS100G(1U)
11869 
11870 #define S_PERR_RX8_PCS100G    8
11871 #define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G)
11872 #define F_PERR_RX8_PCS100G    V_PERR_RX8_PCS100G(1U)
11873 
11874 #define S_PERR_RX7_PCS100G    7
11875 #define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G)
11876 #define F_PERR_RX7_PCS100G    V_PERR_RX7_PCS100G(1U)
11877 
11878 #define S_PERR_RX6_PCS100G    6
11879 #define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G)
11880 #define F_PERR_RX6_PCS100G    V_PERR_RX6_PCS100G(1U)
11881 
11882 #define S_PERR_RX5_PCS100G    5
11883 #define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G)
11884 #define F_PERR_RX5_PCS100G    V_PERR_RX5_PCS100G(1U)
11885 
11886 #define S_PERR_RX4_PCS100G    4
11887 #define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G)
11888 #define F_PERR_RX4_PCS100G    V_PERR_RX4_PCS100G(1U)
11889 
11890 #define S_PERR_RX3_PCS100G    3
11891 #define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G)
11892 #define F_PERR_RX3_PCS100G    V_PERR_RX3_PCS100G(1U)
11893 
11894 #define S_PERR_RX2_PCS100G    2
11895 #define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G)
11896 #define F_PERR_RX2_PCS100G    V_PERR_RX2_PCS100G(1U)
11897 
11898 #define S_PERR_RX1_PCS100G    1
11899 #define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G)
11900 #define F_PERR_RX1_PCS100G    V_PERR_RX1_PCS100G(1U)
11901 
11902 #define S_PERR_RX0_PCS100G    0
11903 #define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G)
11904 #define F_PERR_RX0_PCS100G    V_PERR_RX0_PCS100G(1U)
11905 
11906 #define A_MAC_PORT_INT_CAUSE 0x8dc
11907 
11908 #define S_TX_TS_AVAIL    29
11909 #define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
11910 #define F_TX_TS_AVAIL    V_TX_TS_AVAIL(1U)
11911 
11912 #define S_AN_PAGE_RCVD    2
11913 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
11914 #define F_AN_PAGE_RCVD    V_AN_PAGE_RCVD(1U)
11915 
11916 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
11917 
11918 #define S_PERR_PKT_RAM    24
11919 #define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
11920 #define F_PERR_PKT_RAM    V_PERR_PKT_RAM(1U)
11921 
11922 #define S_PERR_MASK_RAM    23
11923 #define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
11924 #define F_PERR_MASK_RAM    V_PERR_MASK_RAM(1U)
11925 
11926 #define S_PERR_CRC_RAM    22
11927 #define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
11928 #define F_PERR_CRC_RAM    V_PERR_CRC_RAM(1U)
11929 
11930 #define S_RX_DFF_SEG0    21
11931 #define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
11932 #define F_RX_DFF_SEG0    V_RX_DFF_SEG0(1U)
11933 
11934 #define S_RX_SFF_SEG0    20
11935 #define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
11936 #define F_RX_SFF_SEG0    V_RX_SFF_SEG0(1U)
11937 
11938 #define S_RX_DFF_MAC10    19
11939 #define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
11940 #define F_RX_DFF_MAC10    V_RX_DFF_MAC10(1U)
11941 
11942 #define S_RX_SFF_MAC10    18
11943 #define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
11944 #define F_RX_SFF_MAC10    V_RX_SFF_MAC10(1U)
11945 
11946 #define S_TX_DFF_SEG0    17
11947 #define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
11948 #define F_TX_DFF_SEG0    V_TX_DFF_SEG0(1U)
11949 
11950 #define S_TX_SFF_SEG0    16
11951 #define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
11952 #define F_TX_SFF_SEG0    V_TX_SFF_SEG0(1U)
11953 
11954 #define S_TX_DFF_MAC10    15
11955 #define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
11956 #define F_TX_DFF_MAC10    V_TX_DFF_MAC10(1U)
11957 
11958 #define S_TX_SFF_MAC10    14
11959 #define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
11960 #define F_TX_SFF_MAC10    V_TX_SFF_MAC10(1U)
11961 
11962 #define S_RX_STATS    13
11963 #define V_RX_STATS(x) ((x) << S_RX_STATS)
11964 #define F_RX_STATS    V_RX_STATS(1U)
11965 
11966 #define S_TX_STATS    12
11967 #define V_TX_STATS(x) ((x) << S_TX_STATS)
11968 #define F_TX_STATS    V_TX_STATS(1U)
11969 
11970 #define S_PERR3_RX_MIX    11
11971 #define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
11972 #define F_PERR3_RX_MIX    V_PERR3_RX_MIX(1U)
11973 
11974 #define S_PERR3_RX_SD    10
11975 #define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
11976 #define F_PERR3_RX_SD    V_PERR3_RX_SD(1U)
11977 
11978 #define S_PERR3_TX    9
11979 #define V_PERR3_TX(x) ((x) << S_PERR3_TX)
11980 #define F_PERR3_TX    V_PERR3_TX(1U)
11981 
11982 #define S_PERR2_RX_MIX    8
11983 #define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
11984 #define F_PERR2_RX_MIX    V_PERR2_RX_MIX(1U)
11985 
11986 #define S_PERR2_RX_SD    7
11987 #define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
11988 #define F_PERR2_RX_SD    V_PERR2_RX_SD(1U)
11989 
11990 #define S_PERR2_TX    6
11991 #define V_PERR2_TX(x) ((x) << S_PERR2_TX)
11992 #define F_PERR2_TX    V_PERR2_TX(1U)
11993 
11994 #define S_PERR1_RX_MIX    5
11995 #define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
11996 #define F_PERR1_RX_MIX    V_PERR1_RX_MIX(1U)
11997 
11998 #define S_PERR1_RX_SD    4
11999 #define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
12000 #define F_PERR1_RX_SD    V_PERR1_RX_SD(1U)
12001 
12002 #define S_PERR1_TX    3
12003 #define V_PERR1_TX(x) ((x) << S_PERR1_TX)
12004 #define F_PERR1_TX    V_PERR1_TX(1U)
12005 
12006 #define S_PERR0_RX_MIX    2
12007 #define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
12008 #define F_PERR0_RX_MIX    V_PERR0_RX_MIX(1U)
12009 
12010 #define S_PERR0_RX_SD    1
12011 #define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
12012 #define F_PERR0_RX_SD    V_PERR0_RX_SD(1U)
12013 
12014 #define S_PERR0_TX    0
12015 #define V_PERR0_TX(x) ((x) << S_PERR0_TX)
12016 #define F_PERR0_TX    V_PERR0_TX(1U)
12017 
12018 #define S_T6_PERR_PKT_RAM    31
12019 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
12020 #define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
12021 
12022 #define S_T6_PERR_MASK_RAM    30
12023 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
12024 #define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
12025 
12026 #define S_T6_PERR_CRC_RAM    29
12027 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
12028 #define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
12029 
12030 #define S_RX_MAC40G    28
12031 #define V_RX_MAC40G(x) ((x) << S_RX_MAC40G)
12032 #define F_RX_MAC40G    V_RX_MAC40G(1U)
12033 
12034 #define S_TX_MAC40G    27
12035 #define V_TX_MAC40G(x) ((x) << S_TX_MAC40G)
12036 #define F_TX_MAC40G    V_TX_MAC40G(1U)
12037 
12038 #define S_RX_ST_MAC40G    26
12039 #define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G)
12040 #define F_RX_ST_MAC40G    V_RX_ST_MAC40G(1U)
12041 
12042 #define S_TX_ST_MAC40G    25
12043 #define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G)
12044 #define F_TX_ST_MAC40G    V_TX_ST_MAC40G(1U)
12045 
12046 #define S_TX_MAC1G10G    24
12047 #define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G)
12048 #define F_TX_MAC1G10G    V_TX_MAC1G10G(1U)
12049 
12050 #define S_RX_MAC1G10G    23
12051 #define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G)
12052 #define F_RX_MAC1G10G    V_RX_MAC1G10G(1U)
12053 
12054 #define S_RX_STATUS_MAC1G10G    22
12055 #define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G)
12056 #define F_RX_STATUS_MAC1G10G    V_RX_STATUS_MAC1G10G(1U)
12057 
12058 #define S_RX_ST_MAC1G10G    21
12059 #define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G)
12060 #define F_RX_ST_MAC1G10G    V_RX_ST_MAC1G10G(1U)
12061 
12062 #define S_TX_ST_MAC1G10G    20
12063 #define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G)
12064 #define F_TX_ST_MAC1G10G    V_TX_ST_MAC1G10G(1U)
12065 
12066 #define S_PERR_TX0_PCS40G    19
12067 #define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G)
12068 #define F_PERR_TX0_PCS40G    V_PERR_TX0_PCS40G(1U)
12069 
12070 #define S_PERR_TX1_PCS40G    18
12071 #define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G)
12072 #define F_PERR_TX1_PCS40G    V_PERR_TX1_PCS40G(1U)
12073 
12074 #define S_PERR_TX2_PCS40G    17
12075 #define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G)
12076 #define F_PERR_TX2_PCS40G    V_PERR_TX2_PCS40G(1U)
12077 
12078 #define S_PERR_TX3_PCS40G    16
12079 #define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G)
12080 #define F_PERR_TX3_PCS40G    V_PERR_TX3_PCS40G(1U)
12081 
12082 #define S_PERR_TX0_FEC40G    15
12083 #define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G)
12084 #define F_PERR_TX0_FEC40G    V_PERR_TX0_FEC40G(1U)
12085 
12086 #define S_PERR_TX1_FEC40G    14
12087 #define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G)
12088 #define F_PERR_TX1_FEC40G    V_PERR_TX1_FEC40G(1U)
12089 
12090 #define S_PERR_TX2_FEC40G    13
12091 #define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G)
12092 #define F_PERR_TX2_FEC40G    V_PERR_TX2_FEC40G(1U)
12093 
12094 #define S_PERR_TX3_FEC40G    12
12095 #define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G)
12096 #define F_PERR_TX3_FEC40G    V_PERR_TX3_FEC40G(1U)
12097 
12098 #define S_PERR_RX0_PCS40G    11
12099 #define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G)
12100 #define F_PERR_RX0_PCS40G    V_PERR_RX0_PCS40G(1U)
12101 
12102 #define S_PERR_RX1_PCS40G    10
12103 #define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G)
12104 #define F_PERR_RX1_PCS40G    V_PERR_RX1_PCS40G(1U)
12105 
12106 #define S_PERR_RX2_PCS40G    9
12107 #define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G)
12108 #define F_PERR_RX2_PCS40G    V_PERR_RX2_PCS40G(1U)
12109 
12110 #define S_PERR_RX3_PCS40G    8
12111 #define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G)
12112 #define F_PERR_RX3_PCS40G    V_PERR_RX3_PCS40G(1U)
12113 
12114 #define S_PERR_RX0_FEC40G    7
12115 #define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G)
12116 #define F_PERR_RX0_FEC40G    V_PERR_RX0_FEC40G(1U)
12117 
12118 #define S_PERR_RX1_FEC40G    6
12119 #define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G)
12120 #define F_PERR_RX1_FEC40G    V_PERR_RX1_FEC40G(1U)
12121 
12122 #define S_PERR_RX2_FEC40G    5
12123 #define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G)
12124 #define F_PERR_RX2_FEC40G    V_PERR_RX2_FEC40G(1U)
12125 
12126 #define S_PERR_RX3_FEC40G    4
12127 #define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G)
12128 #define F_PERR_RX3_FEC40G    V_PERR_RX3_FEC40G(1U)
12129 
12130 #define S_PERR_RX_PCS10G_LPBK    3
12131 #define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK)
12132 #define F_PERR_RX_PCS10G_LPBK    V_PERR_RX_PCS10G_LPBK(1U)
12133 
12134 #define S_PERR_RX_PCS10G    2
12135 #define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G)
12136 #define F_PERR_RX_PCS10G    V_PERR_RX_PCS10G(1U)
12137 
12138 #define S_PERR_RX_PCS1G    1
12139 #define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G)
12140 #define F_PERR_RX_PCS1G    V_PERR_RX_PCS1G(1U)
12141 
12142 #define S_PERR_TX_PCS1G    0
12143 #define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G)
12144 #define F_PERR_TX_PCS1G    V_PERR_TX_PCS1G(1U)
12145 
12146 #define A_MAC_PORT_TX_TS_VAL_LO 0x928
12147 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c
12148 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
12149 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
12150 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
12151 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
12152 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
12153 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
12154 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
12155 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28
12156 
12157 /* registers for module MC_0 */
12158 #define MC_0_BASE_ADDR 0x40000
12159 
12160 #define A_MC_P_PAR_CAUSE 0x41310
12161 #define A_MC_P_INT_CAUSE 0x41318
12162 #define A_MC_P_ECC_STATUS 0x4131c
12163 #define A_MC_P_BIST_CMD 0x41400
12164 
12165 #define S_BURST_LEN    16
12166 #define M_BURST_LEN    0x3U
12167 #define V_BURST_LEN(x) ((x) << S_BURST_LEN)
12168 #define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)
12169 
12170 #define A_MC_P_BIST_CMD_ADDR 0x41404
12171 #define A_MC_P_BIST_CMD_LEN 0x41408
12172 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
12173 #define A_MC_P_BIST_STATUS_RDATA 0x41488
12174 #define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
12175 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
12176 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
12177 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
12178 #define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828
12179 
12180 /* registers for module MC_1 */
12181 #define MC_1_BASE_ADDR 0x48000
12182 
12183 /* registers for module EDC_T50 */
12184 #define EDC_T50_BASE_ADDR 0x50000
12185 
12186 #define A_EDC_H_BIST_CMD 0x50004
12187 #define A_EDC_H_BIST_CMD_ADDR 0x50008
12188 #define A_EDC_H_BIST_CMD_LEN 0x5000c
12189 #define A_EDC_H_BIST_DATA_PATTERN 0x50010
12190 #define A_EDC_H_BIST_STATUS_RDATA 0x50028
12191 #define A_EDC_H_INT_CAUSE 0x50078
12192 
12193 #define S_ECC_UE_INT0_CAUSE    5
12194 #define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE)
12195 #define F_ECC_UE_INT0_CAUSE    V_ECC_UE_INT0_CAUSE(1U)
12196 
12197 #define S_ECC_CE_INT0_CAUSE    4
12198 #define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE)
12199 #define F_ECC_CE_INT0_CAUSE    V_ECC_CE_INT0_CAUSE(1U)
12200 
12201 #define S_PERR_INT0_CAUSE    3
12202 #define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE)
12203 #define F_PERR_INT0_CAUSE    V_PERR_INT0_CAUSE(1U)
12204 
12205 #define A_EDC_H_ECC_STATUS 0x5007c
12206 #define A_EDC_H_ECC_ERR_ADDR 0x50084
12207 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
12208 
12209 /* registers for module EDC_T51 */
12210 #define EDC_T51_BASE_ADDR 0x50800
12211 
12212 /* registers for module HMA_T5 */
12213 #define HMA_T5_BASE_ADDR 0x51000
12214 
12215 
12216 /* registers for module EDC_T60 */
12217 #define EDC_T60_BASE_ADDR 0x50000
12218 
12219 #define S_ECC_ADDR    0
12220 #define M_ECC_ADDR    0x7fffffU
12221 #define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
12222 #define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)
12223 
12224 
12225 /* registers for module EDC_T61 */
12226 #define EDC_T61_BASE_ADDR 0x50800
12227 
12228 /* registers for module HMA_T6 */
12229 #define HMA_T6_BASE_ADDR 0x51000
12230 
12231 #define A_HMA_LOCAL_DEBUG_CFG 0x51320
12232