xref: /illumos-gate/usr/src/uts/sun4u/sys/machasi.h (revision e98fafb9)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_MACHASI_H
27 #define	_SYS_MACHASI_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * Spitfire ancillary state registers, for asrset_t
37  */
38 #define	ASR_GSR	(3)
39 
40 /*
41  * alternate address space identifiers
42  *
43  * 0x00 - 0x7F are privileged
44  * 0x80 - 0xFF can be used by users
45  */
46 
47 
48 /*
49  * UltraSPARC ASIs
50  */
51 #define	ASI_NQUAD_LD		0x24	/* 128-bit atomic load */
52 #define	ASI_NQUAD_LD_L		0x2c	/* 128-bit atomic load little */
53 
54 #define	ASI_QUAD_LDD_PHYS	0x34	/* 128-bit physical atomic load */
55 #define	ASI_QUAD_LDD_PHYS_L	0x3C	/* 128-bit phys. atomic load little */
56 
57 #define	ASI_INTR_DISPATCH_STATUS 0x48	/* interrupt vector dispatch status */
58 #define	ASI_INTR_RECEIVE_STATUS	0x49	/* interrupt vector receive status */
59 
60 #define	ASI_SCRATCHPAD		0x4F	/* Scratchpad registers ASI */
61 
62 #define	ASI_BLK_AIUP		0x70	/* block as if user primary */
63 #define	ASI_BLK_AIUS		0x71	/* block as if user secondary */
64 
65 #define	ASI_SDB_INTR_W		0x77	/* interrupt vector dispatch */
66 #define	ASI_SDB_INTR_R		0x7F	/* incoming interrupt vector */
67 #define	ASI_INTR_DISPATCH	ASI_SDB_INTR_W
68 #define	ASI_INTR_RECEIVE	ASI_SDB_INTR_R
69 
70 #define	ASI_BLK_AIUPL		0x78	/* block as if user primary little */
71 #define	ASI_BLK_AIUSL		0x79	/* block as if user secondary little */
72 
73 /*
74  * Spitfire asis
75  */
76 #define	ASI_LSU			0x45	/* load-store unit control */
77 #define	ASI_DC_INVAL		0x42	/* d$ invalidate */
78 
79 
80 #define	ASI_DC_DATA		0x46	/* d$ data */
81 #define	ASI_DC_TAG		0x47	/* d$ tag */
82 
83 #define	ASI_UPA_CONFIG		0x4A	/* upa configuration reg */
84 
85 #define	ASI_ESTATE_ERR		0x4B	/* estate error enable reg */
86 
87 #define	ASI_AFSR		0x4C	/* asynchronous fault status */
88 #define	ASI_AFAR		0x4D	/* asynchronous fault address */
89 
90 #define	ASI_IMMU		0x50	/* instruction mmu */
91 #define	ASI_IMMU_TSB_8K		0x51	/* immu tsb 8k ptr */
92 #define	ASI_IMMU_TSB_64K	0x52	/* immu tsb 64k ptr */
93 #define	ASI_DEVICE_SERIAL_ID	0x53	/* device serial id */
94 #define	ASI_ITLB_IN		0x54	/* immu tlb data in */
95 #define	ASI_ITLB_ACCESS		0x55	/* immu tlb data access */
96 #define	ASI_ITLB_TAGREAD	0x56	/* immu tlb tag read */
97 #define	ASI_ITLB_DEMAP		0x57	/* immu tlb demap */
98 
99 #define	ASI_DMMU		0x58	/* data mmu */
100 #define	ASI_MMU_CTX		ASI_DMMU
101 #define	ASI_DMMU_TSB_8K		0x59	/* dmmu tsb 8k ptr */
102 #define	ASI_DMMU_TSB_64K	0x5A	/* dmmu tsb 64k ptr */
103 #define	ASI_DMMU_TSB_DIRECT	0x5B	/* dmmu tsb direct ptr */
104 #define	ASI_DTLB_IN		0x5C	/* dmmu tlb data in */
105 #define	ASI_DTLB_ACCESS		0x5D	/* dmmu tlb data access */
106 #define	ASI_DTLB_TAGREAD	0x5E	/* dmmu tlb tag read */
107 #define	ASI_DTLB_DEMAP		0x5F	/* dmmu tlb demap */
108 #define	ASI_ITSB_PREFETCH	0x61	/* IMMU tsb prefetch */
109 #define	ASI_DTSB_PREFETCH	0x62	/* DMMU tsb prefetch */
110 
111 #define	ASI_IC_DATA		0x66	/* i$ data */
112 #define	ASI_IC_TAG		0x67	/* i$ tag */
113 #define	ASI_IC_DECODE		0x6E	/* i$ pre-decode */
114 #define	ASI_IC_NEXT		0x6F	/* i$ next field */
115 
116 #define	ASI_EC_W		0x76	/* e$ access write */
117 #define	ASI_EC_R		0x7E	/* e$ access read */
118 #define	ASI_EC_DIAG		0x4E	/* e$ diagnostic reg */
119 					/* PRM calls this ASI_ECACHE_TAG */
120 
121 #ifdef	__cplusplus
122 }
123 #endif
124 
125 #endif	/* _SYS_MACHASI_H */
126