Lines Matching refs:cpu_id
45 uint32_t cpu_id);
114 px_ib_intr_enable(px_t *px_p, cpuid_t cpu_id, devino_t ino) in px_ib_intr_enable() argument
125 "px_ib_intr_enable: ino=%x cpu_id=%x\n", ino, cpu_id); in px_ib_intr_enable()
136 PX_INTR_ENABLE(px_p->px_dip, sysino, cpu_id); in px_ib_intr_enable()
208 px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino, in px_ib_intr_dist_en() argument
238 if (cpu_id == old_cpu_id) in px_ib_intr_dist_en()
247 sysino, ino, old_cpu_id, cpu_id); in px_ib_intr_dist_en()
253 PX_INTR_ENABLE(dip, sysino, cpu_id); in px_ib_intr_dist_en()
257 px_ib_cpu_ticks_to_ih_nsec(px_ib_t *ib_p, px_ih_t *ih_p, uint32_t cpu_id) in px_ib_cpu_ticks_to_ih_nsec() argument
277 ih_p->ih_nsec += (uint64_t)tick2ns(ticks, cpu_id); in px_ib_cpu_ticks_to_ih_nsec()
354 orig_cpuid = CPU->cpu_id; in px_ib_intr_redist()
870 px_ib_set_intr_target(px_t *px_p, devino_t ino, cpuid_t cpu_id) in px_ib_set_intr_target() argument
880 "cpu_id %x\n", ino, cpu_id); in px_ib_set_intr_target()
898 if ((cpu_id < _ncpu) && (cpu[cpu_id] && cpu_is_online(cpu[cpu_id]))) { in px_ib_set_intr_target()
900 cpu_id); in px_ib_set_intr_target()
901 px_ib_intr_dist_en(dip, cpu_id, ino, B_TRUE); in px_ib_set_intr_target()
902 px_ib_log_new_cpu(px_p->px_ib_p, old_cpu_id, cpu_id, ino); in px_ib_set_intr_target()
905 cpu_id); in px_ib_set_intr_target()
922 msinum_t msi_num, cpuid_t cpu_id) in px_ib_set_msix_target() argument
941 msi_num, cpu_id); in px_ib_set_msix_target()
975 if (cpu_id == old_cpu_id) { in px_ib_set_msix_target()
984 if (!((cpu_id < _ncpu) && (cpu[cpu_id] && in px_ib_set_msix_target()
985 cpu_is_online(cpu[cpu_id])))) { in px_ib_set_msix_target()
988 cpu_id); in px_ib_set_msix_target()
994 DBG(DBG_IB, dip, "px_ib_set_msix_target: Enabling CPU %d\n", cpu_id); in px_ib_set_msix_target()
997 msiq_rec_type, msi_num, cpu_id, &msiq_id)) != DDI_SUCCESS) { in px_ib_set_msix_target()