Lines Matching refs:uint16_t
68 uint16_t smbh_hdl; /* structure handle */
78 uint16_t smbbi_segment; /* segment location of bios address */
112 uint16_t smbbb_chassis; /* chassis handle */
115 uint16_t smbbb_cv[1]; /* array of contained handles */
163 uint16_t smbpr_clkspeed; /* external clock speed in MHz */
164 uint16_t smbpr_maxspeed; /* maximum speed in MHz */
165 uint16_t smbpr_curspeed; /* current speed in MHz */
168 uint16_t smbpr_l1cache; /* L1 cache handle (if any) */
169 uint16_t smbpr_l2cache; /* L2 cache handle (if any) */
170 uint16_t smbpr_l3cache; /* L3 cache handle (if any) */
177 uint16_t smbpr_cflags; /* cpu characteristics (see <smbios.h>) */
178 uint16_t smbpr_family2; /* processor family2 (see <smbios.h>) */
179 uint16_t smbpr_corecount2; /* second number of cores per socket */
180 uint16_t smbpr_coresenabled2; /* second number of enabled cores */
181 uint16_t smbpr_threadcount2; /* second number of enabled threads */
182 uint16_t smpbr_threaden; /* enabled thread count */
191 uint16_t smbca_config; /* cache configuration */
192 uint16_t smbca_maxsize; /* maximum installed size */
193 uint16_t smbca_size; /* installed size */
194 uint16_t smbca_stype; /* supported SRAM type */
195 uint16_t smbca_ctype; /* current SRAM type */
238 uint16_t smbspb_group_no; /* segment group number */
251 uint16_t smbsl_id; /* slot ID */
254 uint16_t smbsl_sg; /* segment group number */
272 uint16_t smbsl_pitch; /* slot pitch */
321 uint16_t smbsel_len; /* log area length */
322 uint16_t smbsel_hdroff; /* header offset */
323 uint16_t smbsel_dataoff; /* data offset */
343 uint16_t smbmarr_err; /* error handle */
344 uint16_t smbmarr_ndevs; /* number of slots or sockets */
355 uint16_t smbamap_array; /* physical memory array handle */
366 uint16_t smbmdev_array; /* array handle */
367 uint16_t smbmdev_error; /* error handle */
368 uint16_t smbmdev_twidth; /* total width */
369 uint16_t smbmdev_dwidth; /* data width */
370 uint16_t smbmdev_size; /* size in either K or MB */
376 uint16_t smbmdev_flags; /* detail flags */
377 uint16_t smbmdev_speed; /* speed in MT/s */
384 uint16_t smbmdev_clkspeed; /* configured clock speed */
385 uint16_t smbmdev_minvolt; /* minimum voltage */
386 uint16_t smbmdev_maxvolt; /* maximum voltage */
387 uint16_t smbmdev_confvolt; /* configured voltage */
390 uint16_t smbmdev_opmode; /* memory operating mode capability */
392 uint16_t smbmdev_modulemfgid; /* module manufacturer ID */
393 uint16_t smbmdev_moduleprodid; /* module product ID */
394 uint16_t smbmdev_memsysmfgid; /* memory controller manufacturer id */
395 uint16_t smbmdev_memsysprodid; /* memory controller product id */
404 uint16_t smbmdev_pmic0mfgid; /* PMIC0 Manufacturer ID */
405 uint16_t smbmdev_pmic0rev; /* PMIC0 Revision */
406 uint16_t smbmdev_rcdmfgid; /* RCD Manufacturer ID */
407 uint16_t smbmdev_rcdrev; /* RCD Revision */
419 uint16_t smbdmap_device; /* memory device handle */
420 uint16_t smbdmap_array; /* memory array mapped address handle */
446 uint16_t smbbat_cap; /* design capacity in mW hours */
447 uint16_t smbbat_volt; /* design voltage in mV */
450 uint16_t smbbat_ssn; /* SBDS serial number */
451 uint16_t smbbat_sdate; /* SBDS manufacture date */
477 uint16_t smbvpr_maxval; /* maximum voltage */
478 uint16_t smbvpr_minval; /* minimum voltage */
479 uint16_t smbvpr_resolution; /* probe resolution */
480 uint16_t smbvpr_tolerance; /* probe tolerance */
481 uint16_t smbvpr_accuracy; /* probe accuracy */
483 uint16_t smbvpr_nominal; /* nominal value */
497 uint16_t smbcdev_tprobe; /* temperature probe */
501 uint16_t smbcdev_nominal; /* nominal value */
519 uint16_t smbtpr_maxval; /* maximum temperature */
520 uint16_t smbtpr_minval; /* minimum temperature */
521 uint16_t smbtpr_resolution; /* probe resolution */
522 uint16_t smbtpr_tolerance; /* probe tolerance */
523 uint16_t smbtpr_accuracy; /* probe accuracy */
525 uint16_t smbtpr_nominal; /* nominal value */
541 uint16_t smbipr_maxval; /* maximum current */
542 uint16_t smbipr_minval; /* minimum current */
543 uint16_t smbipr_resolution; /* probe resolution */
544 uint16_t smbipr_tolerance; /* probe tolerance */
545 uint16_t smbipr_accuracy; /* probe accuracy */
547 uint16_t smbipr_nominal; /* nominal value */
613 uint16_t smbpsup_max; /* max output in milliwatts */
614 uint16_t smbpsup_char; /* characteristics */
615 uint16_t smbpsup_vprobe; /* voltage probe handle */
616 uint16_t smbpsup_cooldev; /* cooling device handle */
617 uint16_t smbpsup_iprobe; /* current probe handle */
643 uint16_t smbaie_rhdl;
657 uint16_t smbobe_sg; /* segment group number */
667 uint16_t smbpai_proc; /* processor handle */
674 uint16_t smbpairv_vers; /* structure revision */
706 uint16_t smbfwii_chars; /* Characteristics */
709 uint16_t smbfwii_comps[]; /* Variable handles */
717 uint16_t smbstrp_prop_id; /* string property ID */
719 uint16_t smbstrp_phdl; /* parent handle */
727 uint16_t smbpre_processor; /* processor handle */
730 uint16_t smbpre_apicid[1]; /* strand initial apic id */
738 uint16_t smbpoe_chassis; /* chassis handle */
739 uint16_t smbpoe_port; /* port connector handle */
741 uint16_t smbpoe_devhdl; /* device handle */
750 uint16_t smbpciexrc_bboard; /* base board handle */
751 uint16_t smbpciexrc_bdf; /* PCI Bus/Dev/Func */
759 uint16_t smbmarre_ma; /* memory array handle */
760 uint16_t smbmarre_component; /* component parent handle */
761 uint16_t smbmarre_bdf; /* PCI bus/dev/funct */
769 uint16_t smbmdeve_mdev; /* memory device handle */
782 uint16_t *smbst_strtab; /* string index -> offset table */
931 uint16_t smbba_stype; /* supported SRAM types (SMB_CAT_*) */
932 uint16_t smbba_ctype; /* current SRAM type (SMB_CAT_*) */
949 uint16_t smbbl_id; /* slot ID */
952 uint16_t smbbl_sg; /* segment group number */