Lines Matching refs:uint16_t
750 uint16_t v_minor;
751 uint16_t v_major;
803 uint16_t psd_mp; /* Maximum Power */
818 uint16_t psd_idlp; /* Idle Power (1.2) */
822 uint16_t psd_actp; /* Active Power (1.2) */
836 uint16_t id_vid; /* PCI vendor ID */
837 uint16_t id_ssvid; /* PCI subsystem vendor ID */
851 uint16_t id_cntlid; /* Unique Controller Identifier (1.1) */
880 uint16_t id_rrls; /* Read Recovery Levels (1.4) */
884 uint16_t id_crdt1; /* Command Retry Delay Time 1 (1.4) */
885 uint16_t id_crdt2; /* Command Retry Delay Time 2 (1.4) */
886 uint16_t id_crdt3; /* Command Retry Delay Time 3 (1.4) */
907 uint16_t oa_security:1; /* Security Send & Receive */
908 uint16_t oa_format:1; /* Format NVM */
909 uint16_t oa_firmware:1; /* Firmware Activate & Download */
910 uint16_t oa_nsmgmt:1; /* Namespace Management (1.2) */
911 uint16_t oa_selftest:1; /* Self Test (1.3) */
912 uint16_t oa_direct:1; /* Directives (1.3) */
913 uint16_t oa_nvmemi:1; /* MI-Send/Recv (1.3) */
914 uint16_t oa_virtmgmt:1; /* Virtualization Management (1.3) */
915 uint16_t oa_doorbell:1; /* Doorbell Buffer Config (1.3) */
916 uint16_t oa_lbastat:1; /* LBA Status (1.4) */
917 uint16_t oa_rsvd:6;
945 uint16_t ap_wctemp; /* Warning Composite Temp. (1.2) */
946 uint16_t ap_cctemp; /* Critical Composite Temp. (1.2) */
947 uint16_t ap_mtfa; /* Maximum Firmware Activation (1.2) */
960 uint16_t ap_edstt; /* Ext. Device Self-test time (1.3) */
966 uint16_t ap_kas; /* Keep Alive Support (1.2) */
968 uint16_t hctma_hctm:1; /* Host Controlled (1.3) */
969 uint16_t hctma_rsvd:15;
971 uint16_t ap_mntmt; /* Minimum Thermal Temperature (1.3) */
972 uint16_t ap_mxtmt; /* Maximum Thermal Temperature (1.3) */
982 uint16_t ap_hmmaxd; /* How Mem Max Desc Entries (1.4) */
983 uint16_t ap_nsetidmax; /* Max NVMe set identifier (1.4) */
984 uint16_t ap_engidmax; /* Max Endurance Group ID (1.4) */
1004 uint16_t id_maxcmd; /* Max Outstanding Commands (1.3) */
1007 uint16_t on_compare:1; /* Compare */
1008 uint16_t on_wr_unc:1; /* Write Uncorrectable */
1009 uint16_t on_dset_mgmt:1; /* Dataset Management */
1010 uint16_t on_wr_zero:1; /* Write Zeros (1.1) */
1011 uint16_t on_save:1; /* Save/Select in Get/Set Feat (1.1) */
1012 uint16_t on_reserve:1; /* Reservations (1.1) */
1013 uint16_t on_ts:1; /* Timestamp (1.3) */
1014 uint16_t on_verify:1; /* Verify (1.4) */
1015 uint16_t on_rsvd:8;
1018 uint16_t f_cmp_wr:1; /* Compare and Write */
1019 uint16_t f_rsvd:15;
1032 uint16_t id_awun; /* Atomic Write Unit Normal */
1033 uint16_t id_awupf; /* Atomic Write Unit Power Fail */
1044 uint16_t id_acwu; /* Atomic Compare & Write Unit (1.1) */
1045 uint16_t id_rsvd_nc_3;
1047 uint16_t sgl_sup:2; /* SGL Supported in NVM cmds (1.3) */
1048 uint16_t sgl_keyed:1; /* Keyed SGL Support (1.2) */
1049 uint16_t sgl_rsvd1:13;
1050 uint16_t sgl_bucket:1; /* SGL Bit Bucket supported (1.1) */
1051 uint16_t sgl_balign:1; /* SGL Byte Aligned (1.2) */
1052 uint16_t sgl_sglgtd:1; /* SGL Length Longer than Data (1.2) */
1053 uint16_t sgl_mptr:1; /* SGL MPTR w/ SGL (1.2) */
1054 uint16_t sgl_offset:1; /* SGL Address is offset (1.2) */
1055 uint16_t sgl_tport:1; /* Transport SGL Data Block (1.4) */
1056 uint16_t sgl_rsvd2:10;
1109 uint16_t lbaf_ms; /* Metadata Size */
1173 uint16_t id_nawun; /* Atomic Write Unit Normal (1.2) */
1174 uint16_t id_nawupf; /* Atomic Write Unit Power Fail (1.2) */
1175 uint16_t id_nacwu; /* Atomic Compare & Write Unit (1.2) */
1176 uint16_t id_nabsn; /* Atomic Boundary Size Normal (1.2) */
1177 uint16_t id_nbao; /* Atomic Boundary Offset (1.2) */
1178 uint16_t id_nabspf; /* Atomic Boundary Size Fail (1.2) */
1179 uint16_t id_noiob; /* Optimal I/O Bondary (1.3) */
1181 uint16_t id_npwg; /* NS Pref. Write Gran. (1.4) */
1182 uint16_t id_npwa; /* NS Pref. Write Align. (1.4) */
1183 uint16_t id_npdg; /* NS Pref. Deallocate Gran. (1.4) */
1184 uint16_t id_npda; /* NS Pref. Deallocate Align. (1.4) */
1185 uint16_t id_nows; /* NS. Optimal Write Size (1.4) */
1193 uint16_t id_nvmsetid; /* NVM Set Identifier (1.4) */
1194 uint16_t id_endgid; /* Endurance Group Identifier (1.4) */
1212 uint16_t cl_nid; /* Number of controller entries */
1214 uint16_t cl_ctlid[NVME_IDENTIFY_BUFSIZE / sizeof (uint16_t) - 1];
1237 uint16_t nipc_cntlid; /* Controller ID */
1238 uint16_t nipc_portid; /* Port Identifier */
1243 uint16_t nipc_vqrfap; /* VQ Resources to Primary */
1244 uint16_t nipc_vqprt; /* VQ Resources Private Total */
1245 uint16_t nipc_vqfrsm; /* VQ Resources Secondary Max */
1246 uint16_t nipc_vqgran; /* VQ Flexible Resource Gran */
1250 uint16_t nipc_virfap; /* VI Flexible Allocated to Primary */
1251 uint16_t nipc_viprt; /* VI Resources Private Total */
1252 uint16_t nipc_vifrsm; /* VI Resources Secondary Max */
1253 uint16_t nipc_vigran; /* VI Flexible Granularity */
1261 uint16_t sf_p:1; /* Phase Tag */
1262 uint16_t sf_sc:8; /* Status Code */
1263 uint16_t sf_sct:3; /* Status Code Type */
1264 uint16_t sf_rsvd2:2;
1265 uint16_t sf_m:1; /* More */
1266 uint16_t sf_dnr:1; /* Do Not Retry */
1303 uint16_t nsl_lidsp; /* Raw Value */
1305 uint16_t nsl_ec512:1;
1306 uint16_t nsl_pel_rsvd0p1:15;
1311 uint16_t ns_lsupp:1;
1312 uint16_t ns_ios:1;
1313 uint16_t ns_rsvd0p2:14;
1331 uint16_t el_sqid; /* Submission Queue ID */
1332 uint16_t el_cid; /* Command ID */
1352 uint16_t hl_temp; /* Temperature */
1370 uint16_t hl_temp_sensor_1; /* Temperature Sensor 1 */
1371 uint16_t hl_temp_sensor_2; /* Temperature Sensor 2 */
1372 uint16_t hl_temp_sensor_3; /* Temperature Sensor 3 */
1373 uint16_t hl_temp_sensor_4; /* Temperature Sensor 4 */
1374 uint16_t hl_temp_sensor_5; /* Temperature Sensor 5 */
1375 uint16_t hl_temp_sensor_6; /* Temperature Sensor 6 */
1376 uint16_t hl_temp_sensor_7; /* Temperature Sensor 7 */
1377 uint16_t hl_temp_sensor_8; /* Temperature Sensor 8 */
1426 uint16_t cmd_cse:3; /* Command submission and execution */
1427 uint16_t cmd_uuid:1; /* UUID select supported, 1.4 */
1428 uint16_t cmd_csp:12; /* Command Scope, 2.0 */
1570 uint16_t tt_tmpth; /* Temperature Threshold */
1571 uint16_t tt_tmpsel:4; /* Temperature Select */
1572 uint16_t tt_thsel:2; /* Temperature Type */
1573 uint16_t tt_resv:10;
1586 uint16_t er_tler; /* Time-Limited Error Recovery */
1587 uint16_t er_rsvd;
1604 uint16_t nq_nsq; /* Number of Submission Queues */
1605 uint16_t nq_ncq; /* Number of Completion Queues */
1615 uint16_t ic_rsvd;
1623 uint16_t iv_iv; /* Interrupt Vector */
1624 uint16_t iv_cd:1; /* Coalescing Disable */
1625 uint16_t iv_rsvd:15;