Lines Matching refs:x1
39 #define PGLCS_REG_INT_STS 0x001d00UL //Access:R DataWidth:0x1 // Multi Field Register.
40 #define PGLCS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42 #define PGLCS_REG_INT_STS_RASDP_ERROR (0x1<<1) // It indicates rasdp error
44 #define PGLCS_REG_INT_MASK 0x001d04UL //Access:RW DataWidth:0x1 // Multi Field Register.
45 #define PGLCS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
47 #define PGLCS_REG_INT_MASK_RASDP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
49 #define PGLCS_REG_INT_STS_WR 0x001d08UL //Access:WR DataWidth:0x1 // Multi Field Register.
50 #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
52 #define PGLCS_REG_INT_STS_WR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
54 #define PGLCS_REG_INT_STS_CLR 0x001d0cUL //Access:RC DataWidth:0x1 // Multi Field Register.
55 #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57 #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
59 #define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF 0x001d10UL //Access:RW DataWidth:0x1 // Disable rasdp error mode check
99 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN (0x1<<0) // Enables IO Access Response. You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
101 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN (0x1<<1) // Enables Memory Access Response. You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
103 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests.
105 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION (0x1<<3) // Special Cycle Enable.
107 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE (0x1<<4) // Memory Write and Invalidate.
109 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP (0x1<<5) // VGA Palette Snoop.
111 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN (0x1<<6) // Controls Logging of Poisoned TLPs.
113 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING (0x1<<7) // IDSEL Stepping.
115 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN (0x1<<8) // Enables Error Reporting.
117 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN (0x1<<10) // Controls generation of interrupts by a function.
121 #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS (0x1<<19) // Emulation interrupt pending.
123 #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST (0x1<<20) // Extended Capability.
125 #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP (0x1<<21) // PCI 66MHz Capability.
127 #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP (0x1<<23) // Fast Back to Back Transaction Capable and Enable.
129 #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE (0x1<<24) // Controls poisoned Completion and Request error reporting.
133 #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT (0x1<<27) // Completer Abort Error.
135 #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT (0x1<<28) // Completer Abort received.
137 #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT (0x1<<29) // Unsupported request completion status received.
139 #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message sent by function.
141 #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR (0x1<<31) // Poisoned TLP received by function.
144 #define PCIEIP_REG_STATUS_COMMAND_IO_SPACE (0x1<<0) // This bit indicates that the device does not support I/O space access because it is zero and can not be modified. IO transactions targeting this device return completion with UR status . Path = i_cfg_func.i_cfg_public.i_cfg_dec
146 #define PCIEIP_REG_STATUS_COMMAND_MEM_SPACE (0x1<<1) // This bit controls the enabling of the memory space. When disabled, memory transactions targeting this device return completion with UR status Path = i_cfg_func.i_cfg_public.i_cfg_dec
148 #define PCIEIP_REG_STATUS_COMMAND_BUS_MASTER (0x1<<2) // This bit controls the enabling of the bus master activity by this device. When low, it disables an Endpoint function from issuing memory or IO requests. Also disables the ability to issue MSI messages. Path = i_cfg_func.i_cfg_public.i_cfg_dec
150 #define PCIEIP_REG_STATUS_COMMAND_SPECIAL_CYCLES (0x1<<3) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
152 #define PCIEIP_REG_STATUS_COMMAND_MWI_CYCLES (0x1<<4) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
154 #define PCIEIP_REG_STATUS_COMMAND_VGA_SNOOP (0x1<<5) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
156 #define PCIEIP_REG_STATUS_COMMAND_PERR_ENA (0x1<<6) // This bit enables the write to the Master data parity error status bit. If this bit is cleared , the master data parity error status bit will never be set. Path = i_cfg_func.i_cfg_public.i_cfg_dec
158 #define PCIEIP_REG_STATUS_COMMAND_STEPPING (0x1<<7) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
160 #define PCIEIP_REG_STATUS_COMMAND_SERR_ENA (0x1<<8) // When set, this bit enables the non fatal and fatal errors detected by the function to be reported to the Root Complex. The function reports such errors to the Root Complex if it is enabled to do so either through this bit or though PCI express specific bits in DCR Path = i_cfg_func.i_cfg_public.i_cfg_dec
162 #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B (0x1<<9) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
164 #define PCIEIP_REG_STATUS_COMMAND_INT_DISABLE (0x1<<10) // When this bit is set, function is not permitted to generate IntX interrupt messages (de-asserted) regardless of any internal chip logic. Setting this bit has no effect on the INT_STATUS bit below. Writing this bit to '0' will un-mask the interrupt and let it run normally. Path = i_cfg_func.i_cfg_public.i_cfg_dec
170 #define PCIEIP_REG_STATUS_COMMAND_INT_STATUS (0x1<<19) // This bit indicates the internal interrupt request state (before being masked by INT_DISABLE. A '0' indicates that no interrupt is pending. A '1' indicates that there is an interrupt pending. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
172 #define PCIEIP_REG_STATUS_COMMAND_CAP_LIST (0x1<<20) // This bit is tied high to indicate that the device supports a capability list. The list starts at address 0x40. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
174 #define PCIEIP_REG_STATUS_COMMAND_CAP_66MHZ (0x1<<21) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
176 #define PCIEIP_REG_STATUS_COMMAND_RESERVED2 (0x1<<22) // These bits are reserved and tied low per the PCI specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
178 #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_CAP (0x1<<23) // Does not apply to PCIE. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
180 #define PCIEIP_REG_STATUS_COMMAND_PRI_MSTR_PERR (0x1<<24) // The master data parity error bit is set by a requester if the parity error enable bit is set in its command register and either of the following 2 conditions occur. If the requester receives a poisoned completion if the requester poisons a write request If the parity Error enable bit is cleared , the master data parity error status bit is never set Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
184 #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_TGT_ABT (0x1<<27) // This bit is set when a function acting as a completer terminates a request by issuing Completer abort completion status to the requester Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
186 #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_TGT_ABT (0x1<<28) // This bit is set when a requester receives a completion with completer abort completion status. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
188 #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_MSTR_ABT (0x1<<29) // This bit is set when a requester receives a completion with UR completion status Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
190 #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_SERR (0x1<<30) // This bit is set when a function sends an ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
192 #define PCIEIP_REG_STATUS_COMMAND_PRI_PAR_ERR (0x1<<31) // When this bit is set, it indicates that the function has received a poisoned TLP Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
215 #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC (0x1<<23) // Specifies whether device is multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
229 #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO (0x1<<0) // BAR0 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
233 #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH (0x1<<3) // BAR0 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
238 #define PCIEIP_REG_BAR_1_MEM_SPACE (0x1<<0) // This bit indicates that BAR_1 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
242 #define PCIEIP_REG_BAR_1_PREFETCH (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register. Path = i_cfg_func.i_cfg_private
247 #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO (0x1<<0) // BAR1 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
251 #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH (0x1<<3) // BAR1 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
257 #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO (0x1<<0) // BAR2 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
261 #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH (0x1<<3) // BAR2 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
266 #define PCIEIP_REG_BAR_3_MEM_SPACE (0x1<<0) // This bit indicates that BAR_2 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
270 #define PCIEIP_REG_BAR_3_PREFETCH (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by the system without side effects. Path = i_cfg_func.i_cfg_private
275 #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO (0x1<<0) // BAR3 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
279 #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH (0x1<<3) // BAR3 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
285 #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO (0x1<<0) // BAR4 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
289 #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH (0x1<<3) // BAR4 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
294 #define PCIEIP_REG_BAR_5_MEM_SPACE (0x1<<0) // This bit indicates that BAR_3 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
298 #define PCIEIP_REG_BAR_5_PREFETCH (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by the system without side effects. Path = i_cfg_func.i_cfg_private
303 #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO (0x1<<0) // BAR5 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
307 #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH (0x1<<3) // BAR5 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
325 #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE (0x1<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
330 #define PCIEIP_REG_EXP_ROM_BAR_BAR_ENA (0x1<<0) // This bit indicates that the Expansion ROM BAR is valid when set to one. If it is zero, the expansion BAR should not be programmed or used. This bit will only be RW if it is enabled by the EXP_ROM_ENA bit which defaults to 0. Path = i_cfg_func.i_cfg_private
365 #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK (0x1<<19) // PCI Clock Requirement.
367 #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO (0x1<<20) // Immediate Readiness on Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
369 #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI (0x1<<21) // Device Specific Initialization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
373 #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT (0x1<<25) // D1 State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
375 #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT (0x1<<26) // D2 State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
382 #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST (0x1<<3) // No soft Reset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
384 #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE (0x1<<8) // PME Enable. The PMC registers this value under aux power. Sometimes it might remember the old value, even if you try to clear it by writing '0'. Note: This register field is sticky.
390 #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS (0x1<<15) // PME Status.
392 #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT (0x1<<22) // B2B3 Support for D3hot.
394 #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN (0x1<<23) // Bus Power/Clock Control Enable.
405 #define PCIEIP_REG_PM_CAP_UNUSED0 (0x1<<18) //
407 #define PCIEIP_REG_PM_CAP_CLOCK (0x1<<19) // This bit indicates that the device relies on the presence of the PCI clock for PME# operation. This chip does not require the PCI clock to generate PME#, therefore this bit is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
409 #define PCIEIP_REG_PM_CAP_RESERVED (0x1<<20) // Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
411 #define PCIEIP_REG_PM_CAP_DSI (0x1<<21) // This bit indicates that the device requires a specific initialization (DSI) sequence following a transition to the D0 un-initialized state. This device does not need this support, so the bit is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
415 #define PCIEIP_REG_PM_CAP_D1_SUPPORT (0x1<<25) // This bit indicates whether the device supports the D1 power management state. This bit is controlled by the D1_SUPPORT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
417 #define PCIEIP_REG_PM_CAP_D2_SUPPORT (0x1<<26) // This bit indicates whether the device supports the D2 power management state. This bit is controlled by the D2_SUPPORT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
419 #define PCIEIP_REG_PM_CAP_PME_IN_D0 (0x1<<27) // This bit indicates whether the device supports transmiting PME message from the D0 power state. This bit is controlled by the PME_IN_D0 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
421 #define PCIEIP_REG_PM_CAP_PME_IN_D1 (0x1<<28) // This bit indicates whether the device supports transmiting PME message from the D1 power state. This bit is controlled by the PME_IN_D1 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
423 #define PCIEIP_REG_PM_CAP_PME_IN_D2 (0x1<<29) // This bit indicates whether the device supports transmiting PME message from the D2 power state. This bit is controlled by the PME_IN_D2 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
425 #define PCIEIP_REG_PM_CAP_PME_IN_D3_HOT (0x1<<30) // This bit indicates whether the device supports transmiting PME message from the D3hot power state. This bit is controlled by the PME_IN_D3_HOT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
427 #define PCIEIP_REG_PM_CAP_PME_IN_D3_COLD (0x1<<31) // This bit indicates whether the device supports transmiting PME message from the D3cold power state. This is supported if the VAUX_PRESENT input pin is high. This bit reflects the input value of the VAUX_PRESENT input pin. Path = input pins to pcie_vaux
432 #define PCIEIP_REG_PM_CSR_RESERVED0 (0x1<<2) // Reserved Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
434 #define PCIEIP_REG_PM_CSR_NO_SOFT_RESET (0x1<<3) // When device transitions from D3 to D0, device does not perform an internal reset. This bit can be programmed through reg space Path = i_cfg_func.i_cfg_private
438 #define PCIEIP_REG_PM_CSR_PME_ENABLE (0x1<<8) // This bit enables the device to transmit PME messages. On HARD reset, this bit resets to '1'. this bit is sticky and is not modified by PERST_B. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
442 #define PCIEIP_REG_PM_CSR_DATA_SCALE (0x3<<13) // These bits indicate the scaling factor to be used when interpreting the values in the PM data register. The hardware default value for this field is 0x1, but this value can be written by firmware through the PCI register space (SCALE_PRG) to modify the read value to the host. Path = i_cfg_func.i_cfg_private
444 #define PCIEIP_REG_PM_CSR_PME_STATUS (0x1<<15) // This bit is set when a PME is asserted from the MAC or RX Parser blocks, regardless of the state of the PME_ENABLE bit. If both this bit and the PME_ENABLE bit are high, then the PME output will be asserted low. This bit is cleared by writing a 1 in this bit position. At power-up, the chip must clear this bit, but on assertions of PCI_RST# after that, this bit is sticky and not modified. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
455 #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE (0x1<<16) // MSI Enable.
461 #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
463 #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT (0x1<<24) // MSI Per Vector Masking Capable.
474 #define PCIEIP_REG_VPD_CAP_FLAG (0x1<<31) // This bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To read a value, this bit is written as zero when the address is written. When the data is available to read, this bit will read as a one. To write data, this bit must written as a one when the address is written. When the bit reads as a zero the write has completed. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap
490 #define PCIEIP_REG_MSI_CAP_MSI_ENABLE (0x1<<16) // When this bit is set, the chip will generate MSI cycles to indicate interrupts instead of asserting the INTA# pin. When this bit is zero, the INTA# pin will be used. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
496 #define PCIEIP_REG_MSI_CAP_CAP_64BIT (0x1<<23) // This bit indicates that the chip is capable of generating 64 bit MSI messages. Path = cfg_defs
498 #define PCIEIP_REG_MSI_CAP_MSI_PVMASK_CAPABLE (0x1<<24) // This bit indicates if the function supports per vector masking. This value comes from the MSI_PV_MASK_CAP bit in the register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
525 #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP (0x1<<24) // PCIe Slot Implemented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
529 #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD (0x1<<30) // Reserved.
536 #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP (0x1<<5) // Extended Tag Field Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
542 #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
548 #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP (0x1<<28) // Function Level Reset Capability (endpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
551 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN (0x1<<0) // Correctable Error Reporting Enable.
553 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN (0x1<<1) // Non-fatal Error Reporting Enable.
555 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN (0x1<<2) // Fatal Error Reporting Enable.
557 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN (0x1<<3) // Unsupported Request Reporting Enable.
559 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER (0x1<<4) // Enable Relaxed Ordering.
563 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN (0x1<<8) // Extended Tag Field Enable. The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
565 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN (0x1<<9) // Phantom Functions Enable. The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
567 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN (0x1<<10) // Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. Note: This register field is sticky.
569 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP (0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
573 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR (0x1<<15) // Initiate Function Level Reset (for endpoints).
575 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED (0x1<<16) // Correctable Error Detected Status.
577 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED (0x1<<17) // Non-Fatal Error Detected Status.
579 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED (0x1<<18) // Fatal Error Detected Status.
581 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED (0x1<<19) // Unsupported Request Detected Status.
583 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED (0x1<<20) // Aux Power Detected Status. This bit is derived by sampling the sys_aux_pwr_det input.
585 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING (0x1<<21) // Transactions Pending Status.
598 #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN (0x1<<18) // Clock Power Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
600 #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP (0x1<<19) // Surprise Down Error Reporting Capable.
602 #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP (0x1<<20) // Data Link Layer Link Active Reporting Capable.
604 #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP (0x1<<21) // Link Bandwidth Notification Capable.
606 #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE (0x1<<22) // ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
613 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB (0x1<<3) // Read Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W
615 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE (0x1<<4) // Initiate Link Disable. In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
617 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK (0x1<<5) // Initiate Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
619 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG (0x1<<6) // Common Clock Configuration.
621 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH (0x1<<7) // Extended Synch.
623 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN (0x1<<8) // Enable Clock Power Management. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO
625 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE (0x1<<9) // Hardware Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
627 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN (0x1<<10) // Link Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
629 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
637 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
639 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG (0x1<<28) // Slot Clock Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
641 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE (0x1<<29) // Data Link Layer Active.
643 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS (0x1<<30) // Link Bandwidth Management Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
645 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS (0x1<<31) // Link Autonomous Bandwidth Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
650 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT (0x1<<4) // Completion Timeout Disable Supported.
652 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT (0x1<<5) // ARI Forwarding Supported.
654 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP (0x1<<6) // Atomic Operation Routing Supported.
656 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP (0x1<<7) // 32 Bit AtomicOp Completer Supported.
658 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP (0x1<<8) // 64 Bit AtomicOp Completer Supported.
660 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP (0x1<<9) // 128 Bit CAS Completer Supported.
662 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
664 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP (0x1<<11) // LTR Mechanism Supported.
666 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0 (0x1<<12) // TPH Completer Supported Bit 0.
668 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1 (0x1<<13) // TPH Completer Supported Bit 1.
675 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE (0x1<<4) // Completion Timeout Disable.
677 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS (0x1<<5) // ARI Forwarding Enable.
679 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN (0x1<<6) // AtomicOp Requester Enable.
681 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK (0x1<<7) // AtomicOp Egress Blocking.
683 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN (0x1<<8) // IDO Request Enable.
685 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN (0x1<<9) // IDO Completion Enable.
687 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN (0x1<<10) // LTR Mechanism Enable. The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG. Note: RW for function #0 and RsdvP for all other functions
694 #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT (0x1<<8) // Cross Link Supported.
696 #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED (0x1<<31) // DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
701 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE (0x1<<4) // Enter Compliance Mode. Note: This register field is sticky.
703 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE (0x1<<5) // Hardware Autonomous Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
705 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. Note: This register field is sticky.
709 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE (0x1<<10) // Enter Modified Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
711 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS (0x1<<11) // Sets Compliance Skip Ordered Sets transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
715 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE
717 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL (0x1<<17) // Equalization 8.0GT/s Complete. Note: This register field is sticky.
719 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: This register field is sticky.
721 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2 (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful. Note: This register field is sticky.
723 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: This register field is sticky.
725 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ (0x1<<21) // Link Equalization Request 8.0GT/s.
729 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
740 #define PCIEIP_REG_MSIX_CAP_FUNC_MASK (0x1<<30) // If 1, all of the vectors associated with the function are masked regardless of their per vector Mask bit. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
742 #define PCIEIP_REG_MSIX_CAP_MSIX_ENABLE (0x1<<31) // If 1, and the MSI enable bit in the MSI message control register is 0, the function is permitted to use MSIX request service and profited from using INTx# messages. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
763 #define PCIEIP_REG_PCIE_CAPABILITY_SLOT_IMPLEMENTED (0x1<<24) // Slot Implemented. This register is not supported. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
774 #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK (0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
776 #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
783 #define PCIEIP_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (0x1<<5) // Extended Tag Field Support. This bit is programmable through register space. Path= i_cfg_func.i_cfg_private
791 #define PCIEIP_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (0x1<<15) // Indicate device is conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions Path= i_cfg_func.i_cfg_private
799 #define PCIEIP_REG_DEVICE_CAPABILITY_FLR_CAP_SUPPORTED (0x1<<28) // FLR capability is advertized when flr_supported bit in private device_capability register space is set.
807 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN (0x1<<0) // Correctable Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
809 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN (0x1<<1) // Non-Fatal Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
811 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN (0x1<<2) // Fatal Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
813 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN (0x1<<3) // Unsupported Request Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
815 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE (0x1<<4) // Relax Ordering Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
819 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN (0x1<<8) // Extended Tag Field Enable. This capability when set allows DUT to generate more than 32 tags. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
821 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNUSED0 (0x1<<9) //
823 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA (0x1<<10) // This bit when set enables device to draw aux power independent of PME AUX power Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
825 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE (0x1<<11) // Enable No Snoop. When this bit is set to 1, PCIE initiates a read request with the No Snoop bit in the attribute field set for the transactions that request the No Snoop attribute. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
829 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FLR_INITIATED (0x1<<15) // Initiate Function Level reset. This bit is writeable only if flr_supported bit in private device_capability register is set. A write of 1 to this bit initiates Function Level Reset. The value read by s/w from this bit is always 0.
831 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_DET (0x1<<16) // Correctable Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
833 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET (0x1<<17) // Non-Fatal Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
835 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_DET (0x1<<18) // Fatal Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
837 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET (0x1<<19) // UnSupported Request Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
839 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_DET (0x1<<20) // This bit is the current state of the VAUX_PRSNT pin of the device. When it is '1', it is indicating that part needs VAUX and detects the VAUX is present. Path= input to pcie_vaux_pipe
841 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initiated by PCIE core is pending to be completed. Path= i_tl_top
859 #define PCIEIP_REG_LINK_CAPABILITY_CLK_PWR_MGMT (0x1<<18) // Clock Power Management. These bits are programmable through register. The feature itself has to be enabled in version.v Path= i_cfg_func.i_cfg_private
861 #define PCIEIP_REG_LINK_CAPABILITY_SUR_DWN_ERR_REP (0x1<<19) // Surprise Down Error Reporting Capable: RC: this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. RC: Not supported and hardwired to 0. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
863 #define PCIEIP_REG_LINK_CAPABILITY_DL_ACTIVE_REP (0x1<<20) // Data Link Layer Link Active Reporting Capable: RC: this bit must be hardwired to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. RC: Implemented (RW) for RC. Default to 0. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_private
865 #define PCIEIP_REG_LINK_CAPABILITY_LINK_BW_NOTIFY (0x1<<21) // Link Bandwidth Notification Capability: RC: A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds. RC: Field is implemented. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
874 #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED0 (0x1<<2) //
876 #define PCIEIP_REG_LINK_STATUS_CONTROL_RCB (0x1<<3) // Read Completion Boundary. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
878 #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE (0x1<<4) // Requesting PHY to disable the link. This bit is only applicable to RC. So for EP it is read only bit. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
880 #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK (0x1<<5) // Requesting PHY to retrain the link. This bit is only applicable to RC. So for EP it is read only bit. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
882 #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK (0x1<<6) // Common Clock Configuration. Value used by logic is resolved to 1 only if all functions (when enabled) have this bit set. For ARI devices, only Function 0 determines the value used. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
884 #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC (0x1<<7) // Extended Synch. This bit when set forces the transmission of 4096 FTS ordered sets in the L0s state followed by a single SKP ordered set prior to entering the L0 state, and the transmission of 1024 TS1 ordered sets in the L1 state prior to entering the Recovery state. Value used by logic is resolved to 1 if either function has this bit set. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
886 #define PCIEIP_REG_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT (0x1<<8) // Enable Clock Power Management: RC: N/A and hardwired to 0. EP: When this bit is set, the device is permitted to use CLKREQ# signal to power management. Feature is enabled through version.v define Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
888 #define PCIEIP_REG_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS (0x1<<9) // Hardware Autonomous Width Disable: When Set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. Other functions are reserved. RC: Not applicable and hardwire to 0 EP: If supported, only apply to function0. Not implemented and hardwire to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
890 #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN (0x1<<10) // Link Bandwidth Management Interrupt Enable: when Set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. RC: N/A and hardwired to 0. EP: Not implemented and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
892 #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_INT_EN (0x1<<11) // Link Autonomous Bandwidth Interrupt Enable: When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set. RC: Not implemented and hardwired to 0. EP: N/A and hardwired to 0 Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
900 #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED2 (0x1<<26) //
902 #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_TRAINING (0x1<<27) // EP: This bit is N/A and is hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
904 #define PCIEIP_REG_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but read/write via backdoor CS bus. Path= i_cfg_func.i_cfg_private
906 #define PCIEIP_REG_LINK_STATUS_CONTROL_DL_ACTIVE (0x1<<29) // Data Link Layer Link Active: returns a 1b to indicate the DL_Active state, 0b otherwise. Not implemented and hardwire to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
924 #define PCIEIP_REG_SLOT_CONTROL_STATUS_PRESENCE_DETECT (0x1<<22) // Not implemented
937 #define PCIEIP_REG_VPD_BASE_VPD_FLAG (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
942 #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED (0x1<<4) // Completion Timeout Disable Supported, Programmable through register space Path= i_cfg_func.i_cfg_private
946 #define PCIEIP_REG_DEVICE_CAPABILITY_2_LTR_MECHANISM_SUPPORTED (0x1<<11) // Latency Tolerance Reporting Mechanism Supported, Programmable through register space. This field will read 1, when bit 5 of ext_cap_ena field in private register space is set.
958 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE (0x1<<4) // Completion Timeout Disable Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
960 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED0 (0x1<<5) //
962 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE (0x1<<6) // Atomic requester Enable. When this bit is set, function and associated VF's are enabled to make Atomic Op requests.
964 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED1 (0x1<<7) //
966 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_REQ_ENABLE (0x1<<8) // IDO Request Enable, This field is writeable, when bit ido_supported bit of private device_capability_2 register is set. When this bit is set, function is permitted to set ID based Ordering Attribute of Requests it initiates.
968 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_CPL_ENABLE (0x1<<9) // IDO Completion Enable, This field is writeable, when bit ido_supported bit of private device_capability_2 register is set. When this bit is set, function is permitted to set ID based Ordering Attribute of Completions it returns.
970 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_LTR_MECHANISM_ENABLE (0x1<<10) // Latency Tolerance Reporting Mechanism Enable, This field is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW only in function 0 and is RsvdP for all other functions.
976 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED3 (0x1<<15) //
984 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE (0x1<<4) //
986 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE (0x1<<5) //
988 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS (0x1<<6) // When link is operating at Gen2 rates, this bit selects the level of de-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value used by logic is resolved to 1 if either function has this bit set.
992 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE (0x1<<10) //
994 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS (0x1<<11) //
996 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH (0x1<<12) //
1000 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL (0x1<<16) // curr_deemph_level Path = pl_top
1002 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_COMPLETE (0x1<<17) // Equalization Complete - when set, this indicates that the Transmitter equalization procedure has completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1004 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE1_SUCCESS (0x1<<18) // Equalization Phase 1 Successful - when set, this indicates that Phase 1 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1006 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE2_SUCCESS (0x1<<19) // Equalization Phase 2 Successful - when set, this indicates that Phase 2 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1008 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE3_SUCCESS (0x1<<20) // Equalization Phase 3 Successful - when set, this indicates that Phase 3 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1010 #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_LINK_EQ_REQUEST (0x1<<21) // This bit is set by hardware to request the link equalization process to be performed on the link. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1035 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS (0x1<<4) // Data Link Protocol Error Status.
1037 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS (0x1<<5) // Surprise Down Error Status (Optional). Note: Not supported.
1039 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS (0x1<<12) // Poisoned TLP Status.
1041 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS (0x1<<13) // Flow Control Protocol Error Status.
1043 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS (0x1<<14) // Completion Timeout Status.
1045 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS (0x1<<15) // Completer Abort Status.
1047 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS (0x1<<16) // Unexpected Completion Status.
1049 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS (0x1<<17) // Receiver Overflow Status.
1051 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS (0x1<<18) // Malformed TLP Status.
1053 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS (0x1<<19) // ECRC Error Status.
1055 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS (0x1<<20) // Unsupported Request Error Status.
1057 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS (0x1<<22) // Uncorrectable Internal Error Status. The core sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.
1059 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS (0x1<<25) // TLP Prefix Blocked Error Status. Note: Not supported.
1064 #define PCIEIP_REG_UC_ERR_STATUS_DLPES (0x1<<4) // Data Link Protocol Error Status
1068 #define PCIEIP_REG_UC_ERR_STATUS_PTLPS (0x1<<12) // Poisoned TLP Status.
1070 #define PCIEIP_REG_UC_ERR_STATUS_FCPES (0x1<<13) // Flow Control Protocol Error Status.
1072 #define PCIEIP_REG_UC_ERR_STATUS_CTS (0x1<<14) // Completer Timeout Status.
1074 #define PCIEIP_REG_UC_ERR_STATUS_CAS (0x1<<15) // Completer Abort Status.
1076 #define PCIEIP_REG_UC_ERR_STATUS_UCS (0x1<<16) // Unexpected Completion Status.
1078 #define PCIEIP_REG_UC_ERR_STATUS_ROS (0x1<<17) // Receiver Overflow Status.
1080 #define PCIEIP_REG_UC_ERR_STATUS_MTLPS (0x1<<18) // Malformed TLP Status.
1082 #define PCIEIP_REG_UC_ERR_STATUS_ECRCS (0x1<<19) // ECRC Error Status
1084 #define PCIEIP_REG_UC_ERR_STATUS_URES (0x1<<20) // Unsupported Request Error Status.
1087 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK (0x1<<4) // Data Link Protocol Error Mask. Note: This register field is sticky.
1089 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK (0x1<<5) // Surprise Down Error Mask. Note: Not supported. Note: This register field is sticky.
1091 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK (0x1<<12) // Poisoned TLP Error Mask. Note: This register field is sticky.
1093 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK (0x1<<13) // Flow Control Protocol Error Mask. Note: This register field is sticky.
1095 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK (0x1<<14) // Completion Timeout Error Mask. Note: This register field is sticky.
1097 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK (0x1<<15) // Completer Abort Error Mask (Optional). Note: This register field is sticky.
1099 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK (0x1<<16) // Unexpected Completion Mask. Note: This register field is sticky.
1101 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK (0x1<<17) // Receiver Overflow Mask (Optional). Note: This register field is sticky.
1103 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK (0x1<<18) // Malformed TLP Mask. Note: This register field is sticky.
1105 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK (0x1<<19) // ECRC Error Mask (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
1107 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK (0x1<<20) // Unsupported Request Error Mask. Note: This register field is sticky.
1109 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK (0x1<<22) // Uncorrectable Internal Error Mask (Optional). Note: This register field is sticky.
1111 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK (0x1<<24) // AtomicOp Egress Block Mask (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
1113 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK (0x1<<25) // TLP Prefix Blocked Error Mask. Note: Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
1118 #define PCIEIP_REG_UCORR_ERR_MASK_DLPEM (0x1<<4) // Data Link Protocol Error Mask.
1120 #define PCIEIP_REG_UCORR_ERR_MASK_SDEM (0x1<<5) // Surprise Down Error Mask
1124 #define PCIEIP_REG_UCORR_ERR_MASK_PTLPM (0x1<<12) // Poisoned TLP Mask.
1126 #define PCIEIP_REG_UCORR_ERR_MASK_FCPEM (0x1<<13) // Flow Control Protocol Error Mask.
1128 #define PCIEIP_REG_UCORR_ERR_MASK_CTM (0x1<<14) // Completer Timeout Mask.
1130 #define PCIEIP_REG_UCORR_ERR_MASK_CAM (0x1<<15) // Completer Abort Mask.
1132 #define PCIEIP_REG_UCORR_ERR_MASK_UCM (0x1<<16) // Unexpected Completion Mask.
1134 #define PCIEIP_REG_UCORR_ERR_MASK_ROM (0x1<<17) // Receiver Overflow Mask.
1136 #define PCIEIP_REG_UCORR_ERR_MASK_MTLPM (0x1<<18) // Malformed TLP Mask.
1138 #define PCIEIP_REG_UCORR_ERR_MASK_ECRCEM (0x1<<19) // ECRC Error Mask
1140 #define PCIEIP_REG_UCORR_ERR_MASK_UREM (0x1<<20) // Unsupported Request Error Mask.
1143 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY (0x1<<4) // Data Link Protocol Error Severity. Note: This register field is sticky.
1145 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY (0x1<<5) // Surprise Down Error Severity (Optional). Note: Not supported. Note: This register field is sticky.
1147 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY (0x1<<12) // Poisoned TLP Severity. Note: This register field is sticky.
1149 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY (0x1<<13) // Flow Control Protocol Error Severity (Optional). Note: This register field is sticky.
1151 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY (0x1<<14) // Completion Timeout Error Severity. Note: This register field is sticky.
1153 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY (0x1<<15) // Completer Abort Error Severity (Optional). Note: This register field is sticky.
1155 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY (0x1<<16) // Unexpected Completion Error Severity. Note: This register field is sticky.
1157 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY (0x1<<17) // Receiver Overflow Error Severity (Optional). Note: This register field is sticky.
1159 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY (0x1<<18) // Malformed TLP Severity. Note: This register field is sticky.
1161 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY (0x1<<19) // ECRC Error Severity (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
1163 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY (0x1<<20) // Unsupported Request Error Severity. Note: This register field is sticky.
1165 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY (0x1<<22) // Uncorrectable Internal Error Severity (Optional). Note: This register field is sticky.
1167 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY (0x1<<24) // AtomicOp Egress Blocked Severity (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
1169 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY (0x1<<25) // TLP Prefix Blocked Error Severity (Optional). Note: Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
1174 #define PCIEIP_REG_UCORR_ERR_SEVR_DLPES (0x1<<4) // Data Link Protocol Error Severity.
1176 #define PCIEIP_REG_UCORR_ERR_SEVR_SDES (0x1<<5) // Surprise Down Error Severity. Hardwire to 1'b1.
1180 #define PCIEIP_REG_UCORR_ERR_SEVR_PTLPS (0x1<<12) // Poisoned TLP Severity.
1182 #define PCIEIP_REG_UCORR_ERR_SEVR_FCPES (0x1<<13) // Flow Control Protocol Error Severity.
1184 #define PCIEIP_REG_UCORR_ERR_SEVR_CTS (0x1<<14) // Completer Timeout Severity.
1186 #define PCIEIP_REG_UCORR_ERR_SEVR_CAS (0x1<<15) // Completer Abort Severity.
1188 #define PCIEIP_REG_UCORR_ERR_SEVR_UCS (0x1<<16) // Unexpected Completion Severity.
1190 #define PCIEIP_REG_UCORR_ERR_SEVR_ROS (0x1<<17) // Receiver Overflow Severity.
1192 #define PCIEIP_REG_UCORR_ERR_SEVR_MTLPS (0x1<<18) // Malformed TLP Severity.
1194 #define PCIEIP_REG_UCORR_ERR_SEVR_ECRCES (0x1<<19) // Ecrc error Severity
1196 #define PCIEIP_REG_UCORR_ERR_SEVR_URES (0x1<<20) // Unsupported Request Error Severity.
1199 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS (0x1<<0) // Receiver Error Status (Optional).
1201 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS (0x1<<6) // Bad TLP Status.
1203 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS (0x1<<7) // Bad DLLP Status.
1205 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS (0x1<<8) // REPLAY_NUM Rollover Status.
1207 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS (0x1<<12) // Replay Timer Timeout Status.
1209 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS (0x1<<13) // Advisory Non-Fatal Error Status.
1211 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS (0x1<<14) // Corrected Internal Error Status (Optional).
1213 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS (0x1<<15) // Header Log Overflow Error Status (Optional).
1216 #define PCIEIP_REG_CORR_ERR_STATUS_RX_ERR_STATUS (0x1<<0) // Receiver Error Status.
1220 #define PCIEIP_REG_CORR_ERR_STATUS_BAD_TLP_STATUS (0x1<<6) // Bad TLP Status.
1222 #define PCIEIP_REG_CORR_ERR_STATUS_BAD_DLLP_STATUS (0x1<<7) // Bad DLLP Status.
1224 #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_NUM_RO_STATUS (0x1<<8) // REPLAY_NUM Rollover Status.
1228 #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_TMR_TO_STATUS (0x1<<12) // Replay Timer Timeout Status.
1230 #define PCIEIP_REG_CORR_ERR_STATUS_ADVSRY_ERR_STATUS (0x1<<13) // Advisory Non fatal Error Status. Only set if role_based_err_rpt is asserted.
1233 #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK (0x1<<0) // Receiver Error Mask (Optional). Note: This register field is sticky.
1235 #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK (0x1<<6) // Bad TLP Mask. Note: This register field is sticky.
1237 #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK (0x1<<7) // Bad DLLP Mask. Note: This register field is sticky.
1239 #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK (0x1<<8) // REPLAY_NUM Rollover Mask. Note: This register field is sticky.
1241 #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK (0x1<<12) // Replay Timer Timeout Mask. Note: This register field is sticky.
1243 #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK (0x1<<13) // Advisory Non-Fatal Error Mask. Note: This register field is sticky.
1245 #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK (0x1<<14) // Corrected Internal Error Mask (Optional). Note: This register field is sticky.
1247 #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK (0x1<<15) // Header Log Overflow Error Mask (Optional). Note: This register field is sticky.
1250 #define PCIEIP_REG_CORR_ERR_MASK_RES (0x1<<0) // Receiver Error Mask.
1254 #define PCIEIP_REG_CORR_ERR_MASK_BTLPS (0x1<<6) // Bad TLP Mask.
1256 #define PCIEIP_REG_CORR_ERR_MASK_BDLLPS (0x1<<7) // Bad DLLP Mask.
1258 #define PCIEIP_REG_CORR_ERR_MASK_RNRS (0x1<<8) // REPLAY_NUM Rollover Mask.
1262 #define PCIEIP_REG_CORR_ERR_MASK_RTTS (0x1<<12) // Replay Timer Timeout Mask.
1264 #define PCIEIP_REG_CORR_ERR_MASK_ANFM (0x1<<13) // Advisory Non fatal Error Mask
1269 #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP (0x1<<5) // ECRC Generation Capable. Note: This register field is sticky.
1271 #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN (0x1<<6) // ECRC Generation Enable. Note: This register field is sticky.
1273 #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP (0x1<<7) // ECRC Check Capable. Note: This register field is sticky.
1275 #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN (0x1<<8) // ECRC Check Enable. Note: This register field is sticky.
1277 #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP (0x1<<9) // Multiple Header Recording Capable. Note: This register field is sticky.
1279 #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN (0x1<<10) // Multiple Header Recording Enable. Note: This register field is sticky.
1284 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGCAP (0x1<<5) // ECRC generation capable, programmable through register space
1286 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGEN (0x1<<6) // ECRC generate Enable
1288 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCCAP (0x1<<7) // ECRC Check Capable, programmable through register space
1290 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN (0x1<<8) // ECRC Check Enable
1409 #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE (0x1<<0) // Requests Hardware to Load VC Arbitration Table.
1413 #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS (0x1<<16) // VC Arbitration Table Status.
1421 #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0 (0x1<<15) // Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
1441 #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0 (0x1<<0) // Bit 0 of TC to VC Mapping.
1445 #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0 (0x1<<16) // Load Port Arbitration Table.
1447 #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0 (0x1<<17) // Port Arbitration Select.
1451 #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0 (0x1<<31) // VC Enable.
1454 #define PCIEIP_REG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC (0x1<<0) // The "System Allocated" bit when set indicates that the power budget for the device is included within the system power budget. Reported Power Budgeting Data for this device should be ignored by software for power budgeting decisions if this bit is set. This register is Read Only. The value can be written indirectly by writing into Power Budget Capability Register (0x550[0]) Path = i_cfg_func.i_cfg_private
1457 #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0 (0x1<<16) // Port Arbitration Table Status.
1459 #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0 (0x1<<17) // VC Negotiation Pending.
1486 #define PCIEIP_REG_VC_RSRC_CONTROL_DEFAULT_VC0 (0x1<<0) // This bit is hardwired to one because DUT is only support VC0. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap
1492 #define PCIEIP_REG_VC_RSRC_CONTROL_VC_ENABLE (0x1<<31) // Enables virtual channel. This bit is hardwired to 1 for the default VC0 and writing to this filed has no effect. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap
1525 #define PCIEIP_REG_VENDOR_CAP_CAP_VER (0xf<<16) // Vendor Specific Extended Capability version. Hardwired to 0x1. Path = cfg_defs
1530 #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC (0x1<<0) // System Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
1549 #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_EN (0x1<<31) // Enable VF Bar0 Stride. When this bit bit is clear, computation of the VF BAR0 offset from the PF SRIOV capability structure is unchanged.
1552 #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability.
1554 #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP (0x1<<1) // ACS Function Groups Capability.
1558 #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN (0x1<<16) // MFVC Function Groups Enable.
1560 #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN (0x1<<17) // ACS Function Groups Enable.
1568 #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_EN (0x1<<31) // Enable VF Bar2 Stride. When this bit bit is clear, computation of the VF BAR2 offset from the PF SRIOV capability structure is unchanged.
1581 #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_EN (0x1<<31) // Enable VF Bar4 Stride. When this bit bit is clear, computation of the VF BAR4 offset from the PF SRIOV capability structure is unchanged.
1584 #define PCIEIP_REG_LINK_CONTROL3_REG_PERFORM_EQ (0x1<<0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
1586 #define PCIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN (0x1<<1) // Link Equalization Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
1662 #define PCIEIP_REG_LTR_CAP_CAP_VER (0xf<<16) // LTR Capability version. Hardwired to 0x1.
1687 #define PCIEIP_REG_ARI_CAP_CAP_VER (0xf<<16) // ARI Capability version. Hardwired to 0x1.
1692 #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP (0x1<<0) // VF Migration Capable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1694 #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED (0x1<<1) // ARI Capable Hierarchy Preserved. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
1699 #define PCIEIP_REG_ARI_CONTROL_REGISTER_MFVC_FUNC_GROUP_CAP (0x1<<0) // Hardwired to 0
1701 #define PCIEIP_REG_ARI_CONTROL_REGISTER_ACS_FUNC_GROUP_CAP (0x1<<1) // Hardwired to 0
1710 #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE (0x1<<0) // VF Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1712 #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE (0x1<<1) // VF Migration Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1714 #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE (0x1<<2) // VF Migration Interrupt Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1716 #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE (0x1<<3) // VF Memory Space Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1718 #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER (0x1<<4) // ARI Capable Hierarchy (Applies to endpoint only). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as write-value
1723 #define PCIEIP_REG_SRIOV_CAP_SRCAP_VER (0xf<<16) // SRIOV Capability version. Hardwired to 0x1.
1733 #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1A (0x1<<0) // The capability is hardwired to 0.
1735 #define PCIEIP_REG_SRIOV_CAPABILITIES_ARI_CAP_HIER_PRESERVED (0x1<<1) // This field is only present in PF0. This bet when set indicates that the ARI capable hierarchy is preserved across certain power state transitions.
1745 #define PCIEIP_REG_SRIOV_CONTROL_VF_ENABLE (0x1<<0) // Enables/Disables VFs.
1747 #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_EN (0x1<<1) //
1749 #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_INTERR_EN (0x1<<2) // This bit has no effect in IP. However spec has defined it to be RW.
1751 #define PCIEIP_REG_SRIOV_CONTROL_VF_MSE (0x1<<3) // When set, memory space is enabled for VFs.
1753 #define PCIEIP_REG_SRIOV_CONTROL_ARI_CAPABLE_HIER (0x1<<4) // When set, the device is permitted to locate VF in Func Number 8 to 255. This field is RW only in PF0 and is RO in all other PFs.
1794 #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH (0x1<<3) // VF BAR0 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1802 #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH (0x1<<3) // VF BAR1 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1810 #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH (0x1<<3) // VF BAR2 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1815 #define PCIEIP_REG_VF_BAR0_MEM_SPACE (0x1<<0) // This bit indicates that VF_BAR0 maps a memory space and is always read as 0.
1819 #define PCIEIP_REG_VF_BAR0_VF_PREFETCH (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x608).
1828 #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH (0x1<<3) // VF BAR3 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1836 #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH (0x1<<3) // VF BAR4 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1841 #define PCIEIP_REG_VF_BAR2_MEM_SPACE (0x1<<0) // This bit indicates that VF_BAR2 maps a memory space and is always read as 0.
1845 #define PCIEIP_REG_VF_BAR2_VF_PREFETCH (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x608).
1854 #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH (0x1<<3) // VF BAR5 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1865 #define PCIEIP_REG_VF_BAR4_MEM_SPACE (0x1<<0) // This bit indicates that VF_BAR4 maps a memory space and is always read as 0.
1869 #define PCIEIP_REG_VF_BAR4_VF_PREFETCH (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x620).
1884 #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE (0x1<<0) // No ST Mode Supported.
1886 #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC (0x1<<1) // Interrupt Vector Mode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
1888 #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC (0x1<<2) // Device Specific Mode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
1890 #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH (0x1<<8) // Extended TPH Requester Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
1892 #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0 (0x1<<9) // ST Table Location Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
1894 #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1 (0x1<<10) // ST Table Location Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
1906 #define PCIEIP_REG_PTM_EXTENDED_CAP_CAP_VER (0xf<<16) // PTM Capability version. Hardwired to 0x1.
1916 #define PCIEIP_REG_PTM_CAP_REG_PTM_REQUESTER_CAPABLE (0x1<<0) // Device implements the PTM Requester role.
1919 #define PCIEIP_REG_PTM_CTRL_REG_PTM_ENABLED (0x1<<0) // When Set, Function is permitted to participate in PTM mechanism
1921 #define PCIEIP_REG_PTM_CTRL_REG_ROOT_SELECT (0x1<<1) // If Set, device is the PTM Root.
1930 #define PCIEIP_REG_ATS_CAP_ATSCAP_VER (0xf<<16) // ATS Capability version. Hardwired to 0x1.
1937 #define PCIEIP_REG_ATS_CONTROL_ATS_PAGE_ALIGNED_REQ (0x1<<5) // This bit when set indicates Untranslated Address is always aligned to 4K boundary. the value in this field is controlled by programming in private register at 0x630
1945 #define PCIEIP_REG_ATS_CONTROL_ATS_ENABLE (0x1<<31) // When set, function is enabled to cache translations.
1950 #define PCIEIP_REG_RBAR_EXT_CAP_RBARCAP_VER (0xf<<16) // RBAR Capability version. Hardwired to 0x1.
1957 #define PCIEIP_REG_RBAR_CAP_SIZE_1M_CAPABILITY (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value reflected here is from corresponding bit in private register.
1959 #define PCIEIP_REG_RBAR_CAP_SIZE_2M_CAPABILITY (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value reflected here is from corresponding bit in private register.
1961 #define PCIEIP_REG_RBAR_CAP_SIZE_4M_CAPABILITY (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value reflected here is from corresponding bit in private register.
1963 #define PCIEIP_REG_RBAR_CAP_SIZE_8M_CAPABILITY (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value reflected here is from corresponding bit in private register.
1965 #define PCIEIP_REG_RBAR_CAP_SIZE_16M_CAPABILITY (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value reflected here is from corresponding bit in private register.
1967 #define PCIEIP_REG_RBAR_CAP_SIZE_32M_CAPABILITY (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value reflected here is from corresponding bit in private register.
1969 #define PCIEIP_REG_RBAR_CAP_SIZE_64M_CAPABILITY (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value reflected here is from corresponding bit in private register.
1971 #define PCIEIP_REG_RBAR_CAP_SIZE_128M_CAPABILITY (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value reflected here is from corresponding bit in private register.
1973 #define PCIEIP_REG_RBAR_CAP_SIZE_256M_CAPABILITY (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value reflected here is from corresponding bit in private register.
1975 #define PCIEIP_REG_RBAR_CAP_SIZE_512M_CAPABILITY (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value reflected here is from corresponding bit in private register.
1977 #define PCIEIP_REG_RBAR_CAP_SIZE_1G_CAPABILITY (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value reflected here is from corresponding bit in private register.
1993 #define PCIEIP_REG_TPH_EXTENDED_CAP_CAP_VER (0xf<<16) // LTR Capability version. Hardwired to 0x1.
1998 #define PCIEIP_REG_TPH_REQ_CAPABILITY_NO_ST_MODE_SUPPORTED (0x1<<0) // Function supports NO ST mode of operation. This mode is required to be supported.
2000 #define PCIEIP_REG_TPH_REQ_CAPABILITY_INT_VECTOR_MODE_SUPPORTED (0x1<<1) // If Set function supports Interrupt Vector mode of operation. Value in this field can be programmed through TPH_CAP register in private space.
2002 #define PCIEIP_REG_TPH_REQ_CAPABILITY_DEVICE_MODE_SUPPORTED (0x1<<2) // If Set function supports device mode of operation.
2006 #define PCIEIP_REG_TPH_REQ_CAPABILITY_EXTENDED_TPH_REQ_SUPP (0x1<<8) // If Set function is capable of generating Req's with TPH TLP prefix.
2029 #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_2_SUPP (0x1<<0) // Advertize L1_2 capability support for PM
2031 #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_1_SUPP (0x1<<1) // Advertize L1_1 capability support for PM
2033 #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_2_SUPP (0x1<<2) // Advertize L1_2 capability support for ASPM
2035 #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_1_SUPP (0x1<<3) // Advertize L1_1 capability support for ASPM
2037 #define PCIEIP_REG_PML1_SUB_CAP_REG_CLKREQ_L1SUB_SUPP (0x1<<4) // Clkreq based L1 substates is supported.
2045 #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_0 (0x1<<18) //
2052 #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_2_ENABLE (0x1<<0) // When set, PM L1.2 is enabled.
2054 #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_1_ENABLE (0x1<<1) // When set, PM L1.1 is enabled.
2056 #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_2_ENABLE (0x1<<2) // When set, ASPM L1.2 is enabled.
2058 #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_1_ENABLE (0x1<<3) // When set, ASPM L1.1 is enabled.
2060 #define PCIEIP_REG_PML1_SUB_CONTROL1_L1PM_SUB_MECH (0x1<<4) // Value of 0 is hardwired indicating support for only CLKREQ based PM mechanism.
2075 #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_A (0x1<<2) //
2116 #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS (0x1<<7) // Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky.
2118 #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT (0xf<<8) // Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky.
2124 #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This register field is sticky.
2126 #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT (0xff<<8) // Time-based Duration Select. Selects the duration of time-based analysis. When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - Else: Reserved Note: This register field is sticky.
2132 #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE (0x1<<0) // Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details, see the EINJ0_CRC_REG register. Note: This register field is sticky.
2134 #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE (0x1<<1) // Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details, see the EINJ1_SEQNUM_REG register. Note: This register field is sticky.
2136 #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE (0x1<<2) // Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details, see the EINJ2_DLLP_REG register. Note: This register field is sticky.
2138 #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE (0x1<<3) // Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details, see the EINJ3_SYMBOL_REG register. Note: This register field is sticky.
2140 #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE (0x1<<4) // Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details, see the EINJ4_FC_REG register. Note: This register field is sticky.
2142 #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE (0x1<<5) // Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details, see the EINJ5_SP_TLP_REG register. Note: This register field is sticky.
2144 #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE (0x1<<6) // Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0. You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0. For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers. Note: This register field is sticky.
2154 #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE (0x1<<8) // Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky.
2180 #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP (0x1<<8) // Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky.
2196 #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_CAP_VER (0xf<<16) // Capability version. Hardwired to 0x1.
2202 #define PCIEIP_REG_LINK_CONTROL3_PERFORM_EQ (0x1<<0) // N/A to endpoints
2204 #define PCIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN (0x1<<1) // N/A to endpoints
2218 #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED0 (0x1<<15) // Reserved
2226 #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED1 (0x1<<31) // Reserved
2236 #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED2 (0x1<<15) // Reserved
2244 #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED3 (0x1<<31) // Reserved
2254 #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED4 (0x1<<15) // Reserved
2262 #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED5 (0x1<<31) // Reserved
2267 #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL (0x1<<8) // Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. Note: This register field is sticky.
2278 #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED6 (0x1<<15) // Reserved
2286 #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED7 (0x1<<31) // Reserved
2295 #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED6 (0x1<<15) // Reserved
2303 #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED7 (0x1<<31) // Reserved
2312 #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED10 (0x1<<15) // Reserved
2320 #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED11 (0x1<<31) // Reserved
2329 #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED12 (0x1<<15) // Reserved
2337 #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED13 (0x1<<31) // Reserved
2346 #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED14 (0x1<<15) // Reserved
2354 #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED15 (0x1<<31) // Reserved
2359 #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN (0x1<<16) // Force Detect Lane Enable. When this bit is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky.
2361 #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM (0x3<<20) // Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The core selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 16 5.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32 Note: This register field is sticky.
2363 #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL (0x3<<22) // Low Power Entry Interval Time. Interval Time that the core starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640ns Note: This register field is sticky.
2366 #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM (0x1<<0) // Hold and Release LTSSM. For as long as this register is '1', the core stays in the current LTSSM. Note: This register field is sticky.
2368 #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST (0x1<<1) // Recovery Request. When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.
2370 #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN (0x1<<2) // Force LinkDown. When this bit is set and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State. Note: This register field is sticky.
2372 #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG (0x1<<8) // Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state. Note: This register field is sticky.
2374 #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT (0x1<<9) // Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state. Note: This register field is sticky.
2376 #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT (0x1<<10) // Detect Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky.
2378 #define PCIEIP_REG_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE (0x1<<16) // Framing Error Recovery Disable. This bit forces a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky.
2381 #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT (0xf<<0) // Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky.
2383 #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY (0x1<<16) // PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky.
2385 #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE (0x1<<17) // PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky.
2387 #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID (0x1<<18) // PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky.
2389 #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE (0x1<<19) // PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky.
2391 #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE (0x1<<20) // PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky.
2398 #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR (0x1<<7) // Framing Error. Indicates Framing Error detection status.
2402 #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL (0x1<<15) // Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky.
2411 #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG (0x1<<12) // PME Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.
2422 #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1 (0x1<<26) // FC_INIT1. Indicates the core is in FC_INIT1(VC0) state. Note: This register field is sticky.
2424 #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2 (0x1<<27) // FC_INIT2. Indicates the core is in FC_INIT2(VC0) state. Note: This register field is sticky.
2427 #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC (0x7<<0) // Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7 Note: This register field is sticky.
2429 #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE (0x1<<3) // Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: Tx Note: This register field is sticky.
2431 #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE (0x3<<4) // Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: Completion Note: This register field is sticky.
2433 #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD (0x1<<6) // Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data Credit Note: This register field is sticky.
2442 #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS (0x1<<7) // Malformed TLP Status. Indicates malformed TLP has occurred.
2445 #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL (0xf<<0) // EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky.
2447 #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_RATE_SEL (0x1<<4) // EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed - 0x1: 16.0GT/s Speed Note: This register field is sticky.
2451 #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE (0x1<<23) // FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky.
2466 #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE (0x1<<28) // Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky.
2468 #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE (0x1<<29) // Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This register field is sticky.
2470 #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE (0x1<<30) // Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This register field is sticky.
2479 #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE (0x1<<28) // Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky.
2482 #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_SEQUENCE (0x1<<0) // EQ Sequence. Indicates that the core is starting the equalization sequence. Note: This register field is sticky.
2484 #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO (0x3<<1) // EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky.
2486 #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION (0x1<<4) // EQ Rule A Violation. Indicates that coefficient rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky.
2488 #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION (0x1<<5) // EQ Rule B Violation. Indicates that coefficient rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky.
2490 #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION (0x1<<6) // EQ Rule C Violation. Indicates that coefficient rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky.
2492 #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT (0x1<<7) // EQ Reject Event. Indicates that the core receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky.
2531 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX (0x1<<0) // Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky.
2533 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER (0x1<<1) // Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky.
2535 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND (0x1<<2) // Error correction disable for AXI bridge outbound request path. Note: This register field is sticky.
2537 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE (0x1<<3) // Error correction disable for DMA write engine. Note: This register field is sticky.
2539 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX (0x1<<4) // Error correction disable for layer 2 Tx path. Note: This register field is sticky.
2541 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX (0x1<<5) // Error correction disable for layer 3 Tx path. Note: This register field is sticky.
2543 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX (0x1<<6) // Error correction disable for Adm Tx path. Note: This register field is sticky.
2545 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX (0x1<<16) // Global error correction disable for all Rx layers. Note: This register field is sticky.
2547 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION (0x1<<17) // Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky.
2549 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST (0x1<<18) // Error correction disable for AXI bridge inbound request path. Note: This register field is sticky.
2551 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ (0x1<<19) // Error correction disable for DMA read engine. Note: This register field is sticky.
2553 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX (0x1<<20) // Error correction disable for layer 2 Rx path. Note: This register field is sticky.
2555 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX (0x1<<21) // Error correction disable for layer 3 Rx path. Note: This register field is sticky.
2557 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX (0x1<<22) // Error correction disable for ADM Rx path. Note: This register field is sticky.
2560 #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS (0x1<<0) // Clear all correctable error counters.
2562 #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS (0x1<<4) // Enable correctable errors counters. - 1: counters increment when the core detects a correctable error - 0: counters are frozen The counters are enabled by default.
2564 #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION (0xf<<20) // Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2571 #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION (0xf<<20) // Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2576 #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS (0x1<<0) // Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared.
2578 #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS (0x1<<4) // Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default.
2580 #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION (0xf<<20) // Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2587 #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION (0xf<<20) // Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2592 #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN (0x1<<0) // Error injection global enable. When set enables the error insertion logic.
2601 #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR (0xf<<4) // Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2605 #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR (0xf<<20) // Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2610 #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR (0xf<<4) // Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2614 #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR (0xf<<20) // Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved
2619 #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN (0x1<<0) // Write '1' to enable the core enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky.
2621 #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN (0x1<<1) // Write '1' to enable the core to bring the link down when the core enters RASDP error mode. Note: This register field is sticky.
2624 #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR (0x1<<0) // Write '1' to take the core out of RASDP error mode. The core will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.
2644 #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE (0x1<<0) // PTM Requester Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
2646 #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE (0x1<<1) // PTM Responder Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
2648 #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE (0x1<<2) // PTM Root Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
2653 #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE (0x1<<0) // PTM Enable. When set, this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.
2655 #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT (0x1<<1) // PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
2674 #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Requester will automatically atempt to update it's context every 10ms. For more details, see the PTM section in the Databook. Note: This register field is sticky.
2676 #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE (0x1<<1) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is self clearing. For more details, see the PTM section in the Databook.
2678 #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS (0x1<<2) // PTM Fast Timers - Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output will go high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The requester operation will otherwise remain the same. For more details, see the PTM section in the Databook. Note: This register field is sticky.
2683 #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID (0x1<<0) // PTM Requester Context Valid - Indicate that the Timing Context is valid. For more details, see the PTM section in the Databook.
2685 #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or not a Manual Update can be signalled. For more details, see the PTM section in the Databook.
2701 #define PCIEIP_REG_CONFIG_2_BAR1_64ENA (0x1<<4) // This bit enables the advertisement of bar_1 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_1. This value is sticky and only reset by HARD Reset. If set it is 64bit addressing.
2703 #define PCIEIP_REG_CONFIG_2_EXP_ROM_RETRY (0x1<<5) // This bit will force the PCI bus to re-try all cycles to the current Expansion ROM BAR area. When this bit is set, then no Expansion ROM interrupt will be generated. This bit must be cleared to allow the interrupt to be generated.
2705 #define PCIEIP_REG_CONFIG_2_CFG_CYCLE_RETRY (0x1<<6) // This bit will force the PCI bus to re-try all cycles to the configuration space until it is cleared. This is used to block the host from accessing context if needed to prevent reading of false data. This bit may be used in combination with the FIRST_CFG_DONE bit below to prevent changing of the configuration space values after they have be read by the system. Normally this bit will be set by the firmware while the configuration space is programmed. This bit also exists in each VF and can be used to control individual VF.
2707 #define PCIEIP_REG_CONFIG_2_FIRST_CFG_DONE (0x1<<7) // This bit will be set the first time since PCI reset that a configuration cycle hass been done by the PCI block. This may be used by firmware to detect if the host already has the reset values of the configuration space. this may happen if the NVM system is much slower than expected. Tn this case, the firmware can choose to not exist or show an error on LEDs, etc. instead of changing the configuratio space values that the host ahas already read.
2711 #define PCIEIP_REG_CONFIG_2_BAR_PREFETCH (0x1<<16) // This bit when set is reflected in bit 3 of bar_1 and indicates that the BAR is pre-fetchable
2721 #define PCIEIP_REG_CONFIG_3_VF_MEM_DSICARD (0x1<<16) // This bits exists in VF only Setting this bit to '1' forces the VF to drop any mem request that it receives. UR completion will be returned for mem read requests. This bit along with the CRS bit can be used by software to control when VF is up.
2725 #define PCIEIP_REG_CONFIG_3_FORCE_PME (0x1<<24) // Setting this bit to '1' forces the PME message to be send This simulates the PME event. The PME control bits in the configuration space still control the output normally. This value is sticky and only reset by HARD Reset.
2727 #define PCIEIP_REG_CONFIG_3_PME_STATUS (0x1<<25) // This bit indicates the current state of the PME_STATUS bit in configuration space. This value is sticky and only reset by HARD Reset.
2729 #define PCIEIP_REG_CONFIG_3_PME_ENABLE (0x1<<26) // This is the current state of the PME_ENABLE bit in configuration space. This value is sticky and only reset by HARD Reset.
2733 #define PCIEIP_REG_CONFIG_3_UNUSED1 (0x1<<29) //
2735 #define PCIEIP_REG_CONFIG_3_VAUX_PRESENT (0x1<<30) // This bit indicates the input level on the VAUX_PRESENT pin. This indicates if the VAUX supply is available in the current configuration. The value also controls the value of the Power Management PME_SUPPORT register in configuration space. Field is local in each PF
2737 #define PCIEIP_REG_CONFIG_3_PCI_POWER (0x1<<31) // PCI_POWER This bit indicates the current state of power on the PCI bus. If this bit is '1', it indicates that the PCI padring has power. If this bit is '0', it indicates that the PCI padring does not have power (D3 Cold).
2769 #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_UNUSED0 (0x1<<15) //
2789 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB (0x1<<4) // Up to 1MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2791 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB (0x1<<5) // Up to 2MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2793 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB (0x1<<6) // Up to 4MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2795 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB (0x1<<7) // Up to 8MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2797 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB (0x1<<8) // Up to 16MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2799 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB (0x1<<9) // Up to 32MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2801 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB (0x1<<10) // Up to 64MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2803 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB (0x1<<11) // Up to 128MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2805 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB (0x1<<12) // Up to 256MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2807 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB (0x1<<13) // Up to 512MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2809 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB (0x1<<14) // Up to 1GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2811 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB (0x1<<15) // Up to 2GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2813 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB (0x1<<16) // Up to 4GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2815 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB (0x1<<17) // Up to 8GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2817 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB (0x1<<18) // Up to 16GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2819 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB (0x1<<19) // Up to 32GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2821 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB (0x1<<20) // Up to 64GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2823 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB (0x1<<21) // Up to 128GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2825 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB (0x1<<22) // Up to 256GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2827 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB (0x1<<23) // Up to 512GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
2830 #define PCIEIP_REG_REG_VPD_INTF_INTF_REQ (0x1<<0) // This bit will be set if there is a pending request for action by the firmware to handle a Vital Product Data interface. This bit is set when the vpd_flag_addr register in configuation space is written. This bit is cleared when the vpd_data register below is written.
2844 #define PCIEIP_REG_REG_VPD_ADDR_FLAG_WR (0x1<<31) // This bit indicates if the host is requesting a read or a write cycle. If this bit is set, then the host has requested the data in the vpd_data register to be passed to the NVM interface. If the value is clear, then the host has requested the data to be passed from the NVM interface to the vpd_data register. The value of this bit is only valid if the INTF_REQ bit is set. This bit is a RO copy of the flag bit in the vpd_flag_addr register in configuration space.
2869 #define PCIEIP_REG_REG_ID_VAL4_MSI_PV_MASK_CAPABLE (0x1<<8) // This value controls the per vector masking capability in the MSI control field
2875 #define PCIEIP_REG_REG_ID_VAL4_MSI_ENABLE (0x1<<15) // This bit indicates the programming of the MSI Enable bit in PCI configuration space. If this bit is set, it means that the interrupt output is masked and all interrupts must be indicated with MSI cycles.
2880 #define PCIEIP_REG_REG_ID_VAL5_D1_SUPPORT (0x1<<0) // This bit indicates whether the device supports the D1 power management state. It is reflected in the D1_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
2882 #define PCIEIP_REG_REG_ID_VAL5_D2_SUPPORT (0x1<<1) // This bit indicates whether the device supports the D2 power management state. It is reflected in the D2_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
2884 #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D0 (0x1<<2) // This bit indicates whether the device supports transmiting PME message from the D0 power state. It is reflected in the PME_IN_D0 bit in the configuration space. This value is sticky and only reset by HARD Reset.
2886 #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D1 (0x1<<3) // This bit indicates whether the device supports transmiting PME message from the D1 power state. It is reflected in the PME_IN_D1 bit in the configuration space. This value is sticky and only reset by HARD Reset.
2888 #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D2 (0x1<<4) // This bit indicates whether the device supports transmiting PME message from the D2 power state. It is reflected in the PME_IN_D2 bit in the configuration space. This value is sticky and only reset by HARD Reset.
2890 #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D3_HOT (0x1<<5) // This bit indicates whether the device supports transmiting PME message from the D3hot power state. It is reflected in the PME_IN_D3_HOT bit in the configuration space. This value is sticky and only reset by HARD Reset.
2894 #define PCIEIP_REG_REG_ID_VAL5_NO_SOFT_RESET (0x1<<9) // This indicates function does not perform an internal reset when transitioning from D3 to D0. the value is reflected in corresponding field in PM CSR.
2933 #define PCIEIP_REG_REG_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (0x1<<5) // This bit when set, hides any PCIE spec 2.0 defined registers (bits) and enables design to be 1.1 compliant
2935 #define PCIEIP_REG_REG_PCIE_CAPABILITY_ASPM_OPTIONALITY (0x1<<6) // This bit when set, sets the ASPM optionality bit in the Link cap register. This bit is recommended to be set for newer PCIe devices and required for 3.0 compliant devices
2942 #define PCIEIP_REG_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (0x1<<5) // This controls the value of this field in the DEVICE_CAP register in the configuration field
2950 #define PCIEIP_REG_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (0x1<<15) // This controls value in configuration space
2954 #define PCIEIP_REG_REG_DEVICE_CAPABILITY_FLR_SUPPORTED (0x1<<28) // This controls value in configuration space and allows FLR capability to be advertized by DUT.
2959 #define PCIEIP_REG_REG_DEVICE_CONTROL_FLR_IN_PROGRESS (0x1<<27) // When FLR is initiated, this register will read a value of 1 indicating that the Function is in FLR state. Func can be brought out of FLR state either by writing 1 to this register (at least 50 ms after FLR was initiated), or it can also be cleared automatically after 55 ms if auto_clear bit in private reg space is set. This bit also exists in VF register space
2961 #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED1 (0x1<<28) //
2963 #define PCIEIP_REG_REG_DEVICE_CONTROL_SRIOV_DISABLE_IN_PROGRESS (0x1<<29) // When VF Enable is cleared(after it was previously set), this register will read a value of 1, indicating that all the VFs that belong to this PF should be flushed. Software should clear this bit within 1 second of VF Enable being set by writing a 1 to it, so that VFs are visible to the system again.
2970 #define PCIEIP_REG_REG_LINK_CAPABILITY_CLK_POWER_MGMT (0x1<<9) // This controls the value of the same field in the link_capability register in configuration space
2987 #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_64ENA (0x1<<4) // This bit enables the advertisement of bar_3 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_3. This value is sticky and only reset by HARD Reset. Default is 64bit addressing.
2989 #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_PREFETCH (0x1<<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that the BAR is pre-fetchable
2996 #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (0x1<<4) // Completion Timeout Disable Supported, Controls value in same field in the config space
3000 #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_IDO_SUPPORTED (0x1<<10) // This bit is valid only if IDO_Enabled is defined in version.v. When this bit is set, IDO feature is made visible to external config access.
3010 #define PCIEIP_REG_REG_PCIE_LINK_CONTROL_RC_RCB (0x1<<0) // Not supported for EP
3013 #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_RC_DL_ACTIVE_CAP (0x1<<0) // RC only. If set, indicates dl_active capability at bit 20 of link_capability register. For EP, this field will not has any effect in link_capability register.
3015 #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_SLOT_CLK_CONFIG (0x1<<1) // If set, indicates device use the same reference clock that the platform provides on the connector.
3020 #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_64ENA (0x1<<4) // This bit enables the advertisement of bar_5 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_5. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3022 #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_PREFETCH (0x1<<5) // This bit when set is reflected in bit 3 of bar_5 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3027 #define PCIEIP_REG_REG_ROOT_CAP_RC_CRS_CAP (0x1<<0) // This register is reserved for RC only. It is not applicable for EP.
3029 #define PCIEIP_REG_REG_ROOT_CAP_RC_LTR_SUPPORTED (0x1<<1) // This register is reserved for RC only. It is not applicable for EP.
3031 #define PCIEIP_REG_REG_ROOT_CAP_RC_CLKREQ_SUPPORTED (0x1<<2) // This register is reserved for RC only. It is not applicable for EP.
3036 #define PCIEIP_REG_REG_ROOT_CONTROL_RC_CLKREQ_ENABLED (0x1<<0) // This register is reserved for RC only. It is not applicable for EP.
3052 #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_CHK_CAP (0x1<<0) // This value controls the corresponding bit in the ADV_ERR_CAP _CONTROL (0x128)
3054 #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_GEN_CAP (0x1<<1) // This value controls the corresponding bit in the ADV_ERR_CAP _CONTROL (0x128)
3109 #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_2_SUPP (0x1<<0) // Advertize L1_2 capability support for PM
3111 #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_1_SUPP (0x1<<1) // Advertize L1_1 capability support for PM
3113 #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_2_SUPP (0x1<<2) // Advertize L1_2 capability support for ASPM
3115 #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_1_SUPP (0x1<<3) // Advertize L1_1 capability support for ASPM
3117 #define PCIEIP_REG_REG_L1SUB_CAP_CLKREQ_L1SUB_SUPP (0x1<<4) // Clkreq based L1 substates is supported.
3125 #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_0 (0x1<<18) //
3137 #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_PWR_SYSTEM_ALLOC (0x1<<0) // This bit controls the system alloc bit in the PWR_BDGT_CAP (0x15c) in the configuration space
3153 #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_EN1 (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transactions received in Rx direction are compared against the user defined address range before it is forwarded to user. If requests do not fall in this USer BAR area, the request is target aborted.
3165 #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_EN2 (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transactions received in Rx direction are compared against the user defined address range before it is forwarded to user. If requests do not fall in this USer BAR area, the request is target aborted.
3176 #define PCIEIP_REG_REG_PTM_CAP_PTM_REQ_CAPABLE (0x1<<0) // This field will be reflected in the PTM capability register.
3178 #define PCIEIP_REG_REG_PTM_CAP_PTM_CAP_SUPP (0x1<<1) // This field will be reflected in the PTM capability register. Field indicates device is capable of generating PTM requests.
3181 #define PCIEIP_REG_REG_TPH_CAP_TPH_INT_VEC_MODE_SUPP (0x1<<0) // when Set, it indicates function supports Interrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3183 #define PCIEIP_REG_REG_TPH_CAP_TPH_DEV_SPEC_MODE (0x1<<1) // When Set, it indicates function suports device specific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3192 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1M_CAPABILITY (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3194 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_2M_CAPABILITY (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3196 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_4M_CAPABILITY (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3198 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_8M_CAPABILITY (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3200 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_16M_CAPABILITY (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3202 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_32M_CAPABILITY (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3204 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_64M_CAPABILITY (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3206 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_128M_CAPABILITY (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3208 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_256M_CAPABILITY (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3210 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512M_CAPABILITY (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3212 #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1G_CAPABILITY (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3232 #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_64ENA (0x1<<4) // This bit enables the advertisement of VF BAR0 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR0. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3234 #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_PREFETCH (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3240 #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_64ENA (0x1<<12) // This bit enables the advertisement of VF BAR2 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR2. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3242 #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_PREFETCH (0x1<<13) // This bit when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3254 #define PCIEIP_REG_REG_VF_CAP_EN_VF_CAP_EN (0x1<<0) // This value controls the read value of the next capability pointers in the VF configuration space and allows each extra capability to be independently disabled by manipulation of the next pointer values. The read values for each enable combination is shown below. PCIE capability is always enabled. Bit 0 enables the MSIX capability. This value is sticky and only reset by HARD Reset. Value affects only the VF's that belong to the PF.
3278 #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_64ENA (0x1<<4) // This bit enables the advertisement of VF BAR4 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR4. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3280 #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_PREFETCH (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3295 #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_PAGE_ALIGNED_REQ (0x1<<5) // This register controls the corresponding value in the ATS capability register. This field qhen Set, indicates the Untranslated Address always aligns to a 4K byte boundary. Setting this bit is recommended.
3300 #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_INT_VEC_MODE_SUPP (0x1<<0) // when Set, it indicates function supports Interrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3302 #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_DEV_SPEC_MODE (0x1<<1) // When Set, it indicates function suports device specific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3310 #define PCIEIP_REG_REG_VFTPH_CAP_TPH_SUPP_INVF (0x1<<31) // This field when set enables TPH capability in all the VF's.
3323 #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN (0x1<<15) // Force Link. The core supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the core to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the core to transmit the command specified by the Forced Link Command field. This is a self-clearing register field. Reading from this register field always returns a "0".
3340 #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky.
3343 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ (0x1<<0) // Vendor Specific DLLP Request. When software writes a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always returns a '0'.
3345 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE (0x1<<1) // Scramble Disable. Turns off data scrambling. Note: This register field is sticky.
3347 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE (0x1<<2) // Loopback Enable. Turns on loopback. For more details, see "Loopback". For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration). M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start. Note: This register field is sticky.
3349 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT (0x1<<3) // Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky.
3351 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN (0x1<<5) // DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the core does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky.
3353 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE (0x1<<6) // LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky.
3355 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE (0x1<<7) // Fast Link Mode. Sets all internal timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : 1024) for all internal timers. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to "1". For more details, see "SII Signals: Diagnostic Control". For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32). Note: This register field is sticky.
3359 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE (0x3f<<16) // Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported) This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
3361 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE (0x1<<24) // BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
3363 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE (0x1<<25) // CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
3365 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH (0x1<<26) // EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky.
3367 #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE (0x1<<27) // TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
3372 #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE (0x1<<24) // Flow Control Disable. Prevents the core from sending FC DLLPs. Note: This register field is sticky.
3374 #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE (0x1<<25) // Ack/Nak Disable. Prevents the core from sending ACK and NAK DLLPs. Note: This register field is sticky.
3376 #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky.
3394 #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER (0x1<<15) // Disable FC Watchdog Timer. Note: This register field is sticky.
3417 #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN (0x1<<0) // Received TLP FC Credits Not Returned. Indicates that the core has sent a TLP but has not yet received an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.
3419 #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE (0x1<<1) // Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.
3421 #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY (0x1<<2) // Received Queue Not Empty. Indicates there is data in one or more of the receive buffers.
3425 #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the core calculates according to the PCIe specification. Note: This register field is sticky.
3450 #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4 (0x1<<20) // Reserved. Note: This register field is sticky.
3456 #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0 (0x1<<30) // TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky.
3458 #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q (0x1<<31) // VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robin Note: This register field is sticky.
3465 #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6 (0x1<<20) // Reserved. Note: This register field is sticky.
3476 #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8 (0x1<<20) // Reserved. Note: This register field is sticky.
3483 #define PCIEIP_REG_TL_CONTROL_0_PM_TL_IGNORE_REQS (0x1<<0) // When set the TL TX does not send out pending requests if PM requests to block TLPS. By default TL will send all pending dma requests and completions when PM requests it to prepare for leaving L0 before asserting tlp blocked. When this bit is set , if min credits are available, TL indicates to PM that TLP is blocked and does not send out any pending dma requests or completions.
3485 #define PCIEIP_REG_TL_CONTROL_0_MEMRD_1DW_CHK (0x1<<1) // Target mem Rd should not be greater than 1 DW if set.
3487 #define PCIEIP_REG_TL_CONTROL_0_MEMRD_3DW_CHK (0x1<<2) // Target mem Rd should not be greater than 3 DW if set.
3489 #define PCIEIP_REG_TL_CONTROL_0_MEMWR_1DW_CHK (0x1<<3) // Target mem Wr should not be greater than 1 DW if set.
3491 #define PCIEIP_REG_TL_CONTROL_0_EXPROM_3DW_CHK (0x1<<4) // Target Expansion ROM should not be greater than 3 DW if set.
3493 #define PCIEIP_REG_TL_CONTROL_0_MEMRD_16DW_CHK (0x1<<5) // Target mem Rd should not be greater than 16 DW if set .
3495 #define PCIEIP_REG_TL_CONTROL_0_MEMRD_4DW_CHK (0x1<<6) // Target mem Rd should not be greater than 4 DW if set .
3497 #define PCIEIP_REG_TL_CONTROL_0_MEMWR_4DW_CHK (0x1<<7) // Target mem Wr should not be greater than 4 DW if set .
3499 #define PCIEIP_REG_TL_CONTROL_0_MEMWR_32DW_CHK (0x1<<8) // Target mem Wr should not be greater than 32 DW if set .
3501 #define PCIEIP_REG_TL_CONTROL_0_MEMRD_32DW_CHK (0x1<<9) // Target mem Rd should not be greater than 32 DW if set .
3505 #define PCIEIP_REG_TL_CONTROL_0_RETAIN_RID (0x1<<12) // This bit if set will force DUT to not reset its RID after an FLR.
3507 #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_FLR_AFTER_55MS (0x1<<13) // If set, DUT will automatically exit FLR state after a 55ms timer expires.
3509 #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_CRS_POST_FLR (0x1<<14) // If set, DUT will automatically return Successful completion when it has completed FLR.
3511 #define PCIEIP_REG_TL_CONTROL_0_NO_CMPL_IN_FLR (0x1<<15) // If set, completions received for a function which is in FLR will not be directed to user.
3513 #define PCIEIP_REG_TL_CONTROL_0_CFG_FUNC_EN0 (0x1<<16) // If set, this causes func0 to be hidden
3515 #define PCIEIP_REG_TL_CONTROL_0_UNUSED_2 (0x1<<17) //
3517 #define PCIEIP_REG_TL_CONTROL_0_CFG_MSI_LOW_MODE (0x1<<18) // when set, forces MSI_En to low.
3519 #define PCIEIP_REG_TL_CONTROL_0_BEACON_MULTI_EN (0x1<<19) // When set Beacon is enabled for all lanes
3521 #define PCIEIP_REG_TL_CONTROL_0_BEACON_DIS (0x1<<20) // When set, Beacon generation is disabled
3523 #define PCIEIP_REG_TL_CONTROL_0_WAKE_L0_L1_EN (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bit is set and corresponding status is enabled
3525 #define PCIEIP_REG_TL_CONTROL_0_UNUSED_4 (0x1<<22) //
3527 #define PCIEIP_REG_TL_CONTROL_0_RST_IGNORE_DLPDOWN (0x1<<23) // When set, TL does not get reset on DLPDOWN and Pcie_rst_b does not get asserted on DLPDOWN
3529 #define PCIEIP_REG_TL_CONTROL_0_PM_DIS_L1_REENTRY (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 power state
3531 #define PCIEIP_REG_TL_CONTROL_0_PCIE_PHY_TX_SWING (0x1<<25) // This bit is used by PCIE SERDES to determine source of tx margin signals
3533 #define PCIEIP_REG_TL_CONTROL_0_PERST_B_80USSEL (0x1<<26) // Select the 150us delayed perst_b instead of the raw perst_b
3535 #define PCIEIP_REG_TL_CONTROL_0_REG_PERST_B_10MSSEL (0x1<<27) // Select the 10ms delayed perst_b instead of the raw perst_b
3537 #define PCIEIP_REG_TL_CONTROL_0_REG_SCND_RST_ON_HOT (0x1<<28) // In RC mode, when set, it enables pcie_scnd_rst_b to be asserted when Secondary reset bit in BridgeControl register is set.
3539 #define PCIEIP_REG_TL_CONTROL_0_REG_FORCE_SCND_RST (0x1<<29) // In RC mode, when set, it forces pcie_scnd_rst_b to be asserted
3544 #define PCIEIP_REG_TL_CONTROL_1_EN_4G_CHK (0x1<<0) // Enable check to determine if mem requests do not have upper 32 bits of address to be all 0
3546 #define PCIEIP_REG_TL_CONTROL_1_EN_4K_CHK (0x1<<1) // Enable checks to determine TLP doesn not cross 4k boundary
3548 #define PCIEIP_REG_TL_CONTROL_1_EN_BC_CHK (0x1<<2) // Enable check to determine if the length field and bytecount field are in sync
3550 #define PCIEIP_REG_TL_CONTROL_1_EN_BE_CHK (0x1<<3) // Enable check to determine if received TLP follows all the Byte enable rules
3552 #define PCIEIP_REG_TL_CONTROL_1_EN_EP_CHK (0x1<<4) // Enable check for Poisoned TLP
3554 #define PCIEIP_REG_TL_CONTROL_1_EN_MPS_CHECK (0x1<<5) // Enable Check for max payload size Violation
3556 #define PCIEIP_REG_TL_CONTROL_1_EN_RCB_CHK (0x1<<6) // Enable checks to determine completion TLPs do not violate RCB
3558 #define PCIEIP_REG_TL_CONTROL_1_EN_RTE_CHK (0x1<<7) // Enable Check to determine if the routing type is correct when receiving message TLP
3560 #define PCIEIP_REG_TL_CONTROL_1_EN_TAC_CHK (0x1<<8) // Enable Configuration attribute and class check
3562 #define PCIEIP_REG_TL_CONTROL_1_EN_FC_CHK (0x1<<9) // Enable Flow Control Check
3564 #define PCIEIP_REG_TL_CONTROL_1_EN_TO_CHK (0x1<<10) // Enable Completion Timeout Check( This bit is no longer used, instead bit defined by ECN 1.1 is used)
3566 #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_1 (0x1<<11) // This bit is used to disable function 1. Bit 17 of 800 can also be used. That bit is retained for software compatibility purpose.
3568 #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_2 (0x1<<12) // This bit is used to disable function 2.
3570 #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_3 (0x1<<13) // This bit is used to disable function 3.
3572 #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_4 (0x1<<14) // This bit is used to disable function 4.
3574 #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_5 (0x1<<15) // This bit is used to disable function 5.
3576 #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_6 (0x1<<16) // This bit is used to disable function 6.
3578 #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_7 (0x1<<17) // This bit is used to disable function 7.
3580 #define PCIEIP_REG_TL_CONTROL_1_RESERVED (0x1<<18) //
3582 #define PCIEIP_REG_TL_CONTROL_1_REG_IGNORE_LTRWT_REQMT (0x1<<19) // When set, hardware will return completions and not wait for LTR message to be sent first even though device state may have changed to non-D0.
3584 #define PCIEIP_REG_TL_CONTROL_1_REG_REL_NPHCRDT_ECRCERR (0x1<<20) // Release NPH credit even if ECRC error is detected on NPH TLP.
3586 #define PCIEIP_REG_TL_CONTROL_1_REG_UCOR_INT_ERR_EN (0x1<<21) // Enables uncorrectable Internal Error Reporting if feature is implemented in h/w
3588 #define PCIEIP_REG_TL_CONTROL_1_REG_EN_BYTCNT_CHK (0x1<<22) // When enabled, hardware checks the bytecount field in completion headers.
3590 #define PCIEIP_REG_TL_CONTROL_1_REG_EN_LTR1 (0x1<<23) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h848 whenever the h/w asserts the user_send_ltr1 port. This bit is used only if LTR_ENABLED is defined in version.v and if h/w supports 3 LTR states.
3592 #define PCIEIP_REG_TL_CONTROL_1_EN_AUTOCRSCLR (0x1<<24) // This bit enables CRS status to be automatically cleared when internal timer is equal to either 1 second or a programmable value(which ever is smaller). This bit is used only if AutoCRSClrOn is defined in version.v
3594 #define PCIEIP_REG_TL_CONTROL_1_EN_LTR2 (0x1<<25) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h84c whenever the h/w asserts the user_send_ltr2 port. This bit is used only if LTR_ENABLED is defined in version.v
3598 #define PCIEIP_REG_TL_CONTROL_1_EN_ASPM_LTR (0x1<<30) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h844 and 'h848 whenever the DUT enters or leaves ASPM L1. This bit is used only if LTR_ENABLED is defined in version.v
3600 #define PCIEIP_REG_TL_CONTROL_1_SEND_IMMED_LTR (0x1<<31) // This bit instructs h/w to immediately send an LTR message with LTR values programmed in 'h840. This state has highest priority and when this bit is set, no other LTR message (other than those required by PCIE spec) will be sent. This bit is used only if LTR_ENABLED is defined in version.v
3603 #define PCIEIP_REG_TL_CONTROL_2_PES0_MASK (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3605 #define PCIEIP_REG_TL_CONTROL_2_FCPES0_MASK (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3607 #define PCIEIP_REG_TL_CONTROL_2_CTS0_MASK (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3609 #define PCIEIP_REG_TL_CONTROL_2_RX_UR0_MASK (0x1<<3) // Received UR Status, Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3611 #define PCIEIP_REG_TL_CONTROL_2_UCS0_MASK (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3613 #define PCIEIP_REG_TL_CONTROL_2_ROS0_MASK (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3615 #define PCIEIP_REG_TL_CONTROL_2_MTLPS0_MASK (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3617 #define PCIEIP_REG_TL_CONTROL_2_ECRCS0_MASK (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3619 #define PCIEIP_REG_TL_CONTROL_2_URES0_MASK (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3621 #define PCIEIP_REG_TL_CONTROL_2_RXTABRT0_MASK (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3623 #define PCIEIP_REG_TL_CONTROL_2_PES1_MASK (0x1<<10) // Poisoned Error Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3625 #define PCIEIP_REG_TL_CONTROL_2_FCPES1_MASK (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3627 #define PCIEIP_REG_TL_CONTROL_2_CTS1_MASK (0x1<<12) // Completer Timeout Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3629 #define PCIEIP_REG_TL_CONTROL_2_RX_UR1_MASK (0x1<<13) // Received UR Status, Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3631 #define PCIEIP_REG_TL_CONTROL_2_UCS1_MASK (0x1<<14) // Unexpected Completion Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3633 #define PCIEIP_REG_TL_CONTROL_2_ROS1_MASK (0x1<<15) // Receiver Overflow Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3635 #define PCIEIP_REG_TL_CONTROL_2_MTLPS1_MASK (0x1<<16) // Malformed TLP Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3637 #define PCIEIP_REG_TL_CONTROL_2_ECRCS1_MASK (0x1<<17) // ECRC Error TLP Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3639 #define PCIEIP_REG_TL_CONTROL_2_URES1_MASK (0x1<<18) // Unsupported Request Error Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3641 #define PCIEIP_REG_TL_CONTROL_2_RXTABRT1_MASK (0x1<<19) // Received target Abort Error Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3643 #define PCIEIP_REG_TL_CONTROL_2_RTAG_VAL_UNEXP_ATTN_MASK (0x1<<20) // rtag_val_unexp_attn Mask. If set, does not generate pcie_err_attn output when this error is seen.
3645 #define PCIEIP_REG_TL_CONTROL_2_TX_TAG_IN_USE_ATTN_MASK (0x1<<21) // tx_tag_in_use_attn Mask. If set, does not generate pcie_err_attn output when this error is seen.
3647 #define PCIEIP_REG_TL_CONTROL_2_DL_ERR_ATTN_MASK (0x1<<22) // DL Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
3649 #define PCIEIP_REG_TL_CONTROL_2_PHY_ERR_ATTN_MASK (0x1<<23) // PHY Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
3651 #define PCIEIP_REG_TL_CONTROL_2_TXINTF_OVERFLOW_ATTN_MASK (0x1<<24) //
3653 #define PCIEIP_REG_TL_CONTROL_2_BRIDGE_FORWARD_ERR_ATTN_MASK (0x1<<25) // If set, TX reports user interface violation
3655 #define PCIEIP_REG_TL_CONTROL_2_TTX_MPS_ERR_MASK (0x1<<26) //
3657 #define PCIEIP_REG_TL_CONTROL_2_TTX_MRRS_ERR_MASK (0x1<<27) //
3659 #define PCIEIP_REG_TL_CONTROL_2_TTX_4KBOUND_ERR_MASK (0x1<<28) //
3661 #define PCIEIP_REG_TL_CONTROL_2_TTX_UNKNOWNTYPE_ERR_MASK (0x1<<29) //
3672 #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN (0x1<<16) // Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the core. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
3674 #define PCIEIP_REG_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE (0x1<<17) // Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs, the core will clear the contents of this field; and a read to this field by your software will return a "0". To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the core clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W
3676 #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE (0x1<<18) // Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The core drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
3678 #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX (0x1<<19) // Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1"). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
3680 #define PCIEIP_REG_GEN2_CTRL_OFF_SEL_DEEMPHASIS (0x1<<20) // Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
3682 #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE (0x1<<21) // Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the core by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky.
3685 #define PCIEIP_REG_TL_CONTROL_3_EN_CMPL_RETRY (0x1<<0) // Enable Completion retry upon completion timeout. (feature is not supported, but bit is defined for posterity.)
3687 #define PCIEIP_REG_TL_CONTROL_3_EN_PSND_RETRY (0x1<<1) // Enable Poisoned completions retry. (feature is not supported but bit is defined for posterity.)
3689 #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_PHCRDT (0x1<<2) // Hold releasing of Posted header credit. When this bit is set, PH credits are not released by IP if FIFO at the DL-TL boundary reaches a critical threshold. This feature allows the FIFO to unload without overflowing
3691 #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_DMACRDT (0x1<<3) // Indicates no non-posted credit is available to user when bit is set. The credits to user are artificially reduced to 0, when FIFO at DL_TL boundary has reached a critical threshold and is in danger of overflowing. This feature allows the FIFO to unload without overflowing
3693 #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ADVERR_RX_ERR (0x1<<4) // Enable the reporting of receiver errors in the advanced error reporting structure.
3695 #define PCIEIP_REG_TL_CONTROL_3_REG_DIS_D0STATE_L1 (0x1<<5) // When set , disables entry into L1, due to function being in D0unint state. When set, it would require all enabled functions to be in D3hot to request L1 entry.
3701 #define PCIEIP_REG_TL_CONTROL_3_OVERRIDE_L1_ENTRY (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in non-d0 state.
3713 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP (0x1<<0) // This bit is set when h/w detects Poisoned Error Status . If set, h/w generates pcie_err_attn output .
3715 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Status . If set, h/w generates pcie_err_attn output .
3717 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT (0x1<<2) // This bit is set when h/w detects Completer Timeout Status . If set, h/w generates pcie_err_attn output .
3719 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT (0x1<<3) // This bit is set when h/w detects Receive UR Status. If set, h/w generates pcie_err_attn output .
3721 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status . If set, h/w generates pcie_err_attn output .
3723 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status . If set, h/w generates pcie_err_attn output .
3725 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP (0x1<<6) // This bit is set when h/w detects Malformed TLP Status . If set, h/w generates pcie_err_attn output .
3727 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status , If set, h/w generates pcie_err_attn output .
3729 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status . If set, h/w generates pcie_err_attn output .
3731 #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT (0x1<<9) //
3733 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP1 (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 1. If set, h/w generates pcie_err_attn output.
3735 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL1 (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 1. If set, h/w generates pcie_err_attn output .
3737 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT1 (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 1. If set, h/w generates pcie_err_attn output .
3739 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT1 (0x1<<13) // This bits is set when h/w detects Receive UR Status in function 1. If set, h/w generates pcie_err_attn output .
3741 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL1 (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 1. If set, h/w generates pcie_err_attn output when this error is seen.
3743 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW1 (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 1. If set, h/w generates pcie_err_attn output .
3745 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP1 (0x1<<16) // This bit is set when h/w detects Malformed TLP Status in function 1. If set, h/w generates pcie_err_attn output .
3747 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC1 (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 1. If set, h/w generates pcie_err_attn output .
3749 #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT1 (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in function1. If set, h/w generates pcie_err_attn output .
3751 #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT1 (0x1<<19) //
3753 #define PCIEIP_REG_TL_CTRLSTAT_5_TRX_ERR_UNEXP_RTAG (0x1<<20) //
3755 #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_ERR_NP_TAG_IN_USE (0x1<<21) //
3757 #define PCIEIP_REG_TL_CTRLSTAT_5_DL_ERR_ATTN (0x1<<22) //
3759 #define PCIEIP_REG_TL_CTRLSTAT_5_PHY_ERR_ATTN (0x1<<23) //
3761 #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_TXINTF_OVERFLOW (0x1<<24) //
3763 #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_BRIDGE_FORWARD_ERR (0x1<<25) //
3765 #define PCIEIP_REG_TL_CTRLSTAT_5_MPS_ERR_ATTN (0x1<<26) //
3767 #define PCIEIP_REG_TL_CTRLSTAT_5_MRRS_ERR_ATTN (0x1<<27) //
3769 #define PCIEIP_REG_TL_CTRLSTAT_5_BOUNDARY4K_ERR_ATTN (0x1<<28) //
3771 #define PCIEIP_REG_TL_CTRLSTAT_5_UNKNOWNTYPE_ERR_ATTN (0x1<<29) //
3784 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_8 (0x1<<0) // This bit is used to disable function 8.
3786 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_9 (0x1<<1) // This bit is used to disable function 9.
3788 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_10 (0x1<<2) // This bit is used to disable function 10.
3790 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_11 (0x1<<3) // This bit is used to disable function 11.
3792 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_12 (0x1<<4) // This bit is used to disable function 12.
3794 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_13 (0x1<<5) // This bit is used to disable function 13.
3796 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_14 (0x1<<6) // This bit is used to disable function 14.
3798 #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_15 (0x1<<7) // This bit is used to disable function 15.
3809 #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_REQ (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
3817 #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_REQ (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
3826 #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_REQ (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
3834 #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_REQ (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
3843 #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_REQ (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
3851 #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_REQ (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
3860 #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_REQ (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
3868 #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_REQ (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
3871 #define PCIEIP_REG_TL_FUNC345_MASK_PES2_MASK (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3873 #define PCIEIP_REG_TL_FUNC345_MASK_FCPES2_MASK (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3875 #define PCIEIP_REG_TL_FUNC345_MASK_CTS2_MASK (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3877 #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR2_MASK (0x1<<3) // Received UR Status, Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3879 #define PCIEIP_REG_TL_FUNC345_MASK_UCS2_MASK (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3881 #define PCIEIP_REG_TL_FUNC345_MASK_ROS2_MASK (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3883 #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS2_MASK (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3885 #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS2_MASK (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3887 #define PCIEIP_REG_TL_FUNC345_MASK_URES2_MASK (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3889 #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT2_MASK (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3891 #define PCIEIP_REG_TL_FUNC345_MASK_PES3_MASK (0x1<<10) // Poisoned Error Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
3893 #define PCIEIP_REG_TL_FUNC345_MASK_FCPES3_MASK (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
3895 #define PCIEIP_REG_TL_FUNC345_MASK_CTS3_MASK (0x1<<12) // Completer Timeout Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
3897 #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR3_MASK (0x1<<13) // Received UR Status, Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
3899 #define PCIEIP_REG_TL_FUNC345_MASK_UCS3_MASK (0x1<<14) // Unexpected Completion Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
3901 #define PCIEIP_REG_TL_FUNC345_MASK_ROS3_MASK (0x1<<15) // Receiver Overflow Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
3903 #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS3_MASK (0x1<<16) // Malformed TLP Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
3905 #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS3_MASK (0x1<<17) // ECRC Error TLP Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
3907 #define PCIEIP_REG_TL_FUNC345_MASK_URES3_MASK (0x1<<18) // Unsupported Request Error Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
3909 #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT3_MASK (0x1<<19) // Received target Abort Error Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
3911 #define PCIEIP_REG_TL_FUNC345_MASK_PES4_MASK (0x1<<20) // Poisoned Error Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
3913 #define PCIEIP_REG_TL_FUNC345_MASK_FCPES4_MASK (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
3915 #define PCIEIP_REG_TL_FUNC345_MASK_CTS4_MASK (0x1<<22) // Completer Timeout Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
3917 #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR4_MASK (0x1<<23) // Received UR Status, Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
3919 #define PCIEIP_REG_TL_FUNC345_MASK_UCS4_MASK (0x1<<24) // Unexpected Completion Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
3921 #define PCIEIP_REG_TL_FUNC345_MASK_ROS4_MASK (0x1<<25) // Receiver Overflow Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
3923 #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS4_MASK (0x1<<26) // Malformed TLP Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
3925 #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS4_MASK (0x1<<27) // ECRC Error TLP Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
3927 #define PCIEIP_REG_TL_FUNC345_MASK_URES4_MASK (0x1<<28) // Unsupported Request Error Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
3929 #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT4_MASK (0x1<<29) // Received target Abort Error Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
3934 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP2 (0x1<<0) // This bit is set when h/w detects Poisoned Error Status for Function 2. If set, h/w generates pcie_err_attn output .
3936 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL2 (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Status for Function 2. If set, h/w generates pcie_err_attn output .
3938 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 (0x1<<2) // This bit is set when h/w detects Completer Timeout Status for Function 2. If set, h/w generates pcie_err_attn output .
3940 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT2 (0x1<<3) // This bit is set when h/w detects Receive UR Status in Function 2. If set, h/w generates pcie_err_attn output .
3942 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL2 (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status for Function 2. If set, h/w generates pcie_err_attn output .
3944 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW2 (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status for Function 2. If set, h/w generates pcie_err_attn output .
3946 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP2 (0x1<<6) // This bit is set when h/w detects Malformed TLP Status for Function 2. If set, h/w generates pcie_err_attn output
3948 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC2 (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status for Function 2. If set, h/w generates pcie_err_attn output
3950 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT2 (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status for Function 2. If set, h/w generates pcie_err_attn output .
3952 #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (0x1<<9) //
3954 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP3 (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 3. If set, h/w generates pcie_err_attn output
3956 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL3 (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 3. If set, h/w generates pcie_err_attn output when this error is seen.
3958 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 3. If set, h/w generates pcie_err_attn output .
3960 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT3 (0x1<<13) // This bit is set when h/w detects Receive UR Status in function 3. If set, h/w generates pcie_err_attn output .
3962 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL3 (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 3. If set, h/w generates pcie_err_attn output .
3964 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW3 (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 3. If set, h/w generates pcie_err_attn output .
3966 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP3 (0x1<<16) // s bit is set when h/w detects Malformed TLP Status Status in function 3. If set, h/w generates pcie_err_attn output .
3968 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC3 (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 3. If set, h/w generates pcie_err_attn output .
3970 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT3 (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in function3. If set, h/w generates pcie_err_attn output when this error is seen.
3972 #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (0x1<<19) //
3974 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP4 (0x1<<20) // This bit is set when h/w detects Poisoned Error Status Status in function 4. If set, h/w generates pcie_err_attn output .
3976 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL4 (0x1<<21) // This bit is set when h/w detects Flow Control Protocol Error Status in function 4. If set, h/w generates pcie_err_attn output .
3978 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 (0x1<<22) // This bit is set when h/w detects Completer Timeout Status in function 4. If set, h/w generates pcie_err_attn output .
3980 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT4 (0x1<<23) // This bit is set when h/w detects Receive UR Statusin function 4. If set, h/w generates pcie_err_attn output .
3982 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL4 (0x1<<24) // This bit is set when h/w detects Unexpected Completion Status in function 4. If set, h/w generates pcie_err_attn output .
3984 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW4 (0x1<<25) // This bit is set when h/w detects Receiver Overflow Status in function 4. If set, h/w generates pcie_err_attn output .
3986 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP4 (0x1<<26) // This bit is set when h/w detects Malformed TLP Status in function 4. If set, h/w generates pcie_err_attn output .
3988 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC4 (0x1<<27) // This bit is set when h/w detects ECRC Error TLP Status in function 4. If set, h/w generates pcie_err_attn output .
3990 #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT4 (0x1<<28) // This bit is set when h/w detects Unsupported Request Error Status in function4. If set, h/w generates pcie_err_attn output .
3992 #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (0x1<<29) //
3997 #define PCIEIP_REG_TL_FUNC678_MASK_PES5_MASK (0x1<<0) // Poisoned Error Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
3999 #define PCIEIP_REG_TL_FUNC678_MASK_FCPES5_MASK (0x1<<1) // Flow Control Protocol Error Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4001 #define PCIEIP_REG_TL_FUNC678_MASK_CTS5_MASK (0x1<<2) // Completer Timeout Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4003 #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR5_MASK (0x1<<3) // Received UR Status, Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4005 #define PCIEIP_REG_TL_FUNC678_MASK_UCS5_MASK (0x1<<4) // Unexpected Completion Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4007 #define PCIEIP_REG_TL_FUNC678_MASK_ROS5_MASK (0x1<<5) // Receiver Overflow Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
4009 #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS5_MASK (0x1<<6) // Malformed TLP Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
4011 #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS5_MASK (0x1<<7) // ECRC Error TLP Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
4013 #define PCIEIP_REG_TL_FUNC678_MASK_URES5_MASK (0x1<<8) // Unsupported Request Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4015 #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT5_MASK (0x1<<9) // Received target Abort Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4017 #define PCIEIP_REG_TL_FUNC678_MASK_PES6_MASK (0x1<<10) // Poisoned Error Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4019 #define PCIEIP_REG_TL_FUNC678_MASK_FCPES6_MASK (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4021 #define PCIEIP_REG_TL_FUNC678_MASK_CTS6_MASK (0x1<<12) // Completer Timeout Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4023 #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR6_MASK (0x1<<13) // Received UR Status, Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4025 #define PCIEIP_REG_TL_FUNC678_MASK_UCS6_MASK (0x1<<14) // Unexpected Completion Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4027 #define PCIEIP_REG_TL_FUNC678_MASK_ROS6_MASK (0x1<<15) // Receiver Overflow Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4029 #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS6_MASK (0x1<<16) // Malformed TLP Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4031 #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS6_MASK (0x1<<17) // ECRC Error TLP Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4033 #define PCIEIP_REG_TL_FUNC678_MASK_URES6_MASK (0x1<<18) // Unsupported Request Error Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4035 #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT6_MASK (0x1<<19) // Received target Abort Error Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4037 #define PCIEIP_REG_TL_FUNC678_MASK_PES7_MASK (0x1<<20) // Poisoned Error Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
4039 #define PCIEIP_REG_TL_FUNC678_MASK_FCPES7_MASK (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4041 #define PCIEIP_REG_TL_FUNC678_MASK_CTS7_MASK (0x1<<22) // Completer Timeout Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4043 #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR7_MASK (0x1<<23) // Received UR Status, Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4045 #define PCIEIP_REG_TL_FUNC678_MASK_UCS7_MASK (0x1<<24) // Unexpected Completion Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4047 #define PCIEIP_REG_TL_FUNC678_MASK_ROS7_MASK (0x1<<25) // Receiver Overflow Status Status Mask for Function7, if set, does not generate pcie_err_attn output when this error is seen..
4049 #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS7_MASK (0x1<<26) // Malformed TLP Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
4051 #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS7_MASK (0x1<<27) // ECRC Error TLP Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
4053 #define PCIEIP_REG_TL_FUNC678_MASK_URES7_MASK (0x1<<28) // Unsupported Request Error Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4055 #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT7_MASK (0x1<<29) // Received target Abort Error Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4060 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP5 (0x1<<0) // Poisoned Error Status detected for Function 5. If set, hw generates pcie_err_attn output.
4062 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL5 (0x1<<1) // Flow Control Protocol Error Status detected for Function 5, if set, generate pcie_err_attn output.
4064 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 (0x1<<2) // Completer Timeout Status detected for Function 5. If set, hw generates pcie_err_attn output.
4066 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT5 (0x1<<3) // Receive UR Status detectedfor Function 5. If set, generate pcie_err_attn output.
4068 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL5 (0x1<<4) // Unexpected Completion Status detected for Function 5, if set, generate pcie_err_attn output.
4070 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW5 (0x1<<5) // Receiver Overflow Status detected for Function 5. If set, hw generates pcie_err_attn output.
4072 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP5 (0x1<<6) // Malformed TLP Status detected for Function 5. If set, hw generates pcie_err_attn output.
4074 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC5 (0x1<<7) // ECRC Error TLP Status detected for Function 5. If set, hw generates pcie_err_attn output.
4076 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT5 (0x1<<8) // Unsupported Request Error Status detected for Function 5. If set, hw generates pcie_err_attn output.
4078 #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (0x1<<9) //
4080 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP6 (0x1<<10) // Poisoned Error Status detected in function 6. If set, hw generates pcie_err_attn output.
4082 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL6 (0x1<<11) // Flow Control Protocol Error Status detected in function 6, if set, generate pcie_err_attn output.
4084 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 (0x1<<12) // Completer Timeout Status detected in function 6. If set, hw generates pcie_err_attn output.
4086 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT6 (0x1<<13) // Receive UR Status detectedin function 6. If set, generate pcie_err_attn output.
4088 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL6 (0x1<<14) // Unexpected Completion Status detected in function 6, if set, generate pcie_err_attn output.
4090 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW6 (0x1<<15) // Receiver Overflow Status detected in function 6. If set, hw generates pcie_err_attn output.
4092 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP6 (0x1<<16) // Malformed TLP Status detected in function 6. If set, hw generates pcie_err_attn output.
4094 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC6 (0x1<<17) // ECRC Error TLP Status detected in function 6. If set, hw generates pcie_err_attn output.
4096 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT6 (0x1<<18) // Unsupported Request Error Status detected in function6. If set, hw generates pcie_err_attn output.
4098 #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (0x1<<19) //
4100 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP7 (0x1<<20) // Poisoned Error Status detected in function 7. If set, hw generates pcie_err_attn output.
4102 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL7 (0x1<<21) // Flow Control Protocol Error Status detected in function 7, if set, generate pcie_err_attn output.
4104 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 (0x1<<22) // Completer Timeout Status detected in function 7. If set, hw generates pcie_err_attn output.
4106 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT7 (0x1<<23) // Receive UR Status detectedin function 7. If set, generate pcie_err_attn output.
4108 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL7 (0x1<<24) // Unexpected Completion Status detected in function 7, if set, generate pcie_err_attn output.
4110 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW7 (0x1<<25) // Receiver Overflow Status detected in function 7. If set, hw generates pcie_err_attn output.
4112 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP7 (0x1<<26) // Malformed TLP Status detected in function 7. If set, hw generates pcie_err_attn output.
4114 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC7 (0x1<<27) // ECRC Error TLP Status detected in function 7. If set, hw generates pcie_err_attn output.
4116 #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT7 (0x1<<28) // Unsupported Request Error Status detected in function7. If set, hw generates pcie_err_attn output.
4118 #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (0x1<<29) //
4161 #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_MDIO_PERST (0x1<<0) // This bit when cleared will keep the Serdes MDIO regs in reset till PERST_N is released. Default behavior is to release Serdes MDIO from reset on Vaux power being present.
4163 #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_UC_PERST (0x1<<1) // This bit when cleared will keep the micro in reset till PERST_N is released. Default behavior is to release micro from reset on Vaux power being present.
4165 #define PCIEIP_REG_TL_RST_CTRL_SOFT_MDIO_RST (0x1<<2) // This bit when set will reset the Serdes register space, provided bit 3 is also set.
4167 #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST (0x1<<3) // Tthis bit when set will allow bit 2 value to propogate to Serdes. This bit acts as the mux sel for a soft MDIO reset.
4169 #define PCIEIP_REG_TL_RST_CTRL_SOFT_UC_RST (0x1<<4) // This bit when set will reset the micro, provided bit 5 is also set.
4171 #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_UC_RST (0x1<<5) // For gen3 serdes, this bit when set will allow bit 4 value to propogate to uc reset. This bit acts as the mux sel for a soft micro reset.
4175 #define PCIEIP_REG_TL_RST_CTRL_ENABLE_ALT_MSG_ERROR (0x1<<8) // Based on 3.0 errata, allows interpreting Rx messages with routing errors or hdr type errors to be UR instead of malformed.
4182 #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED0 (0x1<<7) //
4186 #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED1 (0x1<<15) //
4191 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_1_HIDDEN (0x1<<0) // Set if func1 is hidden either due to hide_func_1 pad being driven high or due to programming bit in TL reg This bit is tied to 0, if IP does not support multiple functions.
4193 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_2_HIDDEN (0x1<<1) // Set if func2 is hidden either due to hide_func_2 pad being driven high or due to programming bit in TL reg
4195 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_3_HIDDEN (0x1<<2) // Set if func3 is hidden either due to hide_func_3 pad being driven high or due to programming bit in TL reg
4197 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_4_HIDDEN (0x1<<3) // Set if func4 is hidden either due to hide_func_4 pad being driven high or due to programming bit in TL reg
4199 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_5_HIDDEN (0x1<<4) // Set if func5 is hidden either due to hide_func_5 pad being driven high or due to programming bit in TL reg
4201 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_6_HIDDEN (0x1<<5) // Set if func6 is hidden either due to hide_func_6 pad being driven high or due to programming bit in TL reg
4203 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_7_HIDDEN (0x1<<6) // Set if func7 is hidden either due to hide_func_7 pad being driven high or due to programming bit in TL reg
4205 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_8_HIDDEN (0x1<<7) // Set if func8 is hidden either due to hide_func_8 pad being driven high or due to programming bit in TL reg
4207 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_9_HIDDEN (0x1<<8) // Set if func9 is hidden either due to hide_func_9 pad being driven high or due to programming bit in TL reg
4209 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_10_HIDDEN (0x1<<9) // Set if func10 is hidden either due to hide_func_10 pad being driven high or due to programming bit in TL reg
4211 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_11_HIDDEN (0x1<<10) // Set if func11 is hidden either due to hide_func_11 pad being driven high or due to programming bit in TL reg
4213 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_12_HIDDEN (0x1<<11) // Set if func12 is hidden either due to hide_func_12 pad being driven high or due to programming bit in TL reg
4215 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_13_HIDDEN (0x1<<12) // Set if func13 is hidden either due to hide_func_13 pad being driven high or due to programming bit in TL reg
4217 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_14_HIDDEN (0x1<<13) // Set if func14 is hidden either due to hide_func_14 pad being driven high or due to programming bit in TL reg
4219 #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_15_HIDDEN (0x1<<14) // Set if func15 is hidden either due to hide_func_15 pad being driven high or due to programming bit in TL reg
4237 #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE0 (0x1<<0) // Direct reflection of Config PM PME enable bit for function 0.
4239 #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS0 (0x1<<1) // Direct reflection of config PM PME status bit for function 0.
4241 #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN0 (0x1<<2) // Direct reflection of CFG link control, Aux power PM enabled.
4243 #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE1 (0x1<<3) // Direct reflection of Config PM PME enable bit for function 1.
4245 #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS1 (0x1<<4) // Direct reflection of config PM PME status bit for function 1.
4247 #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN1 (0x1<<5) // Direct reflection of CFG link control, Aux power PM enabled.
4254 #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES8_MASK (0x1<<0) // Poisoned Error Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4256 #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES8_MASK (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4258 #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS8_MASK (0x1<<2) // Completer Timeout Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4260 #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR8_MASK (0x1<<3) // Received UR Status, Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4262 #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS8_MASK (0x1<<4) // Unexpected Completion Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4264 #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS8_MASK (0x1<<5) // Receiver Overflow Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4266 #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS8_MASK (0x1<<6) // Malformed TLP Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4268 #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS8_MASK (0x1<<7) // ECRC Error TLP Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4270 #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES8_MASK (0x1<<8) // Unsupported Request Error Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4272 #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT8_MASK (0x1<<9) // Received target Abort Error Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4274 #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES9_MASK (0x1<<10) // Poisoned Error Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4276 #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES9_MASK (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4278 #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS9_MASK (0x1<<12) // Completer Timeout Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4280 #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR9_MASK (0x1<<13) // Received UR Status, Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4282 #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS9_MASK (0x1<<14) // Unexpected Completion Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4284 #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS9_MASK (0x1<<15) // Receiver Overflow Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4286 #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS9_MASK (0x1<<16) // Malformed TLP Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4288 #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS9_MASK (0x1<<17) // ECRC Error TLP Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4290 #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES9_MASK (0x1<<18) // Unsupported Request Error Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4292 #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT9_MASK (0x1<<19) // Received target Abort Error Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4294 #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES10_MASK (0x1<<20) // Poisoned Error Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4296 #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES10_MASK (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4298 #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS10_MASK (0x1<<22) // Completer Timeout Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4300 #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR10_MASK (0x1<<23) // Received UR Status, Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4302 #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS10_MASK (0x1<<24) // Unexpected Completion Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4304 #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS10_MASK (0x1<<25) // Receiver Overflow Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4306 #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS10_MASK (0x1<<26) // Malformed TLP Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4308 #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS10_MASK (0x1<<27) // ECRC Error TLP Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4310 #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES10_MASK (0x1<<28) // Unsupported Request Error Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4312 #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT10_MASK (0x1<<29) // Received target Abort Error Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4317 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP8 (0x1<<0) // Poisoned Error Status detected for Function 8. If set, hw generates pcie_err_attn output.
4319 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL8 (0x1<<1) // Flow Control Protocol Error Status detected for Function 8, if set, generate pcie_err_attn output.
4321 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT8 (0x1<<2) // Completer Timeout Status detected for Function 8. If set, hw generates pcie_err_attn output.
4323 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT8 (0x1<<3) // Receive UR Status detectedfor Function 8. If set, generate pcie_err_attn output.
4325 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL8 (0x1<<4) // Unexpected Completion Status detected for Function 8, if set, generate pcie_err_attn output.
4327 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW8 (0x1<<5) // Receiver Overflow Status detected for Function 8. If set, hw generates pcie_err_attn output.
4329 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP8 (0x1<<6) // Malformed TLP Status detected for Function 8. If set, hw generates pcie_err_attn output.
4331 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC8 (0x1<<7) // ECRC Error TLP Status detected for Function 8. If set, hw generates pcie_err_attn output.
4333 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT8 (0x1<<8) // Unsupported Request Error Status detected for Function 8. If set, hw generates pcie_err_attn output.
4335 #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT8 (0x1<<9) //
4337 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP9 (0x1<<10) // Poisoned Error Status detected in function 9. If set, hw generates pcie_err_attn output.
4339 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL9 (0x1<<11) // Flow Control Protocol Error Status detected in function 9, if set, generate pcie_err_attn output.
4341 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT9 (0x1<<12) // Completer Timeout Status detected in function 9. If set, hw generates pcie_err_attn output.
4343 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT9 (0x1<<13) // Receive UR Status detectedin function 9. If set, generate pcie_err_attn output.
4345 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL9 (0x1<<14) // Unexpected Completion Status detected in function 9, if set, generate pcie_err_attn output.
4347 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW9 (0x1<<15) // Receiver Overflow Status detected in function 9. If set, hw generates pcie_err_attn output.
4349 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP9 (0x1<<16) // Malformed TLP Status detected in function 9. If set, hw generates pcie_err_attn output.
4351 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC9 (0x1<<17) // ECRC Error TLP Status detected in function 9. If set, hw generates pcie_err_attn output.
4353 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT9 (0x1<<18) // Unsupported Request Error Status detected in function9. If set, hw generates pcie_err_attn output.
4355 #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT9 (0x1<<19) //
4357 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP10 (0x1<<20) // Poisoned Error Status detected in function 10. If set, hw generates pcie_err_attn output.
4359 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL10 (0x1<<21) // Flow Control Protocol Error Status detected in function 10, if set, generate pcie_err_attn output.
4361 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT10 (0x1<<22) // Completer Timeout Status detected in function 10. If set, hw generates pcie_err_attn output.
4363 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT10 (0x1<<23) // Receive UR Status detectedin function 10. If set, generate pcie_err_attn output.
4365 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL10 (0x1<<24) // Unexpected Completion Status detected in function 10, if set, generate pcie_err_attn output.
4367 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW10 (0x1<<25) // Receiver Overflow Status detected in function 10. If set, hw generates pcie_err_attn output.
4369 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP10 (0x1<<26) // Malformed TLP Status detected in function 10. If set, hw generates pcie_err_attn output.
4371 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC10 (0x1<<27) // ECRC Error TLP Status detected in function 10. If set, hw generates pcie_err_attn output.
4373 #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT10 (0x1<<28) // Unsupported Request Error Status detected in function10. If set, hw generates pcie_err_attn output.
4375 #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT10 (0x1<<29) //
4380 #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES11_MASK (0x1<<0) // Poisoned Error Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4382 #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES11_MASK (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4384 #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS11_MASK (0x1<<2) // Completer Timeout Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4386 #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR11_MASK (0x1<<3) // Received UR Status, Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4388 #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS11_MASK (0x1<<4) // Unexpected Completion Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4390 #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS11_MASK (0x1<<5) // Receiver Overflow Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4392 #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS11_MASK (0x1<<6) // Malformed TLP Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4394 #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS11_MASK (0x1<<7) // ECRC Error TLP Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4396 #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES11_MASK (0x1<<8) // Unsupported Request Error Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4398 #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT11_MASK (0x1<<9) // Received target Abort Error Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4400 #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES12_MASK (0x1<<10) // Poisoned Error Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4402 #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES12_MASK (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4404 #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS12_MASK (0x1<<12) // Completer Timeout Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4406 #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR12_MASK (0x1<<13) // Received UR Status, Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4408 #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS12_MASK (0x1<<14) // Unexpected Completion Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4410 #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS12_MASK (0x1<<15) // Receiver Overflow Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4412 #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS12_MASK (0x1<<16) // Malformed TLP Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4414 #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS12_MASK (0x1<<17) // ECRC Error TLP Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4416 #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES12_MASK (0x1<<18) // Unsupported Request Error Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4418 #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT12_MASK (0x1<<19) // Received target Abort Error Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4420 #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES13_MASK (0x1<<20) // Poisoned Error Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4422 #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES13_MASK (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4424 #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS13_MASK (0x1<<22) // Completer Timeout Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4426 #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR13_MASK (0x1<<23) // Received UR Status, Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4428 #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS13_MASK (0x1<<24) // Unexpected Completion Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4430 #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS13_MASK (0x1<<25) // Receiver Overflow Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4432 #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS13_MASK (0x1<<26) // Malformed TLP Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4434 #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS13_MASK (0x1<<27) // ECRC Error TLP Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4436 #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES13_MASK (0x1<<28) // Unsupported Request Error Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4438 #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT13_MASK (0x1<<29) // Received target Abort Error Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4443 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP11 (0x1<<0) // Poisoned Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
4445 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL11 (0x1<<1) // Flow Control Protocol Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
4447 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT11 (0x1<<2) // Completer Timeout Status detected for Function 11. If set, hw generates pcie_err_attn output.
4449 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT11 (0x1<<3) // Receive UR Status detectedfor Function 11. If set, hw generates pcie_err_attn output.
4451 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL11 (0x1<<4) // Unexpected Completion Status detected for Function 11. If set, hw generates, generate pcie_err_attn output.
4453 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW11 (0x1<<5) // Receiver Overflow Status detected for Function 11. If set, hw generates pcie_err_attn output.
4455 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP11 (0x1<<6) // Malformed TLP Status detected for Function 11. If set, hw generates pcie_err_attn output.
4457 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC11 (0x1<<7) // ECRC Error TLP Status detected for Function 11. If set, hw generates pcie_err_attn output.
4459 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT11 (0x1<<8) // Unsupported Request Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
4461 #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT11 (0x1<<9) //
4463 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP12 (0x1<<10) // Poisoned Error Status detected in function 12. If set, hw generates pcie_err_attn output.
4465 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL12 (0x1<<11) // Flow Control Protocol Error Status detected in function 12. If set, hw generates pcie_err_attn output.
4467 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT12 (0x1<<12) // Completer Timeout Status detected in function 12. If set, hw generates pcie_err_attn output.
4469 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT12 (0x1<<13) // Receive UR Status detectedin function 12. If set, hw generates pcie_err_attn output.
4471 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL12 (0x1<<14) // Unexpected Completion Status detected in function 12. If set, hw generates pcie_err_attn output.
4473 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW12 (0x1<<15) // Receiver Overflow Status detected in function 12. If set, hw generates pcie_err_attn output.
4475 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP12 (0x1<<16) // Malformed TLP Status detected in function 12. If set, hw generates pcie_err_attn output.
4477 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC12 (0x1<<17) // ECRC Error TLP Status detected in function 12. If set, hw generates pcie_err_attn output.
4479 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT12 (0x1<<18) // Unsupported Request Error Status detected in function12. If set, hw generates pcie_err_attn output.
4481 #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT12 (0x1<<19) //
4483 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP13 (0x1<<20) // Poisoned Error Status detected in function 13. If set, hw generates pcie_err_attn output.
4485 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL13 (0x1<<21) // Flow Control Protocol Error Status detected in function 13. If set, hw generates pcie_err_attn output.
4487 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT13 (0x1<<22) // Completer Timeout Status detected in function 13. If set, hw generates pcie_err_attn output.
4489 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT13 (0x1<<23) // Receive UR Status detectedin function 13. If set, hw generates pcie_err_attn output.
4491 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL13 (0x1<<24) // Unexpected Completion Status detected in function 13. If set, hw generates pcie_err_attn output.
4493 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW13 (0x1<<25) // Receiver Overflow Status detected in function 13. If set, hw generates pcie_err_attn output.
4495 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP13 (0x1<<26) // Malformed TLP Status detected in function 13. If set, hw generates pcie_err_attn output.
4497 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC13 (0x1<<27) // ECRC Error TLP Status detected in function 13. If set, hw generates pcie_err_attn output.
4499 #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT13 (0x1<<28) // Unsupported Request Error Status detected in function13. If set, hw generates pcie_err_attn output.
4501 #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT13 (0x1<<29) //
4506 #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL (0x1<<0) // Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates. Note: This register field is sticky.
4508 #define PCIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3 (0x1<<8) // Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the core needs to be disabled when the scrambling function is implemented outside of the core (for example within the PHY). Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky.
4510 #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_PHASE_2_3 (0x1<<9) // Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky.
4512 #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_EIEOS_CNT (0x1<<10) // Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky.
4514 #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_REDO (0x1<<11) // Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky.
4516 #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_PH01_EN (0x1<<12) // Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky.
4518 #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS (0x1<<13) // When set to '1', the core as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky.
4520 #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE (0x1<<16) // Equalization Disable. Disable equalization feature. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky.
4522 #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE (0x1<<17) // DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky.
4524 #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE (0x1<<18) // DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky.
4526 #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE (0x1<<23) // Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky.
4529 #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES14_MASK (0x1<<0) // Poisoned Error Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4531 #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES14_MASK (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4533 #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS14_MASK (0x1<<2) // Completer Timeout Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4535 #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR14_MASK (0x1<<3) // Received UR Status, Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4537 #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS14_MASK (0x1<<4) // Unexpected Completion Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4539 #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS14_MASK (0x1<<5) // Receiver Overflow Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4541 #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS14_MASK (0x1<<6) // Malformed TLP Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4543 #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS14_MASK (0x1<<7) // ECRC Error TLP Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4545 #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES14_MASK (0x1<<8) // Unsupported Request Error Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4547 #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT14_MASK (0x1<<9) // Received target Abort Error Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4549 #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES15_MASK (0x1<<10) // Poisoned Error Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4551 #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES15_MASK (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4553 #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS15_MASK (0x1<<12) // Completer Timeout Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4555 #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR15_MASK (0x1<<13) // Received UR Status, Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4557 #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS15_MASK (0x1<<14) // Unexpected Completion Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4559 #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS15_MASK (0x1<<15) // Receiver Overflow Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4561 #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS15_MASK (0x1<<16) // Malformed TLP Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4563 #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS15_MASK (0x1<<17) // ECRC Error TLP Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4565 #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES15_MASK (0x1<<18) // Unsupported Request Error Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4567 #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT15_MASK (0x1<<19) // Received target Abort Error Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4572 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP14 (0x1<<0) // Poisoned Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
4574 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL14 (0x1<<1) // Flow Control Protocol Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
4576 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT14 (0x1<<2) // Completer Timeout Status detected for Function 14. If set, hw generates pcie_err_attn output.
4578 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT14 (0x1<<3) // Receive UR Status detectedfor Function 14. If set, hw generates pcie_err_attn output.
4580 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL14 (0x1<<4) // Unexpected Completion Status detected for Function 14. If set, hw generates pcie_err_attn output.
4582 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW14 (0x1<<5) // Receiver Overflow Status detected for Function 14. If set, hw generates pcie_err_attn output.
4584 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP14 (0x1<<6) // Malformed TLP Status detected for Function 14. If set, hw generates pcie_err_attn output.
4586 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC14 (0x1<<7) // ECRC Error TLP Status detected for Function 14. If set, hw generates pcie_err_attn output.
4588 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT14 (0x1<<8) // Unsupported Request Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
4590 #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT14 (0x1<<9) //
4592 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP15 (0x1<<10) // Poisoned Error Status detected in function 15. If set, hw generates pcie_err_attn output.
4594 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL15 (0x1<<11) // Flow Control Protocol Error Status detected in function 15. If set, hw generates pcie_err_attn output.
4596 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT15 (0x1<<12) // Completer Timeout Status detected in function 15. If set, hw generates pcie_err_attn output.
4598 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT15 (0x1<<13) // Receive UR Status detectedin function 15. If set, hw generates pcie_err_attn output.
4600 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL15 (0x1<<14) // Unexpected Completion Status detected in function 15. If set, hw geneartes pcie_err_attn output.
4602 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW15 (0x1<<15) // Receiver Overflow Status detected in function 15. If set, hw generates pcie_err_attn output.
4604 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP15 (0x1<<16) // Malformed TLP Status detected in function 15. If set, hw generates pcie_err_attn output.
4606 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC15 (0x1<<17) // ECRC Error TLP Status detected in function 15. If set, hw generates pcie_err_attn output.
4608 #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT15 (0x1<<18) // Unsupported Request Error Status detected in function15. If set, hw generates pcie_err_attn output.
4610 #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT15 (0x1<<19) //
4650 #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE (0x1<<4) // Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2" For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2" Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky.
4652 #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE (0x1<<5) // Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky.
4656 #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL (0x1<<24) // Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky.
4658 #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF (0x1<<25) // GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky.
4660 #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP (0x1<<26) // Request core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky.
4683 #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky.
4686 #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN (0x1<<0) // Write to RO Registers Using DBI. When you set this field to "1", then some RO and HwInit bits are writable from the local application through the DBI. For more details, see "Writing to Read-Only Registers." Note: This register field is sticky.
4689 #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH (0x3f<<0) // Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32 This field is reserved (fixed to '0') for M-PCIe.
4691 #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE (0x1<<6) // Directed Link Width Change. The core always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the core starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the core does not start upconfigure or autonomous width downsizing in the Configuration state. The core self-clears this field when the core accepts this request. This field is reserved (fixed to '0') for M-PCIe.
4693 #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT (0x1<<7) // Upconfigure Support. The core sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
4698 #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1 (0x1<<9) // L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
4703 #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN (0x1<<31) // This is a one shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'.
4706 #define PCIEIP_REG_PL_LAST_OFF_PL_LAST (0x1<<0) // PL_LAST is an internally reserved field. Do not use.
4791 #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED0 (0x1<<7) //
4795 #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED1 (0x1<<15) //
4797 #define PCIEIP_REG_TL_TGT_CRDT_ST_NP_CRDT_CNTR (0x1<<16) // Available Non-posted credit for target reads or config.
4823 #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_MDIO_N (0x1<<11) //
4825 #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_UC_N (0x1<<12) //
4827 #define PCIEIP_REG_TL_RST_DEBUG_HARD_RST_CFG_B (0x1<<13) //
4829 #define PCIEIP_REG_TL_RST_DEBUG_PERST_CFG_B (0x1<<14) //
4831 #define PCIEIP_REG_TL_RST_DEBUG_RESERVED (0x1<<15) //
4838 #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_NEXTBUS (0x1<<0) // This bit when set enables the DUT to assume that VFs are residing on a bus number that is different than the one on which the PFs reside. When this bit is enabled, VF_offset is automatically set to be greater than 256. So VFs reside on the next bus number and PCIE IP will consume multiple bus numbers. In this case VFs are accessed using Cfg Type 1 Transactions. This bit should be set if ARI is not supported in the hierarchy.
4840 #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_OFFSET_VETO (0x1<<1) // This bit when set, prevents DUT from automatically setting VF offset to be greater than 256(when vf_nextbus, bit 0 is set). User would have to set the offset bit on their own in this case.
4842 #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_EN_BAR_ADJUST (0x1<<2) // This bit when set, enables DUT to automatically adjust the VF BAR size based on the System Page Size programming. When system Page size is programmed to be greater than User Page Size, DUT will change the VF BAR size advertized to be the new Effective system Page Size.
4849 #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_IMMEDIATE (0x1<<20) // When set, released non-posted credits are flagged for immediate update. When clear, the credits may or not be updated until one or more of the accumulated credit thresholds for non-posted header or non-posted data is reached. (If clear and infinite credits are advertised, the thresholds are not used to force immediate updates.)
4853 #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_UPD_10US (0x1<<25) // When set, outstanding non-posted credit updates are forwarded to the DLL as immediate updates after a given number of microseconds (see below) elapses since the last update. This is typically used with non-immediate (threshold-based) updates.
4860 #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_IMMEDIATE (0x1<<20) // When set, released posted credits are flagged for immediate update. When clear, the credits may or not be updated until one or more of the accumulated credit thresholds for posted header or posted data is reached. (If clear and infinite credits are advertised, the thresholds are not used to force immediate updates.)
4864 #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_UPD_10US (0x1<<25) // When set, outstanding posted credit updates are forwarded to the DLL as immediate updates after a given number of microseconds (see below) elapses since the last update. This is typically used with non-immediate (threshold-based) updates.
4886 #define PCIEIP_REG_VDM_CTL0_REG_VDM_ENABLED (0x1<<16) // VDM is enabled when this bit is set. PCIe will pass VDM messgaes to user interface when this bit is enabled, else it will be silently dropped.
4889 #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_START (0x1<<0) // This bit when set, forces hardware to generate a PTM Request message. Hardware automatically clears this bit, when the PTM response is received.
4891 #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_MASK (0x1<<1) // This field when set will prevent hardware from generating attention when PTM req- response handshake has completed.
4895 #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_STAT (0x1<<30) // This field when set inidcates that the PTM req-response handshake initiated by software has completed. This bit is cleared by writing to it.
4897 #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_STATUS (0x1<<31) // This field when set inidcates that the PTM req-response handshake completed successfully. This field is valid only when bit 30 is set.
4907 #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_EN (0x1<<0) // TLP Statistics Enable. Setting this bit to '1' enables the tx TLP statistics collection. Hardware will count various types of TLPs in the TX direction, as programmed in the reg_ttx_det_tlp_type register. When this bit is reset to '0', the counting stops and software can read the results. This bit is automatically cleared after the specified time if reg_ttx_tlp_stat_len is non-zero. All statistic read-back registers are cleared when this transitions from '0' to '1'.
4925 #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED0 (0x1<<7) //
4929 #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED1 (0x1<<15) //
4933 #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED2 (0x1<<23) //
4940 #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_EN (0x1<<0) // TLP Statistics Enable. Setting this bit to '1' enables the rx TLP statistics collection. Hardware will count various types of TLPs programmed in the reg_trx_det_tlp_type register in RX direction. When this bit is reset to '0', the counting stops and software can read the results. This bit is automatically cleared after the specified time if reg_trx_tlp_stat_len is non-zero. All statistic read-back registers are cleared when this transitions from '0' to '1'.
4958 #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED0 (0x1<<7) //
4962 #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED1 (0x1<<15) //
4966 #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED2 (0x1<<23) //
4977 #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE (0x1<<15) // Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
4983 #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE (0x1<<31) // No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
4991 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_RD_CTRL_CSRD_USER_B (0x1<<8) // When cleared, indicates that the DBG FIFO is read by user interface. When set, indicates that the DBG FIFO is read by CS registers only.
4997 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_ST (0x1<<26) // Asserted when attn signal is generated and active. Write 1 to clear the attn.
4999 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN (0x1<<27) // Enables to generate attention to trigger external logic analyzers.
5001 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_RESERVED_28 (0x1<<28) //
5003 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_PRETRIG_FULL (0x1<<29) // Indicates that DBG FIFO has filled the pretrigger buffer before the trigger occurred. If the trigger occurs before the pretrigger buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
5005 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIGGERED (0x1<<30) // Indicates that the DBG FIFO is triggered.
5007 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ACTIVE (0x1<<31) // When set by write, activates the DBG FIFO logic. To retrigger, this must be cleared then set again. When read, this indicates that the DBG FIFO is active (waiting for a trigger).
5012 #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_AUTOINC (0x1<<9) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
5016 #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_AUTOINC (0x1<<19) // When set, the indirect read address register is incremented on reads.
5018 #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_NO_RADDR (0x1<<20) // When set, the indirect write address register is used for indirect reads as well.
5030 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_7 (0x1<<7) //
5034 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_DBG_FIFO_ATTN (0x1<<10) // Debug fifo attn signal status
5038 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_CTRL_ATTN (0x1<<24) // When set, asserts attn signal irrespective of attnsm state
5040 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_25 (0x1<<25) // When set, resets user side interface for tlda2 fifo
5042 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_26 (0x1<<26) // When set, resets user side interface for tlda fifo
5044 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_27 (0x1<<27) // When set, resets user side interface for dbg fifo
5046 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_28 (0x1<<28) // When set, clears the debug fifo active also enables user side flush for debug fifo
5048 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_29 (0x1<<29) // When set, activates debug fifo
5050 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_30 (0x1<<30) // When set, resets notrig_cnt and trigsm
5052 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_31 (0x1<<31) // When set, dbg_fifo_triggered will get asserted irrespective of trigsm state
5061 #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_15 (0x1<<15) //
5082 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RADDR_DWSEL (0x1<<7) // When set, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
5084 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RDAUTOINC (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 will automatically increment the read address.
5086 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_SERIES (0x1<<9) // When set, the FIFOs are linked in series to increase the depth of the FIFO.
5088 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_PARA (0x1<<10) // When set, the FIFOs are linked in parallel to increase the width of the FIFO.
5090 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UI_PRETRIG_ALL (0x1<<11) // Valid only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid and will be present on the interface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
5092 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UNUSED0 (0x1<<12) //
5094 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_DATA_AT_TRIG (0x1<<13) // When set after FIFO has triggered, indicates that data at the trigger has been collected (as opposed to filtered out based on indirect register settings).
5096 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_MODE (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read from the registers. When cleared, indicates that the FIFO is operating through reads from the user interface.
5102 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_FULL (0x1<<29) // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
5104 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_TRIGGERED (0x1<<30) // Indicates that the TLDA is triggered. For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the TLDA has collected all needed data.
5106 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_ACTIVE (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must be cleared then set again. When read, this indicates that the TLDA is active (waiting for a trigger).
5111 #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_AUTOINC (0x1<<8) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
5115 #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_AUTOINC (0x1<<17) // When set, the indirect read address register is incremented on reads.
5117 #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_NO_RD_ADDR (0x1<<18) // When set, the indirect write address register (below) is used for indirect reads as well.
5132 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RADDR_DWSEL (0x1<<7) // When set, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
5134 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RDAUTOINC (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 will automatically increment the read address.
5136 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_SERIES (0x1<<9) // When set, this indicates the FIFOs are linked in series to increase the depth of the FIFO.
5138 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_PARA (0x1<<10) // When set, this indicates the FIFOs are linked in parallel to increase the width of the FIFO.
5140 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UI_PRETRIG_ALL (0x1<<11) // Valid only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid and will be present on the interface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
5142 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UNUSED0 (0x1<<12) //
5144 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_DATA_AT_TRIG (0x1<<13) // When set after FIFO has triggered, indicates that data at the trigger has been collected (as opposed to filtered out based on indirect register settings).
5146 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_MODE (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read from the registers. When cleared, indicates that the FIFO is operating through reads from the user interface.
5152 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_FULL (0x1<<29) // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
5154 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_TRIGGERED (0x1<<30) // Indicates that the TLDA is triggered. For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the TLDA has collected all needed data.
5156 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_ACTIVE (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must be cleared then set again. When read, this indicates that the TLDA is active (waiting for a trigger).
5161 #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_AUTOINC (0x1<<8) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
5165 #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_AUTOINC (0x1<<17) // When set, the indirect read address register is incremented on reads.
5167 #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_NO_RD_ADDR (0x1<<18) // When set, the indirect write address register (below) is used for indirect reads as well.
5180 #define PCIEIP_REG_PDL_CONTROL_0_ENA_SCRAM (0x1<<0) // PHY: Enable Scrambler. Default for FPGA is 0
5182 #define PCIEIP_REG_PDL_CONTROL_0_DIS_INV_POLARITY (0x1<<1) // PHY: Disable Inverse Polarity. Setting this bit to '1' disables the polarity inversion regardless of what hardware detects during the training.
5184 #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_TIMER (0x1<<2) // DL: Disable Replay Timer. In effect, REPLAY only occurs when NACK DLLP is received.
5186 #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_3 (0x1<<3) //
5188 #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLL (0x1<<4) // DL: Disable CRC check for incoming DLLP packets
5190 #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLP (0x1<<5) // DL: Disable CRC check for incoming TLP packets
5192 #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_BUFF (0x1<<6) // DL: If set, REPLAY EMPTY will be asserted.
5196 #define PCIEIP_REG_PDL_CONTROL_0_DIS_ELECIDLE_RETRAIN (0x1<<10) // PHY: Disable Electrical Idle Retrain. Setting this bit to '1' prevents link from doing retrain if either inferred electrical idle occurs or signal is not detected on all lanes while in L0 or RxL0s.
5198 #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_AUTO_CRDUPD (0x1<<11) // DL: Disable Auto Credit Update. If this bit is set to '1', DL will not automatically generate UpdateFC every 30us (or 120 us if Ext Sync is set)
5200 #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_RETRAIN_REQ (0x1<<12) // DL:Disable hardware from triggering link retraining due to Replay timer roll over, Replay timeout, or detecting maximum number of correctable errors.
5202 #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL1 (0x1<<13) // DL: Force L0 to L1. When this bit is set to '1', DL will send PM_Enter_L1 DLLP to link partner.
5206 #define PCIEIP_REG_PDL_CONTROL_0_FORCE_RCVR_DETECT_ALL (0x1<<23) // PHY: Force Receiver Detect All. When this bit is set to '1', internal Receiver Detected signals are forced to '1' as if link partner receiver has been detected for all lanes.
5210 #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL2 (0x1<<27) // DL: Force L0 to L2. When this bit is set to '1', DL will send PM_Enter_L23 DLLP to link partner.
5212 #define PCIEIP_REG_PDL_CONTROL_0_DIS_HOT_RESET (0x1<<28) // PHY: Disable Hot Reset.
5216 #define PCIEIP_REG_PDL_CONTROL_0_DIRECT_RECOV_TO_CONFIG (0x1<<31) // PHY: Direct Recovery to Configuration State. When this bit is set to '1', LTSSM is directed to transition from Recovery.Idle to Configuration state.
5221 #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_P_LAT_SEL (0x1<<7) // When this bit is set, the software value will be used for UpdateFC Latency of Posted credit.
5223 #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_3 (0x1<<8) // Reserved
5225 #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_NP_LAT_SEL (0x1<<9) // When this bit is set, the software value will be used for UpdateFC Latency of Non-Posted credit.
5227 #define PCIEIP_REG_PDL_CONTROL_1_DIS_NAK_RST_TMR (0x1<<10) // DL: When this bit is set to '1', Replay Timer will not be reset if a NAK is received during a Replay operation. While not in Replay, a NAK always resets the timer regardless of the setting of this bit.
5229 #define PCIEIP_REG_PDL_CONTROL_1_FORCE_TX_L0S (0x1<<11) // PHY: Force to TX L0s. Setting this bit to '1' forces LTSSM to enter TX L0s state.
5233 #define PCIEIP_REG_PDL_CONTROL_1_RETRAIN_REQ (0x1<<14) // This initiates Link re-training by directing PHY LTSSM to recovery state. It is a pulse, so reading this bit always returns '0'.
5235 #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_1 (0x1<<15) // Reserved
5241 #define PCIEIP_REG_PDL_CONTROL_1_INT_ASPM_L1_ENA (0x1<<30) // Internal ASPM L1 Enable. When this bit is set to '1', hardware autonomously control ASPM L1 by monitoring link activities. Signal user_early_l1_exit also works in this mode.
5243 #define PCIEIP_REG_PDL_CONTROL_1_EXT_ASPM_L1_ENA (0x1<<31) // External ASPM L1 Enable. When this bit is set to '1', user can directly control when to enter ASPM L1 using signal user_l1_enter. Actual L1 entering is contingent to link activities. If user_early_l1_exit is also set, it overrides user_l1_enter signal.
5248 #define PCIEIP_REG_PDL_CONTROL_2_DIS_SOS_INTERVAL (0x1<<2) // PHY: Disable SKP OS. When this bit is set to '1', periodic SKP OS transmitting is disabled.
5250 #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER (0x1<<3) // DL: If set, it will enable ACK Latency Timer. In this case, DL ACK or NACK requests are only sent out when timer reaches MAX_ACK_LAT_TIMER. When this timer is disabled, ACK/NACK requests will be sent to PCIE bus as soon as they are asserted.
5252 #define PCIEIP_REG_PDL_CONTROL_2_SW_ACK_LAT_SEL (0x1<<4) // If set, override hardwired value with the programmable ACK Latency timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programmable register for ACK LAT is at address 0x1034
5254 #define PCIEIP_REG_PDL_CONTROL_2_SW_REPLAY_TIMER_SEL (0x1<<5) // If set, override hardwired value with programmable REPLAY timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programmable REPLAY register is at address 0x102C
5262 #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_P (0x1<<16) // DL: Enable Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL will send out FC update for Posted
5264 #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_N (0x1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL will send out FC update for Non-Posted
5287 #define PCIEIP_REG_PDL_CONTROL_5_DOWNSTREAM_PORT (0x1<<8) // This bit is set to '1' if IP is configured as a Downstream Port.
5289 #define PCIEIP_REG_PDL_CONTROL_5_GLOOPBACK (0x1<<9) //
5324 #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_RXENABLE (0x1<<8) // Enable checksum feature on receiving side
5326 #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_ENABLE (0x1<<9) // Enable checksum feature on transmit side
5328 #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_WRITE_NULLIFY (0x1<<10) // DL: If set and DL has detected checksum error earlier, DL will nullify all subsequence memory write request whose pcie_cksum_err bit is not set.
5330 #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_NULLIFY (0x1<<11) // If set DL will nullify the first packet with bad checksum. Subsequent MWR packets will get nullified if DL_CS_WRITE_NULLIFY is set, regardless if they have bad or good checksum If this bit is clear and checksum mismatch occurs, Error attention will be set, but no packet will get nullified.
5360 #define PCIEIP_REG_PDL_CONTROL_14_UNUSED_1 (0x1<<26) //
5366 #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_ENA (0x1<<31) // Enable GRC to control the driving of the debug bus. When this bit is set, it provides the capability to expand the debug bus
5369 #define PCIEIP_REG_DLATTN_VEC_DL_CHKSUM_ERR (0x1<<0) // DL: Assert when DL detects checksum error while transmitting a TLP. Generates pcie_err_att status to chip. This status is not cleared till a 1 is written to it.
5371 #define PCIEIP_REG_DLATTN_VEC_DL_D2TBUF_OFLOW_ERR (0x1<<1) // Signal DLP2TLP buffer on receive side is overflow.
5373 #define PCIEIP_REG_DLATTN_VEC_DLP2TLP_PARITY_ERROR (0x1<<2) // Set if DLP2TLP buffer detects parity error
5375 #define PCIEIP_REG_DLATTN_VEC_REPLAY_ADDRESS_PARITY_ERROR (0x1<<3) // Set if Replay Address buffer detects parity error
5377 #define PCIEIP_REG_DLATTN_VEC_REPLAY_WRAPPER_PARITY_ERROR (0x1<<4) // Set if Replay Wrapper has parity error
5379 #define PCIEIP_REG_DLATTN_VEC_DL_CORRECTABLE_ERROR (0x1<<5) // Assert when Correctable Error counter reach max CORR_ERR_REG_MAX value defined at bit [27:18] of reg 0x1008. The counter is incremented if there is any error associate with LCRC mismatch in DLP, DLL, PHY on receiving side.
5381 #define PCIEIP_REG_DLATTN_VEC_DE_FRAMING_ERROR (0x1<<6) // Indicate un-decoded condition in de-framing logic
5383 #define PCIEIP_REG_DLATTN_VEC_DLP_ERROR_STATUS (0x1<<7) // Assert when LCRC mismatch and sequence number is correct
5385 #define PCIEIP_REG_DLATTN_VEC_DLP_INCORRECT (0x1<<8) // RX: Indicate DLP is too long or TLP dataphases is more than max payload.
5387 #define PCIEIP_REG_DLATTN_VEC_TLPBUFRDERR (0x1<<9) // RX: Asserted when one or more TLP does have either incorrect LCRC, sequence number, or ending with EDB
5389 #define PCIEIP_REG_DLATTN_VEC_REPLAY_SEQUENCE_OVERRUN (0x1<<10) // REPLAY SEQUENCE is overrun
5391 #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_ACK (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in Replay Buffer.
5393 #define PCIEIP_REG_DLATTN_VEC_REPLAY_BUFFER_OVERRUN (0x1<<12) // Set if Replay buffer is overwritten
5395 #define PCIEIP_REG_DLATTN_VEC_REPLAY_NUMBER_ROLL_OVER (0x1<<13) // Set if number of Replay reaches max value. Default of this value is 4 times.
5397 #define PCIEIP_REG_DLATTN_VEC_REPLAY_TIMEOUT (0x1<<14) // Set if Replay Timer expired without receiving any ACK or NACK from RC
5399 #define PCIEIP_REG_DLATTN_VEC_DL_TX_UNDRUN (0x1<<15) // DL TX Underrun. This bit is set to '1' if underrun occurs at the DL/PL TX interface.
5401 #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_STATUS (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
5403 #define PCIEIP_REG_DLATTN_VEC_DLL_PE_INIT_STATUS (0x1<<17) // Receive UPDATEFC DLLP when DL has not completed FC_INIT1 state, or receive INITFC1 DLLP when DL has already finished the FC initialization.
5405 #define PCIEIP_REG_DLATTN_VEC_UNUSED_3 (0x1<<18) //
5407 #define PCIEIP_REG_DLATTN_VEC_TLP_INCORRECT (0x1<<19) // This signal is set to '1' when the TLP length that TL indicates to DL does not match to the actual length of the TLP transmitted across the TL/DL TX interface.
5409 #define PCIEIP_REG_DLATTN_VEC_TLP_2_DLPBUF_PARITY_ERROR (0x1<<20) // Set if TLP2DLP Buf has parity error
5419 #define PCIEIP_REG_DL_STATUS_REPLAY_ALM_FULL (0x1<<10) // If set, indicates Replay buffer is almost full. Replay available entries are two or less than two
5423 #define PCIEIP_REG_DL_STATUS_PHYLINKUP (0x1<<13) // If set, indicates link is trained
5425 #define PCIEIP_REG_DL_STATUS_DL_ACTIVE (0x1<<14) // If set, signal DL finishes both INITFC1 and INITFC2
5427 #define PCIEIP_REG_DL_STATUS_DL_INIT (0x1<<15) // If set, DL is doing VC0 FC initialization
5444 #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_THRS_ENA (0x1<<0) // T2D FIFO Threshold Enable. This bit is set to '1' to enable the T2D FIFO threshold feature. Depending on TL, DL bus width and clock relationship, after the first data in T2D FIFO becomes available, next data may not be available as fast as DL can retrieve. This can cause data underrun at the DL/PL TX interface. To prevent this underrun issue, when this bit is set, DL will start reading data out of T2D FIFO when one of below conditions occurs: - TLP ends in one entry. - The number of valid entries in T2D FIFO is greater than or equal to dl_t2d_count_thrs. - DL has waited at least dl_t2d_time_thrs clock cycles. This is neccessary in case the TLP size is smaller than the count threshold.
5459 #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_SEL (0x1<<30) // Replay FIFO Test Size Select. When this bit is set to '1', the value in replayfifo_testsize will be used as Replay FIFO size. This is for simulation purpose only.
5461 #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_SEL (0x1<<31) // D2T FIFO Test Size Select. When this bit is set to '1', the value in d2tfifo_testsize will be used as D2T FIFO size. This is for simulation purpose only.
5474 #define PCIEIP_REG_MDIO_WR_DATA_CMD (0x1<<31) // This bit must be written as a '1' to initiate write cycle based ont the data in bits [15:0] and the mdio_addr value. When the write has completed, this bit will read as '0'.
5479 #define PCIEIP_REG_MDIO_RD_DATA_CMD (0x1<<31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit will read as '1'. This bit is automatically cleared by a write to the mdio_addr register.
5488 #define PCIEIP_REG_ATE_TLP_CFG_ATE_NULLIFY (0x1<<8) // ATE TLP Nullify. When this bit is set to '1', an internal signal is asserted together with the last data word to nullify the transaction (i.e. emulate user_tx_nullify).
5497 #define PCIEIP_REG_ATE_TLP_CTL_ATE_TLP_GO (0x1<<0) // ATE TLP Go bit. When this bit is set to '1', the TX User Interface is bypassed and internal logic generates packets to TL logic. After all packets are transferred, this bit is reset to '0' by hardware.
5501 #define PCIEIP_REG_ATE_TLP_CTL_REG_TRX_CLR_RX_TLP_SB (0x1<<4) // Clear RX TLP scoreboard logic bit. SW needs to read trx_reg_sb_op_done (bit[31]). If trx_reg_sb_op_done register value is 1, it indicates that HW is done comparing RX TLPs. SW needs to write reg_trx_clr_rx_tlp_sb to '1' which will clear trx_reg_sb_op_done (bit[31]), trx_reg_err_tlp_num(bits[27:20]), trx_reg_data_mismatch (bit[17]) and trx_reg_hdr_mismatch (bit[16]) registers. It is a self clearing bit.
5505 #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_HDR_MISMATCH (0x1<<16) // Header Mismatch. A value of '1' indicates that transmitted TLP header does not match with received TLP header. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
5507 #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_DATA_MISMATCH (0x1<<17) // Data Mismatch. A value of '1' indicates that transmitted TLP data do not match with received TLP data. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
5515 #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_SB_OP_DONE (0x1<<31) // Value of '1' indicates that number of TLPs received is equal to number of TLPs transmitted (ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user writes '1' to ATE_TLP_GO (bit[0] of ate_tlp_ctl - offset 0x1120) register.
5535 #define PCIEIP_REG_SERDES_PMI_WDATA_RCMD (0x1<<30) // This bit must be written as a '1' to initiate read cycle to the pmi_addr value. When the read has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time this operation is unpredictable.
5537 #define PCIEIP_REG_SERDES_PMI_WDATA_WCMD (0x1<<31) // This bit must be written as a '1' to initiate write cycle based on the data in bits [15:0] and the pmi_addr value. When the write has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time this operation is unpredictable.
5544 #define PCIEIP_REG_SERDES_PMI_RDATA_VALID (0x1<<31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit will read as '1'. This bit is automatically cleared by a write to the serdes_pmi_wdata register.
5567 #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_WIDTH_CHANGE_REQ (0x1<<0) // Request a width change (ie -make the link wider, if possible). Do not assert if the "other side" is not capable of upconfiguration.
5569 #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_SPEED_CHANGE_REQ (0x1<<1) // Request a speed change (ie -make the link fast or slower, depending on the advertised speeds).
5573 #define PCIEIP_REG_REG_PHY_CTL_0_REG_IDLE_TO_RLOCK_ENA (0x1<<5) // Enable the shortcut transition from Config.Complete to Recovery.RcvrLock Software should not change this field while the PCIE link is active.
5575 #define PCIEIP_REG_REG_PHY_CTL_0_REG_UPCONFIG_ENA (0x1<<6) // For multi-lane links on a 2.0 compliant core, enable advertisement of the capability to upconfigure the number of lanes in the link.
5577 #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_2 (0x1<<7) //
5579 #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_FRAMERR (0x1<<8) // Consider DLLP and TLP framing errors as errors when reporting physical layer errors
5581 #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_NOLOCK (0x1<<9) // Consider loss of bit and symbol lock from the PCIe Serdes as errors reporting physical layer errors
5583 #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_SKEW (0x1<<10) // Consider link skew errors as errors when reporting physical layer errors
5585 #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFOVER (0x1<<11) // Consider buffer overrun errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
5587 #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFUNDER (0x1<<12) // Consider buffer underrun errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
5589 #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_DECODE (0x1<<13) // Consider decode errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
5593 #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_POL (0x1<<16) // If set, all symbols of the Modified Compliance Pattern must be of the same polarity (no mixed polarity) for the receiver to lock
5595 #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_ERR (0x1<<17) // If set, both error symbols must match in the received Modified Compliance Pattern before the value is reported
5597 #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_EXIT (0x1<<18) // Directed exit from generating the Modified Compliance Pattern in Polling.Compliance if the Enter Compliance bit of the Link Control 2 register is not set
5599 #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_SIGDET_EXIT (0x1<<19) // Allows exit from Polling.Compliance when generating the Modified Compliance pattern and at least one lane goes to electrical idle
5601 #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_FORCE_ENTRY (0x1<<20) // Forces entry to Polling.Compliance from Polling.Active. This also causes the Compliance Receive bit in the outgoing TS1s to be set in Polling.Active. After entry to Polling.Compliance, the Modified Compliance Pattern is generated instead of the legacy compliance pattern
5603 #define PCIEIP_REG_REG_PHY_CTL_0_REG_TX_DEEMPH (0x1<<21) // The value for the Selectable Deemphasis bit set in TS1s in Polling.Active, Loopback, Recovery, and some Configuration states and set in TS2s in Polling.Configuration
5605 #define PCIEIP_REG_REG_PHY_CTL_0_REG_LOCAL_DEEMPH_LO (0x1<<22) // The initial value of the local deemphasis set in the Detect state (this propagates to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == -3.5 dB (For Gen3, this is the low bit of the local Tx preset if none received in EQ TS2s.)
5607 #define PCIEIP_REG_REG_PHY_CTL_0_REG_AUTONOMOUS_CHANGE (0x1<<23) // The value for the Autonomous Change bit set in TS1s in the Configuration state when PhyLinkUp is set and set in TS2s in the Recovery state
5609 #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_DETECT (0x1<<24) // Directed transition from Loopback or Polling.Compliance states to Detect state
5611 #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_L0 (0x1<<25) // Directed transition from L1 state to Recovery or L2 state to Detect.
5613 #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_ELECIDLE (0x1<<26) // Optionally enable the use of electrical idle or inferred electrical ide as a condition for exiting loopback in 2.0 compliant cores.
5615 #define PCIEIP_REG_REG_PHY_CTL_0_REG_DISABLE_SPEED_EI (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred electrical idle
5617 #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_IEI (0x1<<28) // For 2.0 compliant systems, default to the optional behavior of exiting Loopback on inferred electrical idle at 2.5 GT/s.
5619 #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIS_LANE_REVERSAL (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
5621 #define PCIEIP_REG_REG_PHY_CTL_0_REG_ENABLE_RIDLE_SPD_CLR (0x1<<30) // Enable the clearing of directed_speed_change on the transition to Recovery.Idle. This is newly specified for the 2.1 spec in cases where no speed change occurs even though it is directed.
5623 #define PCIEIP_REG_REG_PHY_CTL_0_GEN2_FEATURES_ENA (0x1<<31) // Enable gen2 features when in 1.1 compliance mode (register 0x4d0, bit 5 is set)
5626 #define PCIEIP_REG_REG_PHY_CTL_1_REG_FORCE_GEN2_16BIT (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 Software should not change this field while the PCIE link is active.
5628 #define PCIEIP_REG_REG_PHY_CTL_1_REG_DISABLE_COMPLIANCE (0x1<<1) // Disable entry to Polling.Compliance
5630 #define PCIEIP_REG_REG_PHY_CTL_1_REG_LANE_POWERDOWN_ENA (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-lane link.
5632 #define PCIEIP_REG_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
5634 #define PCIEIP_REG_REG_PHY_CTL_1_REG_FAREND_LPBK_REQ (0x1<<4) // Initiate PL changes required for a far-end loopback
5636 #define PCIEIP_REG_REG_PHY_CTL_1_REG_COMPL_CFG_DETECT_RST (0x1<<5) // If set, when Detect is entered the compliance configuration that cycles through the rates, deemphasis, and presets is reset back to the first configuration (Gen1).
5638 #define PCIEIP_REG_REG_PHY_CTL_1_REG_LATE_CLR_DESKEW_BUFS (0x1<<6) // When set, clear the statis deskew buffers on assertion of the internal deskew enable signal rather than clearing the buffers on the deassertion. This prevents the transient misalignment of data at the end of L0 (when transitioning to L0s or L1). When clear, the legacy behaviour is enabled where the static deskew buffers are cleared on deassertion of the internal deskew enable signal.
5642 #define PCIEIP_REG_REG_PHY_CTL_1_REG_POWERDOWN_P1PLL_ENA (0x1<<12) // This signal goes to the PCIe Serdes to enable the PLL to power down when all lanes are in L1 If ClkReq is active, this signal is ignored.
5644 #define PCIEIP_REG_REG_PHY_CTL_1_REG_COM_FOR_INF_EIDL (0x1<<13) // Enable using lack of received COM instead of lack of received TS2 in Recovery.RcvrCfg for inferred electrical idle. This is to mimic the "Gen2 0.7 spec" functionality
5648 #define PCIEIP_REG_REG_PHY_CTL_1_REG_RXVALID_FOR_EIE (0x1<<16) // Use valid data as "exit from electrical idle" in the Loopback states
5650 #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ANY_LANES (0x1<<17) // Declare EIE if any lane has TSx/EIEOS (or IEI if no lane has TSx/EIEOS)
5652 #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_SOS (0x1<<18) // Declare an inferred electrical idel in L0 if no Skip Ordered Set (SOS) is received in any 128 us interval. See comments for bit 19 of this register
5654 #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_UPDFC (0x1<<19) // Declare an inferred electrical idle in L0 if no UpdateFC is received in any 128 us interval. Can be combined with bit 18 of this register. In that case, not receiving both an UpdateFC or a Skip Ordered Set within the 128 us interval is considered an inferred electrical idle
5658 #define PCIEIP_REG_REG_PHY_CTL_1_UNUSED_1 (0x1<<24) //
5660 #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_1KX (0x1<<25) // Speed up training by 1000x (1 ms = 1 us)
5662 #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_2KX (0x1<<26) // Speed up training by 2000x (1 ms = 500 ns). Do not use with Denali
5664 #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_POLL (0x1<<27) // When training is sped up using bits 25 or 26, extend the timeout for Polling.Active to 72 us
5666 #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TS1 (0x1<<28) // Speed up Polling.Active by restricting the number of TS1s to transmit to 32 (instead of 1024)
5668 #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_LTSSM_HIST (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
5670 #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_GEN2_HIST (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
5672 #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_RECOV_HIST (0x1<<31) // Clear the recovery histogram. Not self-clearing
5683 #define PCIEIP_REG_REG_PHY_CTL_2_REG_DIS_SERDES_CLKCOMP (0x1<<30) // When set, the Serdes elastic buffers will be prevented from adjusting - generating dynamic clock compensation events - prior to the MAC performing static deskew. This is controlled via the pcie_lnk_phy_gpin_0 signal. (Also, this is pl_spare_in[2] or train_ctl_in[2].)
5685 #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_3 (0x1<<31) // Reserved - only write 0. Spare flop for the PL - train_ctl_in[3]. Connected to Serdes via pipe_GPin_1.
5692 #define PCIEIP_REG_REG_PHY_CTL_3_REG_GLOOPBACK (0x1<<14) // Enable the "pins" gloopback - assumes an external loopback method
5694 #define PCIEIP_REG_REG_PHY_CTL_3_REG_SPEED_CHANGE_WAIT (0x1<<15) // Wait for the Serdes to indicate speed change using the PhyStatus (otherwise it assumes the rate change was successful).
5696 #define PCIEIP_REG_REG_PHY_CTL_3_UNUSED_2 (0x1<<16) //
5698 #define PCIEIP_REG_REG_PHY_CTL_3_REG_LOSE_DESKEW_ON_SKP (0x1<<17) // Enable a stronger check at the end of lane deskew and clock compensation to look for aligned SKP symbols and COM symbols rather than just COM symbols.
5700 #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DLLRX_IN_IDLE (0x1<<18) // Enable received data to be presented to the DLL in Configuration.Idle or Recovery.Idle if the lane to lane deskew is corrected even if logical idle data symbols have not been received. This is not according to spec but is according to the previous implmentation.
5702 #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_PWRDN_ACK (0x1<<19) // Ignore powerdown change ACk for R.Lock timeouts
5704 #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_SPD_ACK (0x1<<20) // Ignore rate change ACk for R.Lock timeouts
5706 #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_RXEI_IN_SPEED (0x1<<21) // Enable requiring Rx EI before speed change
5708 #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P1_RXEI_REQ (0x1<<22) // Disable requirement for all lanes in EI on transition to P1
5710 #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DETECT_P1 (0x1<<23) // Enable requirement for Serdes to be in P1 before receiver detect
5712 #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P0S_IN_EXIT_L0S (0x1<<24) // Do not wait for P0s before exiting Tx_L0s
5714 #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_GEN1_IN_DISABLED (0x1<<25) // Change the rate to the Serdes to Gen1 in the Disabled state rather than waiting until the LTSSM moves to Detect (per PIPE spec) to mask a Serdes bug.
5721 #define PCIEIP_REG_REG_PHY_CTL_4_REG_SEL_RCVD_DEEMPH (0x1<<0) // For RC only. Select the value to use for the deemphasis set during Recovery from the downstream component instead of from the Link Control 2 register.
5723 #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_UP (0x1<<1) // For RC only. Enale automatic speed match when the link must change to Gen1 (slow down).
5725 #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_DOWN (0x1<<2) // For RC only. Enale automatic speed match when the link must change to Gen2 (speed up).
5727 #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_50MS (0x1<<3) // For RC only. For testing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow down to 50 ms instead of 200 ms.
5729 #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_25MS (0x1<<4) // For RC only. For testing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow down to 25 ms instead of 200 ms.
5731 #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPEED_MATCH_ADV_DETECT (0x1<<5) // For RC only. When the RC is automatically speeding up/slowing down the link to match advertised rates, use the rates from the link partner advertised since Detect rather than those immediately advertised.
5733 #define PCIEIP_REG_REG_PHY_CTL_4_REG_REPORT_SPEED_MATCH (0x1<<6) // For RC only. Report automatic speed up/slow down by the RC in the Autonomous Bandwidth Status bits.
5735 #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_LOCAL_SPD_CHG (0x1<<7) // Allow locally initiated speed change (directed_speed_change) even if the link partner has only advertised Gen1 rate since Detect.
5737 #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_REMOTE_SPD_CHG (0x1<<8) // Allow link partner to initiate speed change (directed_speed_change) even if only Gen1 rate has been advertised since Detect.
5739 #define PCIEIP_REG_REG_PHY_CTL_4_REG_ADV_LINKCAP_RATES (0x1<<9) // For RC only. Advertise the supported rates from the Link Capabilities register instead of the Link Control 2 register.
5743 #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_DIS (0x1<<13) // If set, disables the delay between the assertion of electrical idle to the power state change to P2. This is needed in Gen2 when entering L2. The minimum time to wait in Detect.Quiet (in 32 ns increments) if the state is entered at non-Gen1 speeds
5745 #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_IN_RESET_ENA (0x1<<14) // Allow lanes to be put into P2 state during reset to save power.
5747 #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_2 (0x1<<15) //
5749 #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_EXIT_ON_ANY (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on signal detect on any lane (spec says all lanes must have signal detect to exit).
5751 #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_MIN_LANE_DETECT (0x1<<17) // The minimum number of lanes for signal detect to avoid entry to Compliance. 0 means only 1 is needed, 1 means all are needed.
5753 #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_1 (0x1<<18) //
5768 #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_DIS_FASTL1EXIT (0x1<<21) // When set, disables the control of the Serdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
5774 #define PCIEIP_REG_REG_PHY_CTL_5_UNUSED_1 (0x1<<30) // Reserved - only write 0
5776 #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_NO_L2_CLKREQ (0x1<<31) // When set, disables entry to CLKREQ when L2/L23 is requested (ie, only PM L1 and ASPM L1 etner CLKREQ)
5787 #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_CLR_HIST (0x1<<16) // Clear the clkreq state history
5789 #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_ANY_PHYSTATUS (0x1<<17) // Use any PhyStatus to indicate the P0->P2 transition. Default is that all active lanes must respond.
5791 #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKREQB_ON (0x1<<18) // CLKREQB is always asserted regardless of the clock PM state.
5793 #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKRST_PERST (0x1<<19) // Always reset the Serdes clk mux during perstb and keep it asserted while perstb is asserted. Default is to briefly reset on perstb assertion, then deassert the clk mux reset.
5808 #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TX_ENA (0x1<<16) // Inject transmit DLLP/TLP error or ordered set error.
5810 #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_RX_ENA (0x1<<17) // Inject receive DLLP/TLP error or serdes error.
5814 #define PCIEIP_REG_REG_PHY_CTL_7_REG_DIS_DESKEW_AFTER_ALIGN_ERR (0x1<<31) // When cleared (the default), Gen3 block alignment errors and invalid data result in the link being declared unusable since data alignment is lost. When set, the legacy behavior is maintained and no retrain will occur, with the possiblity of incorrect training and fall back to lower speeds.
5817 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_ELASTIC_ERR (0x1<<0) // If set, either an elastic buffer overflow or underflow (in the Serdes)
5819 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DISPARITY_ERR (0x1<<1) // If set, a disparity error occurred in the Serdes WC 0
5821 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DECODE_ERR (0x1<<2) // If set, an 8b10b decode error occurred in the Serdes
5823 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_LINK_IS_SKEW (0x1<<3) // If set, the link needed to be deskewed
5825 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_TRAIN_ERR (0x1<<4) // If set, the link needed to be retrained
5827 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_L0S_MAIN_ERR (0x1<<5) // Receiver training error in L0S
5829 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_RETRAIN_REQ (0x1<<6) // Request to retrain received from a higher layer
5831 #define PCIEIP_REG_PHY_ERR_ATTN_VEC_CC_ERR_STATUS (0x1<<7) // Clock Compensation deskew error.
5838 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_ELASTIC_ERR (0x1<<0) // If set, masks ELASTIC_ERR from generating attention. If clear, ELASTIC_ERR generates attention
5840 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR (0x1<<1) // If set, masks DISPARITY_ERR from generating attention. If clear, DISPARITY_ERR generates attention
5842 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DECODE_ERR (0x1<<2) // If set, masks DECODE_ERR from generating attention. If clear, DECODE_ERR generates attention
5844 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW (0x1<<3) // If set, masks LINK_IS_SKEW from generating attention. If clear, LINK_IS_SKEW generates attention
5846 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_TRAIN_ERR (0x1<<4) // If set, masks TRAIN_ERR from generating attention. If clear, TRAIN_ERR generates attention RW 1
5848 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_L0S_MAIN_ERROR (0x1<<5) // If set, masks L0S_MAIN_ERR from generating attention. If clear, L0S_MAIN_ERR generates attention
5850 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_RETRAIN_REQ (0x1<<6) // If set, masks RETRAIN_REQ from generating attention. If clear, RETRAIN_REQ generates attention
5852 #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS (0x1<<7) // If set, masks Clock Compensation deskew error from generating attn. If clear, Clock Compensation deskew error generates attn.
5859 #define PCIEIP_REG_REG_PHY_CTL_8_REG_LOSE_DESKEW_ON_FIFO (0x1<<0) // Enable loss of lane alignment on deskew/clkcomp FIFO errors.
5861 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_BLOCK_REALIGN (0x1<<1) // Enable request to the Serdes to realign blocks.
5863 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_FRAMERR_RETRAIN (0x1<<2) // Enable retraining on any Gen3 framing error.
5865 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_BLOCK_ALIGN_ERR (0x1<<3) // Disable error and retrain for block alignment error from Serdes.
5869 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FIXED_DATA_WIDTH (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rates.
5871 #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_EIOS_DET_ELECIDLE (0x1<<9) // Enable the EIOS detector to mask out data.
5873 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SCRAM (0x1<<10) // Disable scrambling in Gen3.
5875 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_TX_STALL (0x1<<11) // *** Do not modify!! Enable transmitting Gen3 stalls (null data or deassertion of the TxDataValid signals periodically).
5877 #define PCIEIP_REG_REG_PHY_CTL_8_REG_MCP_G3_ALLOW_DATA_LOCK (0x1<<12) // Allow locking to the data blocks in Gen3 Modified Compliance Pattern
5879 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_RESTORE_REVERSAL (0x1<<13) // When retraining to enter compliance, the lane assignments, polarity reversal, and lane reversal information is saved, then restored. This bit disables the restoration of the lane reversal since it wasn't explicitly stated.
5881 #define PCIEIP_REG_REG_PHY_CTL_8_REG_CLR_FREEZE_DESKEW (0x1<<14) // Clear the block aligner debug information frozen on an aligner error. Set, then clear immediately.
5883 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SKIP_FIX (0x1<<15) // Disable the logic that corrects for misaligned deassertions of RxDataValid (in other words, null data is inserted on different relative blocks and the logic fixes that to a limited extent).
5885 #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_RECOV_TSX (0x1<<16) // Enable mixed consecutive TS1s and TS2s for Recovery.RcvrLock transitions
5889 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_EQ_TIMEOUTS (0x1<<19) // Enable updated timeouts for Recovery.Equalization phases (now 12 ms for 0 and 1, 32 ms for 3).
5893 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_071_LOADBOARD (0x1<<24) // Enable TX preset encoding for value b1010 in CLB/CBB environments
5895 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFG_IEI_4MS (0x1<<25) // Enable 4 ms inferred electrical idle in Recovery.RcvrCfg at 8 GT/s
5897 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFGSPEED_128X_TS2 (0x1<<26) // Enable transmission of 128 TS2s in Recovery.RcvrCfg prior to transition to Recovery.Speed (instead of 32 TS2s in 0.70 revision).
5899 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_COMPLPAT (0x1<<27) // Enable the updated version fo the Gen3 Compliance pattern generation rather than the 0.70 version.
5901 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_INSERT (0x1<<28) // Enable insertion of DC balance symbols on the transmitted training sequences.
5903 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_RESTORE (0x1<<29) // Enable correction of DC balance symbols on the received training sequences.
5905 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_INGORE_USER_ALLOW_GEN3 (0x1<<30) // Ignore the "strap" setting for user_allow_gen3.
5907 #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FORCE_G3_ADV (0x1<<31) // Force initial setting of Gen3 advertisement.
5912 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_EDS (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a framing/receiver error
5914 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_SYM_CNT_ERR (0x1<<21) // Enable bad block count as a framing/receiver error
5916 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SYNCHEADER_ERR (0x1<<22) // Enable invalid sync header as a framing/receiver error
5918 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_LEN_ERR (0x1<<23) // Enable the auxilliary bad TLP length to be reported as a framing/receiver error.
5920 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_BADSYNC_ALWAYS (0x1<<24) // Enable the auxilliary bad sync header to be reported as an error in all cases.
5922 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_L0_ALIGN_ERR (0x1<<25) // Enable the auxilliary alignment error to be reported as a framing/receiver error in L0.
5924 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ALL_ALIGN_ERR (0x1<<26) // Enable the auxilliary alignment error to be reported as a framing/receiver error in Configuration and Recovery as well as L0.
5926 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BLOCK_LANE_ERR (0x1<<27) // Enable bad sync header errors as lane status errors in the Secondary PCIE structure.
5928 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_AUX_FRAMERR_RETRAIN (0x1<<28) // Enable auxilliary framing errors to cause a retrain (if framing errors are enabled for retraining).
5930 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SKIPDATA_ERR (0x1<<29) // Enable generation of an error if the skipped/null data misaligns.
5932 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_DIS_PARITY_ERR (0x1<<30) // Disable reporting Gen3 data parity errors in the Secondary PCIE structure.
5934 #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_IDLE_START_ERR (0x1<<31) // Eanble error when idle symbols appear in the DW before a TLP or DLLP
5937 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_GEN3_EQ_TSX (0x1<<0) // Disable transmission of the equalization TS1s and TS2s.
5941 #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_5 (0x1<<4) //
5943 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_QUIESCE_GUARANTEE (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
5945 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_NO_REDO (0x1<<6) // Disable redo
5949 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_ON_REDO (0x1<<11) // Disable equalization request on redo.
5951 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_REQUEST_EQUALIZATION (0x1<<12) // Software can request that the link partner initiates equalization.
5953 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_FROM_PHY (0x1<<13) // Disable requests from the Serdes to request equalization.
5955 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_SYM6 (0x1<<14) // Enable symbol 6 (TS1 or TS2) matching requirements for consecutive TS1s or TS2s.
5957 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_PARITY (0x1<<15) // Enable parity matching for Gen3 TS1s, symbols 6 through 9
5959 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQUALIZATION (0x1<<16) // Disable Gen3 equalization.
5961 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_TIMERS (0x1<<17) // For debug purposes, disable timeouts from Recovery.Equalization phases.
5963 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_DLP_HOLD_CLEAR (0x1<<18) // Clear indication that a DLP was received on change to Gen3.
5965 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_TX_DLP_HOLDOFF (0x1<<19) // Hold off sending DLPs until equalization is complete
5967 #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_4 (0x1<<20) //
5969 #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_2 (0x1<<21) //
5971 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC3_ECHO_PRESET (0x1<<22) // enable echo preset bit in Phase 3
5973 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_CLR_RCFG_PRESETS (0x1<<23) // Clear previously received presets on entry to Recovery.RcvrCfg
5975 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_LPBK_EC23_ENA (0x1<<24) // In Gen3 Loopback Slave shall take the transmitter setting specified by the received TS1 if the EC field is set to 2'b10 or 2'b11 depending on whether Slave is an RC or EP respectively. When this bit is set to '1', Slave takes the settings when EC is either 2'10 or 2'11.
5977 #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED (0x1<<25) //
5979 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_PH2_PRESETS (0x1<<26) // Disable presets in Phase 2 (raw data to Serdes)
5981 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EQ_TS1 (0x1<<27) // Enable transmisssion of EQ TS1s (mainly for RC functionality)
5983 #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_1 (0x1<<28) // Reserved - only write 0
5985 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_TXEC_DELAY (0x1<<29) // Disable timeout counter delay waiting for EC bits to change in equalization
5987 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC2_EXIT_ON_TXEC3 (0x1<<30) // Enable exiting Phase 2 only on Tx of EC=2'b11 regardless of what is received
5989 #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_PH2_MATCH_PRESETS (0x1<<31) // Enable preset vs ceofficient matching during Phase 2 based on Serdes request
5994 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_20X (0x1<<5) // 20x timer speedup for use with Gen3 uC equalization
5996 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_50X (0x1<<6) // 50x timer speedup for use with Gen3 uC equalization
5998 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_MATCH_EQ_SYM1TO5 (0x1<<7) // For Gen3 TS1s in Equalization, match symbols 1 to 5 as well
6000 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_DCBAL_SOS (0x1<<8) // Enable SOS data DC balance accumulation
6002 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_SERDES (0x1<<9) // Enable Gen3 redo deskew on request from Serdes
6004 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_PIPE (0x1<<10) // Enable Gen3 redo deskew on PIPE misalignment issues
6006 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_FRAME (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issues
6008 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RLOCK (0x1<<12) // Assert signal to PHY when idle_to_rlock transition is taken.
6010 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RXL0S (0x1<<13) // Assert signal to PHY when Rx_L0s times out
6012 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_TMOUT (0x1<<14) // Enable the L1 failure on 24 ms timeout in R.Lock
6014 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_L0SL1_FAIL (0x1<<15) // Use the l0s/l1 failure signal only for Gen3
6016 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_PHY_L1_ACTIVE (0x1<<16) // Use the phy l1 active signal only for Gen3
6018 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_ANY_EQTS2 (0x1<<17) // Select between requiring all EQ TS2s or any EQ TS2 to set start_eq_w_preset
6020 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_BLOCK_ALIGN_RCFG_RESET (0x1<<18) // Reset needed flops on block align during Recovery.RcvrCfg
6022 #define PCIEIP_REG_REG_PHY_CTL_11_UNUSED (0x1<<19) //
6024 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PRESET_MISMATCH (0x1<<20) // Enable check for mismatch of presets in R.Lock after equalization
6026 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYLINKUP_HOLDOFF (0x1<<21) // Enable PhyLinkUp holdoff in Gen3 (for InitFC vs UpdateFC issue)
6028 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH3_PRESET_COEFF (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup for EQ Phase 3
6030 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH2_TXRX_PRESET_MATCH (0x1<<23) // (PL_FIX_05) Tx/Rx presets in phase 2 must match before preset signal to Serdes asserted
6034 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2 (0x1<<27) // (PL_FIX_15) For a possible ECN, send EQ TS2s
6036 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_REDO (0x1<<28) // (PL_FIX_15) For a possible ECN, send EQ TS2s as an endpoint when redoing equalization
6038 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EIOS (0x1<<29) // Enable Serdes IEI signal on internal EIOS detect
6040 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EI (0x1<<30) // Enable Serdes IEI signal on internal EI detect
6042 #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_IEI (0x1<<31) // Enable Serdes IEI signal on internal IEI
6047 #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_AUTOINC (0x1<<6) // SED read address auto-increment
6049 #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_ADDR (0x1<<7) // SED clear read address to 0
6053 #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR (0x1<<12) // Clear SED memory and write address
6061 #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_TRIG_HOLD (0x1<<28) // Hold off SED triggering
6063 #define PCIEIP_REG_REG_PHY_CTL_12_REG_GEN3_ENA_PH1_FS_LF (0x1<<29) // [DEBUG_BIT}: Captures internal defined FS and LF values when receive use preset = 1 in EQ Phase 1
6076 #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_WRSTB (0x1<<22) // Write strobe for Preset LUT
6078 #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_SERDES_PRESET_SEL (0x1<<23) // Conbtrol bit to select the default preset to use in phase2 advertizement provided on pcie_rx_linkevalfm signal from Serdes to MAC
6082 #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_PRESET_EQ2_REQ (0x1<<28) // Use programmable preset Phase2 EQ in EP mode
6084 #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_COEFF_EQ2_REQ (0x1<<29) // [DEBUG_BIT]: use programmable coefficients in Phase2 EQ
6086 #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_EN_LP_COEFF_MATCH (0x1<<30) // enable LP coeffcient match checking in default/noraml Phase2 EQ
6088 #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_ENA_PH2_PRESET_COEFF (0x1<<31) // [DEBUG_BIT]: enable conversion of preset to coefficients to serdes when LP is always a preset use Phase2 EQ
6095 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ0_TO (0x1<<7) // [SEMI_FUNCTIONAL]: Extend EQ until Phase0 timeout for Normal EQ handshaking
6097 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ1_TO (0x1<<8) // [SEMI_FUNCTIONAL]: Extend EQ until Phase1 timeout for Normal EQ handshaking
6099 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ2_TO (0x1<<9) // [SEMI_FUNCTIONAL]: Extend EQ until Phase2 timeout for Normal EQ handshaking
6101 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ3_TO (0x1<<10) // [SEMI_FUNCTIONAL]: Extend EQ until Phase3 timeout for Normal EQ handshaking
6103 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH0_TIMEOUT (0x1<<11) // Disable timeout for Equalization Phase0
6105 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH1_TIMEOUT (0x1<<12) // Disable timeout for Equalization Phase1
6107 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH2_TIMEOUT (0x1<<13) // Disable timeout for Equalization Phase2
6109 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH3_TIMEOUT (0x1<<14) // Disable timeout for Equalization Phase3
6111 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_L1ONLY_RECOVLOCK_TO (0x1<<15) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State through L1 exit recovery
6113 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_RECOVLOCK_TO (0x1<<16) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State through any exit recovery
6115 #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_SEL (0x1<<17) // [SEMI_FUNCTIONAL]: Extend programmable timeout select control in RecovRecvrLock State
6125 #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_INDEX (0x1<<18) // Gen1/Gen2 deemphasis register control programming index for preset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(-3.5dB)
6127 #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_WRSTB (0x1<<19) // Gen1/Gen2 deemphasis register control programming write strobe for Preset 0 and 1
6129 #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_SEL (0x1<<20) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(-6dB)
6131 #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN123_DEEMPH_PRESET_SEL (0x1<<21) // Select control bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to the corresponding index. 0: Selects Gen3 read preset lut pointing to the reg_gen3_preset_lut_index value 1: Selects Gen1/2 read preset lut pointing to the reg_gen12_deemph_index value
6133 #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_IGNORE_SERDES_EVALDC (0x1<<22) // [DEBUG_BIT]: Ignore serdes direction change and controls from the MAC register
6137 #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC2_EN_COEFFPR_MATCHREJ_TWOTS1 (0x1<<29) // [DEBUG_BIT]: Phase2: Controls enabling of the two consecutive EQ TS1's for checking preset and coefficient matches
6139 #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC3_EN_COEFFPR_MATCHREJ_TWOTS1 (0x1<<30) // [DEBUG_BIT]: Phase3: Controls enabling of the two consecutive EQ TS1's for checking preset and coefficient matches
6141 #define PCIEIP_REG_REG_PHY_CTL_16_REG_CLR_RECOV_EQ_SM_HIST (0x1<<31) // [DEBUG_BIT]: clears the previous statate transitions captured for recovery eq statemachine in ph2(EP) and ph3(RC)
6144 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRECTRL_LSB_EN (0x1<<0) // AFE TX deemphasis register override enable control bit for prectrl[1:0] LSB two bits
6148 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_EN (0x1<<3) // AFE TX deemphasis register override enable control bit for main[1:0] LSB two bits
6152 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_EN (0x1<<6) // AFE TX deemphasis register override enable control bit for postctrl[1:0] LSB two bits
6156 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_EN (0x1<<9) // AFE TX deemphasis register override enable control bit for prectrl[4:2] upper three bits
6160 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_EN (0x1<<13) // AFE TX deemphasis register override enable control bit for main[4:2] upper five bits
6164 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_EN (0x1<<19) // AFE TX deemphasis register override enable control bit for postctrl[5:2] upper four bits
6168 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_EN (0x1<<24) // AFE TX deemphasis register override enable control bit for post2[3:0] four bits
6172 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH2_RXEVAL_TO_SERDES (0x1<<29) // Phase2: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout to occur.
6174 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH3_RXEVAL_TO_SERDES (0x1<<30) // Phase3: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout to occur.
6176 #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_RX_RESET_EIEOS (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Recovery.Equalizations. Default zero value
6179 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_EN (0x1<<0) // Enable bit to control the registered programmed FULL SWING value in Phase 1 of eualization
6183 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_EN (0x1<<7) // Enable bit to control the registered programmed LOW FREQUENCY value in Phase 1 of eualization
6187 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_RX_COEFF_SEL (0x1<<14) // Selects to the received coefficients in the phase 2 of equalization. The default coefficientis a defined value.
6189 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DISABLE_REQ_WAIT_1USEC (0x1<<15) // [DEBUG_BIT]: Disables the 1usec wait time for LP to response for preset or coeff req in phase2(EP and phase3(RC) modes..
6191 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_ENA_EC0_ECHO_PRESET (0x1<<16) // Enables EC0 echo use preset bit in EP mode
6193 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_ENA_EC2_ECHO_PRESET (0x1<<17) // Enables EC2 echo use preset bit in RC mode
6195 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_USE_PRESET_EQ3_REQ (0x1<<18) // Use programmable preset Phase3 EQ in RC mode
6197 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_IGNORE_USE_PRESET_CHECK (0x1<<19) // [DEBUG_BIT]: Ignore the receive ec2 use preset check in phase2 of equalization for the eq eval state machine
6199 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH3_DIS_RULE_CHECK (0x1<<20) // [DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 3 of equalization in EP mode
6201 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH2_DIS_RULE_CHECK (0x1<<21) // [DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 2 of equalization in RC mode
6203 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_IGNORE_USE_PRESET_REDO_CHECK (0x1<<22) // [DEBUG_BIT]: Ignores the phase 2 received usepreset bit when checking for preset mismatch at the end of equalization
6205 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_SKIP_EQ_PHASE23 (0x1<<23) // RC Mode: Skips equalizationphas 2 and Phase 3.
6207 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DIS_EVAL_COEFF_MATCH (0x1<<24) // [DEBUG_BIT]: EP mode Phase2: Disables the coefficient match reject status in EVAL and Adjust eval states
6209 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC3_DIS_EVAL_COEFF_MATCH (0x1<<25) // [DEBUG_BIT]: RC mode Phase3: Disables the coefficient match reject status in EVAL and Adjust eval states
6211 #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_FORCE_EQ_EVERY_SPDCHG (0x1<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
6216 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_ILLEGAL_OS_AFTER_EDS_ERR (0x1<<0) // Enable Illegal Ordered Set After EDS Error. When this bit is set to '1', report Gen3 framing error if an OS other than EIOS, EIEOS, or SKPOS is detected after an EDS token.
6218 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_AFTER_SDS_ERR (0x1<<1) // Enable Ordered Set After SDS Error. When this bit is set to '1', report Gen3 framing error if an OS is detected right after an SDS token.
6220 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_NO_EDS_ERR (0x1<<2) // Enable Ordered Set with No EDS Error. When this bit is set to '1', report Gen3 framing error if an OS is detected without a preceding EDS token while in middle of a data stream.
6222 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FCRC_ERR (0x1<<3) // Enable Bad Framing CRC Error. When this bit is set to '1', report Gen3 framing error if bad framing CRC is detected in a STP token.
6224 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FP_ERR (0x1<<4) // Enable Bad Framing Parity Error. When this bit is set to '1', report Gen3 framing error if bad framing parity is detected in a STP token.
6226 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_EDB_ERR (0x1<<5) // Enable Bad EDB Error. When this bit is set to '1', report Gen3 framing error if a bad EDB token is detected.
6228 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FRAMING_SYM_ERR (0x1<<6) // Enable Bad Framing Symbol Error. When this bit is set to '1', report Gen3 framing error if a framing token is not detected at the expection position.
6230 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_DATA_AFTER_EDS_ERR (0x1<<7) // Enable Data After EDS Error. When this bit is set to '1', report Gen3 framing error if a data block is detected after an EDS token.
6233 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENA (0x1<<0) // Loopback Master Enable. Setting this bit to '1' enables the master loopback operation. Normally, if lpbk_master_len is set to '0', software has to clear this bit to stop the operation. Otherwise, hardware automatically clears this bit when the operation is done. In case the loopback operation is timeout during Loopback.Entry state, hardware clears this bit before returning to Detect state regardless of the setting of lpbk_master_len.
6235 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENTRY (0x1<<1) // Loopback Master Entry State. If this bit is set to '1', loopback is entered from Recovery.Idle state; otherwise, loopback is entered from Configuration.Linkwidth.Start state.
6237 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SET_COMPL_RECV (0x1<<2) // Loopback Master Set Compliance Receive. If this bit is set to '1', the Compliance Receive bit in TS1 is set to '1' when loopback master initiates the loopback operation. This feature allows Loopback Slave to enter Loopback.Active state without achieving symbol lock or block alignment.
6239 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_AUTO_COMPL_RECV (0x1<<3) // Loopback Master Automatically Set Compliance Receive. If this bit is set to '1', hardware automatically sets the Compliance Receive bit in TS1 to '1' during Loopback.Entry state when loopback is entered from Configuration.Linkwidth.Start state and Gen3 is the highest common speed.
6241 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_FRC_SETTING (0x1<<4) // Loopback Master Force Setting. When loopback is entered from Recov.Idle state and this bit is set to '1', hardware applies the settings specified in lpbk_master_slave_setting and lpbak_master_tx_setting registers.
6243 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SKPOS (0x1<<5) // Loopback Master Skip Ordered Set. When this bit is set, SKP OS are periodically inserted to loopback data. If data is generated by PHY, MAC provides SKP OS to PHY using a req/ack handshake. If it is Gen3 and data is generated by PHY without framing, this bit is ignored.
6245 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ONE_SKPOS (0x1<<6) // Loopback Master One Skip Ordered Set. PCIE Spec requires that in Gen3 loopback master inserts two SKIP ordered sets for each SKIP OS interval. For testing purpose, when this bit is set to '1', hardware inserts only one SKP OS for each interval.
6247 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_2 (0x1<<7) //
6259 #define PCIEIP_REG_PL_LPBK_MASTER_STAT_LPBK_MASTER_STAT (0x1<<0) // Loopback Master Status. This is the status of the last loopback operation. 1'b0: completed normally 1'b1: exited because of timeout during Loopback.Entry state
6266 #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_USEPRESET (0x1<<7) // Loopback Master TS1 Use Preset. This value is sent in TS1, byte6[7] if the current rate is Gen3.
6274 #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_G2_DEEMPH (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value is sent in TS1, byte4[6] if the highest common rate is Gen2.
6282 #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_ENA (0x1<<0) // Software LTSSM Enable. Setting this bit to '1' allows software to take control of the LTSSM.
6284 #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_DLYSTART (0x1<<1) // Software LTSSM Delay Start. When this bit is set together with sw_ltssm_ena, hardware continues to operate as normal until LTSSM reaches to the state specified by sw_ltssm_topst and sw_ltssm_subst. Once software starts controlling LTSSM, it continues to do so until sw_ltssm_ena is reset to '0'. This feature allows software to control LTSSM in some certain states but not all.
6286 #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_UPDT (0x1<<2) // Software LTSSM Update. Writing a '1' to this bit updates the internal software LTSSM state with the state specified by sw_ltssm_topst and sw_ltssm_subst. If software is in control, the new state will be applied to LTSSM. This bit is self-cleared, so reading always retuns '0'.
6288 #define PCIEIP_REG_PL_SW_LTSSM_CTL_LTSSM_TMOUT_DIS (0x1<<3) // LTSSM Timeout Disable. When this bit is set to '1', all LTSSM timeouts are disabled.
6300 #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_INT_ENA (0x1<<31) // Software LTSSM Internal Enable. This bit reflects the internal software LTSSM enable that is set to '1' only when S/W is actually in control of the LTSSM. If sw_ltssm_dlystart is '1', the internal enable is not set until LTSSM reaches the desired state.
6303 #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_ENA (0x1<<0) // PCIE Statistic Enable. Setting this bit to '1' enables the PCIE statistic collection. Hardware will count various things such as the number of TLP, DLLP, OS bytes transferred in both RX and TX direction, the number of detected errors etc. When this bit is reset to '0', the counting stops and software can read the results. This bit can be automatically cleared after the specified time if pcie_statis_len is non-zero. All statistic read-back registers are cleared when this bit transitions from '0' to '1'.
6337 #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_ENA (0x1<<0) // LTSSM Statistic Enable. Setting this bit to '1' enables the LTSSM statisic collection. When this bit is reset to '0', information is frozen so S/W can read the results. All statistic registers are reset when this bit transitions from '0' to '1'.
6339 #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_AUTOINC (0x1<<1) // LTSSM Statistic Auto Increment. When this bit is set to '1', hardware automatically increases the ltssm_statis_rdaddr by 1 after register ltssm_statis_N is read.
6341 #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_RDADDR (0x1<<2) // LTSSM Statistic Readback Address. ltssm_statis_0 to ltssm_statis_N are stored in FIFOs. This field indicates the current readback address of the LTSSM Statistic FIFO. Reading ltssm_statis_0 to ltssm_statis_N registers return the values stored at current address. Software writes to this field to specify the starting FIFO offset where it wants to read back LTSSM statistic data.
6373 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_12 (0x1<<7) // For lane 12: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6377 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_13 (0x1<<15) // For lane 13 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6381 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_14 (0x1<<23) // For lane 14: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6385 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_15 (0x1<<31) // For lane 15 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6390 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_8 (0x1<<7) // For lane 8: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6394 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_9 (0x1<<15) // For lane 9 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6398 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_10 (0x1<<23) // For lane 10: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6402 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_11 (0x1<<31) // For lane 11 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6407 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_4 (0x1<<7) // For lane 4: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6411 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_5 (0x1<<15) // For lane 5 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6415 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_6 (0x1<<23) // For lane 6: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6419 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_7 (0x1<<31) // For lane 7 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6424 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_0 (0x1<<7) // For lane 0: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6428 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_1 (0x1<<15) // For lane 1 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6432 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_2 (0x1<<23) // For lane 2: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6436 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_3 (0x1<<31) // For lane 3 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6441 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_12 (0x1<<7) // For lane 12: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6445 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_13 (0x1<<15) // For lane 13 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6449 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_14 (0x1<<23) // For lane 14: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6453 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_15 (0x1<<31) // For lane 15 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6458 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_8 (0x1<<7) // For lane 8: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6462 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_9 (0x1<<15) // For lane 9 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6466 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_10 (0x1<<23) // For lane 10: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6470 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_11 (0x1<<31) // For lane 11 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6475 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_4 (0x1<<7) // For lane 4: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6479 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_5 (0x1<<15) // For lane 5 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6483 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_6 (0x1<<23) // For lane 6: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6487 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_7 (0x1<<31) // For lane 7 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6492 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_0 (0x1<<7) // For lane 0: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6496 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_1 (0x1<<15) // For lane 1 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6500 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_2 (0x1<<23) // For lane 2: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6504 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_3 (0x1<<31) // For lane 3 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6617 #define PCIEIP_REG_ATE_LOOPBACK_INFO_PCIE_PHY_GLOOPBACK (0x1<<5) // Current state of the gloopback signal to the Serdes
6619 #define PCIEIP_REG_ATE_LOOPBACK_INFO_REG_GLOOPBACK (0x1<<6) // Current state of the "pins" gloopback request
6624 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_FRAMING_ERR (0x1<<0) // A framing error occurred
6626 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FCRC (0x1<<1) // FCRC error in the STP token
6628 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FP (0x1<<2) // Parity error in the STP token
6630 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_EDB (0x1<<3) // Badly formed or misplaced EDB token
6632 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FRAMING_SYM (0x1<<4) // No valid framing symbol in the data stream
6634 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_BLOCK_TYPE (0x1<<5) // Serdes indicated a bad block type (sync header of 00b or 11b)
6636 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_AFTER_SDS (0x1<<6) // An ordered set occurred after an SDS without an EDS first
6638 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_DATA_AFTER_EDS (0x1<<7) // Data block occurred immediately after an EDS token
6640 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_NO_EDS (0x1<<8) // An ordered set occurred in the data stream without a prior EDS
6642 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_MULT_ORDEREDSETS (0x1<<9) // Ordered set follows SKP ordered set after EDS
6644 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_RETRAIN_ON_GEN3_BLOCKALIGN (0x1<<10) // Retraining occurred due to block misalignment
6646 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BLOCK_ALIGN_ERR (0x1<<11) // Block alignment error from the Serdes
6648 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_EDS (0x1<<12) // Misplaced or badly formed EDS token
6650 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_SYM_CNT (0x1<<13) // Incorrect length for a data block
6652 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SYNCHEADER (0x1<<14) // Mismatch or misalignment in the sync headers
6654 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_LEN (0x1<<15) // Bad Gen3 TLP length
6656 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SKIPDATA (0x1<<16) // Misalignment in the null/skipped data
6658 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BAD_SKIP_DATA_RATE (0x1<<17) // Too many or too few RxDataValid deassertions in 65 clocks at Gen3.
6660 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_IDLE_START (0x1<<18) // Error when in the same symbol time Idle symbols appear in the DW before a TLP or a DLLP.
6662 #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ILLEGAL_EDSOS (0x1<<19) // This bit is set to '1' when the ordered set following an EDS token is other than SKP OS, EIEOS, or EIOS.
6848 #define PCIEIP_REG_MISC_DBG_STATUS_USER_ALLOW_GEN3_SYNC (0x1<<0) // Instantaneous value of the top-level user_allow_gen3 signal (sync'd to the cfg_clk domain). The reset value will depend on the environment.
6858 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN (0x1<<0) // Enables IO Access Response. You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
6860 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN (0x1<<1) // Enables Memory Access Response. You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
6862 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests.
6864 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION (0x1<<3) // Special Cycle Enable.
6866 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE (0x1<<4) // Memory Write and Invalidate.
6868 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP (0x1<<5) // VGA Palette Snoop.
6870 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN (0x1<<6) // Controls Logging of Poisoned TLPs.
6872 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING (0x1<<7) // IDSEL Stepping.
6874 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN (0x1<<8) // Enables Error Reporting.
6876 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN (0x1<<10) // Controls generation of interrupts by a function.
6880 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS (0x1<<19) // Emulation interrupt pending.
6882 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST (0x1<<20) // Extended Capability.
6884 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP (0x1<<21) // PCI 66MHz Capability.
6886 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP (0x1<<23) // Fast Back to Back Transaction Capable and Enable.
6888 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE (0x1<<24) // Controls poisoned Completion and Request error reporting.
6892 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT (0x1<<27) // Completer Abort Error.
6894 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT (0x1<<28) // Completer Abort received.
6896 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT (0x1<<29) // Unsupported request completion status received.
6898 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message sent by function.
6900 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR (0x1<<31) // Poisoned TLP received by function.
6918 #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC (0x1<<23) // Specifies whether device is multifunction. Note: This register field is sticky.
6923 #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO (0x1<<0) // BAR0 Memory Space Indicator.
6927 #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH (0x1<<3) // BAR0 Prefetchable.
6932 #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO (0x1<<0) // BAR1 Memory Space Indicator.
6936 #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH (0x1<<3) // BAR1 Prefetchable.
6941 #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO (0x1<<0) // BAR2 Memory Space Indicator.
6945 #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH (0x1<<3) // BAR2 Prefetchable.
6950 #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO (0x1<<0) // BAR3 Memory Space Indicator.
6954 #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH (0x1<<3) // BAR3 Prefetchable.
6959 #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO (0x1<<0) // BAR4 Memory Space Indicator.
6963 #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH (0x1<<3) // BAR4 Prefetchable.
6968 #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO (0x1<<0) // BAR5 Memory Space Indicator.
6972 #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH (0x1<<3) // BAR5 Prefetchable.
6999 #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP (0x1<<24) // PCIe Slot Implemented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7003 #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD (0x1<<30) // Reserved.
7010 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP (0x1<<5) // Extended Tag Field Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7016 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT (0x1<<15) // Role-based Error Reporting Implemented.
7022 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP (0x1<<28) // Function Level Reset Capability (endpoints only).
7025 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN (0x1<<0) // Correctable Error Reporting Enable.
7027 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN (0x1<<1) // Non-fatal Error Reporting Enable.
7029 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN (0x1<<2) // Fatal Error Reporting Enable.
7031 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN (0x1<<3) // Unsupported Request Reporting Enable.
7033 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER (0x1<<4) // Enable Relaxed Ordering.
7037 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN (0x1<<8) // Extended Tag Field Enable. The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
7039 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN (0x1<<9) // Phantom Functions Enable. The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
7041 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN (0x1<<10) // Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input.
7043 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP (0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
7047 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR (0x1<<15) // Initiate Function Level Reset (for endpoints).
7049 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED (0x1<<16) // Correctable Error Detected Status.
7051 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED (0x1<<17) // Non-Fatal Error Detected Status.
7053 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED (0x1<<18) // Fatal Error Detected Status.
7055 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED (0x1<<19) // Unsupported Request Detected Status.
7057 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED (0x1<<20) // Aux Power Detected Status. This bit is derived by sampling the sys_aux_pwr_det input.
7059 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING (0x1<<21) // Transactions Pending Status.
7072 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN (0x1<<18) // Clock Power Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7074 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP (0x1<<19) // Surprise Down Error Reporting Capable.
7076 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP (0x1<<20) // Data Link Layer Link Active Reporting Capable.
7078 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP (0x1<<21) // Link Bandwidth Notification Capable.
7080 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE (0x1<<22) // ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
7087 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB (0x1<<3) // Read Completion Boundary (RCB).
7089 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE (0x1<<4) // Initiate Link Disable. In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
7091 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK (0x1<<5) // Initiate Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
7093 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG (0x1<<6) // Common Clock Configuration.
7095 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH (0x1<<7) // Extended Synch.
7097 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN (0x1<<8) // Enable Clock Power Management. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO
7099 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE (0x1<<9) // Hardware Autonomous Width Disable.
7101 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN (0x1<<10) // Link Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
7103 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
7111 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
7113 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG (0x1<<28) // Slot Clock Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7115 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE (0x1<<29) // Data Link Layer Active.
7117 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS (0x1<<30) // Link Bandwidth Management Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
7119 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS (0x1<<31) // Link Autonomous Bandwidth Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
7124 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT (0x1<<4) // Completion Timeout Disable Supported.
7126 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT (0x1<<5) // ARI Forwarding Supported.
7128 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP (0x1<<6) // Atomic Operation Routing Supported.
7130 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP (0x1<<7) // 32 Bit AtomicOp Completer Supported.
7132 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP (0x1<<8) // 64 Bit AtomicOp Completer Supported.
7134 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP (0x1<<9) // 128 Bit CAS Completer Supported.
7136 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
7138 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP (0x1<<11) // LTR Mechanism Supported.
7140 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0 (0x1<<12) // TPH Completer Supported Bit 0.
7142 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1 (0x1<<13) // TPH Completer Supported Bit 1.
7149 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE (0x1<<4) // Completion Timeout Disable.
7151 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS (0x1<<5) // ARI Forwarding Enable.
7153 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN (0x1<<6) // AtomicOp Requester Enable.
7155 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK (0x1<<7) // AtomicOp Egress Blocking.
7157 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN (0x1<<8) // IDO Request Enable.
7159 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN (0x1<<9) // IDO Completion Enable.
7161 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN (0x1<<10) // LTR Mechanism Enable. The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG. Note: RW for function #0 and RsdvP for all other functions
7168 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT (0x1<<8) // Cross Link Supported.
7170 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED (0x1<<31) // DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7175 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE (0x1<<4) // Enter Compliance Mode. Note: This register field is sticky.
7177 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE (0x1<<5) // Hardware Autonomous Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
7179 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. Note: This register field is sticky.
7183 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE (0x1<<10) // Enter Modified Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
7185 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS (0x1<<11) // Sets Compliance Skip Ordered Sets transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
7189 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE
7191 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL (0x1<<17) // Equalization 8.0GT/s Complete. Note: This register field is sticky.
7193 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: This register field is sticky.
7195 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2 (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful. Note: This register field is sticky.
7197 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: This register field is sticky.
7199 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ (0x1<<21) // Link Equalization Request 8.0GT/s.
7203 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
7212 #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK (0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
7214 #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
7234 #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability.
7236 #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP (0x1<<1) // ACS Function Groups Capability.
7240 #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN (0x1<<16) // MFVC Function Groups Enable.
7242 #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN (0x1<<17) // ACS Function Groups Enable.
7254 #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE (0x1<<0) // No ST Mode Supported.
7256 #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC (0x1<<1) // Interrupt Vector Mode Supported. Note: This register field is sticky.
7258 #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC (0x1<<2) // Device Specific Mode Supported. Note: This register field is sticky.
7260 #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH (0x1<<8) // Extended TPH Requester Supported. Note: This register field is sticky.
7262 #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0 (0x1<<9) // ST Table Location Bit 0. Note: This register field is sticky.
7264 #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1 (0x1<<10) // ST Table Location Bit 1. Note: This register field is sticky.
7279 #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED (0x1<<0) // BAR0 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7284 #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED (0x1<<0) // BAR1 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7289 #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED (0x1<<0) // BAR4 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7294 #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED (0x1<<0) // BAR5 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7299 #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED (0x1<<0) // Expansion ROM Bar Mask Register Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if ROM_BAR_ENABLED then W else R
7314 #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED (0x1<<0) // BAR0 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7319 #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED (0x1<<0) // BAR1 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7324 #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED (0x1<<0) // BAR2 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7329 #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED (0x1<<0) // BAR3 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7334 #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED (0x1<<0) // BAR4 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7339 #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED (0x1<<0) // BAR5 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky.
7343 #define SEM_FAST_REG_RAM_EXT_DISABLE 0x000004UL //Access:RW DataWidth:0x1 // Disable for SDM write to int_ram.
7344 #define SEM_FAST_REG_INT_STS 0x000040UL //Access:R DataWidth:0x1 // Multi Field Register.
7345 #define SEM_FAST_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
7347 #define SEM_FAST_REG_INT_MASK 0x000044UL //Access:RW DataWidth:0x1 // Multi Field Register.
7348 #define SEM_FAST_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: SEM_FAST_REG_INT_STS.ADDRESS_ERROR .
7350 #define SEM_FAST_REG_INT_STS_WR 0x000048UL //Access:WR DataWidth:0x1 // Multi Field Register.
7351 #define SEM_FAST_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
7353 #define SEM_FAST_REG_INT_STS_CLR 0x00004cUL //Access:RC DataWidth:0x1 // Multi Field Register.
7354 #define SEM_FAST_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
7356 #define SEM_FAST_REG_ERROR_RST 0x000050UL //Access:W DataWidth:0x1 // Reset to error interrupt.
7357 #define SEM_FAST_REG_PARITY_RST 0x000054UL //Access:W DataWidth:0x1 // Reset to parity interrupt.
7359 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
7361 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
7363 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
7365 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
7367 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
7369 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
7371 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
7407 #define SEM_FAST_REG_STALL_0 0x000488UL //Access:RW DataWidth:0x1 // This register is used to define the state of an independent stall source. This is the first of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.
7408 #define SEM_FAST_REG_STALL_1 0x00048cUL //Access:RW DataWidth:0x1 // This register is used to define the state of an independent stall source. This is the second of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.
7409 #define SEM_FAST_REG_STALL_2 0x000490UL //Access:RW DataWidth:0x1 // This register is used to define the state of an independent stall source. This is the last of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.
7410 #define SEM_FAST_REG_STALLED 0x000494UL //Access:R DataWidth:0x1 // This register provides a status to indicate whether or not the Storm is currently stalled.
7411 #define SEM_FAST_REG_STALL_RST 0x000498UL //Access:W DataWidth:0x1 // Writing this register with any value causes all the internal and external stall sources to be reset, resulting in the negation of the stall signal.
7412 #define SEM_FAST_REG_STORM_ATTN_STALL_CLR 0x00049cUL //Access:W DataWidth:0x1 // Used to clear the latched storm attention stall signal.
7417 #define SEM_FAST_REG_PRAM_PRTY_RELEASE 0x0004b0UL //Access:W DataWidth:0x1 // Writing this register with any value causes the PRAM ECC replay logic to be executed and the PRAM parity stall to be released following the reload of the PRAM data path.
7418 #define SEM_FAST_REG_PRAM_PRTY_INT_CLR 0x0004b4UL //Access:W DataWidth:0x1 // Writing this register with any value causes the PRAM parity error to be cleared.
7420 #define SEM_FAST_REG_PORT_ID_OFFSET 0x0004bcUL //Access:RW DataWidth:0x5 // Defines the offset (in bits) from the lsb of the CID in which to assign to bit-0 of the port ID. I.e. if port_id_wdth is set to 0x1 and port_id_ofset is set to 0x8, then the port ID is assigned from bits [9:8] of the CID.
7421 #define SEM_FAST_REG_ACTIVE_REG_SET 0x0004c0UL //Access:R DataWidth:0x1 // Defines the Storm register file set that is currently active.
7447 #define SEM_FAST_REG_CAM_VALID 0x000650UL //Access:R DataWidth:0x1 // This register delivers the valid bit from CAM for the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All other bits will be zero.
7450 #define SEM_FAST_REG_CAM_CONTROL_CAM_INIT_EN (0x1<<0) // Writing a one to this register bit (transition from 0 to 1) causes the entire CAM to be zeroed and all entries to be invalidated.
7452 #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_HIT_EN (0x1<<1) // When set, this bit enables hit parity scrubbing on the CAM.
7454 #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_MISS_EN (0x1<<2) // When set, this bit enables miss parity scrubbing on the CAM.
7456 #define SEM_FAST_REG_CAM_INIT_IN_PROCESS 0x00065cUL //Access:R DataWidth:0x1 // This register is set after the CAM initialization is started (by writing to cam_init) and remains set until the entire CAM initialization is complete.
7459 #define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL //Access:RW DataWidth:0x1 // Used to activate/deactivate the SEMI fast debug, based on the mode defined by the DebugMode register; 0=inactive, 1=active.
7460 #define SEM_FAST_REG_DEBUG_MODE 0x000744UL //Access:RW DataWidth:0x3 // Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7-Reserved. Note: this register is not applicable when DebugActive=0.
7472 #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_RCRD (0x1<<2) // (a) 1 - use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) for compariso; NOTE: NA if need to filter connection id prior to trigger event (filter_en=01 OR filter_en=11) as the connection id field which arrives from the DBG block (dbg_sem_cid interface) is valid upon triggering event only; (b) 0 - use the configuration connection id field (filter_cid) for comparison.
7474 #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_EN (0x1<<3) // Used to enable CID/TID filter for recording handlers, when set.
7476 #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVNT_ID_EN (0x1<<4) // Used to enable Event ID filter for recording handlers, when set.
7480 #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_EN (0x1<<7) // Used to enable DRA source filter for recording handlers, when set.
7482 #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVENT_ID_RANGE_EN (0x1<<8) // Used to enable filtering based on a range of event IDs rather than "match" filtering. When set, the event ID range is defined by the EventIDRangeStrt and EventIDRangeEnd registers.
7484 #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_STORE_EN (0x1<<9) // Used to enable the debug store address filter for fast debug, when set.
7496 #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_CID_EN (0x1<<0) // Used to enable CID/TID filter for Storm active statistics counter, when set.
7498 #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVNT_ID_EN (0x1<<1) // Used to enable Event ID filter for Storm active statistics counter, when set.
7502 #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC_EN (0x1<<4) // Used to enable DRA source filter for Storm active statistics counter, when set.
7504 #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVENT_ID_RANGE_EN (0x1<<5) // Used to enable active statistics filtering based on a range of event IDs rather than "match" filtering. When set, the event ID range is defined by the EventIDRangeStrt and EventIDRangeEnd registers.
7515 #define SEM_FAST_REG_CAM_BIST_EN 0x000c40UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
7519 #define SEM_FAST_REG_MEMCTRL_WR_RD_N 0x000cc0UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
7525 #define SEM_FAST_REG_CAM_REQUEST 0x009000UL //Access:RW DataWidth:0x4 // Writing this indirect register will cause a CAM command to be executed with the CAM offset specified by the indirect register sub-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numerations apply: 0x0=ADD, 0x1=SRCH, 0x2=INVALIDATE, 0x3=READ. Reading this register returns the OpCode of the most recent RBC-initiated CAM request.
7540 #define VFC_REG_TT_RESULT_EN 0x000024UL //Access:RW DataWidth:0x1 // This register defines value that will be written to DSt vector for analyze operation. If it is set to 1, then row from target table will be rwitten. If it is set to 0, then row from target table OR previous value of DST vector will be written.
7542 #define VFC_REG_INTERRUPT_IND_ADDRESS_INTERRUPT (0x1<<0) // This is error interrupt. It may be asserted when it was access to not existing address in VFC. Also it will be asserted when there is attempt to write to read only register. It will be de-asserted aftre write 1 to it.
7544 #define VFC_REG_INTERRUPT_IND_INP_FIFO_ITERRUPT (0x1<<1) // This is error interrupt. It may be asserted when it was input FIFO overflow.
7546 #define VFC_REG_INTERRUPT_IND_LEN_FIFO_INTERRUPT (0x1<<2) // This is error interrupt. It may be asserted when it was length FIFO overflow.
7548 #define VFC_REG_INTERRUPT_IND_INP_BUF_INTERRUPT (0x1<<3) // This is error interrupt. It may be asserted when it was input buffers overflow.
7550 #define VFC_REG_INTERRUPT_IND_OUT_BUF_INTERRUPT (0x1<<4) // This is error interrupt. It may be asserted when it was output buffer overflow.
7552 #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT (0x1<<5) // This is error interrupt. It may be asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write 1 to it.
7554 #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT (0x1<<6) // This is error interrupt. It may be asserted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
7556 #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT (0x1<<7) // This is error interrupt. It may be asserted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
7558 #define VFC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT (0x1<<8) // This is error interrupt. It may be asserted when it was RBC command with address not equal to 12 bit or data cycle not equal 64 bit or number of data cycles bigger than 6. It will be de-asserted aftre write 1 to it.
7560 #define VFC_REG_INTERRUPT_IND_DEADLOCK_INTERRUPT (0x1<<9) // This is error interrupt. It may be asserted when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write 1 to it.
7563 #define VFC_REG_PARITY_IND_RSS_RAM_PARITY (0x1<<0) // This is parity interrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write 1 to it.
7565 #define VFC_REG_PARITY_IND_CAM_PARITY (0x1<<1) // This is parity interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write 1 to it.
7567 #define VFC_REG_PARITY_IND_TT_RAM_PARITY (0x1<<2) // This is parity interrupt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write 1 to it.
7570 #define VFC_REG_INDICATIONS1_INP_FIFO_EMPTY (0x1<<0) // Empty indication from input FIFO.
7572 #define VFC_REG_INDICATIONS1_LEN_FIFO_EMPTY (0x1<<1) // Empty indication from length command FIFO.
7574 #define VFC_REG_INDICATIONS1_INP_BUF_EMPTY (0x1<<2) // Empty indication from input buffers.
7576 #define VFC_REG_INDICATIONS1_OUT_FIFO_EMPTY (0x1<<3) // Empty indication from output FIFO.
7578 #define VFC_REG_INDICATIONS1_SEM_FIFO_EMPTY (0x1<<4) // Empty indication from SEM output FIFO inside VFC.
7582 #define VFC_REG_INDICATIONS1_INP_FIFO_FULL (0x1<<8) // Full indication from input FIFO.
7584 #define VFC_REG_INDICATIONS1_LEN_FIFO_FULL (0x1<<9) // Full indication from length command FIFO.
7586 #define VFC_REG_INDICATIONS1_INP_BUF_FULL (0x1<<10) // Full indication from input buffers.
7588 #define VFC_REG_INDICATIONS1_OUT_FIFO_FULL (0x1<<11) // Full indication from output FIFO.
7590 #define VFC_REG_INDICATIONS1_SEM_FIFO_FULL (0x1<<12) // Full indication from SEM output FIFO inside VFC.
7594 #define VFC_REG_INDICATIONS1_RBC_RSP_RDY (0x1<<16) // Indicates if RBC response is ready.
7596 #define VFC_REG_INDICATIONS1_VFC_WAITP (0x1<<17) // Indicates if waitp from VFC to STORM is asserted.
7613 #define VFC_REG_SW_RST 0x000038UL //Access:W DataWidth:0x1 // Write to this bit will cause to block reset.
7615 #define VFC_REG_MEMORIES_RST_CAM_RST (0x1<<0) // Write 1 to this bit will cause reset of all CAM rows including valid bit and all bits in a row. Write 0 to it will have no effect. Read 1 from this bit means that CAM reset was finished. Read 0 from this bit means that CAM reset was never done or not finished.
7617 #define VFC_REG_MEMORIES_RST_RAM_RST (0x1<<1) // Write 1 to this bit will cause reset of all RSS RAM rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset is in progress. Read 0 from this bit means that RAM reset was finished.
7619 #define VFC_REG_MEMORIES_RST_TT_RST (0x1<<2) // Write 1 to this bit will cause reset of all Target tables rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset was finished. Read 1 from this bit means that TT RAM reset is in progress. Read 0 from this bit means that TT RAM reset was finished.
7621 #define VFC_REG_CAM_PARITY_EN 0x000040UL //Access:RW DataWidth:0x1 // REQUIRED -If this bit is set then background mechanism for parity check will be enabled; 0 - disabled. This bit must be disabled in palladium and FPGA. Init value of 1 must be done in a chip mode
7629 #define VFC_REG_VFC_CAM_BIST_EN 0x000060UL //Access:RW DataWidth:0x1 // Bist enable bit for Cam.
7634 #define VFC_REG_STORM_CMD_DISABLE 0x000074UL //Access:RW DataWidth:0x1 // When set then it disables selecting of commands from STORM. It will allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted.
7642 #define VFC_REG_DEBUG_DATA_CUR_MSG_EMPTY (0x1<<3) // Empty indication for current message that has first cycle from STORM.
7646 #define VFC_REG_DEBUG_DATA_NEXT_MSG_EMPTY (0x1<<7) // Next message ready indication that has first cycle fro mSTORM.
7650 #define VFC_REG_DEBUG_DATA_STORM_READY (0x1<<16) // Ready indication from STORM to input arbiter.
7652 #define VFC_REG_DEBUG_DATA_RBC_READY (0x1<<17) // Ready indication from RBC to input arbiter.
7683 #define VFC_REG_PORT4_MODE_EN 0x000118UL //Access:RW DataWidth:0x1 // If this bit set to 0 then allows to work with 160 clients. If set to 1 then with 208.
7684 #define VFC_REG_INP_FIFO_DBG_RD_EN 0x00011cUL //Access:RW DataWidth:0x1 // Input FIFO debug enable.
7688 #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
7690 #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
7692 #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
7694 #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
7696 #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
7698 #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
7700 #define VFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
7703 #define VFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port
7705 #define VFC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port
7708 #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port
7710 #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port
7713 #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port
7715 #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port
7719 #define PB_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
7721 #define PB_REG_INT_STS_EOP_ERROR (0x1<<1) // EOP check error.
7723 #define PB_REG_INT_STS_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
7725 #define PB_REG_INT_STS_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
7727 #define PB_REG_INT_STS_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
7729 #define PB_REG_INT_STS_TH_EXEC_ERROR (0x1<<5) //
7731 #define PB_REG_INT_STS_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
7733 #define PB_REG_INT_STS_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
7735 #define PB_REG_INT_STS_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
7738 #define PB_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
7740 #define PB_REG_INT_MASK_EOP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
7742 #define PB_REG_INT_MASK_IFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
7744 #define PB_REG_INT_MASK_PFIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
7746 #define PB_REG_INT_MASK_DB_BUF_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
7748 #define PB_REG_INT_MASK_TH_EXEC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
7750 #define PB_REG_INT_MASK_TQ_ERROR_WR (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
7752 #define PB_REG_INT_MASK_TQ_ERROR_RD_TH (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
7754 #define PB_REG_INT_MASK_TQ_ERROR_RD_IH (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
7757 #define PB_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
7759 #define PB_REG_INT_STS_WR_EOP_ERROR (0x1<<1) // EOP check error.
7761 #define PB_REG_INT_STS_WR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
7763 #define PB_REG_INT_STS_WR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
7765 #define PB_REG_INT_STS_WR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
7767 #define PB_REG_INT_STS_WR_TH_EXEC_ERROR (0x1<<5) //
7769 #define PB_REG_INT_STS_WR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
7771 #define PB_REG_INT_STS_WR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
7773 #define PB_REG_INT_STS_WR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
7776 #define PB_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
7778 #define PB_REG_INT_STS_CLR_EOP_ERROR (0x1<<1) // EOP check error.
7780 #define PB_REG_INT_STS_CLR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
7782 #define PB_REG_INT_STS_CLR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
7784 #define PB_REG_INT_STS_CLR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
7786 #define PB_REG_INT_STS_CLR_TH_EXEC_ERROR (0x1<<5) //
7788 #define PB_REG_INT_STS_CLR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
7790 #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
7792 #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
7794 #define PB_REG_PRTY_MASK 0x000054UL //Access:RW DataWidth:0x1 // Multi Field Register.
7795 #define PB_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
7798 #define PB_REG_CONTROL_BYTE_ORDER_SWITCH (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
7800 #define PB_REG_CONTROL_DB_IGNORE_ERROR (0x1<<1) // Indicates if to ignore the input error indication.
7802 #define PB_REG_CONTROL_DONT_PASS_ERROR (0x1<<2) // Masks error on output of pb.
7804 #define PB_REG_CONTROL_EOP_CHECK_DISABLE (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
7806 #define PB_REG_CONTROL_CRC_COMPARE_DISABLE (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
7808 #define PB_REG_CONTROL_EN_INPUTS (0x1<<5) // Enable inputs.
7810 #define PB_REG_CONTROL_DISABLE_PB (0x1<<6) // Debug only: Disable PB.
7814 #define PB_REG_CONTROL_RELAX_TH (0x1<<11) // Dbug only.
7816 #define PB_REG_CONTROL_DUMMY_ERR_ALLOW (0x1<<12) // Dummy ingress error allow. When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
7830 #define PB_REG_DB_EMPTY 0x000500UL //Access:R DataWidth:0x1 // Data Buffer empty status.
7831 #define PB_REG_DB_FULL 0x000504UL //Access:R DataWidth:0x1 // Data Buffer full status.
7832 #define PB_REG_TQ_EMPTY 0x000508UL //Access:R DataWidth:0x1 // Task Queue empty status.
7833 #define PB_REG_TQ_FULL 0x00050cUL //Access:R DataWidth:0x1 // Task Queue full status.
7834 #define PB_REG_IFIFO_EMPTY 0x000510UL //Access:R DataWidth:0x1 // Instruction FIFO empty status.
7835 #define PB_REG_IFIFO_FULL 0x000514UL //Access:R DataWidth:0x1 // Instruction FIFO full status.
7836 #define PB_REG_PFIFO_EMPTY 0x000518UL //Access:R DataWidth:0x1 // Parameter FIFO empty status.
7837 #define PB_REG_PFIFO_FULL 0x00051cUL //Access:R DataWidth:0x1 // Parameter FIFO full status.
7838 #define PB_REG_TQ_TH_EMPTY 0x000520UL //Access:R DataWidth:0x1 // Task Queue empty status for task handler.
7867 #define ETH_MAC_REG_COMMAND_CONFIG_TX_ENA (0x1<<0) // MAC Transmit Path Enable. Should be set to '1' to enable the MAC transmit path, should be set to '0' (Reset value) to disable the MAC transmit path.
7869 #define ETH_MAC_REG_COMMAND_CONFIG_RX_ENA (0x1<<1) // MAC Receive Path Enable. Should be set to '1' to enable the MAC receive path, should be set to '0' (Reset value) to disable the MAC receive path.
7871 #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV2 (0x1<<2) // reserved
7873 #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV3 (0x1<<3) // reserved
7875 #define ETH_MAC_REG_COMMAND_CONFIG_PROMIS_EN (0x1<<4) // Enable MAC Promiscuous Operation. If set to '1', all frames are received without any MAC address filtering. If set to '0' (Reset value), Unicast frames with a destination address not matching the Core MAC address (programmed in registers MAC_ADDR_0 and MAC_ADDR_1) are rejected.
7877 #define ETH_MAC_REG_COMMAND_CONFIG_PAD_EN (0x1<<5) // reserved, write 0 always. (MAC never removes padding)
7879 #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD (0x1<<6) // Terminate / Forward Received CRC. If set to '1', the CRC field of received frames is forwarded with the frame to the user application. If set to '0' (Reset value), the CRC field is stripped from the frame. Note - If padding (Bit PAD_EN set to ?1?) is enabled, CRC_FWD is ignored.
7881 #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_FWD (0x1<<7) // Terminate / Forward Pause Frames. If set to '1', pause frames are forwarded to the user application. If set to '0' (Reset value), pause frames are terminated and discarded within the MAC.
7883 #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_IGNORE (0x1<<8) // Ignore received Pause frame quanta. If set to '1', received pause frames are ignored by the MAC. If set to '0' (Reset value), the transmit process is stopped for the amount of time specified in the pause quanta received within a pause frame.
7885 #define ETH_MAC_REG_COMMAND_CONFIG_TX_ADDR_INS (0x1<<9) // Set Source MAC Address on Transmit. If set to '1', the MAC overwrites the source MAC address received from the client interface with the MAC address programmed in registers MAC_ADDR_0 and MAC_ADDR_1 . If set to '0' (Reset value), the source MAC address from the client interface is transmitted unmodified to the line.
7887 #define ETH_MAC_REG_COMMAND_CONFIG_LOOPBACK_EN (0x1<<10) // Enable PHY Interface loopback. If set to '1', the signal loop_ena is set to '1'. If set to '0' (Reset value), the signal loop_ena is set to '0'.
7889 #define ETH_MAC_REG_COMMAND_CONFIG_TX_PAD_EN (0x1<<11) // reserved, writable but has no effect. The MAC never appends padding octets; the user application must provide frames of correct minimum size.
7891 #define ETH_MAC_REG_COMMAND_CONFIG_SW_RESET (0x1<<12) // Self-Clearing Software Reset. When written with '1', all Statistics Counters are reset to 0.
7893 #define ETH_MAC_REG_COMMAND_CONFIG_CNTL_FRAME_ENA (0x1<<13) // Enable Reception of all Control Frames. If set to '1', all control frames are accepted. If set to '0', only Pause frames are accepted and all other command frames are rejected.
7895 #define ETH_MAC_REG_COMMAND_CONFIG_RX_ERR_DISC (0x1<<14) // Enable Receive Errored Frame Discard. Use only with RX FIFO Store and Forward. May not be supported by all Core variants.
7897 #define ETH_MAC_REG_COMMAND_CONFIG_PHY_TXENA (0x1<<15) // Controls toplevel pin phy_txena. No internal function
7899 #define ETH_MAC_REG_COMMAND_CONFIG_SEND_IDLE (0x1<<16) // Force Idle Generation. If set to '1', the MAC permanently sends XLGMII Idle sequences even when faults are received.
7901 #define ETH_MAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK (0x1<<17) // Disable Payload Length Check. Not supported; write 0 always.
7903 #define ETH_MAC_REG_COMMAND_CONFIG_RS_COL_CNT_EXT (0x1<<18) // reserved
7905 #define ETH_MAC_REG_COMMAND_CONFIG_PFC_MODE (0x1<<19) // Priority Flow Control Mode enable. If set to 1, the Core generates and processes PFC control frames according to the Priority Flow Control Interface signals. If set to 0 (Reset Value), the Core operates in legacy Pause Frame mode and generates and processes standard Pause Frames.
7907 #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_PFC_COMP (0x1<<20) // Link Pause compatible with PFC mode. Pause is only indicated but does not stop TX.
7909 #define ETH_MAC_REG_COMMAND_CONFIG_RX_SFD_ANY (0x1<<21) // Disable check for SFD (0xd5) and accept frame with any character.
7911 #define ETH_MAC_REG_COMMAND_CONFIG_TX_FLUSH (0x1<<22) // Egress flush enable.
7913 #define ETH_MAC_REG_COMMAND_CONFIG_TX_LOWP_ENA (0x1<<23) // Instruct RS Layer to transmit LPI.
7915 #define ETH_MAC_REG_COMMAND_CONFIG_LOWP_RXEMPTY (0x1<<24) // Mask toplevel pin reg_lowp with RX FIFO empty.
7917 #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV25 (0x1<<25) // reserved
7919 #define ETH_MAC_REG_COMMAND_CONFIG_TX_FIFO_RESET (0x1<<26) // Self-Clearing TX FIFO reset command. May not be supported in all Core variants
7921 #define ETH_MAC_REG_COMMAND_CONFIG_FLT_HDL_DIS (0x1<<27) // Disable RS fault handling. When set to '0' (default), the MAC automatically inserts remote faults and idles in egress direction on detection of local faults and remote faults, respectively, on ingress direction. When set to '1', this feature is disabled.
7923 #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV28 (0x1<<28) // reserved
7925 #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV29 (0x1<<29) // reserved
7927 #define ETH_MAC_REG_COMMAND_CONFIG_SHORT_PREAMBLE (0x1<<30) // reserved; write 0 always
7929 #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV31 (0x1<<31) // reserved
7963 #define ETH_MAC_REG_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME (0x1<<8) // enables (1) or disables (0) multicast frame reception for the entry.
7966 #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_BUSY (0x1<<0) // MDIO busy. If set, a MDIO transaction is currently ongoing. If cleared, the application can access the other registers.
7968 #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_READ_ERROR (0x1<<1) // MDIO read error. If set, the last read transaction had no response from a PHY and the data read could be invalid. This can happen, if the PHY address does not match any PHY that is available on the MDIO bus.
7972 #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_DISABLE_PREAMBLE (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
7974 #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLAUSE45 (0x1<<6) // MDIO transaction use Clause 45 format (1) or Clause 22 format (0).
7983 #define ETH_MAC_REG_MDIO_COMMAND_READ_ADDRESS_POST_INCREMENT (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-increment will be performed in the PHY internal address register.
7985 #define ETH_MAC_REG_MDIO_COMMAND_NORMAL_READ_TRANSACTION (0x1<<15) // If written with 1, a normal read transaction is initiated.
7994 #define ETH_MAC_REG_STATUS_RX_LOC_FAULT (0x1<<0) // Local Fault Status. Set to '1' when the MAC detects Rx Local Fault Sequences on the CGMII receive interface.
7996 #define ETH_MAC_REG_STATUS_RX_REM_FAULT (0x1<<1) // Remote Fault Status. Set to '1' when the MAC detects Rx Remote Fault Sequences on the CGMII receive interface
7998 #define ETH_MAC_REG_STATUS_PHY_LOS (0x1<<2) // PHY indicates loss-of-signal. Represents value of pin "phy_los".
8000 #define ETH_MAC_REG_STATUS_TS_AVAIL (0x1<<3) // Transmit Timestamp Available. Indicates that the timestamp of the last transmitted 1588 event frame is available in the register TS_TIMESTAMP. To clear TS_AVAIL, the bit must be written with a '1'.
8002 #define ETH_MAC_REG_STATUS_RX_LOWP (0x1<<4) // Receiving Low Power Idle (LPI)
8004 #define ETH_MAC_REG_STATUS_TX_EMPTY (0x1<<5) // TX FIFO is empty
8006 #define ETH_MAC_REG_STATUS_RX_EMPTY (0x1<<6) // RX FIFO is empty
8008 #define ETH_MAC_REG_STATUS_RX_LINT_FAULT (0x1<<7) // Special Link Interruption Fault Sequence detected in receive
8010 #define ETH_MAC_REG_STATUS_TX_IS_IDLE (0x1<<8) // TX MAC datapath (statemachine) is idle
8018 #define ETH_MAC_REG_CREDIT_TRIGGER_LOADCREDIT (0x1<<0) // Credit-based FIFO only: When written with a 1, RX FIFO reset occurs and credit counter loaded from the INIT_CREDIT value.
8071 #define ETH_MAC_REG_XIF_MODE_XGMII (0x1<<0) // Enable XGMII-64 (4byte alignment)
8073 #define ETH_MAC_REG_XIF_MODE_PAUSETIMERX8 (0x1<<4) // Enable Pause Timer Compensation when using external XLGMII/GMII Converter
8075 #define ETH_MAC_REG_XIF_MODE_ONESTEPENA (0x1<<5) // Enable 1-step capable datapath (if available)
8078 #define ETH_MAC_REG_STATN_CONFIG_SATURATE (0x1<<0) // Configure saturation behavior. When set to 1, the counters saturate at all-1. Otherwise counters wrap around.
8080 #define ETH_MAC_REG_STATN_CONFIG_CLEAR_ON_READ (0x1<<1) // Configure clear-on-read behavior. When set to 1, the counters are cleared (set to STATN_CLEARVALUE) after having been transferred into the read registers (snapshot captured). When set 0 (default) the counters are not modified when read/captured.
8082 #define ETH_MAC_REG_STATN_CONFIG_CLEAR (0x1<<2) // Clear all counters command (self-clearing). When written with 1 all counters (tx and rx) are cleared (set to STATN_CLEARVALUE).
8215 #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_CORRECTION (0x1<<0) // When 1, bypass the decoder's correction function for reduced latency; When 0, normal FEC operation.
8217 #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_ERROR_INDICATION (0x1<<1) // When 1, configure the FEC decoder to not indicate errors to the PCS layer; When 0, the FEC decoder indicates errors to the PCS layer.
8220 #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_CORRECTION (0x1<<0) // Indicates existence of the receive correction bypass option; The bypass function allows a reduced latency operation.
8222 #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_INDICATION (0x1<<1) // Indicates the ability to disable error propagation to the PCS layer.
8224 #define ETH_RSFEC_REG_RS_FEC_STATUS_HIGH_SER (0x1<<2) // Asserts when error indication bypass is enabled and high symbol error rate is found; Clear on read.
8228 #define ETH_RSFEC_REG_RS_FEC_STATUS_FEC_ALIGN_STATUS (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has locked on incoming data and deskew completed.
8230 #define ETH_RSFEC_REG_RS_FEC_STATUS_PCS_ALIGN_STATUS (0x1<<15) // Always 1.
8278 #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_ENABLE (0x1<<2) // When 1, enable RSFEC datapath instead PCS MLD; When 0, use normal PCS MLD datapath (default).
8280 #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_STATUS (0x1<<15) // Indicates the operatyional outcome of the (above) enable bit control; When 1 = FEC enabled and 0 = disabled.
8285 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LH (0x1<<4) // FEC alignment status; Latched high; Clear on read.
8287 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_MARKER_CHECK_RESTART (0x1<<5) // The marker_check function (PCS sublayer) caused an alignment restart to the FEC; Latched high; Clear on read.
8289 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DATAPATH_RESTART (0x1<<6) // RX datapath (sync) reset occured; Latched high; Clear on read.
8291 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DATAPATH_RESTART (0x1<<7) // TX datapath (sync) reset occured; Latched high; Clear on read.
8293 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DP_OVERFLOW (0x1<<8) // RX datapath 4x66 pacing fifo overflow fatal error; Latched high; Clear on read.
8295 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DP_OVERFLOW (0x1<<9) // TX datapath 4x66 input fifo overflow fatal error; Latched high; Clear on read.
8297 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LL (0x1<<10) // FEC alignment status; Latched high; Sets on read.
8316 #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_OVERWRITE (0x1<<10) // If the bit is set the 10B symbol is replaced by the pattern instead using XOR.
8319 #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_TEST_TRIGGER (0x1<<0) // For bit 0 only, when written with 1 triggers the error insertion (on one word of 16 symbols); This bit clears automatically.
8322 #define ETH_PCS1G_REG_CONTROL_SPEED_6 (0x1<<6) // Speed Selection Indication; always 1
8324 #define ETH_PCS1G_REG_CONTROL_DUPLEX (0x1<<8) // Indicate full-duplex operation; always 1
8326 #define ETH_PCS1G_REG_CONTROL_ANRESTART (0x1<<9) // Restart Autonegotiation
8328 #define ETH_PCS1G_REG_CONTROL_ISOLATE (0x1<<10) // Set PCS isolate mode; Controls toplevel pin only, no internal function.
8330 #define ETH_PCS1G_REG_CONTROL_POWERDOWN (0x1<<11) // Enable powerdown state, if supported.
8332 #define ETH_PCS1G_REG_CONTROL_ANENABLE (0x1<<12) // Autonegotiation enable
8334 #define ETH_PCS1G_REG_CONTROL_SPEED_13 (0x1<<13) // Speed Selection Indication; always 0
8336 #define ETH_PCS1G_REG_CONTROL_LOOPBACK (0x1<<14) // Enable loopback
8338 #define ETH_PCS1G_REG_CONTROL_RESET (0x1<<15) // PCS soft-reset command; self-clearing
8341 #define ETH_PCS1G_REG_STATUS_EXTDCAPABILITY (0x1<<0) // Indicate extended register support; always 1
8343 #define ETH_PCS1G_REG_STATUS_LINKSTATUS (0x1<<2) // Indicate link status; latch-low
8345 #define ETH_PCS1G_REG_STATUS_ANEGABILITY (0x1<<3) // Autonegotiation ability; always 1
8347 #define ETH_PCS1G_REG_STATUS_ANEGCOMPLETE (0x1<<5) // Autonegotiation completed indication
8358 #define ETH_PCS1G_REG_DEV_ABILITY_FD (0x1<<5) // Indicate full-duplex support; SGMII:=reserved
8360 #define ETH_PCS1G_REG_DEV_ABILITY_HD (0x1<<6) // Indicate half-duplex support; SGMII:=reserved
8362 #define ETH_PCS1G_REG_DEV_ABILITY_PS1 (0x1<<7) // Pause Support 1; SGMII:=reserved
8364 #define ETH_PCS1G_REG_DEV_ABILITY_PS2 (0x1<<8) // Pause Support 2; SGMII:=EEE clock stop enable to PHY
8368 #define ETH_PCS1G_REG_DEV_ABILITY_RF1 (0x1<<12) // Remote fault 1; SGMII:=reserved
8370 #define ETH_PCS1G_REG_DEV_ABILITY_RF2 (0x1<<13) // Remote fault 2; SGMII:=reserved
8372 #define ETH_PCS1G_REG_DEV_ABILITY_ACK (0x1<<14) // Acknowledge during autonegotiation
8374 #define ETH_PCS1G_REG_DEV_ABILITY_NP (0x1<<15) // Next Page support; SGMII:=reserved
8379 #define ETH_PCS1G_REG_PARTNER_ABILITY_FD (0x1<<5) // Indicate full-duplex support; SGMII:=reserved
8381 #define ETH_PCS1G_REG_PARTNER_ABILITY_HD (0x1<<6) // Indicate half-duplex support; SGMII:=reserved
8383 #define ETH_PCS1G_REG_PARTNER_ABILITY_PS1 (0x1<<7) // Pause Support 1; SGMII:=reserved
8385 #define ETH_PCS1G_REG_PARTNER_ABILITY_PS2 (0x1<<8) // Pause Support 2; SGMII:=EEE clock stop capability from PHY
8387 #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV9 (0x1<<9) // reserved; SGMII:=EEE capability from PHY
8391 #define ETH_PCS1G_REG_PARTNER_ABILITY_RF1 (0x1<<12) // Remote fault 1; SGMII:=Copper Duplex status from PHY
8393 #define ETH_PCS1G_REG_PARTNER_ABILITY_RF2 (0x1<<13) // Remote fault 2; SGMII:=reserved
8395 #define ETH_PCS1G_REG_PARTNER_ABILITY_ACK (0x1<<14) // Acknowledge during autonegotiation
8397 #define ETH_PCS1G_REG_PARTNER_ABILITY_NP (0x1<<15) // Next Page support; SGMII:=Copper Link Status from PHY
8400 #define ETH_PCS1G_REG_AN_EXPANSION_PAGERECEIVED (0x1<<1) // Autoneg page received indication; latch-high
8402 #define ETH_PCS1G_REG_AN_EXPANSION_NEXTPAGEABLE (0x1<<2) // Indicate PCS supports next page exchange for autonegotiation
8407 #define ETH_PCS1G_REG_NP_TX_TOGGLE (0x1<<11) // Next Page toggle handshaking bit
8409 #define ETH_PCS1G_REG_NP_TX_ACK2 (0x1<<12) // Next Page data acknowledge indication
8411 #define ETH_PCS1G_REG_NP_TX_MP (0x1<<13) // Message Next Page type identification
8413 #define ETH_PCS1G_REG_NP_TX_ACK (0x1<<14) // Acknowledge during page exchange
8415 #define ETH_PCS1G_REG_NP_TX_NP (0x1<<15) // Next Pages to follow indication
8420 #define ETH_PCS1G_REG_LP_NP_RX_TOGGLE (0x1<<11) // Next Page toggle handshaking bit
8422 #define ETH_PCS1G_REG_LP_NP_RX_ACK2 (0x1<<12) // Next Page data acknowledge indication
8424 #define ETH_PCS1G_REG_LP_NP_RX_MP (0x1<<13) // Message Next Page type identification
8426 #define ETH_PCS1G_REG_LP_NP_RX_ACK (0x1<<14) // Acknowledge during page exchange
8428 #define ETH_PCS1G_REG_LP_NP_RX_NP (0x1<<15) // Next Pages to follow indication
8437 #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER0 (0x1<<0) // Bit 0 of link timer value; not writeable and always 0
8445 #define ETH_PCS1G_REG_IF_MODE_SGMII_ENA (0x1<<0) // Enable SGMII mode
8447 #define ETH_PCS1G_REG_IF_MODE_USE_SGMII_AN (0x1<<1) // Use the SGMII autonegotiation results to set SGMII speed
8451 #define ETH_PCS1G_REG_IF_MODE_SGMII_DUPLEX (0x1<<4) // Set SGMII half-duplex mode when not using autonegotiation
8453 #define ETH_PCS1G_REG_IF_MODE_IFMODE_RSV5 (0x1<<5) // reserved; writeable for backward compatibility; write 0 always
8461 #define ETH_PCS10_50G_REG_CONTROL1_SPEED_ALWAYS1 (0x1<<6) // Always 1.
8463 #define ETH_PCS10_50G_REG_CONTROL1_LOW_POWER (0x1<<11) // 0=normal operation (Always 0).
8465 #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECT_ALWAYS1 (0x1<<13) // Always 1.
8467 #define ETH_PCS10_50G_REG_CONTROL1_LOOPBACK (0x1<<14) // 1=Enable loopback, 0=disable loopback.
8469 #define ETH_PCS10_50G_REG_CONTROL1_RESET (0x1<<15) // 1=PCS reset, 0=normal; Self clearing.
8472 #define ETH_PCS10_50G_REG_STATUS1_LOW_POWER_ABILITY (0x1<<1) // Set to 1 to indicate that the PCS implements a low power mode.
8474 #define ETH_PCS10_50G_REG_STATUS1_PCS_RECEIVE_LINK (0x1<<2) // When 1, indicates PCS receive link up; When �0�, indicates PCS receive link is or was down (latching low).
8476 #define ETH_PCS10_50G_REG_STATUS1_FAULT (0x1<<7) // When 1, indicates a fault condition idetected; When �0�, indicates that no fault condition is detected.
8478 #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_ACTIVE (0x1<<8) // 1: receive is currently in LPI state; 0: normal operation.
8480 #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_ACTIVE (0x1<<9) // 1: transmit is currently in LPI state; 0: normal operation.
8482 #define ETH_PCS10_50G_REG_STATUS1_RX_LPI (0x1<<10) // 1: receive is or was in LPI state; 0: normal operation; Latching high.
8484 #define ETH_PCS10_50G_REG_STATUS1_TX_LPI (0x1<<11) // 1: transmit is or was in LPI state; 0: normal operation; Latching high.
8493 #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10GETH (0x1<<0) // When 1, this PCS is 10Geth capable.
8495 #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10PASS_TS (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
8497 #define ETH_PCS10_50G_REG_SPEED_ABILITY_C40G (0x1<<2) // When 1, this PCS is 40G capable.
8499 #define ETH_PCS10_50G_REG_SPEED_ABILITY_C100G (0x1<<3) // When 1, this PCS is 100G capable.
8502 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_CLAUSE22 (0x1<<0) // Clause 22 registers present when 1.
8504 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PMD_PMA (0x1<<1) // PMD/PMA present when 1.
8506 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_WIS_PRES (0x1<<2) // WIS present when 1.
8508 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PCS_PRES (0x1<<3) // PCS present when 1.
8510 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PHY_XS (0x1<<4) // PHY XS present when 1.
8512 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_DTE_XS (0x1<<5) // DTE XS present when 1.
8514 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_TC_PRES (0x1<<6) // TC present when 1.
8517 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_CLAUSE22 (0x1<<13) // Clause 22 extension present
8519 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE1 (0x1<<14) // Vendor specific device 1 present
8521 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE2 (0x1<<15) // Vendor specific device 2 present
8527 #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_R (0x1<<0) // When 1, this PCS is 10GBase-R capable.
8529 #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_X (0x1<<1) // When 1, this PCS is 10GBase-X capable.
8531 #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_W (0x1<<2) // When 1, this PCS is 10GBase-W capable.
8533 #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_T (0x1<<3) // When 1, this PCS is 10GBase-T capable.
8535 #define ETH_PCS10_50G_REG_STATUS2_C40GBASE_R (0x1<<4) // When 1, this PCS is 40GBase-R capable.
8537 #define ETH_PCS10_50G_REG_STATUS2_C100GBASE_R (0x1<<5) // When 1, this PCS is 100GBase-R capable.
8539 #define ETH_PCS10_50G_REG_STATUS2_RECEIVE_FAULT (0x1<<10) // Receive fault. 1=Fault condition on receive path. Latched high
8541 #define ETH_PCS10_50G_REG_STATUS2_TRANSMIT_FAULT (0x1<<11) // Transmit fault. 1=Fault condition on transmit path. Latched high
8552 #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_LPI_FW (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 = Deep sleep for LPI function.
8554 #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
8556 #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
8558 #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
8564 #define ETH_PCS10_50G_REG_BASER_STATUS1_BLOCK_LOCK (0x1<<0) // 1=PCS locked to received blocks.
8566 #define ETH_PCS10_50G_REG_BASER_STATUS1_HIGH_BER (0x1<<1) // 1=PCS reporting a high BER.
8568 #define ETH_PCS10_50G_REG_BASER_STATUS1_RECEIVE_LINK (0x1<<12) // Receive link status. 1=Link up; 0=link down.
8575 #define ETH_PCS10_50G_REG_BASER_STATUS2_HIGH_BER (0x1<<14) // BER flag; Latched high.
8577 #define ETH_PCS10_50G_REG_BASER_STATUS2_BLOCK_LOCK (0x1<<15) // Block Lock; Latched low.
8604 #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
8606 #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_SQUARE (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pattern; 10G only.
8608 #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN (0x1<<2) // Receive test-pattern enable.
8610 #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN (0x1<<3) // Transmit test-pattern enable.
8612 #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_RANDOM (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
8623 #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT (0x1<<15) // High order counter present; Always 1.
8626 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE0_BLOCK_LOCK (0x1<<0) // Lane 0 block lock.
8628 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK (0x1<<1) // Lane 1 block lock.
8630 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE2_BLOCK_LOCK (0x1<<2) // Lane 2 block lock.
8632 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK (0x1<<3) // Lane 3 block lock.
8634 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS (0x1<<12) // Lane alignment status; 1=All Receive lanes locked and aligned.
8637 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK (0x1<<0) // Lane 0 alignment marker lock
8639 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK (0x1<<1) // Lane 1 alignment marker lock
8641 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK (0x1<<2) // Lane 2 alignment marker lock
8643 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK (0x1<<3) // Lane 3 alignment marker lock
8682 #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RXLAUI_ENA (0x1<<0) // Enable Reduced-XLAUI PMA mode using 2 lanes.
8690 #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_ENA_STATUS (0x1<<15) // Indicates if currently the RXLAUI mode is enabled.
8725 #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49 (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 encoder/decoder functions.
8727 #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_DISABLE_MLD (0x1<<1) // When 0 PCS 4-lane MLD function is active; When 1 the MLD function is disabled.
8729 #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49 (0x1<<8) // Current status of Clause 49 setting.
8731 #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD (0x1<<9) // Current status of MLD setting.
8736 #define ETH_PCS10_25G_REG_CONTROL1_SPEED_ALWAYS1 (0x1<<6) // Always 1.
8738 #define ETH_PCS10_25G_REG_CONTROL1_LOW_POWER (0x1<<11) // 0=normal operation (Always 0).
8740 #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECT_ALWAYS1 (0x1<<13) // Always 1.
8742 #define ETH_PCS10_25G_REG_CONTROL1_LOOPBACK (0x1<<14) // 1=Enable loopback, 0=disable loopback.
8744 #define ETH_PCS10_25G_REG_CONTROL1_RESET (0x1<<15) // 1=PCS reset, 0=normal; Self clearing.
8747 #define ETH_PCS10_25G_REG_STATUS1_LOW_POWER_ABILITY (0x1<<1) // Set to 1 to indicate that the PCS implements a low power mode.
8749 #define ETH_PCS10_25G_REG_STATUS1_PCS_RECEIVE_LINK (0x1<<2) // When 1, indicates PCS receive link up; When �0�, indicates PCS receive link is or was down (latching low).
8751 #define ETH_PCS10_25G_REG_STATUS1_FAULT (0x1<<7) // When 1, indicates a fault condition idetected; When �0�, indicates that no fault condition is detected.
8753 #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_ACTIVE (0x1<<8) // 1: receive is currently in LPI state; 0: normal operation.
8755 #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_ACTIVE (0x1<<9) // 1: transmit is currently in LPI state; 0: normal operation.
8757 #define ETH_PCS10_25G_REG_STATUS1_RX_LPI (0x1<<10) // 1: receive is or was in LPI state; 0: normal operation; Latching high.
8759 #define ETH_PCS10_25G_REG_STATUS1_TX_LPI (0x1<<11) // 1: transmit is or was in LPI state; 0: normal operation; Latching high.
8768 #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10GETH (0x1<<0) // When 1, this PCS is 10Geth capable.
8770 #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10PASS_TS (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
8772 #define ETH_PCS10_25G_REG_SPEED_ABILITY_C40G (0x1<<2) // When 1, this PCS is 40G capable.
8774 #define ETH_PCS10_25G_REG_SPEED_ABILITY_C100G (0x1<<3) // When 1, this PCS is 100G capable.
8777 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_CLAUSE22 (0x1<<0) // Clause 22 registers present when 1.
8779 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PMD_PMA (0x1<<1) // PMD/PMA present when 1.
8781 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_WIS_PRES (0x1<<2) // WIS present when 1.
8783 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PCS_PRES (0x1<<3) // PCS present when 1.
8785 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PHY_XS (0x1<<4) // PHY XS present when 1.
8787 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_DTE_XS (0x1<<5) // DTE XS present when 1.
8789 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_TC_PRES (0x1<<6) // TC present when 1.
8792 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_CLAUSE22 (0x1<<13) // Clause 22 extension present
8794 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE1 (0x1<<14) // Vendor specific device 1 present
8796 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE2 (0x1<<15) // Vendor specific device 2 present
8802 #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_R (0x1<<0) // When 1, this PCS is 10GBase-R capable.
8804 #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_X (0x1<<1) // When 1, this PCS is 10GBase-X capable.
8806 #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_W (0x1<<2) // When 1, this PCS is 10GBase-W capable.
8808 #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_T (0x1<<3) // When 1, this PCS is 10GBase-T capable.
8810 #define ETH_PCS10_25G_REG_STATUS2_C40GBASE_R (0x1<<4) // When 1, this PCS is 40GBase-R capable.
8812 #define ETH_PCS10_25G_REG_STATUS2_C100GBASE_R (0x1<<5) // When 1, this PCS is 100GBase-R capable.
8814 #define ETH_PCS10_25G_REG_STATUS2_RECEIVE_FAULT (0x1<<10) // Receive fault. 1=Fault condition on receive path. Latched high
8816 #define ETH_PCS10_25G_REG_STATUS2_TRANSMIT_FAULT (0x1<<11) // Transmit fault. 1=Fault condition on transmit path. Latched high
8827 #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_LPI_FW (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 = Deep sleep for LPI function.
8829 #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
8831 #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
8833 #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
8839 #define ETH_PCS10_25G_REG_BASER_STATUS1_BLOCK_LOCK (0x1<<0) // 1=PCS locked to received blocks.
8841 #define ETH_PCS10_25G_REG_BASER_STATUS1_HIGH_BER (0x1<<1) // 1=PCS reporting a high BER.
8843 #define ETH_PCS10_25G_REG_BASER_STATUS1_RECEIVE_LINK (0x1<<12) // Receive link status. 1=Link up; 0=link down.
8850 #define ETH_PCS10_25G_REG_BASER_STATUS2_HIGH_BER (0x1<<14) // BER flag; Latched high.
8852 #define ETH_PCS10_25G_REG_BASER_STATUS2_BLOCK_LOCK (0x1<<15) // Block Lock; Latched low.
8879 #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
8881 #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_SQUARE (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pattern; 10G only.
8883 #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN (0x1<<2) // Receive test-pattern enable.
8885 #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN (0x1<<3) // Transmit test-pattern enable.
8887 #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_RANDOM (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
8898 #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT (0x1<<15) // High order counter present; Always 1.
8901 #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS (0x1<<12) // Lane alignment status; 1=All Receive lanes locked and aligned.
8904 #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK (0x1<<0) // Lane 0 alignment marker lock.
8906 #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK (0x1<<1) // Lane 1 alignment marker lock.
8908 #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK (0x1<<2) // Lane 2 alignment marker lock.
8910 #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK (0x1<<3) // Lane 3 alignment marker lock.
8969 #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49 (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 encoder/decoder functions.
8971 #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_DISABLE_MLD (0x1<<1) // When 0 PCS 4-lane MLD function is active; When 1 the MLD function is disabled.
8973 #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49 (0x1<<8) // Current status of Clause 49 setting.
8975 #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD (0x1<<9) // Current status of MLD setting.
8989 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER3_RESERVEDFIELD4 (0x1<<7) // Reserved
8994 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER4_RESERVEDFIELD6 (0x1<<7) // Reserved
8999 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER5_RESERVEDFIELD8 (0x1<<7) // Reserved
9009 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD12 (0x1<<0) // Reserved
9011 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD13 (0x1<<1) // Reserved
9013 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER9_RESERVEDFIELD14 (0x1<<2) // Reserved
9018 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER10_RESERVEDFIELD16 (0x1<<0) // Reserved
9021 #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_ATEST_EN (0xf<<0) // Analog test mode enable. Controls the macro that drives the atest1_o/atest2_o bumps located over the CMU macro. 0x0 - off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC circuitry. PHY input pins soc_atest1_i and soc_atest2_i are shorted to atest1_o and atest2_o respectively. rest - reserved
9027 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD17 (0x1<<0) // Reserved
9029 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD18 (0x1<<1) // Reserved
9031 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD19 (0x1<<2) // Reserved
9033 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER11_RESERVEDFIELD20 (0x1<<6) // Reserved
9036 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD21 (0x1<<0) // Reserved
9038 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD22 (0x1<<1) // Reserved
9040 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD23 (0x1<<2) // Reserved
9042 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER12_RESERVEDFIELD24 (0x1<<6) // Reserved
9045 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD25 (0x1<<0) // Reserved
9047 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD26 (0x1<<1) // Reserved
9049 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD27 (0x1<<2) // Reserved
9051 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD28 (0x1<<3) // Reserved
9053 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD29 (0x1<<4) // Reserved
9055 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD30 (0x1<<5) // Reserved
9057 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD31 (0x1<<6) // Reserved
9060 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD32 (0x1<<0) // Reserved
9062 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD33 (0x1<<1) // Reserved
9064 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD34 (0x1<<2) // Reserved
9066 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD35 (0x1<<3) // Reserved
9068 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD36 (0x1<<4) // Reserved
9070 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD37 (0x1<<5) // Reserved
9072 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD38 (0x1<<6) // Reserved
9075 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD39 (0x1<<0) // Reserved
9077 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD40 (0x1<<1) // Reserved
9079 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD41 (0x1<<2) // Reserved
9081 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD42 (0x1<<3) // Reserved
9083 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD43 (0x1<<4) // Reserved
9085 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD44 (0x1<<5) // Reserved
9087 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD45 (0x1<<6) // Reserved
9090 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD46 (0x1<<0) // Reserved
9092 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD47 (0x1<<1) // Reserved
9094 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD48 (0x1<<2) // Reserved
9096 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD49 (0x1<<3) // Reserved
9098 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD50 (0x1<<4) // Reserved
9100 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD51 (0x1<<5) // Reserved
9102 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD52 (0x1<<6) // Reserved
9105 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD53 (0x1<<0) // Reserved
9107 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD54 (0x1<<1) // Reserved
9109 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD55 (0x1<<2) // Reserved
9111 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER17_RESERVEDFIELD56 (0x1<<7) // Reserved
9114 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_RESERVEDFIELD57 (0x1<<0) // Reserved
9116 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER18_RESERVEDFIELD58 (0x1<<7) // Reserved
9119 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_RESERVEDFIELD59 (0x1<<0) // Reserved
9121 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER19_RESERVEDFIELD60 (0x1<<7) // Reserved
9126 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER20_RESERVEDFIELD62 (0x1<<7) // Reserved
9131 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER21_RESERVEDFIELD64 (0x1<<7) // Reserved
9134 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD65 (0x1<<0) // Reserved
9136 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD66 (0x1<<1) // Reserved
9138 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER22_RESERVEDFIELD67 (0x1<<7) // Reserved
9141 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD68 (0x1<<0) // Reserved
9145 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD70 (0x1<<3) // Reserved
9147 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD71 (0x1<<7) // Reserved
9150 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD72 (0x1<<0) // Reserved
9152 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD73 (0x1<<1) // Reserved
9154 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD74 (0x1<<2) // Reserved
9159 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_lc0_clk_cmu.
9162 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD76 (0x1<<0) // Reserved
9164 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD77 (0x1<<1) // Reserved
9166 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD78 (0x1<<2) // Reserved
9171 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_lc0_clk_cmudiv.
9174 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD80 (0x1<<0) // Reserved
9176 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD81 (0x1<<1) // Reserved
9178 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER26_RESERVEDFIELD82 (0x1<<7) // Reserved
9181 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD83 (0x1<<0) // Reserved
9185 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD85 (0x1<<3) // Reserved
9187 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD86 (0x1<<7) // Reserved
9190 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD87 (0x1<<0) // Reserved
9192 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD88 (0x1<<1) // Reserved
9194 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD89 (0x1<<2) // Reserved
9199 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_TBUS_OUT_CG_EN (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll2.
9202 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD91 (0x1<<0) // Reserved
9204 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD92 (0x1<<1) // Reserved
9206 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD93 (0x1<<2) // Reserved
9211 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_TBUS_OUT_CG_EN (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll2div.
9214 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD95 (0x1<<0) // Reserved
9216 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD96 (0x1<<1) // Reserved
9218 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD97 (0x1<<2) // Reserved
9223 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_TBUS_OUT_CG_EN (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll3.
9226 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD99 (0x1<<0) // Reserved
9228 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD100 (0x1<<1) // Reserved
9230 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD101 (0x1<<2) // Reserved
9235 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_TBUS_OUT_CG_EN (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll3div.
9238 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln0_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9240 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_RESERVEDFIELD103 (0x1<<2) // Reserved
9242 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN (0x1<<4) // Clock gate enable for TX bist clock branch
9244 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_RESERVEDFIELD104 (0x1<<7) // Reserved
9247 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD105 (0x1<<0) // Reserved
9249 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD106 (0x1<<1) // Reserved
9251 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD107 (0x1<<2) // Reserved
9253 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER32_RESERVEDFIELD108 (0x1<<7) // Reserved
9258 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN (0x1<<4) // Clock gate enable for RX clock output to customer logics
9260 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN (0x1<<5) // Clock gate enable for RX bist clock branch
9262 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_RESERVEDFIELD110 (0x1<<7) // Reserved
9265 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD111 (0x1<<0) // Reserved
9267 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD112 (0x1<<1) // Reserved
9269 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD113 (0x1<<2) // Reserved
9271 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER33_RESERVEDFIELD114 (0x1<<7) // Reserved
9274 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER34_RESERVEDFIELD115 (0x1<<4) // Reserved
9280 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln1_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9282 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_RESERVEDFIELD117 (0x1<<2) // Reserved
9284 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN (0x1<<4) // Clock gate enable for TX bist clock branch
9286 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_RESERVEDFIELD118 (0x1<<7) // Reserved
9289 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD119 (0x1<<0) // Reserved
9291 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD120 (0x1<<1) // Reserved
9293 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD121 (0x1<<2) // Reserved
9295 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER36_RESERVEDFIELD122 (0x1<<7) // Reserved
9300 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN (0x1<<4) // Clock gate enable for RX clock output to customer logics
9302 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN (0x1<<5) // Clock gate enable for RX bist clock branch
9304 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_RESERVEDFIELD124 (0x1<<7) // Reserved
9307 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD125 (0x1<<0) // Reserved
9309 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD126 (0x1<<1) // Reserved
9311 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD127 (0x1<<2) // Reserved
9313 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER37_RESERVEDFIELD128 (0x1<<7) // Reserved
9316 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER38_RESERVEDFIELD129 (0x1<<4) // Reserved
9322 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln2_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9324 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_RESERVEDFIELD131 (0x1<<2) // Reserved
9326 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN (0x1<<4) // Clock gate enable for TX bist clock branch
9328 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_RESERVEDFIELD132 (0x1<<7) // Reserved
9331 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD133 (0x1<<0) // Reserved
9333 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD134 (0x1<<1) // Reserved
9335 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD135 (0x1<<2) // Reserved
9337 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER40_RESERVEDFIELD136 (0x1<<7) // Reserved
9342 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN (0x1<<4) // Clock gate enable for RX clock output to customer logics
9344 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN (0x1<<5) // Clock gate enable for RX bist clock branch
9346 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_RESERVEDFIELD138 (0x1<<7) // Reserved
9349 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD139 (0x1<<0) // Reserved
9351 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD140 (0x1<<1) // Reserved
9353 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD141 (0x1<<2) // Reserved
9355 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER41_RESERVEDFIELD142 (0x1<<7) // Reserved
9358 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER42_RESERVEDFIELD143 (0x1<<4) // Reserved
9364 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln3_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9366 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_RESERVEDFIELD145 (0x1<<2) // Reserved
9368 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN (0x1<<4) // Clock gate enable for TX bist clock branch
9370 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_RESERVEDFIELD146 (0x1<<7) // Reserved
9373 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD147 (0x1<<0) // Reserved
9375 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD148 (0x1<<1) // Reserved
9377 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD149 (0x1<<2) // Reserved
9379 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER44_RESERVEDFIELD150 (0x1<<7) // Reserved
9384 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN (0x1<<4) // Clock gate enable for RX clock output to customer logics
9386 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN (0x1<<5) // Clock gate enable for RX bist clock branch
9388 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_RESERVEDFIELD152 (0x1<<7) // Reserved
9391 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD153 (0x1<<0) // Reserved
9393 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD154 (0x1<<1) // Reserved
9395 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD155 (0x1<<2) // Reserved
9397 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER45_RESERVEDFIELD156 (0x1<<7) // Reserved
9400 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER46_RESERVEDFIELD157 (0x1<<4) // Reserved
9406 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD159 (0x1<<0) // Reserved
9408 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD160 (0x1<<1) // Reserved
9410 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD161 (0x1<<2) // Reserved
9412 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD162 (0x1<<3) // Reserved
9415 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_RESERVEDFIELD163 (0x1<<0) // Reserved
9417 #define PHY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER49_RESERVEDFIELD164 (0x1<<1) // Reserved
9421 #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_ERR (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an internal error detected by firmware. PHY error code can be used to isolate error event. Decoding table is provided in separate documentation.
9426 #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_REGBUS_ERR (0x1<<0) // Rebug error status. Write 1 to clear.
9429 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_CLR (0x1<<0) // Clear the debug info presented in REGBUS_ERR_INFO_STATUS* registers.
9434 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW (0x1<<2) // Errored register transfer type: 0 = read transfer 1 = write transfer
9452 #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_SIM_1B_MODEL (0x1<<0) // Set if running a 1b simulation. Firmware may check this field to discover its runtime context. Do not set on actual silicon.
9455 #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_RESERVEDFIELD169 (0x1<<0) // Reserved
9457 #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_CRC_DISABLE (0x1<<1) // Prevents firmware from running program memory CRC integrity check at boot up. Must be written before releasing cpu_reset_i
9461 #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_F5 (0x1<<0) // Indicates the presence of a new command to the PHY firmware. It is set automatically when CMD is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
9473 #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_F15 (0x1<<0) // Indicates the presence of a new Response to the PHY firmware. It is set automatically when RSP is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
9492 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER54_F32 (0x1<<0) // Reserved
9498 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER56_F34 (0x1<<0) // Reserved
9501 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER57_F35 (0x1<<0) // Reserved
9504 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER58_F36 (0x1<<0) // Reserved
9510 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER60_F38 (0x1<<0) // Reserved
9516 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER62_F40 (0x1<<0) // Reserved
9522 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER64_F42 (0x1<<0) // Reserved
9528 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER66_F44 (0x1<<0) // Reserved
9531 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER67_F45 (0x1<<0) // Reserved
9534 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER68_F46 (0x1<<0) // Reserved
9540 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER70_F48 (0x1<<0) // Reserved
9544 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER72_F50 (0x1<<0) // Reserved
9550 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER74_F52 (0x1<<0) // Reserved
9556 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER76_F54 (0x1<<0) // Reserved
9559 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER77_F55 (0x1<<0) // Reserved
9562 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER78_F56 (0x1<<0) // Reserved
9568 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER80_F58 (0x1<<0) // Reserved
9574 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER82_F60 (0x1<<0) // Reserved
9580 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER84_F62 (0x1<<0) // Reserved
9586 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RESERVEDREGISTER86_F64 (0x1<<0) // Reserved
9592 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER88_F66 (0x1<<0) // Reserved
9596 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER90_F68 (0x1<<0) // Reserved
9602 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER92_F70 (0x1<<0) // Reserved
9608 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER94_F72 (0x1<<0) // Reserved
9611 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER95_F73 (0x1<<0) // Reserved
9614 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_RESERVEDREGISTER96_F74 (0x1<<0) // Reserved
9620 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER98_F76 (0x1<<0) // Reserved
9623 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER99_F77 (0x1<<0) // Reserved
9626 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER100_F78 (0x1<<0) // Reserved
9630 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER102_F80 (0x1<<0) // Reserved
9633 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER103_F81 (0x1<<0) // Reserved
9639 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER105_F83 (0x1<<0) // Reserved
9645 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER107_F85 (0x1<<0) // Reserved
9651 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER109_F87 (0x1<<0) // Reserved
9657 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER111_F89 (0x1<<0) // Reserved
9660 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER112_F90 (0x1<<0) // Reserved
9663 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER113_F91 (0x1<<0) // Reserved
9669 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER115_F93 (0x1<<0) // Reserved
9675 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER117_F95 (0x1<<0) // Reserved
9678 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER118_F96 (0x1<<0) // Reserved
9681 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER119_F97 (0x1<<0) // Reserved
9684 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER120_F98 (0x1<<0) // Reserved
9687 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER121_F99 (0x1<<0) // Reserved
9690 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER122_F100 (0x1<<0) // Reserved
9693 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER123_F101 (0x1<<0) // Reserved
9696 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER124_F102 (0x1<<0) // Reserved
9699 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER125_F103 (0x1<<0) // Reserved
9705 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER127_F105 (0x1<<0) // Reserved
9708 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER128_F106 (0x1<<0) // Reserved
9711 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER129_F107 (0x1<<0) // Reserved
9717 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER131_F109 (0x1<<0) // Reserved
9723 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER133_F111 (0x1<<0) // Reserved
9729 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER135_F113 (0x1<<0) // Reserved
9735 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER137_F115 (0x1<<0) // Reserved
9741 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER139_F117 (0x1<<0) // Reserved
9747 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER141_F119 (0x1<<0) // Reserved
9753 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER143_F121 (0x1<<0) // Reserved
9759 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER145_F123 (0x1<<0) // Reserved
9765 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER147_F125 (0x1<<0) // Reserved
9771 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER149_F127 (0x1<<0) // Reserved
9777 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER151_F129 (0x1<<0) // Reserved
9783 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER153_F131 (0x1<<0) // Reserved
9789 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER155_F133 (0x1<<0) // Reserved
9795 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER157_F135 (0x1<<0) // Reserved
9801 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER159_F137 (0x1<<0) // Reserved
9807 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER161_F139 (0x1<<0) // Reserved
9813 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER163_F141 (0x1<<0) // Reserved
9819 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER165_F143 (0x1<<0) // Reserved
9825 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER167_F145 (0x1<<0) // Reserved
9831 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER169_F147 (0x1<<0) // Reserved
9837 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER171_F149 (0x1<<0) // Reserved
9843 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER173_F151 (0x1<<0) // Reserved
9849 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER175_F153 (0x1<<0) // Reserved
9855 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER177_F155 (0x1<<0) // Reserved
9858 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER178_F156 (0x1<<0) // Reserved
9861 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER179_F157 (0x1<<0) // Reserved
9867 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER181_F159 (0x1<<0) // Reserved
9873 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER183_F161 (0x1<<0) // Reserved
9879 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER185_F163 (0x1<<0) // Reserved
9885 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER187_F165 (0x1<<0) // Reserved
9891 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER189_F167 (0x1<<0) // Reserved
9897 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER191_F169 (0x1<<0) // Reserved
9903 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER193_F171 (0x1<<0) // Reserved
9909 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER195_F173 (0x1<<0) // Reserved
9915 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER197_F175 (0x1<<0) // Reserved
9921 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER199_F177 (0x1<<0) // Reserved
9927 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER201_F179 (0x1<<0) // Reserved
9933 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER203_F181 (0x1<<0) // Reserved
9939 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER205_F183 (0x1<<0) // Reserved
9945 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER207_F185 (0x1<<0) // Reserved
9951 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER209_F187 (0x1<<0) // Reserved
9957 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER211_F189 (0x1<<0) // Reserved
9963 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER213_F191 (0x1<<0) // Reserved
9969 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER215_F193 (0x1<<0) // Reserved
9972 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER216_F194 (0x1<<0) // Reserved
9975 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER217_F195 (0x1<<0) // Reserved
9978 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER218_F196 (0x1<<0) // Reserved
9981 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER219_F197 (0x1<<0) // Reserved
9984 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER220_F198 (0x1<<0) // Reserved
9987 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER221_F199 (0x1<<0) // Reserved
9990 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER222_F200 (0x1<<0) // Reserved
9993 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER223_F201 (0x1<<0) // Reserved
9996 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER224_F202 (0x1<<0) // Reserved
9999 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER225_F203 (0x1<<0) // Reserved
10002 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER226_F204 (0x1<<0) // Reserved
10005 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER227_F205 (0x1<<0) // Reserved
10011 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER229_F207 (0x1<<0) // Reserved
10017 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER231_F209 (0x1<<0) // Reserved
10020 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER232_F210 (0x1<<0) // Reserved
10023 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER233_F211 (0x1<<0) // Reserved
10029 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER235_F213 (0x1<<0) // Reserved
10035 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER237_F215 (0x1<<0) // Reserved
10041 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER239_F217 (0x1<<0) // Reserved
10044 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER240_F218 (0x1<<0) // Reserved
10047 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER241_F219 (0x1<<0) // Reserved
10053 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER243_F221 (0x1<<0) // Reserved
10056 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RESERVEDREGISTER244_F222 (0x1<<0) // Reserved
10059 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER245_F223 (0x1<<0) // Reserved
10062 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER246_F224 (0x1<<0) // Reserved
10065 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER247_F225 (0x1<<0) // Reserved
10069 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER249_F227 (0x1<<0) // Reserved
10072 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER250_F228 (0x1<<0) // Reserved
10078 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER252_F230 (0x1<<0) // Reserved
10084 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER254_F232 (0x1<<0) // Reserved
10090 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER256_F234 (0x1<<0) // Reserved
10096 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER258_F236 (0x1<<0) // Reserved
10099 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER259_F237 (0x1<<0) // Reserved
10102 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER260_F238 (0x1<<0) // Reserved
10108 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER262_F240 (0x1<<0) // Reserved
10114 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER264_F242 (0x1<<0) // Reserved
10117 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER265_F243 (0x1<<0) // Reserved
10120 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER266_F244 (0x1<<0) // Reserved
10123 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER267_F245 (0x1<<0) // Reserved
10126 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER268_F246 (0x1<<0) // Reserved
10129 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER269_F247 (0x1<<0) // Reserved
10132 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER270_F248 (0x1<<0) // Reserved
10135 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER271_F249 (0x1<<0) // Reserved
10138 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER272_F250 (0x1<<0) // Reserved
10144 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER274_F252 (0x1<<0) // Reserved
10147 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER275_F253 (0x1<<0) // Reserved
10150 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER276_F254 (0x1<<0) // Reserved
10156 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER278_F256 (0x1<<0) // Reserved
10162 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER280_F258 (0x1<<0) // Reserved
10168 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER282_F260 (0x1<<0) // Reserved
10174 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER284_F262 (0x1<<0) // Reserved
10180 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER286_F264 (0x1<<0) // Reserved
10186 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER288_F266 (0x1<<0) // Reserved
10192 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER290_F268 (0x1<<0) // Reserved
10198 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER292_F270 (0x1<<0) // Reserved
10204 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER294_F272 (0x1<<0) // Reserved
10210 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER296_F274 (0x1<<0) // Reserved
10216 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER298_F276 (0x1<<0) // Reserved
10222 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER300_F278 (0x1<<0) // Reserved
10228 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER302_F280 (0x1<<0) // Reserved
10234 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER304_F282 (0x1<<0) // Reserved
10240 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER306_F284 (0x1<<0) // Reserved
10246 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER308_F286 (0x1<<0) // Reserved
10252 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER310_F288 (0x1<<0) // Reserved
10258 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER312_F290 (0x1<<0) // Reserved
10264 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER314_F292 (0x1<<0) // Reserved
10270 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER316_F294 (0x1<<0) // Reserved
10276 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER318_F296 (0x1<<0) // Reserved
10282 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER320_F298 (0x1<<0) // Reserved
10288 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER322_F300 (0x1<<0) // Reserved
10294 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER324_F302 (0x1<<0) // Reserved
10297 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER325_F303 (0x1<<0) // Reserved
10300 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER326_F304 (0x1<<0) // Reserved
10306 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER328_F306 (0x1<<0) // Reserved
10312 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER330_F308 (0x1<<0) // Reserved
10318 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER332_F310 (0x1<<0) // Reserved
10324 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER334_F312 (0x1<<0) // Reserved
10330 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER336_F314 (0x1<<0) // Reserved
10336 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER338_F316 (0x1<<0) // Reserved
10342 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER340_F318 (0x1<<0) // Reserved
10348 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER342_F320 (0x1<<0) // Reserved
10354 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER344_F322 (0x1<<0) // Reserved
10360 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER346_F324 (0x1<<0) // Reserved
10366 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER348_F326 (0x1<<0) // Reserved
10372 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER350_F328 (0x1<<0) // Reserved
10378 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER352_F330 (0x1<<0) // Reserved
10384 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER354_F332 (0x1<<0) // Reserved
10390 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER356_F334 (0x1<<0) // Reserved
10396 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER358_F336 (0x1<<0) // Reserved
10402 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER360_F338 (0x1<<0) // Reserved
10408 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER362_F340 (0x1<<0) // Reserved
10411 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER363_F341 (0x1<<0) // Reserved
10414 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER364_F342 (0x1<<0) // Reserved
10417 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER365_F343 (0x1<<0) // Reserved
10420 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER366_F344 (0x1<<0) // Reserved
10423 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER367_F345 (0x1<<0) // Reserved
10426 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER368_F346 (0x1<<0) // Reserved
10429 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER369_F347 (0x1<<0) // Reserved
10432 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER370_F348 (0x1<<0) // Reserved
10435 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER371_F349 (0x1<<0) // Reserved
10438 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER372_F350 (0x1<<0) // Reserved
10441 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER373_F351 (0x1<<0) // Reserved
10444 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER374_F352 (0x1<<0) // Reserved
10450 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER376_F354 (0x1<<0) // Reserved
10456 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER378_F356 (0x1<<0) // Reserved
10459 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER379_F357 (0x1<<0) // Reserved
10462 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER380_F358 (0x1<<0) // Reserved
10468 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER382_F360 (0x1<<0) // Reserved
10474 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER384_F362 (0x1<<0) // Reserved
10480 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER386_F364 (0x1<<0) // Reserved
10483 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER387_F365 (0x1<<0) // Reserved
10486 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER388_F366 (0x1<<0) // Reserved
10492 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER390_F368 (0x1<<0) // Reserved
10495 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RESERVEDREGISTER391_F369 (0x1<<0) // Reserved
10498 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER392_F370 (0x1<<0) // Reserved
10501 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER393_F371 (0x1<<0) // Reserved
10504 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER394_F372 (0x1<<0) // Reserved
10508 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER396_F374 (0x1<<0) // Reserved
10511 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER397_F375 (0x1<<0) // Reserved
10517 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER399_F377 (0x1<<0) // Reserved
10523 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER401_F379 (0x1<<0) // Reserved
10529 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER403_F381 (0x1<<0) // Reserved
10535 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER405_F383 (0x1<<0) // Reserved
10538 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER406_F384 (0x1<<0) // Reserved
10541 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER407_F385 (0x1<<0) // Reserved
10547 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER409_F387 (0x1<<0) // Reserved
10553 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER411_F389 (0x1<<0) // Reserved
10556 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER412_F390 (0x1<<0) // Reserved
10559 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER413_F391 (0x1<<0) // Reserved
10562 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER414_F392 (0x1<<0) // Reserved
10565 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER415_F393 (0x1<<0) // Reserved
10568 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER416_F394 (0x1<<0) // Reserved
10571 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER417_F395 (0x1<<0) // Reserved
10574 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER418_F396 (0x1<<0) // Reserved
10577 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER419_F397 (0x1<<0) // Reserved
10583 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER421_F399 (0x1<<0) // Reserved
10586 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER422_F400 (0x1<<0) // Reserved
10589 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER423_F401 (0x1<<0) // Reserved
10595 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER425_F403 (0x1<<0) // Reserved
10601 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER427_F405 (0x1<<0) // Reserved
10607 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER429_F407 (0x1<<0) // Reserved
10613 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER431_F409 (0x1<<0) // Reserved
10619 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER433_F411 (0x1<<0) // Reserved
10625 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER435_F413 (0x1<<0) // Reserved
10631 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER437_F415 (0x1<<0) // Reserved
10637 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER439_F417 (0x1<<0) // Reserved
10643 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER441_F419 (0x1<<0) // Reserved
10649 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER443_F421 (0x1<<0) // Reserved
10655 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER445_F423 (0x1<<0) // Reserved
10661 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER447_F425 (0x1<<0) // Reserved
10667 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER449_F427 (0x1<<0) // Reserved
10673 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER451_F429 (0x1<<0) // Reserved
10679 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER453_F431 (0x1<<0) // Reserved
10685 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER455_F433 (0x1<<0) // Reserved
10691 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER457_F435 (0x1<<0) // Reserved
10697 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER459_F437 (0x1<<0) // Reserved
10703 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER461_F439 (0x1<<0) // Reserved
10709 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER463_F441 (0x1<<0) // Reserved
10715 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER465_F443 (0x1<<0) // Reserved
10721 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER467_F445 (0x1<<0) // Reserved
10727 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER469_F447 (0x1<<0) // Reserved
10733 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER471_F449 (0x1<<0) // Reserved
10736 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER472_F450 (0x1<<0) // Reserved
10739 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER473_F451 (0x1<<0) // Reserved
10745 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER475_F453 (0x1<<0) // Reserved
10751 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER477_F455 (0x1<<0) // Reserved
10757 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER479_F457 (0x1<<0) // Reserved
10763 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER481_F459 (0x1<<0) // Reserved
10769 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER483_F461 (0x1<<0) // Reserved
10775 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER485_F463 (0x1<<0) // Reserved
10781 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER487_F465 (0x1<<0) // Reserved
10787 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER489_F467 (0x1<<0) // Reserved
10793 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER491_F469 (0x1<<0) // Reserved
10799 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER493_F471 (0x1<<0) // Reserved
10805 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER495_F473 (0x1<<0) // Reserved
10811 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER497_F475 (0x1<<0) // Reserved
10817 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER499_F477 (0x1<<0) // Reserved
10823 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER501_F479 (0x1<<0) // Reserved
10829 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER503_F481 (0x1<<0) // Reserved
10835 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER505_F483 (0x1<<0) // Reserved
10841 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER507_F485 (0x1<<0) // Reserved
10847 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER509_F487 (0x1<<0) // Reserved
10850 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER510_F488 (0x1<<0) // Reserved
10853 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER511_F489 (0x1<<0) // Reserved
10856 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER512_F490 (0x1<<0) // Reserved
10859 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER513_F491 (0x1<<0) // Reserved
10862 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER514_F492 (0x1<<0) // Reserved
10865 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER515_F493 (0x1<<0) // Reserved
10868 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER516_F494 (0x1<<0) // Reserved
10871 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER517_F495 (0x1<<0) // Reserved
10874 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER518_F496 (0x1<<0) // Reserved
10877 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER519_F497 (0x1<<0) // Reserved
10880 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER520_F498 (0x1<<0) // Reserved
10883 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER521_F499 (0x1<<0) // Reserved
10889 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER523_F501 (0x1<<0) // Reserved
10895 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER525_F503 (0x1<<0) // Reserved
10898 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER526_F504 (0x1<<0) // Reserved
10901 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER527_F505 (0x1<<0) // Reserved
10907 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER529_F507 (0x1<<0) // Reserved
10913 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER531_F509 (0x1<<0) // Reserved
10919 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER533_F511 (0x1<<0) // Reserved
10922 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER534_F512 (0x1<<0) // Reserved
10925 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER535_F513 (0x1<<0) // Reserved
10931 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER537_F515 (0x1<<0) // Reserved
10934 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RESERVEDREGISTER538_F516 (0x1<<0) // Reserved
10937 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER539_F517 (0x1<<0) // Reserved
10940 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER540_F518 (0x1<<0) // Reserved
10943 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER541_F519 (0x1<<0) // Reserved
10947 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER543_F521 (0x1<<0) // Reserved
10950 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER544_F522 (0x1<<0) // Reserved
10956 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER546_F524 (0x1<<0) // Reserved
10962 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER548_F526 (0x1<<0) // Reserved
10968 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER550_F528 (0x1<<0) // Reserved
10974 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER552_F530 (0x1<<0) // Reserved
10977 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER553_F531 (0x1<<0) // Reserved
10980 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER554_F532 (0x1<<0) // Reserved
10986 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER556_F534 (0x1<<0) // Reserved
10992 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER558_F536 (0x1<<0) // Reserved
10995 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER559_F537 (0x1<<0) // Reserved
10998 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER560_F538 (0x1<<0) // Reserved
11001 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER561_F539 (0x1<<0) // Reserved
11004 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER562_F540 (0x1<<0) // Reserved
11007 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER563_F541 (0x1<<0) // Reserved
11010 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER564_F542 (0x1<<0) // Reserved
11013 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER565_F543 (0x1<<0) // Reserved
11016 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER566_F544 (0x1<<0) // Reserved
11022 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER568_F546 (0x1<<0) // Reserved
11025 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER569_F547 (0x1<<0) // Reserved
11028 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER570_F548 (0x1<<0) // Reserved
11034 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER572_F550 (0x1<<0) // Reserved
11040 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER574_F552 (0x1<<0) // Reserved
11046 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER576_F554 (0x1<<0) // Reserved
11052 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER578_F556 (0x1<<0) // Reserved
11058 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER580_F558 (0x1<<0) // Reserved
11064 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER582_F560 (0x1<<0) // Reserved
11070 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER584_F562 (0x1<<0) // Reserved
11076 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER586_F564 (0x1<<0) // Reserved
11082 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER588_F566 (0x1<<0) // Reserved
11088 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER590_F568 (0x1<<0) // Reserved
11094 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER592_F570 (0x1<<0) // Reserved
11100 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER594_F572 (0x1<<0) // Reserved
11106 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER596_F574 (0x1<<0) // Reserved
11112 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER598_F576 (0x1<<0) // Reserved
11118 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER600_F578 (0x1<<0) // Reserved
11124 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER602_F580 (0x1<<0) // Reserved
11130 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER604_F582 (0x1<<0) // Reserved
11136 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER606_F584 (0x1<<0) // Reserved
11142 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER608_F586 (0x1<<0) // Reserved
11148 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER610_F588 (0x1<<0) // Reserved
11154 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER612_F590 (0x1<<0) // Reserved
11160 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER614_F592 (0x1<<0) // Reserved
11166 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER616_F594 (0x1<<0) // Reserved
11172 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER618_F596 (0x1<<0) // Reserved
11175 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER619_F597 (0x1<<0) // Reserved
11178 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER620_F598 (0x1<<0) // Reserved
11184 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER622_F600 (0x1<<0) // Reserved
11190 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER624_F602 (0x1<<0) // Reserved
11196 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER626_F604 (0x1<<0) // Reserved
11202 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER628_F606 (0x1<<0) // Reserved
11208 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER630_F608 (0x1<<0) // Reserved
11214 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER632_F610 (0x1<<0) // Reserved
11220 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER634_F612 (0x1<<0) // Reserved
11226 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER636_F614 (0x1<<0) // Reserved
11232 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER638_F616 (0x1<<0) // Reserved
11238 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER640_F618 (0x1<<0) // Reserved
11244 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER642_F620 (0x1<<0) // Reserved
11250 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER644_F622 (0x1<<0) // Reserved
11256 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER646_F624 (0x1<<0) // Reserved
11262 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER648_F626 (0x1<<0) // Reserved
11268 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER650_F628 (0x1<<0) // Reserved
11274 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER652_F630 (0x1<<0) // Reserved
11280 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER654_F632 (0x1<<0) // Reserved
11286 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER656_F634 (0x1<<0) // Reserved
11289 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER657_F635 (0x1<<0) // Reserved
11292 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER658_F636 (0x1<<0) // Reserved
11295 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER659_F637 (0x1<<0) // Reserved
11298 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER660_F638 (0x1<<0) // Reserved
11301 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER661_F639 (0x1<<0) // Reserved
11304 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER662_F640 (0x1<<0) // Reserved
11307 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER663_F641 (0x1<<0) // Reserved
11310 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER664_F642 (0x1<<0) // Reserved
11313 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER665_F643 (0x1<<0) // Reserved
11316 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER666_F644 (0x1<<0) // Reserved
11319 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER667_F645 (0x1<<0) // Reserved
11322 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER668_F646 (0x1<<0) // Reserved
11328 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER670_F648 (0x1<<0) // Reserved
11334 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER672_F650 (0x1<<0) // Reserved
11337 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER673_F651 (0x1<<0) // Reserved
11340 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER674_F652 (0x1<<0) // Reserved
11346 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER676_F654 (0x1<<0) // Reserved
11352 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER678_F656 (0x1<<0) // Reserved
11358 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER680_F658 (0x1<<0) // Reserved
11361 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER681_F659 (0x1<<0) // Reserved
11364 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER682_F660 (0x1<<0) // Reserved
11370 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER684_F662 (0x1<<0) // Reserved
11373 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RESERVEDREGISTER685_F663 (0x1<<0) // Reserved
11376 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD170 (0x1<<0) // Reserved
11378 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD171 (0x1<<1) // Reserved
11380 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD172 (0x1<<2) // Reserved
11382 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD173 (0x1<<3) // Reserved
11384 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD174 (0x1<<4) // Reserved
11386 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD175 (0x1<<5) // Reserved
11388 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD176 (0x1<<6) // Reserved
11391 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD177 (0x1<<0) // Reserved
11393 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD178 (0x1<<1) // Reserved
11395 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER687_RESERVEDFIELD179 (0x1<<2) // Reserved
11398 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD180 (0x1<<0) // Reserved
11400 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD181 (0x1<<1) // Reserved
11402 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER688_RESERVEDFIELD182 (0x1<<2) // Reserved
11413 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD186 (0x1<<0) // Reserved
11415 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD187 (0x1<<1) // Reserved
11417 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER691_RESERVEDFIELD188 (0x1<<2) // Reserved
11431 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER695_RESERVEDFIELD193 (0x1<<0) // Reserved
11442 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER696_RESERVEDFIELD198 (0x1<<4) // Reserved
11451 #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD201 (0x1<<0) // Reserved
11453 #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_RESERVEDFIELD202 (0x1<<1) // Reserved
11457 #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV (0x7<<5) // Divider control for CMU output clock cm0_clkdiv_o. This is the additional divided CMU clock for SoC logic. A different divider is employed to allow a different clock frequency from cm0_clk_o. This clock can be used in gearbox applications. 0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV40 0x6 - DIV64 0x7 - DIV80 The output clock frequency is the serial data rate divided by the divider setting. For example, the output clock will be 805.66406MHz for the DIV32 setting at 25.78125Gbps.
11464 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER699_RESERVEDFIELD206 (0x1<<4) // Reserved
11473 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER700_RESERVEDFIELD210 (0x1<<7) // Reserved
11483 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_RESERVEDFIELD214 (0x1<<0) // Reserved
11485 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER704_RESERVEDFIELD215 (0x1<<1) // Reserved
11488 #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX (0x3<<0) // Test clock MUX control. This is a test feature that allows certain internal clocks to be muxed into the half-rate TX clock path to provide visibility at the TX driver output. 0x0 - mission mode 0x1 - reference clock 0x2 - life clock 0x3 - CMU PLL word rate clock cm0_clk_o
11490 #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV (0x7<<2) // Test clock divider control. This register controls a programmable divider on the test clock path before clock distribution from the CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10 0x6 - DIV16 0x7 - DIV20
11522 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER710_RESERVEDFIELD228 (0x1<<3) // Reserved
11527 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD230 (0x1<<3) // Reserved
11532 #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_CMU_OK (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the ACTIVE or PARTIAL power state, the PLL has locked to the reference clock, and all output clocks are at the correct frequency
11539 #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_CMU_ERR (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware. CMU error code can be used to isolate error event.
11542 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_RESERVEDFIELD232 (0x1<<0) // Reserved
11544 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER714_RESERVEDFIELD233 (0x1<<1) // Reserved
11547 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER715_RESERVEDFIELD234 (0x1<<0) // Reserved
11550 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD235 (0x1<<0) // Reserved
11554 #define PHY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD237 (0x1<<3) // Reserved
11557 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_RESERVEDFIELD238 (0x1<<0) // Reserved
11559 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER717_RESERVEDFIELD239 (0x1<<1) // Reserved
11562 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_RESERVEDFIELD240 (0x1<<0) // Reserved
11564 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER718_RESERVEDFIELD241 (0x1<<1) // Reserved
11567 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER719_RESERVEDFIELD242 (0x1<<0) // Reserved
11574 #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_CMPLL_V1P8_EN (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha is 1.8V nominal note: it is important that this register is maintained at the correct value matching the nominal vddha setting for all time following POR.
11577 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER720_RESERVEDFIELD245 (0x1<<0) // Reserved
11584 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_RESERVEDFIELD248 (0x1<<0) // Reserved
11586 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER721_RESERVEDFIELD249 (0x1<<1) // Reserved
11589 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD250 (0x1<<0) // Reserved
11591 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER722_RESERVEDFIELD251 (0x1<<1) // Reserved
11598 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD254 (0x1<<3) // Reserved
11600 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD255 (0x1<<4) // Reserved
11611 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD259 (0x1<<0) // Reserved
11613 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD260 (0x1<<1) // Reserved
11615 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER726_RESERVEDFIELD261 (0x1<<2) // Reserved
11621 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER728_RESERVEDFIELD263 (0x1<<0) // Reserved
11634 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER731_RESERVEDFIELD268 (0x1<<1) // Reserved
11643 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD272 (0x1<<2) // Reserved
11647 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD274 (0x1<<6) // Reserved
11650 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER733_RESERVEDFIELD275 (0x1<<0) // Reserved
11653 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER734_RESERVEDFIELD276 (0x1<<0) // Reserved
11696 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD281 (0x1<<4) // Reserved
11698 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER755_RESERVEDFIELD282 (0x1<<7) // Reserved
11715 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD284 (0x1<<2) // Reserved
11717 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD285 (0x1<<3) // Reserved
11724 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD289 (0x1<<6) // Reserved
11726 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER765_RESERVEDFIELD290 (0x1<<7) // Reserved
11729 #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_LOCKED (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PLL has locked to the reference clock, and all output clocks are at the correct frequency
11739 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD296 (0x1<<0) // Reserved
11741 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD297 (0x1<<1) // Reserved
11743 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER771_RESERVEDFIELD298 (0x1<<2) // Reserved
11751 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD302 (0x1<<0) // Reserved
11760 #define PHY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER776_RESERVEDFIELD306 (0x1<<7) // Reserved
11765 #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER779_RESERVEDFIELD307 (0x1<<0) // Reserved
11772 #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER782_RESERVEDFIELD310 (0x1<<0) // Reserved
11782 #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER786_RESERVEDFIELD315 (0x1<<0) // Reserved
11810 #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER796_RESERVEDFIELD327 (0x1<<0) // Reserved
11823 #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER805_RESERVEDFIELD336 (0x1<<0) // Reserved
11826 #define PHY_NW_IP_REG_CMU_LC0_GCFSM2_RESERVEDREGISTER806_RESERVEDFIELD337 (0x1<<0) // Reserved
11832 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD340 (0x1<<0) // Reserved
11834 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD341 (0x1<<1) // Reserved
11836 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD342 (0x1<<2) // Reserved
11838 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD343 (0x1<<3) // Reserved
11840 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD344 (0x1<<4) // Reserved
11842 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD345 (0x1<<5) // Reserved
11844 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD346 (0x1<<6) // Reserved
11847 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD347 (0x1<<0) // Reserved
11849 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD348 (0x1<<1) // Reserved
11851 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD349 (0x1<<2) // Reserved
11853 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD350 (0x1<<3) // Reserved
11855 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD351 (0x1<<4) // Reserved
11857 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD352 (0x1<<5) // Reserved
11859 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD353 (0x1<<6) // Reserved
11872 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER812_RESERVEDFIELD358 (0x1<<0) // Reserved
11877 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER813_RESERVEDFIELD360 (0x1<<0) // Reserved
11880 #define PHY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER814_RESERVEDFIELD361 (0x1<<0) // Reserved
11891 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER823_RESERVEDFIELD362 (0x1<<0) // Reserved
11894 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD363 (0x1<<0) // Reserved
11896 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD364 (0x1<<1) // Reserved
11898 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD365 (0x1<<2) // Reserved
11900 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD366 (0x1<<3) // Reserved
11902 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD367 (0x1<<4) // Reserved
11905 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD368 (0x1<<0) // Reserved
11907 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD369 (0x1<<1) // Reserved
11909 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD370 (0x1<<2) // Reserved
11911 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD371 (0x1<<3) // Reserved
11921 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_RESERVEDFIELD375 (0x1<<0) // Reserved
11923 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER827_RESERVEDFIELD376 (0x1<<1) // Reserved
11938 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD383 (0x1<<6) // Reserved
11941 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_RESERVEDFIELD384 (0x1<<0) // Reserved
11943 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER831_RESERVEDFIELD385 (0x1<<1) // Reserved
11959 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER835_RESERVEDFIELD392 (0x1<<3) // Reserved
11964 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD394 (0x1<<3) // Reserved
11969 #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_CMU_OK (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the ACTIVE or PARTIAL power state, the PLL has locked to the reference clock, and all output clocks are at the correct frequency
11976 #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_CMU_ERR (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware. CMU error code can be used to isolate error event.
11979 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_RESERVEDFIELD396 (0x1<<0) // Reserved
11981 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER839_RESERVEDFIELD397 (0x1<<1) // Reserved
11984 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER840_RESERVEDFIELD398 (0x1<<0) // Reserved
11987 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD399 (0x1<<0) // Reserved
11991 #define PHY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD401 (0x1<<3) // Reserved
11994 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_PD_CMPLL2 (0x1<<0) // Powerdown for RPLL.
11996 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_RESERVEDFIELD402 (0x1<<1) // Reserved
11999 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_FRACN_N (0x1<<0) // Resets the DivN counter in the FracN
12001 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_DIV4P125_N (0x1<<1) // TBD
12006 #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER842_RESERVEDFIELD404 (0x1<<2) // Reserved
12009 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_CMPLL2_REFCLK_SEL (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
12012 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_VCO_KICK (0x1<<0) // TBD
12020 #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER843_RESERVEDFIELD405 (0x1<<0) // Reserved
12026 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_MUTE (0x1<<0) // TBD
12028 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_UP (0x1<<1) // TBD
12030 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_DN (0x1<<2) // TBD
12041 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IDROPI (0x1<<0) // TBD
12043 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IHIZ (0x1<<1) // TBD
12050 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IZERO (0x1<<0) // TBD
12057 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_LPF (0x1<<3) // TBD
12062 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_EN (0x1<<0) // TBD
12067 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_CMPLL2_FRACDIV_EN (0x1<<0) // Selects between FracN and integer divide modes 0 � integer mode 1 � FracN/SSC mode
12070 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_CMPLL2_BIAS_LPF (0x1<<0) // TBD
12125 #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD409 (0x1<<2) // Reserved
12127 #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD410 (0x1<<3) // Reserved
12133 #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD413 (0x1<<6) // Reserved
12135 #define PHY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER871_RESERVEDFIELD414 (0x1<<7) // Reserved
12138 #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_LOCKED (0x1<<0) // For lock detection
12148 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_UPDOWN_EN (0x1<<0) // Enable for both Upspreading and Downspreading in SSC mode
12150 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_FRACSYN_EN (0x1<<1) // Enable for loading freq_offset sr as the offset to establish nominal frequency Freq_offset to implement SSC on
12152 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_SSC_EN (0x1<<2) // Enables SSC generation
12160 #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_FMODE_EN (0x1<<0) // enable the fracN div mode of the fracn_mod digital control block
12169 #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_RESERVEDFIELD417 (0x1<<7) // Reserved
12174 #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER874_RESERVEDFIELD418 (0x1<<0) // Reserved
12181 #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER877_RESERVEDFIELD421 (0x1<<0) // Reserved
12191 #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER881_RESERVEDFIELD426 (0x1<<0) // Reserved
12219 #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER891_RESERVEDFIELD438 (0x1<<0) // Reserved
12232 #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER900_RESERVEDFIELD447 (0x1<<0) // Reserved
12235 #define PHY_NW_IP_REG_CMU_R0_GCFSM2_RESERVEDREGISTER901_RESERVEDFIELD448 (0x1<<0) // Reserved
12241 #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER903_RESERVEDFIELD451 (0x1<<0) // Reserved
12244 #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER904_RESERVEDFIELD452 (0x1<<0) // Reserved
12249 #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER905_RESERVEDFIELD454 (0x1<<0) // Reserved
12252 #define PHY_NW_IP_REG_CMU_R0_FEATURE_RESERVEDREGISTER906_RESERVEDFIELD455 (0x1<<0) // Reserved
12263 #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN (0x1<<0) // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
12265 #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
12267 #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
12269 #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
12289 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_RESERVEDFIELD463 (0x1<<0) // Reserved
12291 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER918_RESERVEDFIELD464 (0x1<<1) // Reserved
12294 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER919_RESERVEDFIELD465 (0x1<<2) // Reserved
12304 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER921_RESERVEDFIELD469 (0x1<<6) // Reserved
12317 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER924_RESERVEDFIELD474 (0x1<<2) // Reserved
12332 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD480 (0x1<<3) // Reserved
12334 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD481 (0x1<<4) // Reserved
12343 #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN (0x1<<0) // Enables register control of TX data path mux in DPL
12347 #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_TXPOLARITY (0x1<<4) // TX data polarity control
12349 #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
12352 #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
12354 #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
12359 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER930_RESERVEDFIELD485 (0x1<<3) // Reserved
12364 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD487 (0x1<<3) // Reserved
12369 #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_LN_OK (0x1<<0) // LANE OK status
12382 #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_RXVALID (0x1<<0) // rxvalid status output
12385 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_RESERVEDFIELD493 (0x1<<0) // Reserved
12387 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER934_RESERVEDFIELD494 (0x1<<1) // Reserved
12390 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER935_RESERVEDFIELD495 (0x1<<0) // Reserved
12393 #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_OVR_EN (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
12395 #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
12400 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD496 (0x1<<0) // Reserved
12402 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD497 (0x1<<3) // Reserved
12404 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD498 (0x1<<4) // Reserved
12406 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD499 (0x1<<5) // Reserved
12409 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER937_RESERVEDFIELD500 (0x1<<0) // Reserved
12411 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER937_RESERVEDFIELD501 (0x1<<4) // Reserved
12414 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD502 (0x1<<0) // Reserved
12416 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD503 (0x1<<5) // Reserved
12418 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER938_RESERVEDFIELD504 (0x1<<6) // Reserved
12421 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD505 (0x1<<0) // Reserved
12425 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD507 (0x1<<3) // Reserved
12428 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD508 (0x1<<0) // Reserved
12430 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD509 (0x1<<1) // Reserved
12432 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER940_RESERVEDFIELD510 (0x1<<2) // Reserved
12435 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER941_RESERVEDFIELD511 (0x1<<0) // Reserved
12440 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER942_RESERVEDFIELD513 (0x1<<0) // Reserved
12449 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD517 (0x1<<6) // Reserved
12451 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD518 (0x1<<7) // Reserved
12454 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD519 (0x1<<0) // Reserved
12456 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD520 (0x1<<1) // Reserved
12460 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD522 (0x1<<4) // Reserved
12462 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD523 (0x1<<5) // Reserved
12464 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER944_RESERVEDFIELD524 (0x1<<6) // Reserved
12473 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_RESERVEDFIELD527 (0x1<<0) // Reserved
12475 #define PHY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER947_RESERVEDFIELD528 (0x1<<1) // Reserved
12480 #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_LANE_ERR (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
12483 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER948_RESERVEDFIELD529 (0x1<<0) // Reserved
12498 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER953_RESERVEDFIELD535 (0x1<<0) // Reserved
12506 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER957_RESERVEDFIELD539 (0x1<<0) // Reserved
12509 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER958_RESERVEDFIELD540 (0x1<<0) // Reserved
12516 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER961_RESERVEDFIELD543 (0x1<<0) // Reserved
12523 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER964_RESERVEDFIELD546 (0x1<<0) // Reserved
12529 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD548 (0x1<<0) // Reserved
12531 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD549 (0x1<<1) // Reserved
12533 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD550 (0x1<<2) // Reserved
12535 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD551 (0x1<<3) // Reserved
12545 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER970_RESERVEDFIELD555 (0x1<<0) // Reserved
12549 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8 (0x1<<0) // Binary-coded DLPF control input to the CDR
12552 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH (0x1<<0) // Indicates that DLPF control input to CDR is too high
12554 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW (0x1<<1) // Indicates that DLPF control input to CDR is too low
12556 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST (0x1<<2) // CDR loss of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
12559 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_LOCKED (0x1<<0) // CDR lock indicator. 1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
12583 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER979_RESERVEDFIELD566 (0x1<<0) // Reserved
12593 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD571 (0x1<<0) // Reserved
12595 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD572 (0x1<<1) // Reserved
12597 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER983_RESERVEDFIELD573 (0x1<<2) // Reserved
12623 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER993_RESERVEDFIELD585 (0x1<<0) // Reserved
12627 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER995_RESERVEDFIELD587 (0x1<<0) // Reserved
12630 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD588 (0x1<<0) // Reserved
12632 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER996_RESERVEDFIELD589 (0x1<<1) // Reserved
12647 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD595 (0x1<<2) // Reserved
12654 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1000_RESERVEDFIELD598 (0x1<<7) // Reserved
12659 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1001_RESERVEDFIELD600 (0x1<<7) // Reserved
12670 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD604 (0x1<<0) // Reserved
12672 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1004_RESERVEDFIELD605 (0x1<<1) // Reserved
12681 #define PHY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1009_RESERVEDFIELD610 (0x1<<0) // Reserved
12687 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_RESERVEDFIELD612 (0x1<<0) // Reserved
12689 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1011_RESERVEDFIELD613 (0x1<<1) // Reserved
12714 #define PHY_NW_IP_REG_LN0_ANEG_CFG11_PSEUDO_SEL (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
12717 #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_AUTONEG_RESTART (0x1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by rising edge of this signal. Not self clearing.
12722 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD625 (0x1<<4) // Reserved
12726 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1021_RESERVEDFIELD627 (0x1<<7) // Reserved
12729 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1022_RESERVEDFIELD628 (0x1<<0) // Reserved
12732 #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LP_AUTONEG_ABLE (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
12734 #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LINK_STATUS (0x1<<2) // Local link Status. When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
12736 #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_ABILITY (0x1<<3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
12738 #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_REMOTE_FAULT (0x1<<4) // Remote Fault
12740 #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_COMPLETE (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
12743 #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PAGE_RX (0x1<<0) // Page Received. To clear it, write 1 to it.
12745 #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_AN_LINK_GOOD (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
12747 #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PARALLEL_DET_FAULT (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
12749 #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_NP_LOADED (0x1<<3) // mr_np_loaded status.
12751 #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_RESERVEDFIELD629 (0x1<<4) // Reserved
12753 #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_RESERVEDFIELD630 (0x1<<5) // Reserved
12765 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_PAUSE (0x1<<2) // Pause advertised ability
12767 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ASM_DIR (0x1<<3) // Pause ASM_DIR advertised ability
12769 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_C2 (0x1<<4) // Reserved always 0
12771 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Remote Fault Local Device
12773 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Next Page
12779 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // 1000Base-KX technology advertised ability
12781 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // 10GBase-KX4 technology advertised ability
12783 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // 10GBase-KR technology advertised ability
12785 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // 40GBase-KR4 technology advertised ability
12787 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // 40GBase-CR4 technology advertised ability
12789 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // 100GBase-CR10 technology advertised ability
12791 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // 100GBase-KP4 technology advertised ability
12793 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // 100GBase-KR4 technology advertised ability
12796 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // 100GBase-CR4 technology advertised ability
12798 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
12800 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
12808 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // base page bit F0. It advertises FEC ability
12810 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // base page bit F1. It requests FEC to be turned on when supported at the both ends of link
12812 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
12814 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
12817 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_KR (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
12819 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_CR (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
12821 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
12823 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
12825 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
12827 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
12829 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_REQ (0x1<<6) // Extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
12831 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_REQ (0x1<<7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
12837 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD632 (0x1<<3) // Reserved
12839 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD633 (0x1<<4) // Reserved
12841 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD634 (0x1<<5) // Reserved
12843 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD635 (0x1<<7) // Reserved
12850 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD636 (0x1<<0) // Reserved
12852 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD637 (0x1<<1) // Reserved
12854 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD638 (0x1<<2) // Reserved
12856 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD639 (0x1<<3) // Reserved
12858 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD640 (0x1<<4) // Reserved
12860 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD641 (0x1<<5) // Reserved
12862 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD642 (0x1<<6) // Reserved
12864 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD643 (0x1<<7) // Reserved
12867 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD644 (0x1<<0) // Reserved
12869 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD645 (0x1<<1) // Reserved
12871 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD646 (0x1<<2) // Reserved
12873 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD647 (0x1<<3) // Reserved
12875 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD648 (0x1<<4) // Reserved
12877 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD649 (0x1<<5) // Reserved
12879 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD650 (0x1<<6) // Reserved
12889 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_PAUSE (0x1<<2) // Link partner Pause advertised ability
12891 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ASM_DIR (0x1<<3) // Link partner Pause ASM_DIR advertised ability
12893 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_C2 (0x1<<4) // Link partner C2 field always 0
12895 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Link partner Remote Fault
12897 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ACK (0x1<<6) // Link partner Acknowledge always 0
12899 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Link partner Next Page
12905 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // Link partner 1000Base-KX technology advertised ability
12907 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
12909 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // Link partner 10GBase-KR technology advertised ability
12911 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
12913 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
12915 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
12917 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
12919 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
12922 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
12924 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
12926 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
12934 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // Link partner base page bit F0. It advertises FEC ability
12936 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when supported at the both ends of link
12938 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
12940 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
12943 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_KR (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
12945 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_CR (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
12947 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
12949 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
12951 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Link partner extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
12953 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Link partner extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
12955 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_REQ (0x1<<6) // Link partner extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
12957 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_REQ (0x1<<7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
12963 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD652 (0x1<<3) // Reserved
12965 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD653 (0x1<<4) // Reserved
12967 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD654 (0x1<<5) // Reserved
12969 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD655 (0x1<<7) // Reserved
12976 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD656 (0x1<<0) // Reserved
12978 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD657 (0x1<<1) // Reserved
12980 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD658 (0x1<<2) // Reserved
12982 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD659 (0x1<<3) // Reserved
12984 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD660 (0x1<<4) // Reserved
12986 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD661 (0x1<<5) // Reserved
12988 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD662 (0x1<<6) // Reserved
12990 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD663 (0x1<<7) // Reserved
12993 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD664 (0x1<<0) // Reserved
12995 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD665 (0x1<<1) // Reserved
12997 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD666 (0x1<<2) // Reserved
12999 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD667 (0x1<<3) // Reserved
13001 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD668 (0x1<<4) // Reserved
13003 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD669 (0x1<<5) // Reserved
13005 #define PHY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD670 (0x1<<6) // Reserved
13008 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is 1.
13010 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4 (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when status0.an_link_good is 1.
13012 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is 1.
13014 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4 (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good is 1.
13016 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4 (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good is 1.
13018 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10 (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good is 1.
13020 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4 (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good is 1.
13022 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4 (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good is 1.
13025 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4 (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good is 1.
13027 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when status0.an_link_good is 1.
13029 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_good is 1.
13031 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is 1.
13033 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good is 1.
13035 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2 (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good is 1.
13037 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2 (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good is 1.
13040 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_RS (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_good is 1.
13042 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_FC (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when status0.an_link_good is 1.
13045 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_RX (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
13047 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_TX (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when status0.an_link_good is 1.
13050 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_F746 (0x1<<0) // Resolution result for EEE. It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherwise. It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
13053 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_1G_KX (0x1<<0) // link_status for 1000Base-KX
13055 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KX4 (0x1<<1) // link_status for 10GBase-KX4
13057 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KR (0x1<<2) // link_status for 10GBase-KR
13059 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_KR4 (0x1<<3) // link_status for 40GBase-KR4
13061 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_CR4 (0x1<<4) // link_status for 40GBase-CR4
13063 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_CR10 (0x1<<5) // link_status for 100GBase-CR10
13065 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KP4 (0x1<<6) // link_status for 100GBase-KP4
13067 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KR4 (0x1<<7) // link_status for 100GBase-KR4
13070 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_100G_CR4 (0x1<<0) // link_status for 100GBase-CR4
13072 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_GR (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
13074 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_KR (0x1<<3) // link_status for 25GBase-KR
13076 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_CR (0x1<<4) // link_status for 25GBase-CR4
13078 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_KR2 (0x1<<5) // link_status for 50GBase-KR2
13080 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_CR2 (0x1<<6) // link_status for 50GBase-CR2
13085 #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1039_RESERVEDFIELD672 (0x1<<2) // Reserved
13088 #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1040_RESERVEDFIELD673 (0x1<<0) // Reserved
13091 #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1041_RESERVEDFIELD674 (0x1<<0) // Reserved
13094 #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD675 (0x1<<0) // Reserved
13098 #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD677 (0x1<<3) // Reserved
13100 #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD678 (0x1<<4) // Reserved
13103 #define PHY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1043_RESERVEDFIELD679 (0x1<<0) // Reserved
13110 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1046_RESERVEDFIELD683 (0x1<<6) // Reserved
13119 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD687 (0x1<<0) // Reserved
13123 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD689 (0x1<<3) // Reserved
13126 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1050_RESERVEDFIELD690 (0x1<<0) // Reserved
13171 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1059_RESERVEDFIELD708 (0x1<<0) // Reserved
13173 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1059_RESERVEDFIELD709 (0x1<<2) // Reserved
13187 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD716 (0x1<<6) // Reserved
13189 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD717 (0x1<<7) // Reserved
13206 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1070_RESERVEDFIELD726 (0x1<<1) // Reserved
13222 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD732 (0x1<<6) // Reserved
13224 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1075_RESERVEDFIELD733 (0x1<<7) // Reserved
13227 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD734 (0x1<<0) // Reserved
13229 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1076_RESERVEDFIELD735 (0x1<<1) // Reserved
13238 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1077_RESERVEDFIELD739 (0x1<<6) // Reserved
13252 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1083_RESERVEDFIELD746 (0x1<<4) // Reserved
13269 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1086_RESERVEDFIELD750 (0x1<<7) // Reserved
13272 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD751 (0x1<<0) // Reserved
13274 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1087_RESERVEDFIELD752 (0x1<<1) // Reserved
13283 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1088_RESERVEDFIELD756 (0x1<<6) // Reserved
13289 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD758 (0x1<<0) // Reserved
13291 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD759 (0x1<<1) // Reserved
13293 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD760 (0x1<<2) // Reserved
13295 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD761 (0x1<<3) // Reserved
13428 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1116_RESERVEDFIELD813 (0x1<<7) // Reserved
13431 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD814 (0x1<<0) // Reserved
13433 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1117_RESERVEDFIELD815 (0x1<<1) // Reserved
13442 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1118_RESERVEDFIELD819 (0x1<<6) // Reserved
13464 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1121_RESERVEDFIELD824 (0x1<<7) // Reserved
13467 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD825 (0x1<<0) // Reserved
13469 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1122_RESERVEDFIELD826 (0x1<<1) // Reserved
13478 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1123_RESERVEDFIELD830 (0x1<<6) // Reserved
13501 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1130_RESERVEDFIELD838 (0x1<<7) // Reserved
13504 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD839 (0x1<<0) // Reserved
13506 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1131_RESERVEDFIELD840 (0x1<<1) // Reserved
13515 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1132_RESERVEDFIELD844 (0x1<<6) // Reserved
13523 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1134_RESERVEDFIELD847 (0x1<<4) // Reserved
13533 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD850 (0x1<<0) // Reserved
13535 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1137_RESERVEDFIELD851 (0x1<<1) // Reserved
13544 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1138_RESERVEDFIELD855 (0x1<<6) // Reserved
13549 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD858 (0x1<<0) // Reserved
13551 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1141_RESERVEDFIELD859 (0x1<<1) // Reserved
13560 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1142_RESERVEDFIELD863 (0x1<<6) // Reserved
13568 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD869 (0x1<<0) // Reserved
13570 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1148_RESERVEDFIELD870 (0x1<<1) // Reserved
13573 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD871 (0x1<<0) // Reserved
13575 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1149_RESERVEDFIELD872 (0x1<<1) // Reserved
13578 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1150_RESERVEDFIELD873 (0x1<<6) // Reserved
13620 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1171_RESERVEDFIELD890 (0x1<<0) // Reserved
13627 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1173_RESERVEDFIELD892 (0x1<<0) // Reserved
13635 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD895 (0x1<<0) // Reserved
13637 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD896 (0x1<<1) // Reserved
13641 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1175_RESERVEDFIELD898 (0x1<<5) // Reserved
13646 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD900 (0x1<<0) // Reserved
13648 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD901 (0x1<<1) // Reserved
13652 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1176_RESERVEDFIELD903 (0x1<<4) // Reserved
13680 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_REQ (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. Set to 0 once ack is 1.
13683 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_ACK (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
13695 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD915 (0x1<<0) // Reserved
13697 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1183_RESERVEDFIELD916 (0x1<<1) // Reserved
13703 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD917 (0x1<<0) // Reserved
13705 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD918 (0x1<<1) // Reserved
13709 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1184_RESERVEDFIELD920 (0x1<<5) // Reserved
13714 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD922 (0x1<<0) // Reserved
13716 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD923 (0x1<<1) // Reserved
13720 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1185_RESERVEDFIELD925 (0x1<<4) // Reserved
13749 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1192_RESERVEDFIELD936 (0x1<<0) // Reserved
13752 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1193_RESERVEDFIELD937 (0x1<<0) // Reserved
13755 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD938 (0x1<<0) // Reserved
13757 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1194_RESERVEDFIELD939 (0x1<<1) // Reserved
13778 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1197_RESERVEDFIELD948 (0x1<<6) // Reserved
13781 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1198_RESERVEDFIELD949 (0x1<<0) // Reserved
13787 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1200_RESERVEDFIELD952 (0x1<<0) // Reserved
13793 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1202_RESERVEDFIELD955 (0x1<<0) // Reserved
13798 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1203_RESERVEDFIELD957 (0x1<<7) // Reserved
13801 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_REQ (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
13805 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD958 (0x1<<6) // Reserved
13807 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL (0x1<<7) // Set it to 1 when changing DFE tap values
13812 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1204_RESERVEDFIELD960 (0x1<<4) // Reserved
13827 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_ACK (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
13829 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD967 (0x1<<1) // Reserved
13831 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD968 (0x1<<2) // Reserved
13833 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD969 (0x1<<3) // Reserved
13836 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13838 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13840 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13842 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13844 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP2_EN (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13846 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP3_EN (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13848 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP4_EN (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13850 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP5_EN (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13855 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13860 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13865 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13870 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13875 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13880 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13885 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13890 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13895 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13900 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13905 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13910 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13915 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13920 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13925 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13930 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13935 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13940 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13945 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13950 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13955 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13960 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13965 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13970 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
13973 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD970 (0x1<<0) // Reserved
13975 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD971 (0x1<<1) // Reserved
13977 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD972 (0x1<<2) // Reserved
13979 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD973 (0x1<<3) // Reserved
13981 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD974 (0x1<<4) // Reserved
13983 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD975 (0x1<<5) // Reserved
13985 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD976 (0x1<<6) // Reserved
13987 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD977 (0x1<<7) // Reserved
14044 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD996 (0x1<<0) // Reserved
14046 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD997 (0x1<<1) // Reserved
14048 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD998 (0x1<<2) // Reserved
14050 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD999 (0x1<<3) // Reserved
14052 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1000 (0x1<<4) // Reserved
14054 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1001 (0x1<<5) // Reserved
14056 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1002 (0x1<<6) // Reserved
14058 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD1003 (0x1<<7) // Reserved
14061 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1004 (0x1<<0) // Reserved
14063 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1005 (0x1<<1) // Reserved
14065 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1231_RESERVEDFIELD1006 (0x1<<2) // Reserved
14068 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1007 (0x1<<0) // Reserved
14070 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1008 (0x1<<1) // Reserved
14072 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1009 (0x1<<2) // Reserved
14074 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1010 (0x1<<3) // Reserved
14076 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1011 (0x1<<4) // Reserved
14078 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1012 (0x1<<5) // Reserved
14080 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1013 (0x1<<6) // Reserved
14082 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1014 (0x1<<7) // Reserved
14086 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1234_RESERVEDFIELD1016 (0x1<<0) // Reserved
14091 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1018 (0x1<<5) // Reserved
14093 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1235_RESERVEDFIELD1019 (0x1<<6) // Reserved
14096 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1020 (0x1<<0) // Reserved
14098 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1236_RESERVEDFIELD1021 (0x1<<1) // Reserved
14105 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1024 (0x1<<0) // Reserved
14107 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1239_RESERVEDFIELD1025 (0x1<<1) // Reserved
14118 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1030 (0x1<<0) // Reserved
14120 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1031 (0x1<<1) // Reserved
14122 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1244_RESERVEDFIELD1032 (0x1<<2) // Reserved
14125 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1245_RESERVEDFIELD1033 (0x1<<0) // Reserved
14159 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1259_RESERVEDFIELD1051 (0x1<<0) // Reserved
14230 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1088 (0x1<<0) // Reserved
14232 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1296_RESERVEDFIELD1089 (0x1<<1) // Reserved
14237 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1299_RESERVEDFIELD1092 (0x1<<0) // Reserved
14250 #define PHY_NW_IP_REG_LN0_DFE_RXCLK_RESERVEDREGISTER1310_RESERVEDFIELD1103 (0x1<<0) // Reserved
14253 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL (0x1<<0) // Enables analog LOS offset calibration circuits.
14262 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_EN (0x1<<0) // Enables the run-length detection digital LOS filter.
14266 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
14268 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
14279 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_EN (0x1<<0) // Enables the digital deglitching filter.
14282 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1313_RESERVEDFIELD1106 (0x1<<0) // Reserved
14291 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
14293 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE (0x1<<4) // Override value for the LOS output of the digital filtering logic.
14296 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1318_RESERVEDFIELD1111 (0x1<<0) // Reserved
14298 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1318_RESERVEDFIELD1112 (0x1<<4) // Reserved
14303 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1319_RESERVEDFIELD1114 (0x1<<6) // Reserved
14308 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1320_RESERVEDFIELD1116 (0x1<<6) // Reserved
14311 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1117 (0x1<<0) // Reserved
14315 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1321_RESERVEDFIELD1119 (0x1<<4) // Reserved
14318 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1120 (0x1<<0) // Reserved
14320 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1121 (0x1<<1) // Reserved
14322 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1122 (0x1<<2) // Reserved
14329 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1325_RESERVEDFIELD1126 (0x1<<0) // Reserved
14332 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1127 (0x1<<0) // Reserved
14334 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1326_RESERVEDFIELD1128 (0x1<<1) // Reserved
14343 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1131 (0x1<<0) // Reserved
14345 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1329_RESERVEDFIELD1132 (0x1<<1) // Reserved
14348 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_READY (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
14350 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_RESERVEDFIELD1133 (0x1<<1) // Reserved
14352 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS (0x1<<2) // The filtered LOS signal value.
14354 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_RAW (0x1<<3) // The unfiltered LOS signal value.
14356 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_NO_EII (0x1<<4) // The filtered LOS signal value before EII override logic.
14358 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_RESERVEDFIELD1134 (0x1<<5) // Reserved
14361 #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1330_RESERVEDFIELD1135 (0x1<<0) // Reserved
14368 #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1333_RESERVEDFIELD1138 (0x1<<0) // Reserved
14378 #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1337_RESERVEDFIELD1143 (0x1<<0) // Reserved
14406 #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1347_RESERVEDFIELD1155 (0x1<<0) // Reserved
14419 #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1356_RESERVEDFIELD1164 (0x1<<0) // Reserved
14422 #define PHY_NW_IP_REG_LN0_GCFSM2_RESERVEDREGISTER1357_RESERVEDFIELD1165 (0x1<<0) // Reserved
14428 #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_EN (0x1<<0) // Enables BIST Tx data generation.
14430 #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to transmitted: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x9 � MAC Tx data
14437 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_MODE (0x3<<0) // Controls what type of error injection is used: 0x0 � None 0x1 � Single cycle error 0x2 � Timer based
14473 #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_EN (0x1<<0) // Enables BIST Rx data checking.
14475 #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
14477 #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_CLEAR_BER (0x1<<5) // Clears the bit error counter.
14479 #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_STOP_ERROR_COUNT (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER data coherently.
14481 #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be inaccurate.
14484 #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_STATE (0x7<<0) // State of the BIST checker: 0x0 � Off 0x1 � Searching for pattern 0x2 � Waiting for pattern lock conditions 0x3 � Pattern lock acquired 0x4 � Pattern lock lost
14486 #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_PATTERN_DET (0xf<<3) // Indicates the pattern detected: 0x0 � No pattern detected 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP
14503 #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
14532 #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_AC_COUPLED (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
14535 #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_EN (0x1<<0) // Enables turning on the divided rxclk output
14538 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_RESERVEDFIELD1172 (0x1<<0) // Reserved
14540 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1363_RESERVEDFIELD1173 (0x1<<1) // Reserved
14543 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1174 (0x1<<0) // Reserved
14545 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1175 (0x1<<1) // Reserved
14547 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1176 (0x1<<2) // Reserved
14549 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1177 (0x1<<3) // Reserved
14551 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1178 (0x1<<4) // Reserved
14553 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1179 (0x1<<5) // Reserved
14556 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1180 (0x1<<0) // Reserved
14558 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1181 (0x1<<1) // Reserved
14560 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1182 (0x1<<2) // Reserved
14562 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1183 (0x1<<3) // Reserved
14565 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1184 (0x1<<0) // Reserved
14567 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1185 (0x1<<1) // Reserved
14569 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1186 (0x1<<2) // Reserved
14571 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1187 (0x1<<3) // Reserved
14573 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1188 (0x1<<4) // Reserved
14575 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1189 (0x1<<5) // Reserved
14577 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1190 (0x1<<6) // Reserved
14579 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1191 (0x1<<7) // Reserved
14582 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1192 (0x1<<0) // Reserved
14584 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1193 (0x1<<1) // Reserved
14586 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1194 (0x1<<2) // Reserved
14588 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1195 (0x1<<3) // Reserved
14593 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1197 (0x1<<0) // Reserved
14595 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1198 (0x1<<1) // Reserved
14597 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1368_RESERVEDFIELD1199 (0x1<<2) // Reserved
14606 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1371_RESERVEDFIELD1202 (0x1<<0) // Reserved
14612 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_RESERVEDFIELD1205 (0x1<<0) // Reserved
14614 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1373_RESERVEDFIELD1206 (0x1<<1) // Reserved
14617 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_RESERVEDFIELD1207 (0x1<<0) // Reserved
14619 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1374_RESERVEDFIELD1208 (0x1<<1) // Reserved
14622 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_RESERVEDFIELD1209 (0x1<<0) // Reserved
14624 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1375_RESERVEDFIELD1210 (0x1<<1) // Reserved
14627 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1376_RESERVEDFIELD1211 (0x1<<0) // Reserved
14639 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
14641 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD1214 (0x1<<2) // Reserved
14644 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
14646 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD1215 (0x1<<2) // Reserved
14649 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
14651 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
14658 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
14660 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
14662 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
14664 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
14666 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1218 (0x1<<4) // Reserved
14668 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1219 (0x1<<5) // Reserved
14670 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1220 (0x1<<6) // Reserved
14672 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD1221 (0x1<<7) // Reserved
14675 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
14677 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
14684 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1377_RESERVEDFIELD1224 (0x1<<0) // Reserved
14687 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
14689 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
14691 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1225 (0x1<<2) // Reserved
14693 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1226 (0x1<<3) // Reserved
14696 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1227 (0x1<<0) // Reserved
14698 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1228 (0x1<<1) // Reserved
14700 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1229 (0x1<<2) // Reserved
14702 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1230 (0x1<<3) // Reserved
14704 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1231 (0x1<<4) // Reserved
14706 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1232 (0x1<<5) // Reserved
14708 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1233 (0x1<<6) // Reserved
14710 #define PHY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1234 (0x1<<7) // Reserved
14713 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP1_EN (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
14715 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP2_EN (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
14717 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP3_EN (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
14719 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP4_EN (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
14721 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP5_EN (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
14724 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_METHOD_SEL (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
14727 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 1
14729 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1235 (0x1<<1) // Reserved
14731 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1236 (0x1<<2) // Reserved
14733 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1237 (0x1<<3) // Reserved
14736 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 2
14738 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1238 (0x1<<1) // Reserved
14740 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1239 (0x1<<2) // Reserved
14742 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1240 (0x1<<3) // Reserved
14745 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 3
14747 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1241 (0x1<<1) // Reserved
14749 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1242 (0x1<<2) // Reserved
14751 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1243 (0x1<<3) // Reserved
14754 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 4
14756 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1244 (0x1<<1) // Reserved
14758 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1245 (0x1<<2) // Reserved
14760 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1246 (0x1<<3) // Reserved
14763 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 5
14765 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1247 (0x1<<1) // Reserved
14767 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1248 (0x1<<2) // Reserved
14769 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1249 (0x1<<3) // Reserved
14772 #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_EN (0x1<<0) // Enables continuous background adaptation
14774 #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD1250 (0x1<<1) // Reserved
14810 #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1267 (0x1<<0) // Reserved
14812 #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RX_CTRL_DIS (0x1<<1) // Disables the firmware rx_ctrl MSM
14814 #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1268 (0x1<<2) // Reserved
14816 #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1269 (0x1<<3) // Reserved
14827 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING (0x1<<0) // Starts link training procedure when asserted. This is an 802.3 defined variable.
14829 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion. This is an 802.3 defined variable.
14831 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_SIGNAL_DETECT (0x1<<2) // Output corresponding to link training signal detect variable. Should be set when link training has completed successfully.
14833 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR (0x1<<3) // Synchronous reset for LT Tx block.
14839 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_WAIT_TIME_8 (0x1<<0) // Same as above.
14842 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_FRAME_LOCK (0x1<<0) // Input to LTSM that receiver has acquired frame lock. This value should be taken from the corresponding LT Rx register. This an 802.3 defined variable.
14844 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_RX_TRAINED (0x1<<1) // Input to LTSM indicating that the local receiver has completed training. This is an 802.3 defined variable.
14846 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_REMOTE_RX_READY (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready. This value should be taken from the corresponding LT Rx registers. This is an 802.3 defined variable.
14849 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_FAIL (0x1<<0) // Output from LTSM indicating that link training has failed. This is an 802.3 defined variable.
14851 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING (0x1<<1) // Output from LTSM indicating that link training is in progress. This is an 802.3 defined variable.
14853 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_SIGNAL_DETECT (0x1<<2) // Output from LTSM indicating that link training is complete and successful. This is an 802.3 defined variable. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
14855 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
14871 #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE (0x1<<6) // Coefficient update initialize field.
14873 #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET (0x1<<7) // Coefficient update preset field.
14882 #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY (0x1<<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM output of corresponding variable.
14885 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_CURRENT (0x7<<0) // Current state of LTSM. 0x0 � INITIALIZE 0x1 � SEND_TRAINING 0x2 � TRAIN_REMOTE 0x3 � TRAIN_LOCAL 0x4 � S7 0x5 � TRAINING_FAILURE 0x6 � LINK_READY 0x7 � SEND_DATA
14895 #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_CLEAR (0x1<<0) // Synchronous reset for LT Rx block.
14897 #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_TRAINING (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corresponding LTSM output.
14904 #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_UPDATE (0x1<<0) // Assertion indicates that PRBS status information has been updated.
14906 #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_LOCK (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
14913 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_CLEAR_COUNT (0x1<<0) // Clears both the absolute and erroneous frame counters.
14916 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_FRAME_LOCK (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
14929 #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE (0x1<<6) // Received coefficient update initialize field.
14931 #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET (0x1<<7) // Received coefficient update preset field.
14940 #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_LOCAL_RX_READY (0x1<<6) // Received status report field to indicate local receiver is ready.
14942 #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_DME_ERROR (0x1<<7) // Indicates differential manchester decoding error. Not sticky.
14945 #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN (0x1<<0) // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
14947 #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
14949 #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
14951 #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
14971 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_RESERVEDFIELD1277 (0x1<<0) // Reserved
14973 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1402_RESERVEDFIELD1278 (0x1<<1) // Reserved
14976 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1403_RESERVEDFIELD1279 (0x1<<2) // Reserved
14986 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1405_RESERVEDFIELD1283 (0x1<<6) // Reserved
14999 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1408_RESERVEDFIELD1288 (0x1<<2) // Reserved
15014 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1294 (0x1<<3) // Reserved
15016 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1295 (0x1<<4) // Reserved
15025 #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN (0x1<<0) // Enables register control of TX data path mux in DPL
15029 #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_TXPOLARITY (0x1<<4) // TX data polarity control
15031 #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
15034 #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
15036 #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
15041 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1414_RESERVEDFIELD1299 (0x1<<3) // Reserved
15046 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1301 (0x1<<3) // Reserved
15051 #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_LN_OK (0x1<<0) // LANE OK status
15064 #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_RXVALID (0x1<<0) // rxvalid status output
15067 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_RESERVEDFIELD1307 (0x1<<0) // Reserved
15069 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1418_RESERVEDFIELD1308 (0x1<<1) // Reserved
15072 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1419_RESERVEDFIELD1309 (0x1<<0) // Reserved
15075 #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_OVR_EN (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
15077 #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
15082 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1310 (0x1<<0) // Reserved
15084 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1311 (0x1<<3) // Reserved
15086 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1312 (0x1<<4) // Reserved
15088 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1313 (0x1<<5) // Reserved
15091 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1421_RESERVEDFIELD1314 (0x1<<0) // Reserved
15093 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1421_RESERVEDFIELD1315 (0x1<<4) // Reserved
15096 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1316 (0x1<<0) // Reserved
15098 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1317 (0x1<<5) // Reserved
15100 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1422_RESERVEDFIELD1318 (0x1<<6) // Reserved
15103 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1319 (0x1<<0) // Reserved
15107 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1321 (0x1<<3) // Reserved
15110 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1322 (0x1<<0) // Reserved
15112 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1323 (0x1<<1) // Reserved
15114 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1424_RESERVEDFIELD1324 (0x1<<2) // Reserved
15117 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1425_RESERVEDFIELD1325 (0x1<<0) // Reserved
15122 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1426_RESERVEDFIELD1327 (0x1<<0) // Reserved
15131 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1331 (0x1<<6) // Reserved
15133 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1332 (0x1<<7) // Reserved
15136 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1333 (0x1<<0) // Reserved
15138 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1334 (0x1<<1) // Reserved
15142 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1336 (0x1<<4) // Reserved
15144 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1337 (0x1<<5) // Reserved
15146 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1428_RESERVEDFIELD1338 (0x1<<6) // Reserved
15155 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_RESERVEDFIELD1341 (0x1<<0) // Reserved
15157 #define PHY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1431_RESERVEDFIELD1342 (0x1<<1) // Reserved
15162 #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_LANE_ERR (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
15165 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1432_RESERVEDFIELD1343 (0x1<<0) // Reserved
15180 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1437_RESERVEDFIELD1349 (0x1<<0) // Reserved
15188 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1441_RESERVEDFIELD1353 (0x1<<0) // Reserved
15191 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1442_RESERVEDFIELD1354 (0x1<<0) // Reserved
15198 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1445_RESERVEDFIELD1357 (0x1<<0) // Reserved
15205 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1448_RESERVEDFIELD1360 (0x1<<0) // Reserved
15211 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1362 (0x1<<0) // Reserved
15213 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1363 (0x1<<1) // Reserved
15215 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1364 (0x1<<2) // Reserved
15217 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1365 (0x1<<3) // Reserved
15227 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1454_RESERVEDFIELD1369 (0x1<<0) // Reserved
15231 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8 (0x1<<0) // Binary-coded DLPF control input to the CDR
15234 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH (0x1<<0) // Indicates that DLPF control input to CDR is too high
15236 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW (0x1<<1) // Indicates that DLPF control input to CDR is too low
15238 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST (0x1<<2) // CDR loss of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
15241 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_LOCKED (0x1<<0) // CDR lock indicator. 1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
15265 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1463_RESERVEDFIELD1380 (0x1<<0) // Reserved
15275 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1385 (0x1<<0) // Reserved
15277 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1386 (0x1<<1) // Reserved
15279 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1467_RESERVEDFIELD1387 (0x1<<2) // Reserved
15305 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1477_RESERVEDFIELD1399 (0x1<<0) // Reserved
15309 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1479_RESERVEDFIELD1401 (0x1<<0) // Reserved
15312 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1402 (0x1<<0) // Reserved
15314 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1480_RESERVEDFIELD1403 (0x1<<1) // Reserved
15329 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1409 (0x1<<2) // Reserved
15336 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1484_RESERVEDFIELD1412 (0x1<<7) // Reserved
15341 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1485_RESERVEDFIELD1414 (0x1<<7) // Reserved
15352 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1418 (0x1<<0) // Reserved
15354 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1488_RESERVEDFIELD1419 (0x1<<1) // Reserved
15363 #define PHY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1493_RESERVEDFIELD1424 (0x1<<0) // Reserved
15369 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_RESERVEDFIELD1426 (0x1<<0) // Reserved
15371 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1495_RESERVEDFIELD1427 (0x1<<1) // Reserved
15396 #define PHY_NW_IP_REG_LN1_ANEG_CFG11_PSEUDO_SEL (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15399 #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_AUTONEG_RESTART (0x1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by rising edge of this signal. Not self clearing.
15404 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1439 (0x1<<4) // Reserved
15408 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1505_RESERVEDFIELD1441 (0x1<<7) // Reserved
15411 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1506_RESERVEDFIELD1442 (0x1<<0) // Reserved
15414 #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LP_AUTONEG_ABLE (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
15416 #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LINK_STATUS (0x1<<2) // Local link Status. When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
15418 #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_ABILITY (0x1<<3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
15420 #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_REMOTE_FAULT (0x1<<4) // Remote Fault
15422 #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_COMPLETE (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
15425 #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PAGE_RX (0x1<<0) // Page Received. To clear it, write 1 to it.
15427 #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_AN_LINK_GOOD (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
15429 #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PARALLEL_DET_FAULT (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
15431 #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_NP_LOADED (0x1<<3) // mr_np_loaded status.
15433 #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_RESERVEDFIELD1443 (0x1<<4) // Reserved
15435 #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_RESERVEDFIELD1444 (0x1<<5) // Reserved
15447 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_PAUSE (0x1<<2) // Pause advertised ability
15449 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ASM_DIR (0x1<<3) // Pause ASM_DIR advertised ability
15451 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_C2 (0x1<<4) // Reserved always 0
15453 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Remote Fault Local Device
15455 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Next Page
15461 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // 1000Base-KX technology advertised ability
15463 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // 10GBase-KX4 technology advertised ability
15465 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // 10GBase-KR technology advertised ability
15467 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // 40GBase-KR4 technology advertised ability
15469 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // 40GBase-CR4 technology advertised ability
15471 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // 100GBase-CR10 technology advertised ability
15473 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // 100GBase-KP4 technology advertised ability
15475 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // 100GBase-KR4 technology advertised ability
15478 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // 100GBase-CR4 technology advertised ability
15480 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
15482 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
15490 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // base page bit F0. It advertises FEC ability
15492 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // base page bit F1. It requests FEC to be turned on when supported at the both ends of link
15494 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
15496 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
15499 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_KR (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
15501 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_CR (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
15503 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15505 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15507 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
15509 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15511 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_REQ (0x1<<6) // Extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15513 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_REQ (0x1<<7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15519 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1446 (0x1<<3) // Reserved
15521 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1447 (0x1<<4) // Reserved
15523 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1448 (0x1<<5) // Reserved
15525 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1449 (0x1<<7) // Reserved
15532 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1450 (0x1<<0) // Reserved
15534 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1451 (0x1<<1) // Reserved
15536 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1452 (0x1<<2) // Reserved
15538 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1453 (0x1<<3) // Reserved
15540 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1454 (0x1<<4) // Reserved
15542 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1455 (0x1<<5) // Reserved
15544 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1456 (0x1<<6) // Reserved
15546 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1457 (0x1<<7) // Reserved
15549 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1458 (0x1<<0) // Reserved
15551 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1459 (0x1<<1) // Reserved
15553 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1460 (0x1<<2) // Reserved
15555 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1461 (0x1<<3) // Reserved
15557 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1462 (0x1<<4) // Reserved
15559 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1463 (0x1<<5) // Reserved
15561 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1464 (0x1<<6) // Reserved
15571 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_PAUSE (0x1<<2) // Link partner Pause advertised ability
15573 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ASM_DIR (0x1<<3) // Link partner Pause ASM_DIR advertised ability
15575 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_C2 (0x1<<4) // Link partner C2 field always 0
15577 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Link partner Remote Fault
15579 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ACK (0x1<<6) // Link partner Acknowledge always 0
15581 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Link partner Next Page
15587 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // Link partner 1000Base-KX technology advertised ability
15589 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
15591 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // Link partner 10GBase-KR technology advertised ability
15593 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
15595 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
15597 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
15599 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
15601 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
15604 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
15606 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
15608 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
15616 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // Link partner base page bit F0. It advertises FEC ability
15618 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when supported at the both ends of link
15620 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
15622 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
15625 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_KR (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
15627 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_CR (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
15629 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15631 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15633 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Link partner extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
15635 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Link partner extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15637 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_REQ (0x1<<6) // Link partner extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15639 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_REQ (0x1<<7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15645 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1466 (0x1<<3) // Reserved
15647 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1467 (0x1<<4) // Reserved
15649 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1468 (0x1<<5) // Reserved
15651 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1469 (0x1<<7) // Reserved
15658 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1470 (0x1<<0) // Reserved
15660 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1471 (0x1<<1) // Reserved
15662 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1472 (0x1<<2) // Reserved
15664 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1473 (0x1<<3) // Reserved
15666 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1474 (0x1<<4) // Reserved
15668 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1475 (0x1<<5) // Reserved
15670 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1476 (0x1<<6) // Reserved
15672 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1477 (0x1<<7) // Reserved
15675 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1478 (0x1<<0) // Reserved
15677 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1479 (0x1<<1) // Reserved
15679 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1480 (0x1<<2) // Reserved
15681 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1481 (0x1<<3) // Reserved
15683 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1482 (0x1<<4) // Reserved
15685 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1483 (0x1<<5) // Reserved
15687 #define PHY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1484 (0x1<<6) // Reserved
15690 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is 1.
15692 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4 (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when status0.an_link_good is 1.
15694 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is 1.
15696 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4 (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good is 1.
15698 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4 (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good is 1.
15700 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10 (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good is 1.
15702 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4 (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good is 1.
15704 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4 (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good is 1.
15707 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4 (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good is 1.
15709 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when status0.an_link_good is 1.
15711 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_good is 1.
15713 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is 1.
15715 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good is 1.
15717 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2 (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good is 1.
15719 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2 (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good is 1.
15722 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_RS (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_good is 1.
15724 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_FC (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when status0.an_link_good is 1.
15727 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_RX (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
15729 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_TX (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when status0.an_link_good is 1.
15732 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_F821 (0x1<<0) // Resolution result for EEE. It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherwise. It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
15735 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_1G_KX (0x1<<0) // link_status for 1000Base-KX
15737 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KX4 (0x1<<1) // link_status for 10GBase-KX4
15739 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KR (0x1<<2) // link_status for 10GBase-KR
15741 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_KR4 (0x1<<3) // link_status for 40GBase-KR4
15743 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_CR4 (0x1<<4) // link_status for 40GBase-CR4
15745 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_CR10 (0x1<<5) // link_status for 100GBase-CR10
15747 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KP4 (0x1<<6) // link_status for 100GBase-KP4
15749 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KR4 (0x1<<7) // link_status for 100GBase-KR4
15752 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_100G_CR4 (0x1<<0) // link_status for 100GBase-CR4
15754 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_GR (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
15756 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_KR (0x1<<3) // link_status for 25GBase-KR
15758 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_CR (0x1<<4) // link_status for 25GBase-CR4
15760 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_KR2 (0x1<<5) // link_status for 50GBase-KR2
15762 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_CR2 (0x1<<6) // link_status for 50GBase-CR2
15767 #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1523_RESERVEDFIELD1486 (0x1<<2) // Reserved
15770 #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1524_RESERVEDFIELD1487 (0x1<<0) // Reserved
15773 #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1525_RESERVEDFIELD1488 (0x1<<0) // Reserved
15776 #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1489 (0x1<<0) // Reserved
15780 #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1491 (0x1<<3) // Reserved
15782 #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1492 (0x1<<4) // Reserved
15785 #define PHY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1527_RESERVEDFIELD1493 (0x1<<0) // Reserved
15792 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1530_RESERVEDFIELD1497 (0x1<<6) // Reserved
15801 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1501 (0x1<<0) // Reserved
15805 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1503 (0x1<<3) // Reserved
15808 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1534_RESERVEDFIELD1504 (0x1<<0) // Reserved
15853 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1543_RESERVEDFIELD1522 (0x1<<0) // Reserved
15855 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1543_RESERVEDFIELD1523 (0x1<<2) // Reserved
15869 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1530 (0x1<<6) // Reserved
15871 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1531 (0x1<<7) // Reserved
15888 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1554_RESERVEDFIELD1540 (0x1<<1) // Reserved
15904 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1546 (0x1<<6) // Reserved
15906 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1559_RESERVEDFIELD1547 (0x1<<7) // Reserved
15909 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1548 (0x1<<0) // Reserved
15911 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1560_RESERVEDFIELD1549 (0x1<<1) // Reserved
15920 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1561_RESERVEDFIELD1553 (0x1<<6) // Reserved
15934 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1567_RESERVEDFIELD1560 (0x1<<4) // Reserved
15951 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1570_RESERVEDFIELD1564 (0x1<<7) // Reserved
15954 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1565 (0x1<<0) // Reserved
15956 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1571_RESERVEDFIELD1566 (0x1<<1) // Reserved
15965 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1572_RESERVEDFIELD1570 (0x1<<6) // Reserved
15971 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1572 (0x1<<0) // Reserved
15973 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1573 (0x1<<1) // Reserved
15975 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1574 (0x1<<2) // Reserved
15977 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1575 (0x1<<3) // Reserved
16110 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1600_RESERVEDFIELD1627 (0x1<<7) // Reserved
16113 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1628 (0x1<<0) // Reserved
16115 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1601_RESERVEDFIELD1629 (0x1<<1) // Reserved
16124 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1602_RESERVEDFIELD1633 (0x1<<6) // Reserved
16146 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1605_RESERVEDFIELD1638 (0x1<<7) // Reserved
16149 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1639 (0x1<<0) // Reserved
16151 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1606_RESERVEDFIELD1640 (0x1<<1) // Reserved
16160 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1607_RESERVEDFIELD1644 (0x1<<6) // Reserved
16183 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1614_RESERVEDFIELD1652 (0x1<<7) // Reserved
16186 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1653 (0x1<<0) // Reserved
16188 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1615_RESERVEDFIELD1654 (0x1<<1) // Reserved
16197 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1616_RESERVEDFIELD1658 (0x1<<6) // Reserved
16205 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1618_RESERVEDFIELD1661 (0x1<<4) // Reserved
16215 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1664 (0x1<<0) // Reserved
16217 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1621_RESERVEDFIELD1665 (0x1<<1) // Reserved
16226 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1622_RESERVEDFIELD1669 (0x1<<6) // Reserved
16231 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1672 (0x1<<0) // Reserved
16233 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1625_RESERVEDFIELD1673 (0x1<<1) // Reserved
16242 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1626_RESERVEDFIELD1677 (0x1<<6) // Reserved
16250 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1683 (0x1<<0) // Reserved
16252 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1632_RESERVEDFIELD1684 (0x1<<1) // Reserved
16255 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1685 (0x1<<0) // Reserved
16257 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1633_RESERVEDFIELD1686 (0x1<<1) // Reserved
16260 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1634_RESERVEDFIELD1687 (0x1<<6) // Reserved
16302 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1655_RESERVEDFIELD1704 (0x1<<0) // Reserved
16309 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1657_RESERVEDFIELD1706 (0x1<<0) // Reserved
16317 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1709 (0x1<<0) // Reserved
16319 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1710 (0x1<<1) // Reserved
16323 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1659_RESERVEDFIELD1712 (0x1<<5) // Reserved
16328 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1714 (0x1<<0) // Reserved
16330 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1715 (0x1<<1) // Reserved
16334 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1660_RESERVEDFIELD1717 (0x1<<4) // Reserved
16362 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_REQ (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. Set to 0 once ack is 1.
16365 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_ACK (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
16377 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1729 (0x1<<0) // Reserved
16379 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1667_RESERVEDFIELD1730 (0x1<<1) // Reserved
16385 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1731 (0x1<<0) // Reserved
16387 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1732 (0x1<<1) // Reserved
16391 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1668_RESERVEDFIELD1734 (0x1<<5) // Reserved
16396 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1736 (0x1<<0) // Reserved
16398 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1737 (0x1<<1) // Reserved
16402 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1669_RESERVEDFIELD1739 (0x1<<4) // Reserved
16431 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1676_RESERVEDFIELD1750 (0x1<<0) // Reserved
16434 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1677_RESERVEDFIELD1751 (0x1<<0) // Reserved
16437 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1752 (0x1<<0) // Reserved
16439 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1678_RESERVEDFIELD1753 (0x1<<1) // Reserved
16460 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1681_RESERVEDFIELD1762 (0x1<<6) // Reserved
16463 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1682_RESERVEDFIELD1763 (0x1<<0) // Reserved
16469 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1684_RESERVEDFIELD1766 (0x1<<0) // Reserved
16475 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1686_RESERVEDFIELD1769 (0x1<<0) // Reserved
16480 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1687_RESERVEDFIELD1771 (0x1<<7) // Reserved
16483 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_REQ (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
16487 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD1772 (0x1<<6) // Reserved
16489 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL (0x1<<7) // Set it to 1 when changing DFE tap values
16494 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1688_RESERVEDFIELD1774 (0x1<<4) // Reserved
16509 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_ACK (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
16511 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1781 (0x1<<1) // Reserved
16513 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1782 (0x1<<2) // Reserved
16515 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1783 (0x1<<3) // Reserved
16518 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16520 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16522 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16524 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16526 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP2_EN (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16528 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP3_EN (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16530 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP4_EN (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16532 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP5_EN (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16537 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16542 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16547 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16552 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16557 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16562 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16567 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16572 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16577 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16582 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16587 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16592 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16597 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16602 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16607 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16612 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16617 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16622 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16627 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16632 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16637 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16642 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16647 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16652 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
16655 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1784 (0x1<<0) // Reserved
16657 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1785 (0x1<<1) // Reserved
16659 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1786 (0x1<<2) // Reserved
16661 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1787 (0x1<<3) // Reserved
16663 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1788 (0x1<<4) // Reserved
16665 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1789 (0x1<<5) // Reserved
16667 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1790 (0x1<<6) // Reserved
16669 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1791 (0x1<<7) // Reserved
16726 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1810 (0x1<<0) // Reserved
16728 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1811 (0x1<<1) // Reserved
16730 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1812 (0x1<<2) // Reserved
16732 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1813 (0x1<<3) // Reserved
16734 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1814 (0x1<<4) // Reserved
16736 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1815 (0x1<<5) // Reserved
16738 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1816 (0x1<<6) // Reserved
16740 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1817 (0x1<<7) // Reserved
16743 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1818 (0x1<<0) // Reserved
16745 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1819 (0x1<<1) // Reserved
16747 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1715_RESERVEDFIELD1820 (0x1<<2) // Reserved
16750 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1821 (0x1<<0) // Reserved
16752 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1822 (0x1<<1) // Reserved
16754 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1823 (0x1<<2) // Reserved
16756 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1824 (0x1<<3) // Reserved
16758 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1825 (0x1<<4) // Reserved
16760 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1826 (0x1<<5) // Reserved
16762 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1827 (0x1<<6) // Reserved
16764 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1828 (0x1<<7) // Reserved
16768 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1718_RESERVEDFIELD1830 (0x1<<0) // Reserved
16773 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1832 (0x1<<5) // Reserved
16775 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1719_RESERVEDFIELD1833 (0x1<<6) // Reserved
16778 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1834 (0x1<<0) // Reserved
16780 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1720_RESERVEDFIELD1835 (0x1<<1) // Reserved
16787 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1838 (0x1<<0) // Reserved
16789 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1723_RESERVEDFIELD1839 (0x1<<1) // Reserved
16800 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1844 (0x1<<0) // Reserved
16802 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1845 (0x1<<1) // Reserved
16804 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1728_RESERVEDFIELD1846 (0x1<<2) // Reserved
16807 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1729_RESERVEDFIELD1847 (0x1<<0) // Reserved
16841 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1743_RESERVEDFIELD1865 (0x1<<0) // Reserved
16912 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1902 (0x1<<0) // Reserved
16914 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1780_RESERVEDFIELD1903 (0x1<<1) // Reserved
16919 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1783_RESERVEDFIELD1906 (0x1<<0) // Reserved
16932 #define PHY_NW_IP_REG_LN1_DFE_RXCLK_RESERVEDREGISTER1794_RESERVEDFIELD1917 (0x1<<0) // Reserved
16935 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL (0x1<<0) // Enables analog LOS offset calibration circuits.
16944 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_EN (0x1<<0) // Enables the run-length detection digital LOS filter.
16948 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
16950 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
16961 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_EN (0x1<<0) // Enables the digital deglitching filter.
16964 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1797_RESERVEDFIELD1920 (0x1<<0) // Reserved
16973 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
16975 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE (0x1<<4) // Override value for the LOS output of the digital filtering logic.
16978 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1802_RESERVEDFIELD1925 (0x1<<0) // Reserved
16980 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1802_RESERVEDFIELD1926 (0x1<<4) // Reserved
16985 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1803_RESERVEDFIELD1928 (0x1<<6) // Reserved
16990 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1804_RESERVEDFIELD1930 (0x1<<6) // Reserved
16993 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1931 (0x1<<0) // Reserved
16997 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1805_RESERVEDFIELD1933 (0x1<<4) // Reserved
17000 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1934 (0x1<<0) // Reserved
17002 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1935 (0x1<<1) // Reserved
17004 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1936 (0x1<<2) // Reserved
17011 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1809_RESERVEDFIELD1940 (0x1<<0) // Reserved
17014 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1941 (0x1<<0) // Reserved
17016 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1810_RESERVEDFIELD1942 (0x1<<1) // Reserved
17025 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1945 (0x1<<0) // Reserved
17027 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1813_RESERVEDFIELD1946 (0x1<<1) // Reserved
17030 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_READY (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
17032 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_RESERVEDFIELD1947 (0x1<<1) // Reserved
17034 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS (0x1<<2) // The filtered LOS signal value.
17036 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_RAW (0x1<<3) // The unfiltered LOS signal value.
17038 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_NO_EII (0x1<<4) // The filtered LOS signal value before EII override logic.
17040 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_RESERVEDFIELD1948 (0x1<<5) // Reserved
17043 #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1814_RESERVEDFIELD1949 (0x1<<0) // Reserved
17050 #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1817_RESERVEDFIELD1952 (0x1<<0) // Reserved
17060 #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1821_RESERVEDFIELD1957 (0x1<<0) // Reserved
17088 #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1831_RESERVEDFIELD1969 (0x1<<0) // Reserved
17101 #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1840_RESERVEDFIELD1978 (0x1<<0) // Reserved
17104 #define PHY_NW_IP_REG_LN1_GCFSM2_RESERVEDREGISTER1841_RESERVEDFIELD1979 (0x1<<0) // Reserved
17110 #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_EN (0x1<<0) // Enables BIST Tx data generation.
17112 #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to transmitted: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x9 � MAC Tx data
17119 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_MODE (0x3<<0) // Controls what type of error injection is used: 0x0 � None 0x1 � Single cycle error 0x2 � Timer based
17155 #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_EN (0x1<<0) // Enables BIST Rx data checking.
17157 #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
17159 #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_CLEAR_BER (0x1<<5) // Clears the bit error counter.
17161 #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_STOP_ERROR_COUNT (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER data coherently.
17163 #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be inaccurate.
17166 #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_STATE (0x7<<0) // State of the BIST checker: 0x0 � Off 0x1 � Searching for pattern 0x2 � Waiting for pattern lock conditions 0x3 � Pattern lock acquired 0x4 � Pattern lock lost
17168 #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_PATTERN_DET (0xf<<3) // Indicates the pattern detected: 0x0 � No pattern detected 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP
17185 #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17214 #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_AC_COUPLED (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
17217 #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_EN (0x1<<0) // Enables turning on the divided rxclk output
17220 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_RESERVEDFIELD1986 (0x1<<0) // Reserved
17222 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1847_RESERVEDFIELD1987 (0x1<<1) // Reserved
17225 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1988 (0x1<<0) // Reserved
17227 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1989 (0x1<<1) // Reserved
17229 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1990 (0x1<<2) // Reserved
17231 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1991 (0x1<<3) // Reserved
17233 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1992 (0x1<<4) // Reserved
17235 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1993 (0x1<<5) // Reserved
17238 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1994 (0x1<<0) // Reserved
17240 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1995 (0x1<<1) // Reserved
17242 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1996 (0x1<<2) // Reserved
17244 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1997 (0x1<<3) // Reserved
17247 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD1998 (0x1<<0) // Reserved
17249 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD1999 (0x1<<1) // Reserved
17251 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2000 (0x1<<2) // Reserved
17253 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2001 (0x1<<3) // Reserved
17255 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2002 (0x1<<4) // Reserved
17257 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2003 (0x1<<5) // Reserved
17259 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2004 (0x1<<6) // Reserved
17261 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2005 (0x1<<7) // Reserved
17264 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2006 (0x1<<0) // Reserved
17266 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2007 (0x1<<1) // Reserved
17268 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2008 (0x1<<2) // Reserved
17270 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2009 (0x1<<3) // Reserved
17275 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2011 (0x1<<0) // Reserved
17277 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2012 (0x1<<1) // Reserved
17279 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1852_RESERVEDFIELD2013 (0x1<<2) // Reserved
17288 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1855_RESERVEDFIELD2016 (0x1<<0) // Reserved
17294 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_RESERVEDFIELD2019 (0x1<<0) // Reserved
17296 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1857_RESERVEDFIELD2020 (0x1<<1) // Reserved
17299 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_RESERVEDFIELD2021 (0x1<<0) // Reserved
17301 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1858_RESERVEDFIELD2022 (0x1<<1) // Reserved
17304 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_RESERVEDFIELD2023 (0x1<<0) // Reserved
17306 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1859_RESERVEDFIELD2024 (0x1<<1) // Reserved
17309 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1860_RESERVEDFIELD2025 (0x1<<0) // Reserved
17321 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
17323 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD2028 (0x1<<2) // Reserved
17326 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
17328 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD2029 (0x1<<2) // Reserved
17331 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
17333 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
17340 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
17342 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
17344 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
17346 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
17348 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2032 (0x1<<4) // Reserved
17350 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2033 (0x1<<5) // Reserved
17352 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2034 (0x1<<6) // Reserved
17354 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2035 (0x1<<7) // Reserved
17357 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
17359 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
17366 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1861_RESERVEDFIELD2038 (0x1<<0) // Reserved
17369 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
17371 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
17373 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2039 (0x1<<2) // Reserved
17375 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2040 (0x1<<3) // Reserved
17378 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2041 (0x1<<0) // Reserved
17380 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2042 (0x1<<1) // Reserved
17382 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2043 (0x1<<2) // Reserved
17384 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2044 (0x1<<3) // Reserved
17386 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2045 (0x1<<4) // Reserved
17388 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2046 (0x1<<5) // Reserved
17390 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2047 (0x1<<6) // Reserved
17392 #define PHY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2048 (0x1<<7) // Reserved
17395 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP1_EN (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
17397 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP2_EN (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
17399 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP3_EN (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
17401 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP4_EN (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
17403 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP5_EN (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
17406 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_METHOD_SEL (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
17409 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 1
17411 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2049 (0x1<<1) // Reserved
17413 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2050 (0x1<<2) // Reserved
17415 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2051 (0x1<<3) // Reserved
17418 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 2
17420 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2052 (0x1<<1) // Reserved
17422 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2053 (0x1<<2) // Reserved
17424 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2054 (0x1<<3) // Reserved
17427 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 3
17429 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2055 (0x1<<1) // Reserved
17431 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2056 (0x1<<2) // Reserved
17433 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2057 (0x1<<3) // Reserved
17436 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 4
17438 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2058 (0x1<<1) // Reserved
17440 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2059 (0x1<<2) // Reserved
17442 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2060 (0x1<<3) // Reserved
17445 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 5
17447 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2061 (0x1<<1) // Reserved
17449 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2062 (0x1<<2) // Reserved
17451 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2063 (0x1<<3) // Reserved
17454 #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_EN (0x1<<0) // Enables continuous background adaptation
17456 #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2064 (0x1<<1) // Reserved
17492 #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2081 (0x1<<0) // Reserved
17494 #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RX_CTRL_DIS (0x1<<1) // Disables the firmware rx_ctrl MSM
17496 #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2082 (0x1<<2) // Reserved
17498 #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2083 (0x1<<3) // Reserved
17509 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING (0x1<<0) // Starts link training procedure when asserted. This is an 802.3 defined variable.
17511 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion. This is an 802.3 defined variable.
17513 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_SIGNAL_DETECT (0x1<<2) // Output corresponding to link training signal detect variable. Should be set when link training has completed successfully.
17515 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_CLEAR (0x1<<3) // Synchronous reset for LT Tx block.
17521 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_WAIT_TIME_8 (0x1<<0) // Same as above.
17524 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_FRAME_LOCK (0x1<<0) // Input to LTSM that receiver has acquired frame lock. This value should be taken from the corresponding LT Rx register. This an 802.3 defined variable.
17526 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_RX_TRAINED (0x1<<1) // Input to LTSM indicating that the local receiver has completed training. This is an 802.3 defined variable.
17528 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_REMOTE_RX_READY (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready. This value should be taken from the corresponding LT Rx registers. This is an 802.3 defined variable.
17531 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_FAIL (0x1<<0) // Output from LTSM indicating that link training has failed. This is an 802.3 defined variable.
17533 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING (0x1<<1) // Output from LTSM indicating that link training is in progress. This is an 802.3 defined variable.
17535 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_SIGNAL_DETECT (0x1<<2) // Output from LTSM indicating that link training is complete and successful. This is an 802.3 defined variable. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17537 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
17553 #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE (0x1<<6) // Coefficient update initialize field.
17555 #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET (0x1<<7) // Coefficient update preset field.
17564 #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY (0x1<<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM output of corresponding variable.
17567 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_CURRENT (0x7<<0) // Current state of LTSM. 0x0 � INITIALIZE 0x1 � SEND_TRAINING 0x2 � TRAIN_REMOTE 0x3 � TRAIN_LOCAL 0x4 � S7 0x5 � TRAINING_FAILURE 0x6 � LINK_READY 0x7 � SEND_DATA
17577 #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_CLEAR (0x1<<0) // Synchronous reset for LT Rx block.
17579 #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_TRAINING (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corresponding LTSM output.
17586 #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_UPDATE (0x1<<0) // Assertion indicates that PRBS status information has been updated.
17588 #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_LOCK (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
17595 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_CLEAR_COUNT (0x1<<0) // Clears both the absolute and erroneous frame counters.
17598 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_FRAME_LOCK (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
17611 #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE (0x1<<6) // Received coefficient update initialize field.
17613 #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET (0x1<<7) // Received coefficient update preset field.
17622 #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_LOCAL_RX_READY (0x1<<6) // Received status report field to indicate local receiver is ready.
17624 #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_DME_ERROR (0x1<<7) // Indicates differential manchester decoding error. Not sticky.
17627 #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN (0x1<<0) // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
17629 #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
17631 #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
17633 #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
17653 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_RESERVEDFIELD2091 (0x1<<0) // Reserved
17655 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1886_RESERVEDFIELD2092 (0x1<<1) // Reserved
17658 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1887_RESERVEDFIELD2093 (0x1<<2) // Reserved
17668 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1889_RESERVEDFIELD2097 (0x1<<6) // Reserved
17681 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1892_RESERVEDFIELD2102 (0x1<<2) // Reserved
17696 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2108 (0x1<<3) // Reserved
17698 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2109 (0x1<<4) // Reserved
17707 #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN (0x1<<0) // Enables register control of TX data path mux in DPL
17711 #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_TXPOLARITY (0x1<<4) // TX data polarity control
17713 #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
17716 #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
17718 #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
17723 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1898_RESERVEDFIELD2113 (0x1<<3) // Reserved
17728 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2115 (0x1<<3) // Reserved
17733 #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_LN_OK (0x1<<0) // LANE OK status
17746 #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_RXVALID (0x1<<0) // rxvalid status output
17749 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_RESERVEDFIELD2121 (0x1<<0) // Reserved
17751 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1902_RESERVEDFIELD2122 (0x1<<1) // Reserved
17754 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1903_RESERVEDFIELD2123 (0x1<<0) // Reserved
17757 #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_OVR_EN (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
17759 #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
17764 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2124 (0x1<<0) // Reserved
17766 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2125 (0x1<<3) // Reserved
17768 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2126 (0x1<<4) // Reserved
17770 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2127 (0x1<<5) // Reserved
17773 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1905_RESERVEDFIELD2128 (0x1<<0) // Reserved
17775 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1905_RESERVEDFIELD2129 (0x1<<4) // Reserved
17778 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2130 (0x1<<0) // Reserved
17780 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2131 (0x1<<5) // Reserved
17782 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1906_RESERVEDFIELD2132 (0x1<<6) // Reserved
17785 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2133 (0x1<<0) // Reserved
17789 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2135 (0x1<<3) // Reserved
17792 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2136 (0x1<<0) // Reserved
17794 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2137 (0x1<<1) // Reserved
17796 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1908_RESERVEDFIELD2138 (0x1<<2) // Reserved
17799 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1909_RESERVEDFIELD2139 (0x1<<0) // Reserved
17804 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1910_RESERVEDFIELD2141 (0x1<<0) // Reserved
17813 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2145 (0x1<<6) // Reserved
17815 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2146 (0x1<<7) // Reserved
17818 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2147 (0x1<<0) // Reserved
17820 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2148 (0x1<<1) // Reserved
17824 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2150 (0x1<<4) // Reserved
17826 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2151 (0x1<<5) // Reserved
17828 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1912_RESERVEDFIELD2152 (0x1<<6) // Reserved
17837 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_RESERVEDFIELD2155 (0x1<<0) // Reserved
17839 #define PHY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1915_RESERVEDFIELD2156 (0x1<<1) // Reserved
17844 #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_LANE_ERR (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
17847 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1916_RESERVEDFIELD2157 (0x1<<0) // Reserved
17862 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1921_RESERVEDFIELD2163 (0x1<<0) // Reserved
17870 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1925_RESERVEDFIELD2167 (0x1<<0) // Reserved
17873 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1926_RESERVEDFIELD2168 (0x1<<0) // Reserved
17880 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1929_RESERVEDFIELD2171 (0x1<<0) // Reserved
17887 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1932_RESERVEDFIELD2174 (0x1<<0) // Reserved
17893 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2176 (0x1<<0) // Reserved
17895 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2177 (0x1<<1) // Reserved
17897 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2178 (0x1<<2) // Reserved
17899 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2179 (0x1<<3) // Reserved
17909 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1938_RESERVEDFIELD2183 (0x1<<0) // Reserved
17913 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8 (0x1<<0) // Binary-coded DLPF control input to the CDR
17916 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH (0x1<<0) // Indicates that DLPF control input to CDR is too high
17918 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW (0x1<<1) // Indicates that DLPF control input to CDR is too low
17920 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST (0x1<<2) // CDR loss of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
17923 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_LOCKED (0x1<<0) // CDR lock indicator. 1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
17947 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1947_RESERVEDFIELD2194 (0x1<<0) // Reserved
17957 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2199 (0x1<<0) // Reserved
17959 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2200 (0x1<<1) // Reserved
17961 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1951_RESERVEDFIELD2201 (0x1<<2) // Reserved
17987 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1961_RESERVEDFIELD2213 (0x1<<0) // Reserved
17991 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1963_RESERVEDFIELD2215 (0x1<<0) // Reserved
17994 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2216 (0x1<<0) // Reserved
17996 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1964_RESERVEDFIELD2217 (0x1<<1) // Reserved
18011 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2223 (0x1<<2) // Reserved
18018 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1968_RESERVEDFIELD2226 (0x1<<7) // Reserved
18023 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1969_RESERVEDFIELD2228 (0x1<<7) // Reserved
18034 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2232 (0x1<<0) // Reserved
18036 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1972_RESERVEDFIELD2233 (0x1<<1) // Reserved
18045 #define PHY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1977_RESERVEDFIELD2238 (0x1<<0) // Reserved
18051 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_RESERVEDFIELD2240 (0x1<<0) // Reserved
18053 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1979_RESERVEDFIELD2241 (0x1<<1) // Reserved
18078 #define PHY_NW_IP_REG_LN2_ANEG_CFG11_PSEUDO_SEL (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18081 #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_AUTONEG_RESTART (0x1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by rising edge of this signal. Not self clearing.
18086 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2253 (0x1<<4) // Reserved
18090 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1989_RESERVEDFIELD2255 (0x1<<7) // Reserved
18093 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1990_RESERVEDFIELD2256 (0x1<<0) // Reserved
18096 #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LP_AUTONEG_ABLE (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
18098 #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LINK_STATUS (0x1<<2) // Local link Status. When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
18100 #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_ABILITY (0x1<<3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
18102 #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_REMOTE_FAULT (0x1<<4) // Remote Fault
18104 #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_COMPLETE (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
18107 #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PAGE_RX (0x1<<0) // Page Received. To clear it, write 1 to it.
18109 #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_AN_LINK_GOOD (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
18111 #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PARALLEL_DET_FAULT (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
18113 #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_NP_LOADED (0x1<<3) // mr_np_loaded status.
18115 #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_RESERVEDFIELD2257 (0x1<<4) // Reserved
18117 #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_RESERVEDFIELD2258 (0x1<<5) // Reserved
18129 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_PAUSE (0x1<<2) // Pause advertised ability
18131 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ASM_DIR (0x1<<3) // Pause ASM_DIR advertised ability
18133 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_C2 (0x1<<4) // Reserved always 0
18135 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Remote Fault Local Device
18137 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Next Page
18143 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // 1000Base-KX technology advertised ability
18145 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // 10GBase-KX4 technology advertised ability
18147 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // 10GBase-KR technology advertised ability
18149 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // 40GBase-KR4 technology advertised ability
18151 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // 40GBase-CR4 technology advertised ability
18153 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // 100GBase-CR10 technology advertised ability
18155 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // 100GBase-KP4 technology advertised ability
18157 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // 100GBase-KR4 technology advertised ability
18160 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // 100GBase-CR4 technology advertised ability
18162 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
18164 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
18172 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // base page bit F0. It advertises FEC ability
18174 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // base page bit F1. It requests FEC to be turned on when supported at the both ends of link
18176 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
18178 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
18181 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_KR (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
18183 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_CR (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
18185 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
18187 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
18189 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
18191 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18193 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_REQ (0x1<<6) // Extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18195 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_REQ (0x1<<7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18201 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2260 (0x1<<3) // Reserved
18203 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2261 (0x1<<4) // Reserved
18205 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2262 (0x1<<5) // Reserved
18207 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2263 (0x1<<7) // Reserved
18214 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2264 (0x1<<0) // Reserved
18216 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2265 (0x1<<1) // Reserved
18218 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2266 (0x1<<2) // Reserved
18220 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2267 (0x1<<3) // Reserved
18222 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2268 (0x1<<4) // Reserved
18224 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2269 (0x1<<5) // Reserved
18226 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2270 (0x1<<6) // Reserved
18228 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2271 (0x1<<7) // Reserved
18231 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2272 (0x1<<0) // Reserved
18233 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2273 (0x1<<1) // Reserved
18235 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2274 (0x1<<2) // Reserved
18237 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2275 (0x1<<3) // Reserved
18239 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2276 (0x1<<4) // Reserved
18241 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2277 (0x1<<5) // Reserved
18243 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2278 (0x1<<6) // Reserved
18253 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_PAUSE (0x1<<2) // Link partner Pause advertised ability
18255 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ASM_DIR (0x1<<3) // Link partner Pause ASM_DIR advertised ability
18257 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_C2 (0x1<<4) // Link partner C2 field always 0
18259 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Link partner Remote Fault
18261 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ACK (0x1<<6) // Link partner Acknowledge always 0
18263 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Link partner Next Page
18269 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // Link partner 1000Base-KX technology advertised ability
18271 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
18273 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // Link partner 10GBase-KR technology advertised ability
18275 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
18277 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
18279 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
18281 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
18283 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
18286 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
18288 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
18290 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
18298 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // Link partner base page bit F0. It advertises FEC ability
18300 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when supported at the both ends of link
18302 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
18304 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
18307 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_KR (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
18309 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_CR (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
18311 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
18313 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
18315 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Link partner extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
18317 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Link partner extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18319 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_REQ (0x1<<6) // Link partner extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18321 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_REQ (0x1<<7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
18327 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2280 (0x1<<3) // Reserved
18329 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2281 (0x1<<4) // Reserved
18331 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2282 (0x1<<5) // Reserved
18333 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2283 (0x1<<7) // Reserved
18340 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2284 (0x1<<0) // Reserved
18342 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2285 (0x1<<1) // Reserved
18344 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2286 (0x1<<2) // Reserved
18346 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2287 (0x1<<3) // Reserved
18348 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2288 (0x1<<4) // Reserved
18350 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2289 (0x1<<5) // Reserved
18352 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2290 (0x1<<6) // Reserved
18354 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2291 (0x1<<7) // Reserved
18357 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2292 (0x1<<0) // Reserved
18359 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2293 (0x1<<1) // Reserved
18361 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2294 (0x1<<2) // Reserved
18363 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2295 (0x1<<3) // Reserved
18365 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2296 (0x1<<4) // Reserved
18367 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2297 (0x1<<5) // Reserved
18369 #define PHY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2298 (0x1<<6) // Reserved
18372 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is 1.
18374 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4 (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when status0.an_link_good is 1.
18376 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is 1.
18378 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4 (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good is 1.
18380 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4 (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good is 1.
18382 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10 (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good is 1.
18384 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4 (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good is 1.
18386 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4 (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good is 1.
18389 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4 (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good is 1.
18391 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when status0.an_link_good is 1.
18393 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_good is 1.
18395 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is 1.
18397 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good is 1.
18399 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2 (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good is 1.
18401 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2 (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good is 1.
18404 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_RS (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_good is 1.
18406 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_FC (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when status0.an_link_good is 1.
18409 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_RX (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
18411 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_TX (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when status0.an_link_good is 1.
18414 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_F896 (0x1<<0) // Resolution result for EEE. It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherwise. It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
18417 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_1G_KX (0x1<<0) // link_status for 1000Base-KX
18419 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KX4 (0x1<<1) // link_status for 10GBase-KX4
18421 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KR (0x1<<2) // link_status for 10GBase-KR
18423 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_KR4 (0x1<<3) // link_status for 40GBase-KR4
18425 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_CR4 (0x1<<4) // link_status for 40GBase-CR4
18427 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_CR10 (0x1<<5) // link_status for 100GBase-CR10
18429 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KP4 (0x1<<6) // link_status for 100GBase-KP4
18431 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KR4 (0x1<<7) // link_status for 100GBase-KR4
18434 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_100G_CR4 (0x1<<0) // link_status for 100GBase-CR4
18436 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_GR (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
18438 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_KR (0x1<<3) // link_status for 25GBase-KR
18440 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_CR (0x1<<4) // link_status for 25GBase-CR4
18442 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_KR2 (0x1<<5) // link_status for 50GBase-KR2
18444 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_CR2 (0x1<<6) // link_status for 50GBase-CR2
18449 #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2007_RESERVEDFIELD2300 (0x1<<2) // Reserved
18452 #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2008_RESERVEDFIELD2301 (0x1<<0) // Reserved
18455 #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2009_RESERVEDFIELD2302 (0x1<<0) // Reserved
18458 #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2303 (0x1<<0) // Reserved
18462 #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2305 (0x1<<3) // Reserved
18464 #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2306 (0x1<<4) // Reserved
18467 #define PHY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2011_RESERVEDFIELD2307 (0x1<<0) // Reserved
18474 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2014_RESERVEDFIELD2311 (0x1<<6) // Reserved
18483 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2315 (0x1<<0) // Reserved
18487 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2317 (0x1<<3) // Reserved
18490 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2018_RESERVEDFIELD2318 (0x1<<0) // Reserved
18535 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2027_RESERVEDFIELD2336 (0x1<<0) // Reserved
18537 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2027_RESERVEDFIELD2337 (0x1<<2) // Reserved
18551 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2344 (0x1<<6) // Reserved
18553 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2345 (0x1<<7) // Reserved
18570 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2038_RESERVEDFIELD2354 (0x1<<1) // Reserved
18586 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2360 (0x1<<6) // Reserved
18588 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2043_RESERVEDFIELD2361 (0x1<<7) // Reserved
18591 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2362 (0x1<<0) // Reserved
18593 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2044_RESERVEDFIELD2363 (0x1<<1) // Reserved
18602 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2045_RESERVEDFIELD2367 (0x1<<6) // Reserved
18616 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2051_RESERVEDFIELD2374 (0x1<<4) // Reserved
18633 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2054_RESERVEDFIELD2378 (0x1<<7) // Reserved
18636 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2379 (0x1<<0) // Reserved
18638 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2055_RESERVEDFIELD2380 (0x1<<1) // Reserved
18647 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2056_RESERVEDFIELD2384 (0x1<<6) // Reserved
18653 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2386 (0x1<<0) // Reserved
18655 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2387 (0x1<<1) // Reserved
18657 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2388 (0x1<<2) // Reserved
18659 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2389 (0x1<<3) // Reserved
18792 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2084_RESERVEDFIELD2441 (0x1<<7) // Reserved
18795 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2442 (0x1<<0) // Reserved
18797 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2085_RESERVEDFIELD2443 (0x1<<1) // Reserved
18806 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2086_RESERVEDFIELD2447 (0x1<<6) // Reserved
18828 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2089_RESERVEDFIELD2452 (0x1<<7) // Reserved
18831 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2453 (0x1<<0) // Reserved
18833 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2090_RESERVEDFIELD2454 (0x1<<1) // Reserved
18842 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2091_RESERVEDFIELD2458 (0x1<<6) // Reserved
18865 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2098_RESERVEDFIELD2466 (0x1<<7) // Reserved
18868 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2467 (0x1<<0) // Reserved
18870 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2099_RESERVEDFIELD2468 (0x1<<1) // Reserved
18879 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2100_RESERVEDFIELD2472 (0x1<<6) // Reserved
18887 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2102_RESERVEDFIELD2475 (0x1<<4) // Reserved
18897 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2478 (0x1<<0) // Reserved
18899 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2105_RESERVEDFIELD2479 (0x1<<1) // Reserved
18908 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2106_RESERVEDFIELD2483 (0x1<<6) // Reserved
18913 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2486 (0x1<<0) // Reserved
18915 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2109_RESERVEDFIELD2487 (0x1<<1) // Reserved
18924 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2110_RESERVEDFIELD2491 (0x1<<6) // Reserved
18932 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2497 (0x1<<0) // Reserved
18934 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2116_RESERVEDFIELD2498 (0x1<<1) // Reserved
18937 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2499 (0x1<<0) // Reserved
18939 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2117_RESERVEDFIELD2500 (0x1<<1) // Reserved
18942 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2118_RESERVEDFIELD2501 (0x1<<6) // Reserved
18984 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2139_RESERVEDFIELD2518 (0x1<<0) // Reserved
18991 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2141_RESERVEDFIELD2520 (0x1<<0) // Reserved
18999 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2523 (0x1<<0) // Reserved
19001 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2524 (0x1<<1) // Reserved
19005 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2143_RESERVEDFIELD2526 (0x1<<5) // Reserved
19010 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2528 (0x1<<0) // Reserved
19012 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2529 (0x1<<1) // Reserved
19016 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2144_RESERVEDFIELD2531 (0x1<<4) // Reserved
19044 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_REQ (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. Set to 0 once ack is 1.
19047 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_ACK (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
19059 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2543 (0x1<<0) // Reserved
19061 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2151_RESERVEDFIELD2544 (0x1<<1) // Reserved
19067 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2545 (0x1<<0) // Reserved
19069 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2546 (0x1<<1) // Reserved
19073 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2152_RESERVEDFIELD2548 (0x1<<5) // Reserved
19078 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2550 (0x1<<0) // Reserved
19080 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2551 (0x1<<1) // Reserved
19084 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2153_RESERVEDFIELD2553 (0x1<<4) // Reserved
19113 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2160_RESERVEDFIELD2564 (0x1<<0) // Reserved
19116 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2161_RESERVEDFIELD2565 (0x1<<0) // Reserved
19119 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2566 (0x1<<0) // Reserved
19121 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2162_RESERVEDFIELD2567 (0x1<<1) // Reserved
19142 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2165_RESERVEDFIELD2576 (0x1<<6) // Reserved
19145 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2166_RESERVEDFIELD2577 (0x1<<0) // Reserved
19151 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2168_RESERVEDFIELD2580 (0x1<<0) // Reserved
19157 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2170_RESERVEDFIELD2583 (0x1<<0) // Reserved
19162 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2171_RESERVEDFIELD2585 (0x1<<7) // Reserved
19165 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_REQ (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
19169 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD2586 (0x1<<6) // Reserved
19171 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL (0x1<<7) // Set it to 1 when changing DFE tap values
19176 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2172_RESERVEDFIELD2588 (0x1<<4) // Reserved
19191 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_ACK (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
19193 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2595 (0x1<<1) // Reserved
19195 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2596 (0x1<<2) // Reserved
19197 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2597 (0x1<<3) // Reserved
19200 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
19202 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
19204 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
19206 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
19208 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP2_EN (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19210 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP3_EN (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19212 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP4_EN (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19214 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP5_EN (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19219 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19224 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19229 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19234 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19239 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19244 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19249 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19254 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19259 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19264 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19269 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19274 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19279 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19284 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19289 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19294 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19299 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19304 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19309 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19314 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19319 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19324 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19329 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19334 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
19337 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2598 (0x1<<0) // Reserved
19339 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2599 (0x1<<1) // Reserved
19341 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2600 (0x1<<2) // Reserved
19343 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2601 (0x1<<3) // Reserved
19345 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2602 (0x1<<4) // Reserved
19347 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2603 (0x1<<5) // Reserved
19349 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2604 (0x1<<6) // Reserved
19351 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2605 (0x1<<7) // Reserved
19408 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2624 (0x1<<0) // Reserved
19410 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2625 (0x1<<1) // Reserved
19412 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2626 (0x1<<2) // Reserved
19414 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2627 (0x1<<3) // Reserved
19416 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2628 (0x1<<4) // Reserved
19418 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2629 (0x1<<5) // Reserved
19420 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2630 (0x1<<6) // Reserved
19422 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2631 (0x1<<7) // Reserved
19425 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2632 (0x1<<0) // Reserved
19427 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2633 (0x1<<1) // Reserved
19429 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2199_RESERVEDFIELD2634 (0x1<<2) // Reserved
19432 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2635 (0x1<<0) // Reserved
19434 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2636 (0x1<<1) // Reserved
19436 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2637 (0x1<<2) // Reserved
19438 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2638 (0x1<<3) // Reserved
19440 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2639 (0x1<<4) // Reserved
19442 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2640 (0x1<<5) // Reserved
19444 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2641 (0x1<<6) // Reserved
19446 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2642 (0x1<<7) // Reserved
19450 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2202_RESERVEDFIELD2644 (0x1<<0) // Reserved
19455 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2646 (0x1<<5) // Reserved
19457 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2203_RESERVEDFIELD2647 (0x1<<6) // Reserved
19460 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2648 (0x1<<0) // Reserved
19462 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2204_RESERVEDFIELD2649 (0x1<<1) // Reserved
19469 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2652 (0x1<<0) // Reserved
19471 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2207_RESERVEDFIELD2653 (0x1<<1) // Reserved
19482 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2658 (0x1<<0) // Reserved
19484 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2659 (0x1<<1) // Reserved
19486 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2212_RESERVEDFIELD2660 (0x1<<2) // Reserved
19489 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2213_RESERVEDFIELD2661 (0x1<<0) // Reserved
19523 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2227_RESERVEDFIELD2679 (0x1<<0) // Reserved
19594 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2716 (0x1<<0) // Reserved
19596 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2264_RESERVEDFIELD2717 (0x1<<1) // Reserved
19601 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2267_RESERVEDFIELD2720 (0x1<<0) // Reserved
19614 #define PHY_NW_IP_REG_LN2_DFE_RXCLK_RESERVEDREGISTER2278_RESERVEDFIELD2731 (0x1<<0) // Reserved
19617 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL (0x1<<0) // Enables analog LOS offset calibration circuits.
19626 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_EN (0x1<<0) // Enables the run-length detection digital LOS filter.
19630 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
19632 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
19643 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_EN (0x1<<0) // Enables the digital deglitching filter.
19646 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2281_RESERVEDFIELD2734 (0x1<<0) // Reserved
19655 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
19657 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE (0x1<<4) // Override value for the LOS output of the digital filtering logic.
19660 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2286_RESERVEDFIELD2739 (0x1<<0) // Reserved
19662 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2286_RESERVEDFIELD2740 (0x1<<4) // Reserved
19667 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2287_RESERVEDFIELD2742 (0x1<<6) // Reserved
19672 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2288_RESERVEDFIELD2744 (0x1<<6) // Reserved
19675 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2745 (0x1<<0) // Reserved
19679 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2289_RESERVEDFIELD2747 (0x1<<4) // Reserved
19682 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2748 (0x1<<0) // Reserved
19684 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2749 (0x1<<1) // Reserved
19686 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2750 (0x1<<2) // Reserved
19693 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2293_RESERVEDFIELD2754 (0x1<<0) // Reserved
19696 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2755 (0x1<<0) // Reserved
19698 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2294_RESERVEDFIELD2756 (0x1<<1) // Reserved
19707 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2759 (0x1<<0) // Reserved
19709 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2297_RESERVEDFIELD2760 (0x1<<1) // Reserved
19712 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_READY (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
19714 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_RESERVEDFIELD2761 (0x1<<1) // Reserved
19716 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS (0x1<<2) // The filtered LOS signal value.
19718 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_RAW (0x1<<3) // The unfiltered LOS signal value.
19720 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_NO_EII (0x1<<4) // The filtered LOS signal value before EII override logic.
19722 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_RESERVEDFIELD2762 (0x1<<5) // Reserved
19725 #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2298_RESERVEDFIELD2763 (0x1<<0) // Reserved
19732 #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2301_RESERVEDFIELD2766 (0x1<<0) // Reserved
19742 #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2305_RESERVEDFIELD2771 (0x1<<0) // Reserved
19770 #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2315_RESERVEDFIELD2783 (0x1<<0) // Reserved
19783 #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2324_RESERVEDFIELD2792 (0x1<<0) // Reserved
19786 #define PHY_NW_IP_REG_LN2_GCFSM2_RESERVEDREGISTER2325_RESERVEDFIELD2793 (0x1<<0) // Reserved
19792 #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_EN (0x1<<0) // Enables BIST Tx data generation.
19794 #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to transmitted: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x9 � MAC Tx data
19801 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_MODE (0x3<<0) // Controls what type of error injection is used: 0x0 � None 0x1 � Single cycle error 0x2 � Timer based
19837 #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_EN (0x1<<0) // Enables BIST Rx data checking.
19839 #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
19841 #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_CLEAR_BER (0x1<<5) // Clears the bit error counter.
19843 #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_STOP_ERROR_COUNT (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER data coherently.
19845 #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be inaccurate.
19848 #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_STATE (0x7<<0) // State of the BIST checker: 0x0 � Off 0x1 � Searching for pattern 0x2 � Waiting for pattern lock conditions 0x3 � Pattern lock acquired 0x4 � Pattern lock lost
19850 #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_PATTERN_DET (0xf<<3) // Indicates the pattern detected: 0x0 � No pattern detected 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP
19867 #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
19896 #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_AC_COUPLED (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
19899 #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_EN (0x1<<0) // Enables turning on the divided rxclk output
19902 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_RESERVEDFIELD2800 (0x1<<0) // Reserved
19904 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2331_RESERVEDFIELD2801 (0x1<<1) // Reserved
19907 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2802 (0x1<<0) // Reserved
19909 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2803 (0x1<<1) // Reserved
19911 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2804 (0x1<<2) // Reserved
19913 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2805 (0x1<<3) // Reserved
19915 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2806 (0x1<<4) // Reserved
19917 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2807 (0x1<<5) // Reserved
19920 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2808 (0x1<<0) // Reserved
19922 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2809 (0x1<<1) // Reserved
19924 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2810 (0x1<<2) // Reserved
19926 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2811 (0x1<<3) // Reserved
19929 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2812 (0x1<<0) // Reserved
19931 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2813 (0x1<<1) // Reserved
19933 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2814 (0x1<<2) // Reserved
19935 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2815 (0x1<<3) // Reserved
19937 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2816 (0x1<<4) // Reserved
19939 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2817 (0x1<<5) // Reserved
19941 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2818 (0x1<<6) // Reserved
19943 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2819 (0x1<<7) // Reserved
19946 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2820 (0x1<<0) // Reserved
19948 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2821 (0x1<<1) // Reserved
19950 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2822 (0x1<<2) // Reserved
19952 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2823 (0x1<<3) // Reserved
19957 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2825 (0x1<<0) // Reserved
19959 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2826 (0x1<<1) // Reserved
19961 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2336_RESERVEDFIELD2827 (0x1<<2) // Reserved
19970 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2339_RESERVEDFIELD2830 (0x1<<0) // Reserved
19976 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_RESERVEDFIELD2833 (0x1<<0) // Reserved
19978 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2341_RESERVEDFIELD2834 (0x1<<1) // Reserved
19981 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_RESERVEDFIELD2835 (0x1<<0) // Reserved
19983 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2342_RESERVEDFIELD2836 (0x1<<1) // Reserved
19986 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_RESERVEDFIELD2837 (0x1<<0) // Reserved
19988 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2343_RESERVEDFIELD2838 (0x1<<1) // Reserved
19991 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2344_RESERVEDFIELD2839 (0x1<<0) // Reserved
20003 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
20005 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD2842 (0x1<<2) // Reserved
20008 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
20010 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD2843 (0x1<<2) // Reserved
20013 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
20015 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
20022 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
20024 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
20026 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
20028 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
20030 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2846 (0x1<<4) // Reserved
20032 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2847 (0x1<<5) // Reserved
20034 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2848 (0x1<<6) // Reserved
20036 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD2849 (0x1<<7) // Reserved
20039 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
20041 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
20048 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2345_RESERVEDFIELD2852 (0x1<<0) // Reserved
20051 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
20053 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
20055 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2853 (0x1<<2) // Reserved
20057 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2854 (0x1<<3) // Reserved
20060 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2855 (0x1<<0) // Reserved
20062 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2856 (0x1<<1) // Reserved
20064 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2857 (0x1<<2) // Reserved
20066 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2858 (0x1<<3) // Reserved
20068 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2859 (0x1<<4) // Reserved
20070 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2860 (0x1<<5) // Reserved
20072 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2861 (0x1<<6) // Reserved
20074 #define PHY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2862 (0x1<<7) // Reserved
20077 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP1_EN (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
20079 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP2_EN (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
20081 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP3_EN (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
20083 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP4_EN (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
20085 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP5_EN (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
20088 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_METHOD_SEL (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
20091 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 1
20093 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2863 (0x1<<1) // Reserved
20095 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2864 (0x1<<2) // Reserved
20097 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2865 (0x1<<3) // Reserved
20100 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 2
20102 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2866 (0x1<<1) // Reserved
20104 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2867 (0x1<<2) // Reserved
20106 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2868 (0x1<<3) // Reserved
20109 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 3
20111 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2869 (0x1<<1) // Reserved
20113 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2870 (0x1<<2) // Reserved
20115 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2871 (0x1<<3) // Reserved
20118 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 4
20120 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2872 (0x1<<1) // Reserved
20122 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2873 (0x1<<2) // Reserved
20124 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2874 (0x1<<3) // Reserved
20127 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 5
20129 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2875 (0x1<<1) // Reserved
20131 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2876 (0x1<<2) // Reserved
20133 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2877 (0x1<<3) // Reserved
20136 #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_EN (0x1<<0) // Enables continuous background adaptation
20138 #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD2878 (0x1<<1) // Reserved
20174 #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2895 (0x1<<0) // Reserved
20176 #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RX_CTRL_DIS (0x1<<1) // Disables the firmware rx_ctrl MSM
20178 #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2896 (0x1<<2) // Reserved
20180 #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2897 (0x1<<3) // Reserved
20191 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING (0x1<<0) // Starts link training procedure when asserted. This is an 802.3 defined variable.
20193 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion. This is an 802.3 defined variable.
20195 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_SIGNAL_DETECT (0x1<<2) // Output corresponding to link training signal detect variable. Should be set when link training has completed successfully.
20197 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_CLEAR (0x1<<3) // Synchronous reset for LT Tx block.
20203 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_WAIT_TIME_8 (0x1<<0) // Same as above.
20206 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_FRAME_LOCK (0x1<<0) // Input to LTSM that receiver has acquired frame lock. This value should be taken from the corresponding LT Rx register. This an 802.3 defined variable.
20208 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_RX_TRAINED (0x1<<1) // Input to LTSM indicating that the local receiver has completed training. This is an 802.3 defined variable.
20210 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_REMOTE_RX_READY (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready. This value should be taken from the corresponding LT Rx registers. This is an 802.3 defined variable.
20213 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_FAIL (0x1<<0) // Output from LTSM indicating that link training has failed. This is an 802.3 defined variable.
20215 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING (0x1<<1) // Output from LTSM indicating that link training is in progress. This is an 802.3 defined variable.
20217 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_SIGNAL_DETECT (0x1<<2) // Output from LTSM indicating that link training is complete and successful. This is an 802.3 defined variable. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
20219 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
20235 #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE (0x1<<6) // Coefficient update initialize field.
20237 #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET (0x1<<7) // Coefficient update preset field.
20246 #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY (0x1<<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM output of corresponding variable.
20249 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_CURRENT (0x7<<0) // Current state of LTSM. 0x0 � INITIALIZE 0x1 � SEND_TRAINING 0x2 � TRAIN_REMOTE 0x3 � TRAIN_LOCAL 0x4 � S7 0x5 � TRAINING_FAILURE 0x6 � LINK_READY 0x7 � SEND_DATA
20259 #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_CLEAR (0x1<<0) // Synchronous reset for LT Rx block.
20261 #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_TRAINING (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corresponding LTSM output.
20268 #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_UPDATE (0x1<<0) // Assertion indicates that PRBS status information has been updated.
20270 #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_LOCK (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
20277 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_CLEAR_COUNT (0x1<<0) // Clears both the absolute and erroneous frame counters.
20280 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_FRAME_LOCK (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
20293 #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE (0x1<<6) // Received coefficient update initialize field.
20295 #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET (0x1<<7) // Received coefficient update preset field.
20304 #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_LOCAL_RX_READY (0x1<<6) // Received status report field to indicate local receiver is ready.
20306 #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_DME_ERROR (0x1<<7) // Indicates differential manchester decoding error. Not sticky.
20309 #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN (0x1<<0) // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
20311 #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
20313 #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
20315 #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
20335 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_RESERVEDFIELD2905 (0x1<<0) // Reserved
20337 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2370_RESERVEDFIELD2906 (0x1<<1) // Reserved
20340 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2371_RESERVEDFIELD2907 (0x1<<2) // Reserved
20350 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2373_RESERVEDFIELD2911 (0x1<<6) // Reserved
20363 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2376_RESERVEDFIELD2916 (0x1<<2) // Reserved
20378 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2922 (0x1<<3) // Reserved
20380 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2923 (0x1<<4) // Reserved
20389 #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN (0x1<<0) // Enables register control of TX data path mux in DPL
20393 #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_TXPOLARITY (0x1<<4) // TX data polarity control
20395 #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
20398 #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
20400 #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
20405 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2382_RESERVEDFIELD2927 (0x1<<3) // Reserved
20410 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2929 (0x1<<3) // Reserved
20415 #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_LN_OK (0x1<<0) // LANE OK status
20428 #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_RXVALID (0x1<<0) // rxvalid status output
20431 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_RESERVEDFIELD2935 (0x1<<0) // Reserved
20433 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2386_RESERVEDFIELD2936 (0x1<<1) // Reserved
20436 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2387_RESERVEDFIELD2937 (0x1<<0) // Reserved
20439 #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_OVR_EN (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
20441 #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH (0x7<<1) // lnX_data_width_i override value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
20446 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2938 (0x1<<0) // Reserved
20448 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2939 (0x1<<3) // Reserved
20450 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2940 (0x1<<4) // Reserved
20452 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2941 (0x1<<5) // Reserved
20455 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2389_RESERVEDFIELD2942 (0x1<<0) // Reserved
20457 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2389_RESERVEDFIELD2943 (0x1<<4) // Reserved
20460 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2944 (0x1<<0) // Reserved
20462 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2945 (0x1<<5) // Reserved
20464 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2390_RESERVEDFIELD2946 (0x1<<6) // Reserved
20467 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2947 (0x1<<0) // Reserved
20471 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2949 (0x1<<3) // Reserved
20474 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2950 (0x1<<0) // Reserved
20476 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2951 (0x1<<1) // Reserved
20478 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2392_RESERVEDFIELD2952 (0x1<<2) // Reserved
20481 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2393_RESERVEDFIELD2953 (0x1<<0) // Reserved
20486 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2394_RESERVEDFIELD2955 (0x1<<0) // Reserved
20495 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2959 (0x1<<6) // Reserved
20497 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2960 (0x1<<7) // Reserved
20500 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2961 (0x1<<0) // Reserved
20502 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2962 (0x1<<1) // Reserved
20506 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2964 (0x1<<4) // Reserved
20508 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2965 (0x1<<5) // Reserved
20510 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2396_RESERVEDFIELD2966 (0x1<<6) // Reserved
20519 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_RESERVEDFIELD2969 (0x1<<0) // Reserved
20521 #define PHY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2399_RESERVEDFIELD2970 (0x1<<1) // Reserved
20526 #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_LANE_ERR (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
20529 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2400_RESERVEDFIELD2971 (0x1<<0) // Reserved
20544 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2405_RESERVEDFIELD2977 (0x1<<0) // Reserved
20552 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2409_RESERVEDFIELD2981 (0x1<<0) // Reserved
20555 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2410_RESERVEDFIELD2982 (0x1<<0) // Reserved
20562 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2413_RESERVEDFIELD2985 (0x1<<0) // Reserved
20569 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2416_RESERVEDFIELD2988 (0x1<<0) // Reserved
20575 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2990 (0x1<<0) // Reserved
20577 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2991 (0x1<<1) // Reserved
20579 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2992 (0x1<<2) // Reserved
20581 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2993 (0x1<<3) // Reserved
20591 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2422_RESERVEDFIELD2997 (0x1<<0) // Reserved
20595 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8 (0x1<<0) // Binary-coded DLPF control input to the CDR
20598 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH (0x1<<0) // Indicates that DLPF control input to CDR is too high
20600 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW (0x1<<1) // Indicates that DLPF control input to CDR is too low
20602 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST (0x1<<2) // CDR loss of lock indicator. 1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
20605 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_LOCKED (0x1<<0) // CDR lock indicator. 1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
20629 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2431_RESERVEDFIELD3008 (0x1<<0) // Reserved
20639 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3013 (0x1<<0) // Reserved
20641 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3014 (0x1<<1) // Reserved
20643 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2435_RESERVEDFIELD3015 (0x1<<2) // Reserved
20669 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2445_RESERVEDFIELD3027 (0x1<<0) // Reserved
20673 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2447_RESERVEDFIELD3029 (0x1<<0) // Reserved
20676 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3030 (0x1<<0) // Reserved
20678 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2448_RESERVEDFIELD3031 (0x1<<1) // Reserved
20693 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3037 (0x1<<2) // Reserved
20700 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2452_RESERVEDFIELD3040 (0x1<<7) // Reserved
20705 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2453_RESERVEDFIELD3042 (0x1<<7) // Reserved
20716 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3046 (0x1<<0) // Reserved
20718 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2456_RESERVEDFIELD3047 (0x1<<1) // Reserved
20727 #define PHY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2461_RESERVEDFIELD3052 (0x1<<0) // Reserved
20733 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_RESERVEDFIELD3054 (0x1<<0) // Reserved
20735 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2463_RESERVEDFIELD3055 (0x1<<1) // Reserved
20760 #define PHY_NW_IP_REG_LN3_ANEG_CFG11_PSEUDO_SEL (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
20763 #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_AUTONEG_RESTART (0x1<<0) // Restarts AN that is already in progress or otherwise completed. Reset is triggered by rising edge of this signal. Not self clearing.
20768 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3067 (0x1<<4) // Reserved
20772 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2473_RESERVEDFIELD3069 (0x1<<7) // Reserved
20775 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2474_RESERVEDFIELD3070 (0x1<<0) // Reserved
20778 #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LP_AUTONEG_ABLE (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
20780 #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LINK_STATUS (0x1<<2) // Local link Status. When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
20782 #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_ABILITY (0x1<<3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
20784 #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_REMOTE_FAULT (0x1<<4) // Remote Fault
20786 #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_COMPLETE (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
20789 #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PAGE_RX (0x1<<0) // Page Received. To clear it, write 1 to it.
20791 #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_AN_LINK_GOOD (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
20793 #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PARALLEL_DET_FAULT (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
20795 #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_NP_LOADED (0x1<<3) // mr_np_loaded status.
20797 #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_RESERVEDFIELD3071 (0x1<<4) // Reserved
20799 #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_RESERVEDFIELD3072 (0x1<<5) // Reserved
20811 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_PAUSE (0x1<<2) // Pause advertised ability
20813 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ASM_DIR (0x1<<3) // Pause ASM_DIR advertised ability
20815 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_C2 (0x1<<4) // Reserved always 0
20817 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Remote Fault Local Device
20819 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Next Page
20825 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // 1000Base-KX technology advertised ability
20827 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // 10GBase-KX4 technology advertised ability
20829 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // 10GBase-KR technology advertised ability
20831 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // 40GBase-KR4 technology advertised ability
20833 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // 40GBase-CR4 technology advertised ability
20835 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // 100GBase-CR10 technology advertised ability
20837 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // 100GBase-KP4 technology advertised ability
20839 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // 100GBase-KR4 technology advertised ability
20842 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // 100GBase-CR4 technology advertised ability
20844 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
20846 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
20854 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // base page bit F0. It advertises FEC ability
20856 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // base page bit F1. It requests FEC to be turned on when supported at the both ends of link
20858 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
20860 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
20863 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_KR (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
20865 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_CR (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
20867 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
20869 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
20871 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
20873 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
20875 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_REQ (0x1<<6) // Extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
20877 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_REQ (0x1<<7) // Extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
20883 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3074 (0x1<<3) // Reserved
20885 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3075 (0x1<<4) // Reserved
20887 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3076 (0x1<<5) // Reserved
20889 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3077 (0x1<<7) // Reserved
20896 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3078 (0x1<<0) // Reserved
20898 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3079 (0x1<<1) // Reserved
20900 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3080 (0x1<<2) // Reserved
20902 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3081 (0x1<<3) // Reserved
20904 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3082 (0x1<<4) // Reserved
20906 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3083 (0x1<<5) // Reserved
20908 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3084 (0x1<<6) // Reserved
20910 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3085 (0x1<<7) // Reserved
20913 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3086 (0x1<<0) // Reserved
20915 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3087 (0x1<<1) // Reserved
20917 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3088 (0x1<<2) // Reserved
20919 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3089 (0x1<<3) // Reserved
20921 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3090 (0x1<<4) // Reserved
20923 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3091 (0x1<<5) // Reserved
20925 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3092 (0x1<<6) // Reserved
20935 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_PAUSE (0x1<<2) // Link partner Pause advertised ability
20937 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ASM_DIR (0x1<<3) // Link partner Pause ASM_DIR advertised ability
20939 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_C2 (0x1<<4) // Link partner C2 field always 0
20941 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_REMOTE_FAULT (0x1<<5) // Link partner Remote Fault
20943 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ACK (0x1<<6) // Link partner Acknowledge always 0
20945 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_NEXT_PAGE (0x1<<7) // Link partner Next Page
20951 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX (0x1<<0) // Link partner 1000Base-KX technology advertised ability
20953 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4 (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
20955 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR (0x1<<2) // Link partner 10GBase-KR technology advertised ability
20957 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4 (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
20959 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4 (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
20961 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10 (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
20963 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4 (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
20965 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4 (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
20968 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4 (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
20970 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A9 in base page.
20972 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. For prior versions, it corresponds to A10 in base page.
20980 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY (0x1<<0) // Link partner base page bit F0. It advertises FEC ability
20982 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_REQ (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when supported at the both ends of link
20984 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A23 in base page.
20986 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IEEE 802.3by. For prior versions, it corresponds to A24 in base page.
20989 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_KR (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
20991 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_CR (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
20993 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_KR2 (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
20995 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_CR2 (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
20997 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_ABILITY (0x1<<4) // Link partner extended advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
20999 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_ABILITY (0x1<<5) // Link partner extended advertised FEC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21001 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_REQ (0x1<<6) // Link partner extended advertised FEC field 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21003 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_REQ (0x1<<7) // Link partner extended advertised FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
21009 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3094 (0x1<<3) // Reserved
21011 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3095 (0x1<<4) // Reserved
21013 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3096 (0x1<<5) // Reserved
21015 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3097 (0x1<<7) // Reserved
21022 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3098 (0x1<<0) // Reserved
21024 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3099 (0x1<<1) // Reserved
21026 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3100 (0x1<<2) // Reserved
21028 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3101 (0x1<<3) // Reserved
21030 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3102 (0x1<<4) // Reserved
21032 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3103 (0x1<<5) // Reserved
21034 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3104 (0x1<<6) // Reserved
21036 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3105 (0x1<<7) // Reserved
21039 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3106 (0x1<<0) // Reserved
21041 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3107 (0x1<<1) // Reserved
21043 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3108 (0x1<<2) // Reserved
21045 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3109 (0x1<<3) // Reserved
21047 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3110 (0x1<<4) // Reserved
21049 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3111 (0x1<<5) // Reserved
21051 #define PHY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3112 (0x1<<6) // Reserved
21054 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX (0x1<<0) // Resolution result for 1000Base-KX. It is valid when status0.an_link_good is 1.
21056 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4 (0x1<<1) // Resolution result for 10GBase-KX4. It is valid when status0.an_link_good is 1.
21058 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR (0x1<<2) // Resolution result for 10GBase-KR. It is valid when status0.an_link_good is 1.
21060 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4 (0x1<<3) // Resolution result for 40GBase-KR4. It is valid when status0.an_link_good is 1.
21062 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4 (0x1<<4) // Resolution result for 40GBase-CR4. It is valid when status0.an_link_good is 1.
21064 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10 (0x1<<5) // Resolution result for 100GBase-CR10. It is valid when status0.an_link_good is 1.
21066 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4 (0x1<<6) // Resolution result for 100GBase-KP4. It is valid when status0.an_link_good is 1.
21068 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4 (0x1<<7) // Resolution result for 100GBase-KR4. It is valid when status0.an_link_good is 1.
21071 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4 (0x1<<0) // Resolution result for 100GBase-CR4. It is valid when status0.an_link_good is 1.
21073 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is valid when status0.an_link_good is 1.
21075 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is valid when status0.an_link_good is 1.
21077 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR (0x1<<3) // Resolution result for 25GBase-KR. It is valid when status0.an_link_good is 1.
21079 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR (0x1<<4) // Resolution result for 25GBase-CR4. It is valid when status0.an_link_good is 1.
21081 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2 (0x1<<5) // Resolution result for 50GBase-KR2. It is valid when status0.an_link_good is 1.
21083 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2 (0x1<<6) // Resolution result for 50GBase-CR2. It is valid when status0.an_link_good is 1.
21086 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_RS (0x1<<0) // Resolution result for Reed-Solomon FEC. It is valid when status0.an_link_good is 1.
21088 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_FC (0x1<<1) // Resolution result for Firecode base page FEC. It is valid when status0.an_link_good is 1.
21091 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_RX (0x1<<0) // Resolution result for RX PAUSE enable. It is valid when status0.an_link_good is 1.
21093 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_TX (0x1<<1) // Resolution result for TX PAUSE enable. It is valid when status0.an_link_good is 1.
21096 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_F971 (0x1<<0) // Resolution result for EEE. It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherwise. It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
21099 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_1G_KX (0x1<<0) // link_status for 1000Base-KX
21101 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KX4 (0x1<<1) // link_status for 10GBase-KX4
21103 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KR (0x1<<2) // link_status for 10GBase-KR
21105 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_KR4 (0x1<<3) // link_status for 40GBase-KR4
21107 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_CR4 (0x1<<4) // link_status for 40GBase-CR4
21109 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_CR10 (0x1<<5) // link_status for 100GBase-CR10
21111 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KP4 (0x1<<6) // link_status for 100GBase-KP4
21113 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KR4 (0x1<<7) // link_status for 100GBase-KR4
21116 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_100G_CR4 (0x1<<0) // link_status for 100GBase-CR4
21118 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_GR (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
21120 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_KR (0x1<<3) // link_status for 25GBase-KR
21122 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_CR (0x1<<4) // link_status for 25GBase-CR4
21124 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_KR2 (0x1<<5) // link_status for 50GBase-KR2
21126 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_CR2 (0x1<<6) // link_status for 50GBase-CR2
21131 #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2491_RESERVEDFIELD3114 (0x1<<2) // Reserved
21134 #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2492_RESERVEDFIELD3115 (0x1<<0) // Reserved
21137 #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2493_RESERVEDFIELD3116 (0x1<<0) // Reserved
21140 #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3117 (0x1<<0) // Reserved
21144 #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3119 (0x1<<3) // Reserved
21146 #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3120 (0x1<<4) // Reserved
21149 #define PHY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2495_RESERVEDFIELD3121 (0x1<<0) // Reserved
21156 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2498_RESERVEDFIELD3125 (0x1<<6) // Reserved
21165 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3129 (0x1<<0) // Reserved
21169 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3131 (0x1<<3) // Reserved
21172 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2502_RESERVEDFIELD3132 (0x1<<0) // Reserved
21217 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2511_RESERVEDFIELD3150 (0x1<<0) // Reserved
21219 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2511_RESERVEDFIELD3151 (0x1<<2) // Reserved
21233 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3158 (0x1<<6) // Reserved
21235 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3159 (0x1<<7) // Reserved
21252 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2522_RESERVEDFIELD3168 (0x1<<1) // Reserved
21268 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3174 (0x1<<6) // Reserved
21270 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2527_RESERVEDFIELD3175 (0x1<<7) // Reserved
21273 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3176 (0x1<<0) // Reserved
21275 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2528_RESERVEDFIELD3177 (0x1<<1) // Reserved
21284 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2529_RESERVEDFIELD3181 (0x1<<6) // Reserved
21298 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2535_RESERVEDFIELD3188 (0x1<<4) // Reserved
21315 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2538_RESERVEDFIELD3192 (0x1<<7) // Reserved
21318 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3193 (0x1<<0) // Reserved
21320 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2539_RESERVEDFIELD3194 (0x1<<1) // Reserved
21329 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2540_RESERVEDFIELD3198 (0x1<<6) // Reserved
21335 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3200 (0x1<<0) // Reserved
21337 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3201 (0x1<<1) // Reserved
21339 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3202 (0x1<<2) // Reserved
21341 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3203 (0x1<<3) // Reserved
21474 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2568_RESERVEDFIELD3255 (0x1<<7) // Reserved
21477 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3256 (0x1<<0) // Reserved
21479 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2569_RESERVEDFIELD3257 (0x1<<1) // Reserved
21488 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2570_RESERVEDFIELD3261 (0x1<<6) // Reserved
21510 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2573_RESERVEDFIELD3266 (0x1<<7) // Reserved
21513 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3267 (0x1<<0) // Reserved
21515 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2574_RESERVEDFIELD3268 (0x1<<1) // Reserved
21524 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2575_RESERVEDFIELD3272 (0x1<<6) // Reserved
21547 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2582_RESERVEDFIELD3280 (0x1<<7) // Reserved
21550 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3281 (0x1<<0) // Reserved
21552 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2583_RESERVEDFIELD3282 (0x1<<1) // Reserved
21561 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2584_RESERVEDFIELD3286 (0x1<<6) // Reserved
21569 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2586_RESERVEDFIELD3289 (0x1<<4) // Reserved
21579 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3292 (0x1<<0) // Reserved
21581 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2589_RESERVEDFIELD3293 (0x1<<1) // Reserved
21590 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2590_RESERVEDFIELD3297 (0x1<<6) // Reserved
21595 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3300 (0x1<<0) // Reserved
21597 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2593_RESERVEDFIELD3301 (0x1<<1) // Reserved
21606 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2594_RESERVEDFIELD3305 (0x1<<6) // Reserved
21614 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3311 (0x1<<0) // Reserved
21616 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2600_RESERVEDFIELD3312 (0x1<<1) // Reserved
21619 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3313 (0x1<<0) // Reserved
21621 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2601_RESERVEDFIELD3314 (0x1<<1) // Reserved
21624 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2602_RESERVEDFIELD3315 (0x1<<6) // Reserved
21666 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2623_RESERVEDFIELD3332 (0x1<<0) // Reserved
21673 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2625_RESERVEDFIELD3334 (0x1<<0) // Reserved
21681 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3337 (0x1<<0) // Reserved
21683 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3338 (0x1<<1) // Reserved
21687 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2627_RESERVEDFIELD3340 (0x1<<5) // Reserved
21692 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3342 (0x1<<0) // Reserved
21694 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3343 (0x1<<1) // Reserved
21698 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2628_RESERVEDFIELD3345 (0x1<<4) // Reserved
21726 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_REQ (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1. Set to 0 once ack is 1.
21729 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_ACK (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
21741 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3357 (0x1<<0) // Reserved
21743 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2635_RESERVEDFIELD3358 (0x1<<1) // Reserved
21749 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3359 (0x1<<0) // Reserved
21751 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3360 (0x1<<1) // Reserved
21755 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2636_RESERVEDFIELD3362 (0x1<<5) // Reserved
21760 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3364 (0x1<<0) // Reserved
21762 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3365 (0x1<<1) // Reserved
21766 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2637_RESERVEDFIELD3367 (0x1<<4) // Reserved
21795 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2644_RESERVEDFIELD3378 (0x1<<0) // Reserved
21798 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2645_RESERVEDFIELD3379 (0x1<<0) // Reserved
21801 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3380 (0x1<<0) // Reserved
21803 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2646_RESERVEDFIELD3381 (0x1<<1) // Reserved
21824 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2649_RESERVEDFIELD3390 (0x1<<6) // Reserved
21827 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2650_RESERVEDFIELD3391 (0x1<<0) // Reserved
21833 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2652_RESERVEDFIELD3394 (0x1<<0) // Reserved
21839 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2654_RESERVEDFIELD3397 (0x1<<0) // Reserved
21844 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2655_RESERVEDFIELD3399 (0x1<<7) // Reserved
21847 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_REQ (0x1<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
21851 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_RESERVEDFIELD3400 (0x1<<6) // Reserved
21853 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL (0x1<<7) // Set it to 1 when changing DFE tap values
21858 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2656_RESERVEDFIELD3402 (0x1<<4) // Reserved
21873 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_ACK (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
21875 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3409 (0x1<<1) // Reserved
21877 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3410 (0x1<<2) // Reserved
21879 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3411 (0x1<<3) // Reserved
21882 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
21884 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
21886 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
21888 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
21890 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP2_EN (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
21892 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP3_EN (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
21894 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP4_EN (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
21896 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP5_EN (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
21901 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
21906 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
21911 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
21916 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
21921 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21926 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21931 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21936 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21941 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
21946 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
21951 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
21956 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
21961 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21966 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21971 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21976 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21981 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21986 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21991 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
21996 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
22001 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
22006 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
22011 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
22016 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY (0x1<<7) // polarity 0 = negative, 1 = positive
22019 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3412 (0x1<<0) // Reserved
22021 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3413 (0x1<<1) // Reserved
22023 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3414 (0x1<<2) // Reserved
22025 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3415 (0x1<<3) // Reserved
22027 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3416 (0x1<<4) // Reserved
22029 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3417 (0x1<<5) // Reserved
22031 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3418 (0x1<<6) // Reserved
22033 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3419 (0x1<<7) // Reserved
22090 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3438 (0x1<<0) // Reserved
22092 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3439 (0x1<<1) // Reserved
22094 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3440 (0x1<<2) // Reserved
22096 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3441 (0x1<<3) // Reserved
22098 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3442 (0x1<<4) // Reserved
22100 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3443 (0x1<<5) // Reserved
22102 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3444 (0x1<<6) // Reserved
22104 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3445 (0x1<<7) // Reserved
22107 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3446 (0x1<<0) // Reserved
22109 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3447 (0x1<<1) // Reserved
22111 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2683_RESERVEDFIELD3448 (0x1<<2) // Reserved
22114 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3449 (0x1<<0) // Reserved
22116 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3450 (0x1<<1) // Reserved
22118 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3451 (0x1<<2) // Reserved
22120 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3452 (0x1<<3) // Reserved
22122 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3453 (0x1<<4) // Reserved
22124 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3454 (0x1<<5) // Reserved
22126 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3455 (0x1<<6) // Reserved
22128 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3456 (0x1<<7) // Reserved
22132 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2686_RESERVEDFIELD3458 (0x1<<0) // Reserved
22137 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3460 (0x1<<5) // Reserved
22139 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2687_RESERVEDFIELD3461 (0x1<<6) // Reserved
22142 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3462 (0x1<<0) // Reserved
22144 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2688_RESERVEDFIELD3463 (0x1<<1) // Reserved
22151 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3466 (0x1<<0) // Reserved
22153 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2691_RESERVEDFIELD3467 (0x1<<1) // Reserved
22164 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3472 (0x1<<0) // Reserved
22166 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3473 (0x1<<1) // Reserved
22168 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2696_RESERVEDFIELD3474 (0x1<<2) // Reserved
22171 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2697_RESERVEDFIELD3475 (0x1<<0) // Reserved
22205 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2711_RESERVEDFIELD3493 (0x1<<0) // Reserved
22276 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3530 (0x1<<0) // Reserved
22278 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2748_RESERVEDFIELD3531 (0x1<<1) // Reserved
22283 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2751_RESERVEDFIELD3534 (0x1<<0) // Reserved
22296 #define PHY_NW_IP_REG_LN3_DFE_RXCLK_RESERVEDREGISTER2762_RESERVEDFIELD3545 (0x1<<0) // Reserved
22299 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL (0x1<<0) // Enables analog LOS offset calibration circuits.
22308 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_EN (0x1<<0) // Enables the run-length detection digital LOS filter.
22312 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
22314 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
22325 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_EN (0x1<<0) // Enables the digital deglitching filter.
22328 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2765_RESERVEDFIELD3548 (0x1<<0) // Reserved
22337 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
22339 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE (0x1<<4) // Override value for the LOS output of the digital filtering logic.
22342 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2770_RESERVEDFIELD3553 (0x1<<0) // Reserved
22344 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2770_RESERVEDFIELD3554 (0x1<<4) // Reserved
22349 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2771_RESERVEDFIELD3556 (0x1<<6) // Reserved
22354 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2772_RESERVEDFIELD3558 (0x1<<6) // Reserved
22357 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3559 (0x1<<0) // Reserved
22361 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2773_RESERVEDFIELD3561 (0x1<<4) // Reserved
22364 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3562 (0x1<<0) // Reserved
22366 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3563 (0x1<<1) // Reserved
22368 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3564 (0x1<<2) // Reserved
22375 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2777_RESERVEDFIELD3568 (0x1<<0) // Reserved
22378 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3569 (0x1<<0) // Reserved
22380 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2778_RESERVEDFIELD3570 (0x1<<1) // Reserved
22389 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3573 (0x1<<0) // Reserved
22391 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2781_RESERVEDFIELD3574 (0x1<<1) // Reserved
22394 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_READY (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
22396 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_RESERVEDFIELD3575 (0x1<<1) // Reserved
22398 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS (0x1<<2) // The filtered LOS signal value.
22400 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_RAW (0x1<<3) // The unfiltered LOS signal value.
22402 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_NO_EII (0x1<<4) // The filtered LOS signal value before EII override logic.
22404 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_RESERVEDFIELD3576 (0x1<<5) // Reserved
22407 #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2782_RESERVEDFIELD3577 (0x1<<0) // Reserved
22414 #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2785_RESERVEDFIELD3580 (0x1<<0) // Reserved
22424 #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2789_RESERVEDFIELD3585 (0x1<<0) // Reserved
22452 #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2799_RESERVEDFIELD3597 (0x1<<0) // Reserved
22465 #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2808_RESERVEDFIELD3606 (0x1<<0) // Reserved
22468 #define PHY_NW_IP_REG_LN3_GCFSM2_RESERVEDREGISTER2809_RESERVEDFIELD3607 (0x1<<0) // Reserved
22474 #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_EN (0x1<<0) // Enables BIST Tx data generation.
22476 #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to transmitted: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x9 � MAC Tx data
22483 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_MODE (0x3<<0) // Controls what type of error injection is used: 0x0 � None 0x1 � Single cycle error 0x2 � Timer based
22519 #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_EN (0x1<<0) // Enables BIST Rx data checking.
22521 #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_PATTERN_SEL (0xf<<1) // Selects the pattern to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
22523 #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_CLEAR_BER (0x1<<5) // Clears the bit error counter.
22525 #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_STOP_ERROR_COUNT (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER data coherently.
22527 #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be inaccurate.
22530 #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_STATE (0x7<<0) // State of the BIST checker: 0x0 � Off 0x1 � Searching for pattern 0x2 � Waiting for pattern lock conditions 0x3 � Pattern lock acquired 0x4 � Pattern lock lost
22532 #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_PATTERN_DET (0xf<<3) // Indicates the pattern detected: 0x0 � No pattern detected 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP
22549 #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22578 #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_AC_COUPLED (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
22581 #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_EN (0x1<<0) // Enables turning on the divided rxclk output
22584 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_RESERVEDFIELD3614 (0x1<<0) // Reserved
22586 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2815_RESERVEDFIELD3615 (0x1<<1) // Reserved
22589 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3616 (0x1<<0) // Reserved
22591 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3617 (0x1<<1) // Reserved
22593 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3618 (0x1<<2) // Reserved
22595 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3619 (0x1<<3) // Reserved
22597 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3620 (0x1<<4) // Reserved
22599 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3621 (0x1<<5) // Reserved
22602 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3622 (0x1<<0) // Reserved
22604 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3623 (0x1<<1) // Reserved
22606 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3624 (0x1<<2) // Reserved
22608 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3625 (0x1<<3) // Reserved
22611 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3626 (0x1<<0) // Reserved
22613 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3627 (0x1<<1) // Reserved
22615 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3628 (0x1<<2) // Reserved
22617 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3629 (0x1<<3) // Reserved
22619 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3630 (0x1<<4) // Reserved
22621 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3631 (0x1<<5) // Reserved
22623 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3632 (0x1<<6) // Reserved
22625 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3633 (0x1<<7) // Reserved
22628 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3634 (0x1<<0) // Reserved
22630 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3635 (0x1<<1) // Reserved
22632 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3636 (0x1<<2) // Reserved
22634 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3637 (0x1<<3) // Reserved
22639 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3639 (0x1<<0) // Reserved
22641 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3640 (0x1<<1) // Reserved
22643 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2820_RESERVEDFIELD3641 (0x1<<2) // Reserved
22652 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2823_RESERVEDFIELD3644 (0x1<<0) // Reserved
22658 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_RESERVEDFIELD3647 (0x1<<0) // Reserved
22660 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2825_RESERVEDFIELD3648 (0x1<<1) // Reserved
22663 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_RESERVEDFIELD3649 (0x1<<0) // Reserved
22665 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2826_RESERVEDFIELD3650 (0x1<<1) // Reserved
22668 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_RESERVEDFIELD3651 (0x1<<0) // Reserved
22670 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2827_RESERVEDFIELD3652 (0x1<<1) // Reserved
22673 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2828_RESERVEDFIELD3653 (0x1<<0) // Reserved
22685 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
22687 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_RESERVEDFIELD3656 (0x1<<2) // Reserved
22690 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
22692 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_RESERVEDFIELD3657 (0x1<<2) // Reserved
22695 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
22697 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
22704 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
22706 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
22708 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
22710 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
22712 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3660 (0x1<<4) // Reserved
22714 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3661 (0x1<<5) // Reserved
22716 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3662 (0x1<<6) // Reserved
22718 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_RESERVEDFIELD3663 (0x1<<7) // Reserved
22721 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
22723 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
22730 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2829_RESERVEDFIELD3666 (0x1<<0) // Reserved
22733 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
22735 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
22737 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3667 (0x1<<2) // Reserved
22739 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3668 (0x1<<3) // Reserved
22742 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3669 (0x1<<0) // Reserved
22744 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3670 (0x1<<1) // Reserved
22746 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3671 (0x1<<2) // Reserved
22748 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3672 (0x1<<3) // Reserved
22750 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3673 (0x1<<4) // Reserved
22752 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3674 (0x1<<5) // Reserved
22754 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3675 (0x1<<6) // Reserved
22756 #define PHY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3676 (0x1<<7) // Reserved
22759 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP1_EN (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
22761 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP2_EN (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
22763 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP3_EN (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
22765 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP4_EN (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
22767 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP5_EN (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
22770 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_METHOD_SEL (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
22773 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 1
22775 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3677 (0x1<<1) // Reserved
22777 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3678 (0x1<<2) // Reserved
22779 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3679 (0x1<<3) // Reserved
22782 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 2
22784 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3680 (0x1<<1) // Reserved
22786 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3681 (0x1<<2) // Reserved
22788 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3682 (0x1<<3) // Reserved
22791 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 3
22793 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3683 (0x1<<1) // Reserved
22795 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3684 (0x1<<2) // Reserved
22797 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3685 (0x1<<3) // Reserved
22800 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 4
22802 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3686 (0x1<<1) // Reserved
22804 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3687 (0x1<<2) // Reserved
22806 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3688 (0x1<<3) // Reserved
22809 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN (0x1<<0) // Enables initial adaptations for Tap 5
22811 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3689 (0x1<<1) // Reserved
22813 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3690 (0x1<<2) // Reserved
22815 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3691 (0x1<<3) // Reserved
22818 #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_EN (0x1<<0) // Enables continuous background adaptation
22820 #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_RESERVEDFIELD3692 (0x1<<1) // Reserved
22856 #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3709 (0x1<<0) // Reserved
22858 #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RX_CTRL_DIS (0x1<<1) // Disables the firmware rx_ctrl MSM
22860 #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3710 (0x1<<2) // Reserved
22862 #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3711 (0x1<<3) // Reserved
22873 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING (0x1<<0) // Starts link training procedure when asserted. This is an 802.3 defined variable.
22875 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion. This is an 802.3 defined variable.
22877 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_SIGNAL_DETECT (0x1<<2) // Output corresponding to link training signal detect variable. Should be set when link training has completed successfully.
22879 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_CLEAR (0x1<<3) // Synchronous reset for LT Tx block.
22885 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_WAIT_TIME_8 (0x1<<0) // Same as above.
22888 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_FRAME_LOCK (0x1<<0) // Input to LTSM that receiver has acquired frame lock. This value should be taken from the corresponding LT Rx register. This an 802.3 defined variable.
22890 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_RX_TRAINED (0x1<<1) // Input to LTSM indicating that the local receiver has completed training. This is an 802.3 defined variable.
22892 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_REMOTE_RX_READY (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready. This value should be taken from the corresponding LT Rx registers. This is an 802.3 defined variable.
22895 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_FAIL (0x1<<0) // Output from LTSM indicating that link training has failed. This is an 802.3 defined variable.
22897 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING (0x1<<1) // Output from LTSM indicating that link training is in progress. This is an 802.3 defined variable.
22899 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_SIGNAL_DETECT (0x1<<2) // Output from LTSM indicating that link training is complete and successful. This is an 802.3 defined variable. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
22901 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
22917 #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE (0x1<<6) // Coefficient update initialize field.
22919 #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET (0x1<<7) // Coefficient update preset field.
22928 #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY (0x1<<6) // Status report field to indicate local receiver is ready. Should be set based on LTSM output of corresponding variable.
22931 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_CURRENT (0x7<<0) // Current state of LTSM. 0x0 � INITIALIZE 0x1 � SEND_TRAINING 0x2 � TRAIN_REMOTE 0x3 � TRAIN_LOCAL 0x4 � S7 0x5 � TRAINING_FAILURE 0x6 � LINK_READY 0x7 � SEND_DATA
22941 #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_CLEAR (0x1<<0) // Synchronous reset for LT Rx block.
22943 #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_TRAINING (0x1<<1) // This is the 802.3 defined training variable. It should be set according to corresponding LTSM output.
22950 #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_UPDATE (0x1<<0) // Assertion indicates that PRBS status information has been updated.
22952 #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_LOCK (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
22959 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_CLEAR_COUNT (0x1<<0) // Clears both the absolute and erroneous frame counters.
22962 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_FRAME_LOCK (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
22975 #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE (0x1<<6) // Received coefficient update initialize field.
22977 #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET (0x1<<7) // Received coefficient update preset field.
22986 #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_LOCAL_RX_READY (0x1<<6) // Received status report field to indicate local receiver is ready.
22988 #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_DME_ERROR (0x1<<7) // Indicates differential manchester decoding error. Not sticky.
23002 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
23018 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O (0x1<<2) // CMU reference div2 enable
23020 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O (0x1<<3) // CMU FL prediv4 enable
23022 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O (0x1<<4) // Reference clock startup deglitch circuit disable
23047 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O (0x1<<0) // GCFSM output override enable
23054 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
23056 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
23058 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override
23161 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O (0x1<<2) // State of qsample for PLL to be considered locked
23172 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O (0x1<<6) // CMU PLL HIZ setting
23174 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
23179 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O (0x1<<3) // Charge pump chop enable
23183 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O (0x1<<7) // Bandgap startup circuit bypass
23193 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O (0x1<<0) // Force PFD to output down
23195 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O (0x1<<1) // Force PFD to output up
23197 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O (0x1<<2) // Override enable for overriding N-div value
23199 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O (0x1<<3) // CMU V2I filter enable
23201 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O (0x1<<4) // CMU VCO PMOS proportional current increase
23203 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O (0x1<<5) // CMU VCO PMOS proportional current decrease
23211 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O (0x1<<2) // Enable to reduce charge pump reference current
23221 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O (0x1<<3) // Override enable for overriding VCOFR value
23231 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O (0x1<<7) // Reference clock select override
23234 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
23236 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
23238 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
23240 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
23242 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
23244 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
23246 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
23253 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O (0x1<<4) // Active high Enable for SSC generator SSC mode
23255 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O (0x1<<5) // Active high Enable for SSC block synth or SSC mode
23262 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O (0x1<<4) // Enable for SSC generator with Fractional Synthesis
23264 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O (0x1<<5) // Enable fractional division mode and SSC mode
23266 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
23275 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
23277 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O (0x1<<7) // Clock divider for High Speed clock source
23282 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
23284 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O (0x1<<6) // chicken bit for counter polarity
23286 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O (0x1<<7) // override enable to use above value
23295 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O (0x1<<5) // Refclk Termination override enable
23300 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O (0x1<<5) // Rx Termination override enable
23304 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8 (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
23311 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
23316 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O (0x1<<0) // Master reset for CMU
23377 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
23379 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
23381 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
23383 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
23385 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
23387 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
23389 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
23391 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
23394 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
23396 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
23398 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
23400 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
23402 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
23404 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
23406 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
23408 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
23411 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
23413 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
23415 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
23417 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O (0x1<<3) // Not used
23419 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O (0x1<<4) // Not used
23421 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O (0x1<<5) // Not used
23423 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O (0x1<<6) // Not used
23425 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O (0x1<<7) // Not used
23428 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for iddq_bias
23430 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for pd_bias
23432 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
23434 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O (0x1<<3) // MSM Function RST mode default value for pd_cmu
23436 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O (0x1<<4) // MSM Function RST mode default value for pd_cmureg
23438 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
23440 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O (0x1<<6) // MSM Function RST mode default value for pd_ref
23442 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
23445 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for reset_cmu
23447 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
23449 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for reset_cmureg
23451 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
23453 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
23455 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
23457 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
23459 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O (0x1<<7) // MSM Function RST mode default value for lfi_extzero
23462 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for soc_clk_en
23464 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for refclk_en
23466 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for pll_lock_en
23468 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O (0x1<<3) // Not used
23470 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O (0x1<<4) // Not used
23472 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O (0x1<<5) // Not used
23474 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O (0x1<<6) // Not used
23476 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O (0x1<<7) // Not used
23479 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
23481 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
23483 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
23485 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
23487 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
23489 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
23491 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
23493 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
23496 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
23498 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
23500 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
23502 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
23504 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
23506 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
23508 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
23510 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
23513 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
23515 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
23517 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
23519 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O (0x1<<3) // Not used
23521 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O (0x1<<4) // Not used
23523 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O (0x1<<5) // Not used
23525 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O (0x1<<6) // Not used
23527 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O (0x1<<7) // Not used
23530 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
23532 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
23534 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
23536 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
23538 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
23540 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
23542 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
23544 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
23547 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
23549 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
23551 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
23553 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
23555 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
23557 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
23559 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
23561 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
23564 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
23566 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
23568 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
23570 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O (0x1<<3) // Not used
23572 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O (0x1<<4) // Not used
23574 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O (0x1<<5) // Not used
23576 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O (0x1<<6) // Not used
23578 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O (0x1<<7) // Not used
23584 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_DIV_SEL_O (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
23588 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
23593 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
23597 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
23602 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_DIV_SEL_O (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
23606 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
23609 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0 (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
23611 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1 (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
23626 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
23628 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
23630 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
23632 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O (0x1<<5) // Bist generator master reset.
23634 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
23636 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist generator generates data
23641 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
23653 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
23655 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
23660 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O (0x1<<3) // Bist checker mode select. 0X0 � UDP pattern. 0x1 � PRBS pattern
23664 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
23672 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
23714 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2 (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Select LANE registers
23716 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
23718 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
23726 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
23728 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
23730 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
23732 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override.
23748 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28 (0x1<<0) // Not currently used
23754 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8 (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
23771 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
23773 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
23775 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O (0x1<<2) // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
23785 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
23793 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O (0x1<<0) // Asserting this register will bypass the symbol aligner
23799 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O (0x1<<2) // Clears the elec idle control error flag
23801 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O (0x1<<3) // Override for ei_inferred signal
23803 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O (0x1<<4) // Override for ei_mask signal
23805 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O (0x1<<5) // Override for ei_exit_type signal
23807 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O (0x1<<6) // EI control override enable
23817 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O (0x1<<4) // Control signal to force decoder into loopback mode
23820 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O (0x1<<0) // FES loopback enable.
23822 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O (0x1<<1) // NES loopback enable.
23824 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O (0x1<<2) // HS recovered clock to transmit loopback enable.
23827 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O (0x1<<0) // RX boost override enable
23837 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
23839 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O (0x1<<7) // RX FL calibration clock DIV4 enable
23854 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O (0x1<<6) // DLPF DIV2 enable
23856 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O (0x1<<7) // CDR DivN clock divider enable.
23869 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
23874 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O (0x1<<3) // Override enable for RXVCOFR override vakue
23889 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
23891 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O (0x1<<2) // Reset signal for eye alignment mechanism.
23893 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
23895 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
23897 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
23910 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O (0x1<<4) // CDR clock divider bypass enable.
23915 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O (0x1<<5) // TX bleed enable
23934 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0 (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
23936 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0 (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
23938 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA (0x1<<6) // enable override calibrated txterm value
23940 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
23948 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0 (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
23955 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O (0x1<<0) // DFE block enable signal.
23959 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
23961 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
23963 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
23965 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6 (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
24019 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS (0x1<<0) // Disable auto cal w/ rx_superbst
24023 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O (0x1<<5) // Enable Max limiting for BOOST auto-calibration
24030 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O (0x1<<2) // boost_adj_en
24032 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O (0x1<<3) // boost_adj_dir
24039 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O (0x1<<7) // CMP Offset Noise Averaging Enable
24047 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS (0x1<<6) // Disable auto cal w/ rx_att_gain
24049 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
24054 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O (0x1<<7) // Override enable for DFE signals.
24059 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
24066 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
24068 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6 (0x1<<6) // DFE TAP CMP no offset override enable
24070 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7 (0x1<<7) // DFE TAP override enable
24075 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0 (0x1<<5) // DFE offset calibrated value override enable
24077 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1 (0x1<<6) // DFE offset cal enable override
24079 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2 (0x1<<7) // DFE comparator cal enable override
24100 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7 (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
24103 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0 (0x1<<0) // cdfe enable bit. 1: enable cdfe when rate is 2'b01 or 2'b10. 0: disable cdfe.
24113 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO (0x1<<4) //
24115 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL (0x1<<5) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
24117 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL (0x1<<6) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
24119 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL (0x1<<7) // EI exit cdfe calibration enable. 1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. 0: the cdfe calibration is disabled when EI exits. Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
24122 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL (0x1<<0) // Continuous cdfe calibration enable. 1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. 0: the continuous cdfe calibration is disabled. Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
24124 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
24126 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL (0x1<<2) // Enables cdfe calibration post Txeq adaptation. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
24128 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibration. 0: disables cdfe calibration.
24130 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibration. 0: disables cdfe calibration.
24136 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll overwrite for cdfe. 0: disable coarse dll overwrite for cdfe.
24229 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll overwrite for cdfe. 0: disable fine dll overwrite for cdfe.
24232 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8 (0x1<<0) //
24234 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8 (0x1<<1) //
24236 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8 (0x1<<2) //
24238 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8 (0x1<<3) //
24245 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN (0x1<<0) // Override enable for CDFE calibration direction
24247 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL (0x1<<1) // Override value for CDFE calibration direction
24249 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
24251 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
24253 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
24255 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay overwrite for cdfe. 0: disable eye delay overwrite for cdfe.
24257 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
24261 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
24267 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
24269 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN (0x1<<1) // cdfe dlev overwrite enable. 1: enable dlev overwrite for cdfe. 0: disable dlev overwrite for cdfe.
24273 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8 (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
24295 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
24298 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
24300 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O (0x1<<1) //
24302 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O (0x1<<2) //
24304 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O (0x1<<7) //
24307 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O (0x1<<0) //
24309 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O (0x1<<1) //
24317 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O (0x1<<5) // Forces the positive dlev training pattern to be used
24319 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O (0x1<<6) // Forces the negative dlev training pattern to be used
24418 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
24420 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
24422 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24424 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24428 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
24431 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
24433 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24435 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24437 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
24439 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24441 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24443 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O (0x1<<6) // Used as Reg0 polarity select
24446 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24448 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24452 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24 (0x1<<5) // Bit 24: txdrv_c2_in[3]
24454 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O (0x1<<6) // Enable bit for width_chng module
24456 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O (0x1<<7) // Txterm calibration enable
24472 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O (0x1<<6) // 8b/10b encoder enable.
24474 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O (0x1<<7) // 8b/10b decoder enable.
24480 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O (0x1<<5) // PIPE interface block enable.
24482 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O (0x1<<6) // SAPIS interface block enable.
24484 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE (0x1<<7) // Signal Detect USB mode enable
24490 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
24492 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
24494 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
24496 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0 (0x1<<3) // Receive amplifier powerdown override, when cisel is high
24503 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O (0x1<<0) // Beacon Override Enable
24505 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O (0x1<<1) // Beacon Override
24507 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O (0x1<<2) // Enables 16b/20b decoder
24509 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O (0x1<<3) // Enables 16b/20b encoder
24527 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
24529 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
24538 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48 (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
24540 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
24542 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN (0x1<<6) // OOB detect enable
24544 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49 (0x1<<7) // OOB detect enable
24554 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50 (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
24557 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - gcfsm_refmux_clk = lane_ref_clk
24560 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O (0x1<<0) // Enable/Disable the internal PRBS data pattern inverter. 0x0 � Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
24562 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O (0x1<<1) // Enable/Disable the internal PRBS data pattern inverter. 0x0 � Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
24580 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O (0x1<<1) // Enable resetting of railed DLPF
24583 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O (0x1<<0) // Enable DOSC adjustement for railed DLPF
24587 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O (0x1<<6) // Default DOSC adjustement direction for railed DLPF
24590 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O (0x1<<0) // Enable eye scan counter
24592 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O (0x1<<1) // Run eye scan counter
24594 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O (0x1<<2) // Shift edge samples
24596 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O (0x1<<3) // Determines shift direction of edge samples
24598 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O (0x1<<4) // Shift edge samples by 2 bits
24695 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O (0x1<<0) // Enables programmable tx det rx pulse
24702 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
24704 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
24706 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
24708 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
24710 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
24712 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
24714 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
24716 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
24719 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
24721 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
24723 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
24725 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
24727 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
24729 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
24731 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
24733 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
24736 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
24738 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
24740 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
24742 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
24744 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
24746 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
24748 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
24750 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
24753 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
24755 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
24757 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
24759 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
24762 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
24764 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
24766 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
24768 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
24770 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
24772 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
24774 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
24776 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
24779 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
24781 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
24783 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
24785 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
24787 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
24789 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
24791 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
24793 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
24796 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
24798 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
24800 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
24802 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
24804 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
24806 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
24808 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
24810 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
24813 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
24815 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
24817 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
24819 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
24822 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
24824 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
24826 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
24828 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
24830 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
24832 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
24834 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
24836 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
24839 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
24841 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
24843 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
24845 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
24847 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
24849 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
24851 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
24853 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
24856 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
24858 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
24860 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
24862 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
24864 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
24866 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
24868 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
24870 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
24873 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
24875 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
24877 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
24879 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
24882 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
24884 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
24886 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
24888 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
24890 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
24892 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
24894 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
24896 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
24899 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
24901 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
24903 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
24905 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
24907 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
24909 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
24911 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
24913 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
24916 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
24918 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
24920 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
24922 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
24924 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
24926 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
24928 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
24930 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
24933 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
24935 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
24937 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
24939 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
24942 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
24944 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
24946 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
24948 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
24950 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
24952 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
24954 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
24956 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
24959 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
24961 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
24963 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
24965 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
24967 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
24969 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
24971 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
24973 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
24976 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
24978 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
24980 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
24982 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
24984 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
24986 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
24988 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
24990 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
24993 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
24995 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
24997 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
24999 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
25014 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8 (0x1<<0) // OOB detector COMINIT maximum idle length.
25018 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8 (0x1<<0) // OOB detector COMINIT maximum idle length.
25022 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8 (0x1<<0) // OOB detector COMWAKE minimum idle length.
25026 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8 (0x1<<0) // OOB detector COMWAKE maximum idle length.
25030 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8 (0x1<<0) // OOB detector COMSAS maximum idle length.
25034 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8 (0x1<<0) // OOB detector COMSAS maximum idle length.
25037 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O (0x1<<6) // Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed
25039 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O (0x1<<7) // Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed
25050 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O (0x1<<6) // Enable phase detector during CDR VCO calibration
25055 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O (0x1<<4) // Assertion causes repeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are selected by rxeq_recal_o[6:0]/rxeq_rate2_recal_o[6:0].
25057 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O (0x1<<6) // Set all DFE calibration values to mid-scale instead of using start values at start of calibration
25071 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O (0x1<<0) // Repeat calibration whenever exiting RX electrical idle. Calibrations performed are selected by rxeq_recal_o[6:0]/rxeq_lane2_recal_o[6:0]
25106 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O (0x1<<0) // comparator offset override enable
25113 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
25120 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for boost
25124 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap1
25128 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap2
25132 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap3
25136 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap4
25140 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap5
25145 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O (0x1<<6) // RXEQ ctrl_test mode enable
25147 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O (0x1<<7) // Step calibration in test mode, rising edge triggers step
25152 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O (0x1<<7) // Take the floor of the calibration result
25163 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O (0x1<<5) // Reverse order of tap power down signals
25168 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O (0x1<<5) // By pass comparator DC offset calibration
25170 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O (0x1<<6) // Changes the dfe tap offset cal direction
25174 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for boost in rate2
25178 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for boost in rate3
25192 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL (0x1<<7) // DFE shadow offset read select
25221 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
25227 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
25229 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1 (0x1<<1) // Initiate TXEQ adaptation for Gen3 rate
25350 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN (0x1<<0) //
25352 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN (0x1<<1) //
25405 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN (0x1<<6) //
25415 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O (0x1<<7) //
25428 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O (0x1<<3) //
25434 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25436 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25438 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25440 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25442 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25444 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25446 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25448 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25451 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25453 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25455 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25457 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25459 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25461 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25463 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25465 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25468 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25470 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25472 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25474 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25476 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25478 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25480 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25482 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25485 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25487 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25489 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25491 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25494 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25496 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25498 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25500 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25502 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25504 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25506 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25508 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25511 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25513 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25515 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25517 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25519 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25521 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25523 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25525 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25528 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25530 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25532 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25534 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25536 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25538 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25540 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25542 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25545 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25547 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25549 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25551 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25554 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25556 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25558 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25560 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25562 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25564 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25566 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25568 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25571 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25573 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25575 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25577 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25579 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25581 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25583 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25585 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25588 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25590 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25592 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25594 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25596 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25598 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25600 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25602 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25605 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25607 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25609 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25611 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25614 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25616 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25618 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25620 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25622 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25624 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25626 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25628 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25631 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25633 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25635 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25637 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25639 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25641 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25643 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25645 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25648 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25650 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25652 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25654 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25656 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25658 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25660 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25662 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25665 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25667 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25669 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25671 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
25681 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O (0x1<<0) // Lane0 master reset
25683 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O (0x1<<1) // Lane1 master reset
25685 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O (0x1<<2) // Lane2 master reset
25687 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O (0x1<<3) // Lane3 master reset
25690 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O (0x1<<0) // fast_sim_register
25698 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0 (0x1<<3) // CMU OK Status
25700 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1 (0x1<<4) // CMU1 OK Status
25703 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0 (0x1<<0) // Lane 0 Signal Detect Valid Status
25705 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1 (0x1<<1) // Lane 1 Signal Detect Valid Status
25707 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2 (0x1<<2) // Lane 2 Signal Detect Valid Status
25709 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3 (0x1<<3) // Lane 3 Signal Detect Valid Status
25711 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4 (0x1<<4) // Lane 0 OK Status
25713 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5 (0x1<<5) // Lane 1 OK Status
25715 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6 (0x1<<6) // Lane 2 OK Status
25717 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7 (0x1<<7) // Lane 3 OK Status
25768 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25770 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25772 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25774 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25776 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25778 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25780 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25782 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25785 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25787 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25789 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25791 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25793 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25795 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25797 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25799 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25802 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25804 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25806 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25808 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25810 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25812 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25814 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25816 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25819 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25821 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25823 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25825 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25828 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25830 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25832 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25834 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25836 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25838 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25840 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25842 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25845 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25847 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25849 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25851 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25853 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25855 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25857 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25859 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25862 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25864 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25866 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25868 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25870 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25872 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25874 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25876 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25879 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25881 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25883 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25885 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25888 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25890 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25892 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25894 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25896 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25898 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25900 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25902 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25905 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25907 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25909 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25911 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25913 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25915 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25917 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25919 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25922 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25924 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25926 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25928 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25930 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25932 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25934 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25936 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25939 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25941 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25943 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25945 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
25966 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_BURNIN_REF_LIFE_CLK_SEL_O (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
25982 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O (0x1<<2) // CMU reference div2 enable
25984 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PREDIV4_ENA_O (0x1<<3) // CMU FL prediv4 enable
25986 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O (0x1<<4) // Reference clock startup deglitch circuit disable
26011 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_OUT_OVR_EN_O (0x1<<0) // GCFSM output override enable
26018 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
26020 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
26022 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override
26125 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_GOOD_STATE_O (0x1<<2) // State of qsample for PLL to be considered locked
26136 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_HIZ_O (0x1<<6) // CMU PLL HIZ setting
26138 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_C1_SEL_O (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
26143 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O (0x1<<3) // Charge pump chop enable
26147 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_BGSTART_BYP_O (0x1<<7) // Bandgap startup circuit bypass
26157 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_DN_O (0x1<<0) // Force PFD to output down
26159 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_UP_O (0x1<<1) // Force PFD to output up
26161 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_SR_NDIV_OVR_ENA_O (0x1<<2) // Override enable for overriding N-div value
26163 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O (0x1<<3) // CMU V2I filter enable
26165 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O (0x1<<4) // CMU VCO PMOS proportional current increase
26167 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O (0x1<<5) // CMU VCO PMOS proportional current decrease
26175 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_I_DROPI_O (0x1<<2) // Enable to reduce charge pump reference current
26185 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_SEL_O (0x1<<3) // Override enable for overriding VCOFR value
26195 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_SEL_OVR_O (0x1<<7) // Reference clock select override
26198 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_L_O (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
26200 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_R_O (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
26202 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_L_O (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
26204 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_R_O (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
26206 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_CM_HV2P5SEL_O (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
26208 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_L_O (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
26210 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_R_O (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
26217 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_GEN_EN_O (0x1<<4) // Active high Enable for SSC generator SSC mode
26219 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_EN_O (0x1<<5) // Active high Enable for SSC block synth or SSC mode
26226 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_FRACSYN_EN_O (0x1<<4) // Enable for SSC generator with Fractional Synthesis
26228 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_EN_FRACN_FRCDIV_MODE_O (0x1<<5) // Enable fractional division mode and SSC mode
26230 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_UPDOWN_EN_O (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
26239 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_SRC_SEL_O (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26241 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_DIV_SEL_O (0x1<<7) // Clock divider for High Speed clock source
26246 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLL_EN_O (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
26248 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLARITY_O (0x1<<6) // chicken bit for counter polarity
26250 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_EN_O (0x1<<7) // override enable to use above value
26259 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_EN_O (0x1<<5) // Refclk Termination override enable
26264 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_EN_O (0x1<<5) // Rx Termination override enable
26268 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_UP_8 (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
26275 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_GC_TCCAL_ENA_OVR (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
26280 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_CMU_MASTER_CDN_O (0x1<<0) // Master reset for CMU
26341 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_IDDQ_BIAS_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
26343 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_BIAS_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
26345 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
26347 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMU_IDDQ_SETVAL_O (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
26349 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREG_IDDQ_SETVAL_O (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
26351 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREGREF_IDDQ_SETVAL_O (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
26353 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_REF_IDDQ_SETVAL_O (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
26355 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_CMU_FL_IDDQ_SETVAL_O (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
26358 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
26360 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
26362 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREG_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
26364 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREGREF_IDDQ_SETVAL_O (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
26366 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
26368 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUVCO_IDDQ_SETVAL_O (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
26370 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
26372 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LFI_EXTZERO_IDDQ_SETVAL_O (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
26375 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_SOC_CLK_EN_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
26377 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_REFCLK_EN_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
26379 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PLL_LOCK_EN_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
26381 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_TXCLK_IDDQ_SETVAL_O (0x1<<3) // Not used
26383 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_CLKDIV_IDDQ_SETVAL_O (0x1<<4) // Not used
26385 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_IDDQ_SETVAL_O (0x1<<5) // Not used
26387 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O (0x1<<6) // Not used
26389 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O (0x1<<7) // Not used
26392 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_IDDQ_BIAS_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for iddq_bias
26394 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_BIAS_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for pd_bias
26396 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
26398 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMU_RST_SETVAL_O (0x1<<3) // MSM Function RST mode default value for pd_cmu
26400 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREG_RST_SETVAL_O (0x1<<4) // MSM Function RST mode default value for pd_cmureg
26402 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREGREF_RST_SETVAL_O (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
26404 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_REF_RST_SETVAL_O (0x1<<6) // MSM Function RST mode default value for pd_ref
26406 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_CMU_FL_RST_SETVAL_O (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
26409 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for reset_cmu
26411 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_GCRX_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
26413 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREG_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for reset_cmureg
26415 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREGREF_RST_SETVAL_O (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
26417 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUSYNTH_RST_SETVAL_O (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
26419 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUVCO_RST_SETVAL_O (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
26421 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LF_EXTZERO_ENA_RST_SETVAL_O (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
26423 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LFI_EXTZERO_RST_SETVAL_O (0x1<<7) // MSM Function RST mode default value for lfi_extzero
26426 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_SOC_CLK_EN_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for soc_clk_en
26428 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_REFCLK_EN_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for refclk_en
26430 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PLL_LOCK_EN_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for pll_lock_en
26432 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_TXCLK_RST_SETVAL_O (0x1<<3) // Not used
26434 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_CLKDIV_RST_SETVAL_O (0x1<<4) // Not used
26436 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_RST_SETVAL_O (0x1<<5) // Not used
26438 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O (0x1<<6) // Not used
26440 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O (0x1<<7) // Not used
26443 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_IDDQ_BIAS_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
26445 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_BIAS_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
26447 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
26449 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMU_NORM_SETVAL_O (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
26451 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREG_NORM_SETVAL_O (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
26453 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREGREF_NORM_SETVAL_O (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
26455 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_REF_NORM_SETVAL_O (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
26457 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_CMU_FL_NORM_SETVAL_O (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
26460 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
26462 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_GCRX_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
26464 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREG_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
26466 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREGREF_NORM_SETVAL_O (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
26468 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUSYNTH_NORM_SETVAL_O (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
26470 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUVCO_NORM_SETVAL_O (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
26472 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LF_EXTZERO_ENA_NORM_SETVAL_O (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
26474 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LFI_EXTZERO_NORM_SETVAL_O (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
26477 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_SOC_CLK_EN_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
26479 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_REFCLK_EN_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
26481 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PLL_LOCK_EN_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
26483 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_TXCLK_NORM_SETVAL_O (0x1<<3) // Not used
26485 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_CLKDIV_NORM_SETVAL_O (0x1<<4) // Not used
26487 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_NORM_SETVAL_O (0x1<<5) // Not used
26489 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O (0x1<<6) // Not used
26491 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O (0x1<<7) // Not used
26494 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_IDDQ_BIAS_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
26496 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_BIAS_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
26498 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
26500 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMU_PD_SETVAL_O (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
26502 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREG_PD_SETVAL_O (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
26504 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREGREF_PD_SETVAL_O (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
26506 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_REF_PD_SETVAL_O (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
26508 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_CMU_FL_PD_SETVAL_O (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
26511 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
26513 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_GCRX_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
26515 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREG_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
26517 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREGREF_PD_SETVAL_O (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
26519 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUSYNTH_PD_SETVAL_O (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
26521 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUVCO_PD_SETVAL_O (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
26523 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LF_EXTZERO_ENA_PD_SETVAL_O (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
26525 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LFI_EXTZERO_PD_SETVAL_O (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
26528 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_SOC_CLK_EN_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
26530 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_REFCLK_EN_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
26532 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PLL_LOCK_EN_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
26534 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_TXCLK_PD_SETVAL_O (0x1<<3) // Not used
26536 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_CLKDIV_PD_SETVAL_O (0x1<<4) // Not used
26538 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_PD_SETVAL_O (0x1<<5) // Not used
26540 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O (0x1<<6) // Not used
26542 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O (0x1<<7) // Not used
26557 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
26573 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O (0x1<<2) // CMU reference div2 enable
26575 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O (0x1<<3) // CMU FL prediv4 enable
26577 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O (0x1<<4) // Reference clock startup deglitch circuit disable
26602 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O (0x1<<0) // GCFSM output override enable
26609 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
26611 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
26613 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override
26705 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O (0x1<<2) // State of qsample for PLL to be considered locked
26716 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O (0x1<<6) // CMU PLL HIZ setting
26718 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
26723 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O (0x1<<3) // Charge pump chop enable
26727 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O (0x1<<7) // Bandgap startup circuit bypass
26737 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O (0x1<<0) // Force PFD to output down
26739 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O (0x1<<1) // Force PFD to output up
26741 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O (0x1<<2) // Override enable for overriding N-div value
26743 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O (0x1<<3) // CMU V2I filter enable
26745 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O (0x1<<4) // CMU VCO PMOS proportional current increase
26747 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O (0x1<<5) // CMU VCO PMOS proportional current decrease
26755 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O (0x1<<2) // Enable to reduce charge pump reference current
26765 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O (0x1<<3) // Override enable for overriding VCOFR value
26770 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O (0x1<<7) // Reference clock select override
26773 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
26775 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
26777 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
26779 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
26781 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
26783 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
26785 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
26792 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O (0x1<<4) // Active high Enable for SSC generator SSC mode
26794 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O (0x1<<5) // Active high Enable for SSC block synth or SSC mode
26801 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O (0x1<<4) // Enable for SSC generator with Fractional Synthesis
26803 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O (0x1<<5) // Enable fractional division mode and SSC mode
26805 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
26814 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26816 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O (0x1<<7) // Clock divider for High Speed clock source
26821 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
26823 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O (0x1<<6) // chicken bit for counter polarity
26825 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O (0x1<<7) // override enable to use above value
26834 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O (0x1<<5) // Refclk Termination override enable
26839 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O (0x1<<5) // Rx Termination override enable
26843 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8 (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
26850 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
26855 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O (0x1<<0) // Master reset for CMU
26884 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_EN_O (0x1<<2) // Override enable for overridng internal signal cmu_rate_is_gen3
26886 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_O (0x1<<3) // Override for internal signal cmu_rate_is_gen3
26895 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_HIZ_GEN3_O (0x1<<6) // CMU PLL HIZ setting in gen3 rate Used only in PCIe3 1CMU config
26897 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_C1_SEL_GEN3_O (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
26902 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O (0x1<<3) // Charge pump chop enable in gen3 rate Used only in PCIe3 1CMU config
26906 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_BGSTART_BYP_GEN3_O (0x1<<7) // Bandgap startup circuit bypass
26916 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_DN_GEN3_O (0x1<<0) // Force PFD to output down in gen3 rate Used only in PCIe3 1CMU config
26918 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_UP_GEN3_O (0x1<<1) // Force PFD to output up in gen3 rate Used only in PCIe3 1CMU config
26920 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_V2I_FILTER_SW_ON_GEN3_O (0x1<<2) // CMU V2I filter enable in gen3 rate Used only in PCIe3 1CMU config
26922 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O (0x1<<3) // CMU VCO PMOS proportional current increase
26924 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_GEN3_O (0x1<<4) // CMU VCO PMOS proportional current decrease
26932 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_I_DROPI_GEN3_O (0x1<<2) // Enable to reduce charge pump reference current
26942 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PLL_REFDIV2_ENA_GEN3_O (0x1<<3) // Not used
26944 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PREDIV4_ENA_GEN3_O (0x1<<4) // Not used
26994 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
26996 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
26998 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
27000 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
27002 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
27004 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
27006 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
27008 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
27011 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
27013 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
27015 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
27017 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
27019 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
27021 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
27023 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
27025 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
27028 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
27030 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
27032 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
27034 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O (0x1<<3) // Not used
27036 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O (0x1<<4) // Not used
27038 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O (0x1<<5) // Not used
27040 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O (0x1<<6) // Not used
27042 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O (0x1<<7) // Not used
27045 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for iddq_bias
27047 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for pd_bias
27049 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
27051 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O (0x1<<3) // MSM Function RST mode default value for pd_cmu
27053 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O (0x1<<4) // MSM Function RST mode default value for pd_cmureg
27055 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
27057 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O (0x1<<6) // MSM Function RST mode default value for pd_ref
27059 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
27062 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for reset_cmu
27064 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
27066 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for reset_cmureg
27068 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
27070 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
27072 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
27074 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
27076 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O (0x1<<7) // MSM Function RST mode default value for lfi_extzero
27079 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O (0x1<<0) // MSM Function RST mode default value for soc_clk_en
27081 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O (0x1<<1) // MSM Function RST mode default value for refclk_en
27083 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O (0x1<<2) // MSM Function RST mode default value for pll_lock_en
27085 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O (0x1<<3) // Not used
27087 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O (0x1<<4) // Not used
27089 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O (0x1<<5) // Not used
27091 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O (0x1<<6) // Not used
27093 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O (0x1<<7) // Not used
27096 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
27098 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
27100 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
27102 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
27104 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
27106 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
27108 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
27110 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
27113 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
27115 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
27117 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
27119 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
27121 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
27123 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
27125 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
27127 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
27130 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
27132 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
27134 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
27136 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O (0x1<<3) // Not used
27138 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O (0x1<<4) // Not used
27140 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O (0x1<<5) // Not used
27142 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O (0x1<<6) // Not used
27144 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O (0x1<<7) // Not used
27147 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
27149 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
27151 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
27153 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
27155 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
27157 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
27159 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
27161 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
27164 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
27166 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
27168 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
27170 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
27172 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
27174 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
27176 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
27178 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
27181 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
27183 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
27185 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
27187 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O (0x1<<3) // Not used
27189 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O (0x1<<4) // Not used
27191 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O (0x1<<5) // Not used
27193 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O (0x1<<6) // Not used
27195 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O (0x1<<7) // Not used
27198 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_IDDQ_BIAS_NORM_REFCLK_SETVAL_O (0x1<<0) // MSM Function NORM REFCLK mode default value for iddq_bias
27200 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_BIAS_NORM_REFCLK_SETVAL_O (0x1<<1) // MSM Function NORM REFCLK mode default value for pd_bias
27202 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_TXCLK_PCS_CLK_NORM_REFCLK_SETVAL_O (0x1<<2) // MSM Function NORM REFCLK mode default value for pcs_clk_ena
27204 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMU_NORM_REFCLK_SETVAL_O (0x1<<3) // MSM Function NORM REFCLK mode default value for pd_cmu
27206 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREG_NORM_REFCLK_SETVAL_O (0x1<<4) // MSM Function NORM REFCLK mode default value for pd_cmureg
27208 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREGREF_NORM_REFCLK_SETVAL_O (0x1<<5) // MSM Function NORM REFCLK mode default value for pd_cmuregref
27210 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_REF_NORM_REFCLK_SETVAL_O (0x1<<6) // MSM Function NORM REFCLK mode default value for pd_ref
27212 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_CMU_FL_NORM_REFCLK_SETVAL_O (0x1<<7) // MSM Function NORM REFCLK mode default value for reset_cmu_fl
27215 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_NORM_REFCLK_SETVAL_O (0x1<<0) // MSM Function NORM REFCLK mode default value for reset_cmu
27217 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_GCRX_NORM_REFCLK_SETVAL_O (0x1<<1) // MSM Function NORM REFCLK mode default value for reset_cmu_gcrx
27219 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREG_NORM_REFCLK_SETVAL_O (0x1<<2) // MSM Function NORM REFCLK mode default value for reset_cmureg
27221 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREGREF_NORM_REFCLK_SETVAL_O (0x1<<3) // MSM Function NORM REFCLK mode default value for reset_cmuregref
27223 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUSYNTH_NORM_REFCLK_SETVAL_O (0x1<<4) // MSM Function NORM REFCLK mode default value for reset_cmusynth
27225 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUVCO_NORM_REFCLK_SETVAL_O (0x1<<5) // MSM Function NORM REFCLK mode default value for reset_cmuvco
27227 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LF_EXTZERO_ENA_NORM_REFCLK_SETVAL_O (0x1<<6) // MSM Function NORM REFCLK mode default value for lf_extzero_ena
27229 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LFI_EXTZERO_NORM_REFCLK_SETVAL_O (0x1<<7) // MSM Function NORM REFCLK mode default value for lfi_extzero
27232 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_SOC_CLK_EN_NORM_REFCLK_SETVAL_O (0x1<<0) // MSM Function NORM REFCLK mode default value for soc_clk_en
27234 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_REFCLK_EN_NORM_REFCLK_SETVAL_O (0x1<<1) // MSM Function NORM REFCLK mode default value for refclk_en
27236 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PLL_LOCK_EN_NORM_REFCLK_SETVAL_O (0x1<<2) // MSM Function NORM REFCLK mode default value for pll_lock_en
27238 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_TXCLK_NORM_REFCLK_SETVAL_O (0x1<<3) // Not used
27240 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_CLKDIV_NORM_REFCLK_SETVAL_O (0x1<<4) // Not used
27242 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_NORM_REFCLK_SETVAL_O (0x1<<5) // Not used
27244 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_LEFT_NORM_REFCLK_SETVAL_O (0x1<<6) // Not used
27246 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_RIGHT_NORM_REFCLK_SETVAL_O (0x1<<7) // Not used
27249 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_IDDQ_BIAS_P1_2_SETVAL_O (0x1<<0) // MSM Function P1_2 mode default value for iddq_bias
27251 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_BIAS_P1_2_SETVAL_O (0x1<<1) // MSM Function P1_2 mode default value for pd_bias
27253 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_TXCLK_PCS_CLK_P1_2_SETVAL_O (0x1<<2) // MSM Function P1_2 mode default value for pcs_clk_ena
27255 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMU_P1_2_SETVAL_O (0x1<<3) // MSM Function P1_2 mode default value for pd_cmu
27257 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREG_P1_2_SETVAL_O (0x1<<4) // MSM Function P1_2 mode default value for pd_cmureg
27259 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREGREF_P1_2_SETVAL_O (0x1<<5) // MSM Function P1_2 mode default value for pd_cmuregref
27261 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_REF_P1_2_SETVAL_O (0x1<<6) // MSM Function P1_2 mode default value for pd_ref
27263 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_CMU_FL_P1_2_SETVAL_O (0x1<<7) // MSM Function P1_2 mode default value for reset_cmu_fl
27266 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_P1_2_SETVAL_O (0x1<<0) // MSM Function P1_2 mode default value for reset_cmu
27268 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_GCRX_P1_2_SETVAL_O (0x1<<1) // MSM Function P1_2 mode default value for reset_cmu_gcrx
27270 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREG_P1_2_SETVAL_O (0x1<<2) // MSM Function P1_2 mode default value for reset_cmureg
27272 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREGREF_P1_2_SETVAL_O (0x1<<3) // MSM Function P1_2 mode default value for reset_cmuregref
27274 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUSYNTH_P1_2_SETVAL_O (0x1<<4) // MSM Function P1_2 mode default value for reset_cmusynth
27276 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUVCO_P1_2_SETVAL_O (0x1<<5) // MSM Function P1_2 mode default value for reset_cmuvco
27278 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LF_EXTZERO_ENA_P1_2_SETVAL_O (0x1<<6) // MSM Function P1_2 mode default value for lf_extzero_ena
27280 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LFI_EXTZERO_P1_2_SETVAL_O (0x1<<7) // MSM Function P1_2 mode default value for lfi_extzero
27283 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_SOC_CLK_EN_P1_2_SETVAL_O (0x1<<0) // MSM Function P1_2 mode default value for soc_clk_en
27285 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_REFCLK_EN_P1_2_SETVAL_O (0x1<<1) // MSM Function P1_2 mode default value for refclk_en
27287 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PLL_LOCK_EN_P1_2_SETVAL_O (0x1<<2) // MSM Function P1_2 mode default value for pll_lock_en
27289 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_TXCLK_P1_2_SETVAL_O (0x1<<3) // Not used
27291 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_CLKDIV_P1_2_SETVAL_O (0x1<<4) // Not used
27293 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_P1_2_SETVAL_O (0x1<<5) // Not used
27295 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_LEFT_P1_2_SETVAL_O (0x1<<6) // Not used
27297 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_RIGHT_P1_2_SETVAL_O (0x1<<7) // Not used
27304 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
27307 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
27309 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
27312 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
27315 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0 (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
27317 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1 (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
27326 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_AHB_CHNG_REQ_Z_O (0x1<<6) // Not currently used
27336 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
27338 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
27340 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
27342 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O (0x1<<5) // Bist generator master reset.
27344 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
27346 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist generator generates data
27351 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
27363 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
27365 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
27370 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O (0x1<<3) // Bist checker mode select. 0X0 � UDP pattern. 0x1 � PRBS pattern
27374 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
27382 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
27424 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2 (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Select LANE registers
27426 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
27428 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
27436 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
27438 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
27440 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
27442 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override.
27456 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28 (0x1<<0) // Not currently used
27462 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8 (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
27480 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
27482 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
27484 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O (0x1<<2) // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
27494 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
27502 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O (0x1<<0) // Asserting this register will bypass the symbol aligner
27508 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O (0x1<<2) // Clears the elec idle control error flag
27510 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O (0x1<<3) // Override for ei_inferred signal
27512 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O (0x1<<4) // Override for ei_mask signal
27514 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O (0x1<<5) // Override for ei_exit_type signal
27516 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O (0x1<<6) // EI control override enable
27526 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O (0x1<<4) // Control signal to force decoder into loopback mode
27529 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O (0x1<<0) // FES loopback enable.
27531 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O (0x1<<1) // NES loopback enable.
27533 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O (0x1<<2) // HS recovered clock to transmit loopback enable.
27536 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O (0x1<<0) // RX boost override enable
27546 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
27548 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O (0x1<<7) // RX FL calibration clock DIV4 enable
27563 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O (0x1<<6) // DLPF DIV2 enable
27565 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O (0x1<<7) // CDR DivN clock divider enable.
27578 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
27583 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O (0x1<<3) // Override enable for RXVCOFR override vakue
27597 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
27599 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O (0x1<<2) // Reset signal for eye alignment mechanism.
27601 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
27603 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
27605 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
27618 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O (0x1<<4) // CDR clock divider bypass enable.
27623 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O (0x1<<5) // TX bleed enable
27626 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O (0x1<<0) // RX boost override enable.
27636 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXUP_GEN3_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
27638 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
27646 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O (0x1<<6) // DLPF DIV2 enable
27648 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O (0x1<<7) // CDR DivN clock divider enable.
27661 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_RXDWN_GEN3_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
27686 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0 (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
27688 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0 (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
27690 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA (0x1<<6) // enable override calibrated txterm value
27692 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
27700 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0 (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
27707 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O (0x1<<0) // DFE block enable signal.
27711 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
27713 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
27715 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
27717 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6 (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
27771 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS (0x1<<0) // Disable auto cal w/ rx_superbst
27775 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O (0x1<<5) // Enable Max limiting for BOOST auto-calibration
27782 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O (0x1<<2) // boost_adj_en
27784 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O (0x1<<3) // boost_adj_dir
27791 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O (0x1<<7) // CMP Offset Noise Averaging Enable
27799 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS (0x1<<6) // Disable auto cal w/ rx_att_gain
27801 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
27806 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O (0x1<<7) // Override enable for DFE signals.
27811 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
27818 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
27820 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6 (0x1<<6) // DFE TAP CMP no offset override enable
27822 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7 (0x1<<7) // DFE TAP override enable
27827 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0 (0x1<<5) // DFE offset calibrated value override enable
27829 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1 (0x1<<6) // DFE offset cal enable override
27831 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2 (0x1<<7) // DFE comparator cal enable override
27849 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ADAPT_EN_O_0 (0x1<<0) // TX Equalizer adaptation function enable
27851 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ERR_SIGN_O_1 (0x1<<1) // TX Equalizer Error Sign
27853 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_FW_OVRIDE_O_2 (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - Enbale firmware based adaptation
27868 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_TXEQ_TRAINING_PATT_O_8 (0x1<<0) // TX Equalizer Training Pattern
27872 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_TXEQ_DONT_CARE_O_8 (0x1<<0) // Mask bit for Txeq training pattern
27875 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7 (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
27878 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_INIT_RX_PRESET_HINT_EN_O (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
27880 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_RECAL_RX_PRESET_HINT_EN_O (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
27883 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_TXEQ_RXRECAL_DONE_I_0 (0x1<<0) // TX - RECAL RX Equalization status
27886 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_BLOCK_DEC_ERR (0x1<<0) // decoder sync header error
27889 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0 (0x1<<0) // cdfe enable bit. 1: enable cdfe when rate is 2'b01 or 2'b10. 0: disable cdfe.
27899 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO (0x1<<4) //
27901 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL (0x1<<5) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
27903 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL (0x1<<6) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
27905 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL (0x1<<7) // EI exit cdfe calibration enable. 1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. 0: the cdfe calibration is disabled when EI exits. Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
27908 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL (0x1<<0) // Continuous cdfe calibration enable. 1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. 0: the continuous cdfe calibration is disabled. Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
27910 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
27912 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL (0x1<<2) // Enables cdfe calibration post Txeq adaptation. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
27914 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibration. 0: disables cdfe calibration.
27916 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibration. 0: disables cdfe calibration.
27922 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll overwrite for cdfe. 0: disable coarse dll overwrite for cdfe.
28009 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll overwrite for cdfe. 0: disable fine dll overwrite for cdfe.
28012 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8 (0x1<<0) //
28014 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8 (0x1<<1) //
28016 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8 (0x1<<2) //
28018 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8 (0x1<<3) //
28025 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN (0x1<<0) // Override enable for CDFE calibration direction
28027 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL (0x1<<1) // Override value for CDFE calibration direction
28029 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
28031 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
28033 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
28035 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay overwrite for cdfe. 0: disable eye delay overwrite for cdfe.
28037 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
28041 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
28047 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
28049 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN (0x1<<1) // cdfe dlev overwrite enable. 1: enable dlev overwrite for cdfe. 0: disable dlev overwrite for cdfe.
28053 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8 (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
28075 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
28078 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
28080 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O (0x1<<1) //
28082 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O (0x1<<2) //
28084 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O (0x1<<7) //
28087 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O (0x1<<0) //
28089 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O (0x1<<1) //
28097 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O (0x1<<5) // Forces the positive dlev training pattern to be used
28099 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O (0x1<<6) // Forces the negative dlev training pattern to be used
28198 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
28200 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
28202 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
28204 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
28208 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
28211 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
28213 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
28215 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
28217 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
28219 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
28221 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
28223 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O (0x1<<6) // Used as Reg0 polarity select
28226 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
28228 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
28232 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24 (0x1<<5) // Bit 24: txdrv_c2_in[3]
28234 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O (0x1<<6) // Enable bit for width_chng module
28236 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O (0x1<<7) // Txterm calibration enable
28252 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O (0x1<<6) // 8b/10b encoder enable.
28254 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O (0x1<<7) // 8b/10b decoder enable.
28259 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_LN_COMMON_SYNC_TXCLK_EN_O (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
28264 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O (0x1<<5) // PIPE interface block enable.
28266 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O (0x1<<6) // SAPIS interface block enable.
28268 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE (0x1<<7) // Signal Detect USB mode enable
28271 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_ENC_CLR_ERR_O (0x1<<1) // 128b/130b encoder clear error
28273 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_EN_ERR_CHK_O (0x1<<3) // 130b/128b error check enable
28277 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CLR_ERR_O (0x1<<7) // 130b/128b: clear error flag
28285 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_RSTN_O (0x1<<0) // Synchronous clear for elastic buffer
28287 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_ALIGN_RSTN_O (0x1<<1) // Synchronous clear for block/symbol aligner
28289 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_SKP_ADD_EN_O (0x1<<2) // Elastic buffer SKP add enable
28291 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_RBUF_RSTN_O (0x1<<3) // TX FIFO synchronous reset
28293 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EN_SKPOS_ERR_O (0x1<<5) // Enables skpos error status propagation in Gen3
28298 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_BLOCK_ALIGN_CTRL_O (0x1<<6) // Disables the primary input lnX_block_align_control
28300 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_EIEOS_CHK_IN_LB_O (0x1<<7) // Disables the EIEOS check in loopback
28303 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_COEF_FE_LIMIT_EN_O (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
28305 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_RXVALID_DIS_AT_RATE_CHG_O_0 (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
28310 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_RX_GEARBOX_DISABLE_O (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
28312 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_TX_GEARBOX_DISABLE_O (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
28315 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
28317 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
28319 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
28321 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0 (0x1<<3) // Receive amplifier powerdown override, when cisel is high
28330 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O (0x1<<0) // Beacon Override Enable
28332 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O (0x1<<1) // Beacon Override
28334 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O (0x1<<2) // Enables 16b/20b decoder
28336 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O (0x1<<3) // Enables 16b/20b encoder
28354 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
28356 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
28365 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48 (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
28367 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
28371 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN (0x1<<6) // OOB detect enable
28373 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49 (0x1<<7) // OOB detect enable
28381 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50 (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
28384 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
28387 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
28389 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
28392 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
28395 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_CMU_SEL_O_0 (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
28397 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_TXCLK_SEL_O_1 (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
28406 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_AHB_CHNG_REQ_Z_O (0x1<<6) // Not currently used
28416 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_MODE8B_O (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
28418 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_ERR_O (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
28420 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_TX_CLOCK_ENABLE (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
28422 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_CDN_O (0x1<<5) // Bist generator master reset.
28424 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_WORD_O (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
28426 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_EN_O (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist generator generates data
28431 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_SEND_PREAM_O (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
28443 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_EN_O (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
28445 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_CLR_O (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
28450 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_DATA_MODE_O (0x1<<3) // Bist checker mode select. 0X0 � UDP pattern. 0x1 � PRBS pattern
28454 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_RX_CLOCK_ENABLE (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
28462 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_SYNC_ON_ZEROS (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
28504 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2 (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Select LANE registers
28506 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_TW_METHOD_EN (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
28508 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_PMA_LOAD_OVR (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
28516 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_OUT_OVR_EN_O (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
28518 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
28520 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
28522 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override.
28536 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_GCFSM_OVR_O_28 (0x1<<0) // Not currently used
28542 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8 (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
28560 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_TW_METHOD_EN (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
28562 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CONTROL_ATT_CTRL_O (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
28564 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_RXEQ_WAIT_EN_O (0x1<<2) // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
28574 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_CAL_LOAD_OVR (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
28582 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_SYM_ALIGN_BYPASS_O (0x1<<0) // Asserting this register will bypass the symbol aligner
28588 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_CLR_ERR_O (0x1<<2) // Clears the elec idle control error flag
28590 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_INFERRED_O (0x1<<3) // Override for ei_inferred signal
28592 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O (0x1<<4) // Override for ei_mask signal
28594 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O (0x1<<5) // Override for ei_exit_type signal
28596 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_OVR_O (0x1<<6) // EI control override enable
28606 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_LOOPBACK_EN_O (0x1<<4) // Control signal to force decoder into loopback mode
28609 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_FES_LB_ENA_O (0x1<<0) // FES loopback enable.
28611 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_NES_LB_ENA_O (0x1<<1) // NES loopback enable.
28613 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_RXCLK_LB_ENA_O (0x1<<2) // HS recovered clock to transmit loopback enable.
28616 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOST_OVR_O (0x1<<0) // RX boost override enable
28626 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXUP_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
28628 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXPREDIV4_ENA_O (0x1<<7) // RX FL calibration clock DIV4 enable
28643 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O (0x1<<6) // DLPF DIV2 enable
28645 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_CDR_DVDR_ENA_O (0x1<<7) // CDR DivN clock divider enable.
28658 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_RXDWN_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
28663 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_SEL_O (0x1<<3) // Override enable for RXVCOFR override vakue
28677 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_DLY_O_8_8 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
28679 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_SGN_RST_O (0x1<<2) // Reset signal for eye alignment mechanism.
28681 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_SD_BWSEL (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
28683 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA270_O (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
28685 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA90_O (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
28698 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_HSCLK_SEL_O (0x1<<4) // CDR clock divider bypass enable.
28703 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TXDRV_BLEED_ENA_O (0x1<<5) // TX bleed enable
28706 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O (0x1<<0) // RX boost override enable.
28716 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXUP_GEN3_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
28718 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
28726 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O (0x1<<6) // DLPF DIV2 enable
28728 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O (0x1<<7) // CDR DivN clock divider enable.
28741 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_RXDWN_GEN3_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
28766 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXP_MARGIN_ADD_0 (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
28768 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXN_MARGIN_ADD_0 (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
28770 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CX_OVR_ENA (0x1<<6) // enable override calibrated txterm value
28772 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TERM_EN_CAL_OVR (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
28780 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_0 (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
28787 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_EN_O (0x1<<0) // DFE block enable signal.
28791 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE1_CAL_EN_O_3 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
28793 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE2_CAL_EN_O_4 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
28795 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE3_CAL_EN_O_5 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
28797 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_FORCE_CAL_O_6 (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
28851 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RXEQ_SUPERBST_AUTOCAL_DIS (0x1<<0) // Disable auto cal w/ rx_superbst
28855 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_EN_O (0x1<<5) // Enable Max limiting for BOOST auto-calibration
28862 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_EN_O (0x1<<2) // boost_adj_en
28864 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_DIR_O (0x1<<3) // boost_adj_dir
28871 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_EN_O (0x1<<7) // CMP Offset Noise Averaging Enable
28879 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS (0x1<<6) // Disable auto cal w/ rx_att_gain
28881 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_SUPERBST_EN_INVERT_O (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
28886 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_EN_O (0x1<<7) // Override enable for DFE signals.
28891 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LATCH_O (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
28898 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_SUPERBST_ENA_OVR (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
28900 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6 (0x1<<6) // DFE TAP CMP no offset override enable
28902 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_OVR_EN_O_7 (0x1<<7) // DFE TAP override enable
28907 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0 (0x1<<5) // DFE offset calibrated value override enable
28909 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_EN_OVR_O_1 (0x1<<6) // DFE offset cal enable override
28911 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_CMP_CAL_EN_OVR_O_2 (0x1<<7) // DFE comparator cal enable override
28929 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ADAPT_EN_O_0 (0x1<<0) // TX Equalizer adaptation function enable
28931 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ERR_SIGN_O_1 (0x1<<1) // TX Equalizer Error Sign
28933 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_FW_OVRIDE_O_2 (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - Enbale firmware based adaptation
28948 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_TXEQ_TRAINING_PATT_O_8 (0x1<<0) // TX Equalizer Training Pattern
28952 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_TXEQ_DONT_CARE_O_8 (0x1<<0) // Mask bit for Txeq training pattern
28955 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_TXEQ_RXRECAL_INIT_O_7 (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
28958 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_INIT_RX_PRESET_HINT_EN_O (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
28960 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_RECAL_RX_PRESET_HINT_EN_O (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
28963 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_TXEQ_RXRECAL_DONE_I_0 (0x1<<0) // TX - RECAL RX Equalization status
28966 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_BLOCK_DEC_ERR (0x1<<0) // decoder sync header error
28969 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_EN_O_0 (0x1<<0) // cdfe enable bit. 1: enable cdfe when rate is 2'b01 or 2'b10. 0: disable cdfe.
28979 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_GO (0x1<<4) //
28981 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_FORCE_CAL (0x1<<5) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
28983 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_RATE_CHANGE_CAL (0x1<<6) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
28985 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_EI_EXIT_CAL (0x1<<7) // EI exit cdfe calibration enable. 1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. 0: the cdfe calibration is disabled when EI exits. Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
28988 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_CONT_CAL (0x1<<0) // Continuous cdfe calibration enable. 1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. 0: the continuous cdfe calibration is disabled. Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
28990 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
28992 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL (0x1<<2) // Enables cdfe calibration post Txeq adaptation. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
28994 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_CAL_EN (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibration. 0: disables cdfe calibration.
28996 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE2_CAL_EN (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibration. 0: disables cdfe calibration.
29002 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_AHB_CDFE_COARSE_DLL_OV_EN (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll overwrite for cdfe. 0: disable coarse dll overwrite for cdfe.
29089 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_FINE_DLL_OV_EN (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll overwrite for cdfe. 0: disable fine dll overwrite for cdfe.
29092 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8 (0x1<<0) //
29094 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8 (0x1<<1) //
29096 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8 (0x1<<2) //
29098 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8 (0x1<<3) //
29105 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_EN (0x1<<0) // Override enable for CDFE calibration direction
29107 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_VAL (0x1<<1) // Override value for CDFE calibration direction
29109 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA270_OVR_EN_O (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
29111 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA90_OVR_EN_O (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
29113 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_PHD_ENA_OVR_EN_O (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
29115 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_DLY_OVR_EN_O (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay overwrite for cdfe. 0: disable eye delay overwrite for cdfe.
29117 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
29121 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
29127 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
29129 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_DLEV_OV_EN (0x1<<1) // cdfe dlev overwrite enable. 1: enable dlev overwrite for cdfe. 0: disable dlev overwrite for cdfe.
29133 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8 (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
29155 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
29158 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
29160 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O (0x1<<1) //
29162 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O (0x1<<2) //
29164 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_AHB_CDFE_DFE_VAL_OVR_EN_O (0x1<<7) //
29167 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O (0x1<<0) //
29169 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_STROBE_EN_O (0x1<<1) //
29177 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O (0x1<<5) // Forces the positive dlev training pattern to be used
29179 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O (0x1<<6) // Forces the negative dlev training pattern to be used
29278 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_RX_SRC_O (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
29280 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_POL_O (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
29282 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_BIT_O (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
29284 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_WORD_O (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
29288 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_P2S_RBUF_AUTOFIX_O (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
29291 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_POL_O (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
29293 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_BIT_O (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
29295 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_WORD_O (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
29297 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_POL_O (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
29299 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_BIT_O (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
29301 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_WORD_O (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
29303 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG0_POL_O (0x1<<6) // Used as Reg0 polarity select
29306 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_BIT_O (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
29308 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_WORD_O (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
29312 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TX_CTRL_O_24 (0x1<<5) // Bit 24: txdrv_c2_in[3]
29314 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_WIDTH_CHNG_EN_O (0x1<<6) // Enable bit for width_chng module
29316 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TXTERM_CAL_SEQ_EN_O (0x1<<7) // Txterm calibration enable
29332 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_ENC_EN_O (0x1<<6) // 8b/10b encoder enable.
29334 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_DEC_EN_O (0x1<<7) // 8b/10b decoder enable.
29339 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_LN_COMMON_SYNC_TXCLK_EN_O (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
29344 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_PIPE_EN_O (0x1<<5) // PIPE interface block enable.
29346 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_SAPIS_EN_O (0x1<<6) // SAPIS interface block enable.
29348 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_USB_MODE (0x1<<7) // Signal Detect USB mode enable
29351 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_ENC_CLR_ERR_O (0x1<<1) // 128b/130b encoder clear error
29353 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_EN_ERR_CHK_O (0x1<<3) // 130b/128b error check enable
29357 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CLR_ERR_O (0x1<<7) // 130b/128b: clear error flag
29365 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_RSTN_O (0x1<<0) // Synchronous clear for elastic buffer
29367 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_ALIGN_RSTN_O (0x1<<1) // Synchronous clear for block/symbol aligner
29369 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_SKP_ADD_EN_O (0x1<<2) // Elastic buffer SKP add enable
29371 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_RBUF_RSTN_O (0x1<<3) // TX FIFO synchronous reset
29373 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EN_SKPOS_ERR_O (0x1<<5) // Enables skpos error status propagation in Gen3
29378 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_BLOCK_ALIGN_CTRL_O (0x1<<6) // Disables the primary input lnX_block_align_control
29380 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_EIEOS_CHK_IN_LB_O (0x1<<7) // Disables the EIEOS check in loopback
29383 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_COEF_FE_LIMIT_EN_O (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
29385 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_RXVALID_DIS_AT_RATE_CHG_O_0 (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
29390 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_RX_GEARBOX_DISABLE_O (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
29392 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_TX_GEARBOX_DISABLE_O (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
29395 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_GEN1_OLD_RXDATA_SRC (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
29397 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN3_O (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
29399 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN12_O (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
29401 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_AHB_LN_PD_RA_CISEL_OVR_O_0 (0x1<<3) // Receive amplifier powerdown override, when cisel is high
29410 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_ENA_O (0x1<<0) // Beacon Override Enable
29412 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_O (0x1<<1) // Beacon Override
29414 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_DEC_EN_OVR_O (0x1<<2) // Enables 16b/20b decoder
29416 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_ENC_EN_OVR_O (0x1<<3) // Enables 16b/20b encoder
29434 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
29436 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
29445 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_48 (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
29447 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_AHB_LN_IN_OVR_CHG_FLAG_O (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
29451 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_OOB_DET_EN (0x1<<6) // OOB detect enable
29453 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_49 (0x1<<7) // OOB detect enable
29461 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_LN_IN_OVR_O_50 (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
29464 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
29467 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
29469 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
29472 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
29475 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_CMU_SEL_O_0 (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
29477 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_TXCLK_SEL_O_1 (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
29486 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_AHB_CHNG_REQ_Z_O (0x1<<6) // Not currently used
29496 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_MODE8B_O (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
29498 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_ERR_O (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
29500 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_TX_CLOCK_ENABLE (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
29502 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_CDN_O (0x1<<5) // Bist generator master reset.
29504 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_WORD_O (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
29506 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_EN_O (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist generator generates data
29511 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_SEND_PREAM_O (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
29523 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_EN_O (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
29525 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_CLR_O (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
29530 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_DATA_MODE_O (0x1<<3) // Bist checker mode select. 0X0 � UDP pattern. 0x1 � PRBS pattern
29534 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_RX_CLOCK_ENABLE (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
29542 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_SYNC_ON_ZEROS (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
29584 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2 (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Select LANE registers
29586 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_TW_METHOD_EN (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
29588 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_PMA_LOAD_OVR (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
29596 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_OUT_OVR_EN_O (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
29598 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
29600 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
29602 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override.
29616 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_GCFSM_OVR_O_28 (0x1<<0) // Not currently used
29622 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8 (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
29640 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_TW_METHOD_EN (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
29642 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CONTROL_ATT_CTRL_O (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
29644 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_RXEQ_WAIT_EN_O (0x1<<2) // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
29654 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_CAL_LOAD_OVR (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
29662 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_SYM_ALIGN_BYPASS_O (0x1<<0) // Asserting this register will bypass the symbol aligner
29668 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_CLR_ERR_O (0x1<<2) // Clears the elec idle control error flag
29670 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_INFERRED_O (0x1<<3) // Override for ei_inferred signal
29672 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O (0x1<<4) // Override for ei_mask signal
29674 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O (0x1<<5) // Override for ei_exit_type signal
29676 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_OVR_O (0x1<<6) // EI control override enable
29686 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_LOOPBACK_EN_O (0x1<<4) // Control signal to force decoder into loopback mode
29689 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_FES_LB_ENA_O (0x1<<0) // FES loopback enable.
29691 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_NES_LB_ENA_O (0x1<<1) // NES loopback enable.
29693 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_RXCLK_LB_ENA_O (0x1<<2) // HS recovered clock to transmit loopback enable.
29696 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOST_OVR_O (0x1<<0) // RX boost override enable
29706 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXUP_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
29708 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXPREDIV4_ENA_O (0x1<<7) // RX FL calibration clock DIV4 enable
29723 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O (0x1<<6) // DLPF DIV2 enable
29725 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_CDR_DVDR_ENA_O (0x1<<7) // CDR DivN clock divider enable.
29738 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_RXDWN_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
29743 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_SEL_O (0x1<<3) // Override enable for RXVCOFR override vakue
29757 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_DLY_O_8_8 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
29759 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_SGN_RST_O (0x1<<2) // Reset signal for eye alignment mechanism.
29761 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_SD_BWSEL (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
29763 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA270_O (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
29765 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA90_O (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
29778 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_HSCLK_SEL_O (0x1<<4) // CDR clock divider bypass enable.
29783 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TXDRV_BLEED_ENA_O (0x1<<5) // TX bleed enable
29786 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O (0x1<<0) // RX boost override enable.
29796 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXUP_GEN3_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
29798 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
29806 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O (0x1<<6) // DLPF DIV2 enable
29808 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O (0x1<<7) // CDR DivN clock divider enable.
29821 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_RXDWN_GEN3_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
29846 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXP_MARGIN_ADD_0 (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
29848 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXN_MARGIN_ADD_0 (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
29850 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CX_OVR_ENA (0x1<<6) // enable override calibrated txterm value
29852 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TERM_EN_CAL_OVR (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
29860 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_0 (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
29867 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_EN_O (0x1<<0) // DFE block enable signal.
29871 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE1_CAL_EN_O_3 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
29873 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE2_CAL_EN_O_4 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
29875 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE3_CAL_EN_O_5 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
29877 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_FORCE_CAL_O_6 (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
29931 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RXEQ_SUPERBST_AUTOCAL_DIS (0x1<<0) // Disable auto cal w/ rx_superbst
29935 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_EN_O (0x1<<5) // Enable Max limiting for BOOST auto-calibration
29942 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_EN_O (0x1<<2) // boost_adj_en
29944 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_DIR_O (0x1<<3) // boost_adj_dir
29951 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_EN_O (0x1<<7) // CMP Offset Noise Averaging Enable
29959 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS (0x1<<6) // Disable auto cal w/ rx_att_gain
29961 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_SUPERBST_EN_INVERT_O (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
29966 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_EN_O (0x1<<7) // Override enable for DFE signals.
29971 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LATCH_O (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
29978 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_SUPERBST_ENA_OVR (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
29980 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6 (0x1<<6) // DFE TAP CMP no offset override enable
29982 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_OVR_EN_O_7 (0x1<<7) // DFE TAP override enable
29987 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0 (0x1<<5) // DFE offset calibrated value override enable
29989 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_EN_OVR_O_1 (0x1<<6) // DFE offset cal enable override
29991 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_CMP_CAL_EN_OVR_O_2 (0x1<<7) // DFE comparator cal enable override
30009 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ADAPT_EN_O_0 (0x1<<0) // TX Equalizer adaptation function enable
30011 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ERR_SIGN_O_1 (0x1<<1) // TX Equalizer Error Sign
30013 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_FW_OVRIDE_O_2 (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - Enbale firmware based adaptation
30028 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_TXEQ_TRAINING_PATT_O_8 (0x1<<0) // TX Equalizer Training Pattern
30032 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_TXEQ_DONT_CARE_O_8 (0x1<<0) // Mask bit for Txeq training pattern
30035 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_TXEQ_RXRECAL_INIT_O_7 (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
30038 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_INIT_RX_PRESET_HINT_EN_O (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
30040 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_RECAL_RX_PRESET_HINT_EN_O (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
30043 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_TXEQ_RXRECAL_DONE_I_0 (0x1<<0) // TX - RECAL RX Equalization status
30046 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_BLOCK_DEC_ERR (0x1<<0) // decoder sync header error
30049 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_EN_O_0 (0x1<<0) // cdfe enable bit. 1: enable cdfe when rate is 2'b01 or 2'b10. 0: disable cdfe.
30059 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_GO (0x1<<4) //
30061 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_FORCE_CAL (0x1<<5) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
30063 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_RATE_CHANGE_CAL (0x1<<6) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
30065 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_EI_EXIT_CAL (0x1<<7) // EI exit cdfe calibration enable. 1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. 0: the cdfe calibration is disabled when EI exits. Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
30068 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_CONT_CAL (0x1<<0) // Continuous cdfe calibration enable. 1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. 0: the continuous cdfe calibration is disabled. Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
30070 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
30072 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL (0x1<<2) // Enables cdfe calibration post Txeq adaptation. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
30074 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_CAL_EN (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibration. 0: disables cdfe calibration.
30076 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE2_CAL_EN (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibration. 0: disables cdfe calibration.
30082 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_AHB_CDFE_COARSE_DLL_OV_EN (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll overwrite for cdfe. 0: disable coarse dll overwrite for cdfe.
30169 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_FINE_DLL_OV_EN (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll overwrite for cdfe. 0: disable fine dll overwrite for cdfe.
30172 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8 (0x1<<0) //
30174 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8 (0x1<<1) //
30176 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8 (0x1<<2) //
30178 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8 (0x1<<3) //
30185 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_EN (0x1<<0) // Override enable for CDFE calibration direction
30187 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_VAL (0x1<<1) // Override value for CDFE calibration direction
30189 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA270_OVR_EN_O (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
30191 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA90_OVR_EN_O (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
30193 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_PHD_ENA_OVR_EN_O (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
30195 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_DLY_OVR_EN_O (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay overwrite for cdfe. 0: disable eye delay overwrite for cdfe.
30197 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
30201 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
30207 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
30209 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_DLEV_OV_EN (0x1<<1) // cdfe dlev overwrite enable. 1: enable dlev overwrite for cdfe. 0: disable dlev overwrite for cdfe.
30213 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8 (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
30235 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
30238 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
30240 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O (0x1<<1) //
30242 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O (0x1<<2) //
30244 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_AHB_CDFE_DFE_VAL_OVR_EN_O (0x1<<7) //
30247 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O (0x1<<0) //
30249 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_STROBE_EN_O (0x1<<1) //
30257 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O (0x1<<5) // Forces the positive dlev training pattern to be used
30259 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O (0x1<<6) // Forces the negative dlev training pattern to be used
30358 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_RX_SRC_O (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
30360 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_POL_O (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
30362 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_BIT_O (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
30364 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_WORD_O (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
30368 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_P2S_RBUF_AUTOFIX_O (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
30371 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_POL_O (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
30373 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_BIT_O (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
30375 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_WORD_O (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
30377 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_POL_O (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
30379 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_BIT_O (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
30381 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_WORD_O (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
30383 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG0_POL_O (0x1<<6) // Used as Reg0 polarity select
30386 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_BIT_O (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
30388 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_WORD_O (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
30392 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TX_CTRL_O_24 (0x1<<5) // Bit 24: txdrv_c2_in[3]
30394 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_WIDTH_CHNG_EN_O (0x1<<6) // Enable bit for width_chng module
30396 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TXTERM_CAL_SEQ_EN_O (0x1<<7) // Txterm calibration enable
30412 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_ENC_EN_O (0x1<<6) // 8b/10b encoder enable.
30414 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_DEC_EN_O (0x1<<7) // 8b/10b decoder enable.
30419 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_LN_COMMON_SYNC_TXCLK_EN_O (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
30424 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_PIPE_EN_O (0x1<<5) // PIPE interface block enable.
30426 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_SAPIS_EN_O (0x1<<6) // SAPIS interface block enable.
30428 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_USB_MODE (0x1<<7) // Signal Detect USB mode enable
30431 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_ENC_CLR_ERR_O (0x1<<1) // 128b/130b encoder clear error
30433 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_EN_ERR_CHK_O (0x1<<3) // 130b/128b error check enable
30437 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CLR_ERR_O (0x1<<7) // 130b/128b: clear error flag
30445 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_RSTN_O (0x1<<0) // Synchronous clear for elastic buffer
30447 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_ALIGN_RSTN_O (0x1<<1) // Synchronous clear for block/symbol aligner
30449 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_SKP_ADD_EN_O (0x1<<2) // Elastic buffer SKP add enable
30451 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_RBUF_RSTN_O (0x1<<3) // TX FIFO synchronous reset
30453 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EN_SKPOS_ERR_O (0x1<<5) // Enables skpos error status propagation in Gen3
30458 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_BLOCK_ALIGN_CTRL_O (0x1<<6) // Disables the primary input lnX_block_align_control
30460 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_EIEOS_CHK_IN_LB_O (0x1<<7) // Disables the EIEOS check in loopback
30463 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_COEF_FE_LIMIT_EN_O (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
30465 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_RXVALID_DIS_AT_RATE_CHG_O_0 (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
30470 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_RX_GEARBOX_DISABLE_O (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
30472 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_TX_GEARBOX_DISABLE_O (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
30475 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_GEN1_OLD_RXDATA_SRC (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
30477 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN3_O (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
30479 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN12_O (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
30481 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_AHB_LN_PD_RA_CISEL_OVR_O_0 (0x1<<3) // Receive amplifier powerdown override, when cisel is high
30490 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_ENA_O (0x1<<0) // Beacon Override Enable
30492 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_O (0x1<<1) // Beacon Override
30494 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_DEC_EN_OVR_O (0x1<<2) // Enables 16b/20b decoder
30496 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_ENC_EN_OVR_O (0x1<<3) // Enables 16b/20b encoder
30514 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
30516 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
30525 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_48 (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
30527 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_AHB_LN_IN_OVR_CHG_FLAG_O (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
30531 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_OOB_DET_EN (0x1<<6) // OOB detect enable
30533 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_49 (0x1<<7) // OOB detect enable
30541 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_LN_IN_OVR_O_50 (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
30544 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
30547 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
30549 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
30552 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
30555 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_CMU_SEL_O_0 (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30557 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_TXCLK_SEL_O_1 (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
30566 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_AHB_CHNG_REQ_Z_O (0x1<<6) // Not currently used
30576 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_MODE8B_O (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
30578 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_ERR_O (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
30580 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_TX_CLOCK_ENABLE (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
30582 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_CDN_O (0x1<<5) // Bist generator master reset.
30584 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_WORD_O (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
30586 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_EN_O (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist generator generates data
30591 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_SEND_PREAM_O (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
30603 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_EN_O (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
30605 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_CLR_O (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
30610 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_DATA_MODE_O (0x1<<3) // Bist checker mode select. 0X0 � UDP pattern. 0x1 � PRBS pattern
30614 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_RX_CLOCK_ENABLE (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
30622 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_SYNC_ON_ZEROS (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
30664 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2 (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Select LANE registers
30666 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_TW_METHOD_EN (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30668 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_PMA_LOAD_OVR (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
30676 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_OUT_OVR_EN_O (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
30678 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_LATCH_OVR_O (0x1<<5) // GCFSM pma_latch_o override
30680 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_GO_OVR_O (0x1<<6) // GCFSM pma_go_o override
30682 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_READ_OVR_O (0x1<<7) // GCFSM pma_read_o override.
30696 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_GCFSM_OVR_O_28 (0x1<<0) // Not currently used
30702 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8 (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
30720 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_TW_METHOD_EN (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30722 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CONTROL_ATT_CTRL_O (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
30724 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_RXEQ_WAIT_EN_O (0x1<<2) // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
30734 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_CAL_LOAD_OVR (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30742 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_SYM_ALIGN_BYPASS_O (0x1<<0) // Asserting this register will bypass the symbol aligner
30748 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_CLR_ERR_O (0x1<<2) // Clears the elec idle control error flag
30750 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_INFERRED_O (0x1<<3) // Override for ei_inferred signal
30752 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O (0x1<<4) // Override for ei_mask signal
30754 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O (0x1<<5) // Override for ei_exit_type signal
30756 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_OVR_O (0x1<<6) // EI control override enable
30766 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_LOOPBACK_EN_O (0x1<<4) // Control signal to force decoder into loopback mode
30769 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_FES_LB_ENA_O (0x1<<0) // FES loopback enable.
30771 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_NES_LB_ENA_O (0x1<<1) // NES loopback enable.
30773 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_RXCLK_LB_ENA_O (0x1<<2) // HS recovered clock to transmit loopback enable.
30776 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOST_OVR_O (0x1<<0) // RX boost override enable
30786 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXUP_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
30788 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXPREDIV4_ENA_O (0x1<<7) // RX FL calibration clock DIV4 enable
30803 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O (0x1<<6) // DLPF DIV2 enable
30805 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_CDR_DVDR_ENA_O (0x1<<7) // CDR DivN clock divider enable.
30818 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_RXDWN_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
30823 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_SEL_O (0x1<<3) // Override enable for RXVCOFR override vakue
30837 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_DLY_O_8_8 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
30839 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_SGN_RST_O (0x1<<2) // Reset signal for eye alignment mechanism.
30841 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_SD_BWSEL (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
30843 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA270_O (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
30845 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA90_O (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
30858 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_HSCLK_SEL_O (0x1<<4) // CDR clock divider bypass enable.
30863 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TXDRV_BLEED_ENA_O (0x1<<5) // TX bleed enable
30866 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O (0x1<<0) // RX boost override enable.
30876 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXUP_GEN3_O (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
30878 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
30886 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O (0x1<<6) // DLPF DIV2 enable
30888 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O (0x1<<7) // CDR DivN clock divider enable.
30901 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_RXDWN_GEN3_O (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
30926 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXP_MARGIN_ADD_0 (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
30928 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXN_MARGIN_ADD_0 (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
30930 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CX_OVR_ENA (0x1<<6) // enable override calibrated txterm value
30932 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TERM_EN_CAL_OVR (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
30940 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_0 (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
30947 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_EN_O (0x1<<0) // DFE block enable signal.
30951 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE1_CAL_EN_O_3 (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
30953 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE2_CAL_EN_O_4 (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
30955 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE3_CAL_EN_O_5 (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
30957 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_FORCE_CAL_O_6 (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
31011 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RXEQ_SUPERBST_AUTOCAL_DIS (0x1<<0) // Disable auto cal w/ rx_superbst
31015 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_EN_O (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31022 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_EN_O (0x1<<2) // boost_adj_en
31024 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_DIR_O (0x1<<3) // boost_adj_dir
31031 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_EN_O (0x1<<7) // CMP Offset Noise Averaging Enable
31039 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS (0x1<<6) // Disable auto cal w/ rx_att_gain
31041 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_SUPERBST_EN_INVERT_O (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
31046 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_EN_O (0x1<<7) // Override enable for DFE signals.
31051 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LATCH_O (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
31058 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_SUPERBST_ENA_OVR (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
31060 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6 (0x1<<6) // DFE TAP CMP no offset override enable
31062 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_OVR_EN_O_7 (0x1<<7) // DFE TAP override enable
31067 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0 (0x1<<5) // DFE offset calibrated value override enable
31069 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_EN_OVR_O_1 (0x1<<6) // DFE offset cal enable override
31071 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_CMP_CAL_EN_OVR_O_2 (0x1<<7) // DFE comparator cal enable override
31089 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ADAPT_EN_O_0 (0x1<<0) // TX Equalizer adaptation function enable
31091 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ERR_SIGN_O_1 (0x1<<1) // TX Equalizer Error Sign
31093 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_FW_OVRIDE_O_2 (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - Enbale firmware based adaptation
31108 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_TXEQ_TRAINING_PATT_O_8 (0x1<<0) // TX Equalizer Training Pattern
31112 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_TXEQ_DONT_CARE_O_8 (0x1<<0) // Mask bit for Txeq training pattern
31115 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_TXEQ_RXRECAL_INIT_O_7 (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
31118 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_INIT_RX_PRESET_HINT_EN_O (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
31120 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_RECAL_RX_PRESET_HINT_EN_O (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
31123 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_TXEQ_RXRECAL_DONE_I_0 (0x1<<0) // TX - RECAL RX Equalization status
31126 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_BLOCK_DEC_ERR (0x1<<0) // decoder sync header error
31129 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_EN_O_0 (0x1<<0) // cdfe enable bit. 1: enable cdfe when rate is 2'b01 or 2'b10. 0: disable cdfe.
31139 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_GO (0x1<<4) //
31141 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_FORCE_CAL (0x1<<5) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
31143 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_RATE_CHANGE_CAL (0x1<<6) // The cdfe force calibration enable. 1: enable force cdfe calibration. 0: disable force cdfe calibration. Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
31145 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_EI_EXIT_CAL (0x1<<7) // EI exit cdfe calibration enable. 1: the cdfe calibration is enabled when EI exits and when rate is 2'b01 or 2'b10. 0: the cdfe calibration is disabled when EI exits. Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
31148 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_CONT_CAL (0x1<<0) // Continuous cdfe calibration enable. 1: the continuous cdfe calibration is enabled when the rate is 2'b01 or 2'b10. 0: the continuous cdfe calibration is disabled. Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
31150 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
31152 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL (0x1<<2) // Enables cdfe calibration post Txeq adaptation. 1: the cdfe calibration is enabled when the rate is 2'b10. 0: the cdfe calibration is disabled.
31154 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_CAL_EN (0x1<<3) // Enables the cdfe calibration in rate3. 1: enables cdfe calibration. 0: disables cdfe calibration.
31156 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE2_CAL_EN (0x1<<4) // Enables the cdfe calibration in rate2. 1: enables cdfe calibration. 0: disables cdfe calibration.
31162 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_AHB_CDFE_COARSE_DLL_OV_EN (0x1<<7) // cdfe coarse dll overwrite enable. 1: enable coarse dll overwrite for cdfe. 0: disable coarse dll overwrite for cdfe.
31249 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_FINE_DLL_OV_EN (0x1<<4) // cdfe fine dll overwrite enable. 1: enable fine dll overwrite for cdfe. 0: disable fine dll overwrite for cdfe.
31252 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8 (0x1<<0) //
31254 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8 (0x1<<1) //
31256 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8 (0x1<<2) //
31258 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8 (0x1<<3) //
31265 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_EN (0x1<<0) // Override enable for CDFE calibration direction
31267 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_VAL (0x1<<1) // Override value for CDFE calibration direction
31269 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA270_OVR_EN_O (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
31271 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA90_OVR_EN_O (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
31273 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_PHD_ENA_OVR_EN_O (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
31275 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_DLY_OVR_EN_O (0x1<<5) // cdfe eye delay overwrite enable. 1: enable eye delay overwrite for cdfe. 0: disable eye delay overwrite for cdfe.
31277 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
31281 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
31287 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8 (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
31289 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_DLEV_OV_EN (0x1<<1) // cdfe dlev overwrite enable. 1: enable dlev overwrite for cdfe. 0: disable dlev overwrite for cdfe.
31293 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8 (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
31315 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
31318 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
31320 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O (0x1<<1) //
31322 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O (0x1<<2) //
31324 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_AHB_CDFE_DFE_VAL_OVR_EN_O (0x1<<7) //
31327 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O (0x1<<0) //
31329 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_STROBE_EN_O (0x1<<1) //
31337 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O (0x1<<5) // Forces the positive dlev training pattern to be used
31339 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O (0x1<<6) // Forces the negative dlev training pattern to be used
31438 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_RX_SRC_O (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
31440 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_POL_O (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
31442 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_BIT_O (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
31444 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_WORD_O (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
31448 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_P2S_RBUF_AUTOFIX_O (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
31451 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_POL_O (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
31453 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_BIT_O (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
31455 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_WORD_O (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
31457 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_POL_O (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
31459 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_BIT_O (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
31461 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_WORD_O (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
31463 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG0_POL_O (0x1<<6) // Used as Reg0 polarity select
31466 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_BIT_O (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
31468 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_WORD_O (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
31472 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TX_CTRL_O_24 (0x1<<5) // Bit 24: txdrv_c2_in[3]
31474 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_WIDTH_CHNG_EN_O (0x1<<6) // Enable bit for width_chng module
31476 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TXTERM_CAL_SEQ_EN_O (0x1<<7) // Txterm calibration enable
31492 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_ENC_EN_O (0x1<<6) // 8b/10b encoder enable.
31494 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_DEC_EN_O (0x1<<7) // 8b/10b decoder enable.
31499 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_LN_COMMON_SYNC_TXCLK_EN_O (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
31504 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_PIPE_EN_O (0x1<<5) // PIPE interface block enable.
31506 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_SAPIS_EN_O (0x1<<6) // SAPIS interface block enable.
31508 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_USB_MODE (0x1<<7) // Signal Detect USB mode enable
31511 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_ENC_CLR_ERR_O (0x1<<1) // 128b/130b encoder clear error
31513 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_EN_ERR_CHK_O (0x1<<3) // 130b/128b error check enable
31517 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CLR_ERR_O (0x1<<7) // 130b/128b: clear error flag
31525 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_RSTN_O (0x1<<0) // Synchronous clear for elastic buffer
31527 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_ALIGN_RSTN_O (0x1<<1) // Synchronous clear for block/symbol aligner
31529 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_SKP_ADD_EN_O (0x1<<2) // Elastic buffer SKP add enable
31531 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_RBUF_RSTN_O (0x1<<3) // TX FIFO synchronous reset
31533 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EN_SKPOS_ERR_O (0x1<<5) // Enables skpos error status propagation in Gen3
31538 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_BLOCK_ALIGN_CTRL_O (0x1<<6) // Disables the primary input lnX_block_align_control
31540 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_EIEOS_CHK_IN_LB_O (0x1<<7) // Disables the EIEOS check in loopback
31543 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_COEF_FE_LIMIT_EN_O (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
31545 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_RXVALID_DIS_AT_RATE_CHG_O_0 (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
31550 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_RX_GEARBOX_DISABLE_O (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
31552 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_TX_GEARBOX_DISABLE_O (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
31555 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_GEN1_OLD_RXDATA_SRC (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
31557 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN3_O (0x1<<1) // To skip cdr calibration routines for PCIe gen3. Can be used when PHY is operating in gen1,2 only.
31559 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN12_O (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2. May not be needed in real scenario.
31561 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_AHB_LN_PD_RA_CISEL_OVR_O_0 (0x1<<3) // Receive amplifier powerdown override, when cisel is high
31570 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_ENA_O (0x1<<0) // Beacon Override Enable
31572 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_O (0x1<<1) // Beacon Override
31574 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_DEC_EN_OVR_O (0x1<<2) // Enables 16b/20b decoder
31576 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_ENC_EN_OVR_O (0x1<<3) // Enables 16b/20b encoder
31594 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
31596 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
31605 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_48 (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
31607 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_AHB_LN_IN_OVR_CHG_FLAG_O (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
31611 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_OOB_DET_EN (0x1<<6) // OOB detect enable
31613 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_49 (0x1<<7) // OOB detect enable
31621 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_LN_IN_OVR_O_50 (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
31624 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - gcfsm_refmux_clk = lane_ref_clk
31627 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O (0x1<<0) // Enable/Disable the internal PRBS data pattern inverter. 0x0 � Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
31629 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O (0x1<<1) // Enable/Disable the internal PRBS data pattern inverter. 0x0 � Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
31659 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_SYNC_HDR_QUAL_EN_O (0x1<<0) // Enables block_aligner skpos_hdr_det qualification
31669 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_EN_O (0x1<<2) // Elastic buffer enable
31699 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O (0x1<<1) // Enable resetting of railed DLPF
31702 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O (0x1<<0) // Enable DOSC adjustement for railed DLPF
31706 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O (0x1<<6) // Default DOSC adjustement direction for railed DLPF
31716 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_DIV_OVRD_O (0x1<<0) //
31718 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_SEL_O (0x1<<1) //
31722 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_EN_O (0x1<<6) //
31730 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN0_INTRPT_I_0 (0x1<<0) //
31732 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN1_INTRPT_I_1 (0x1<<1) //
31734 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN2_INTRPT_I_2 (0x1<<2) //
31736 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN3_INTRPT_I_3 (0x1<<3) //
31739 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O (0x1<<0) // Enable eye scan counter
31741 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O (0x1<<1) // Run eye scan counter
31743 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O (0x1<<2) // Shift edge samples
31745 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O (0x1<<3) // Determines shift direction of edge samples
31747 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O (0x1<<4) // Shift edge samples by 2 bits
31844 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O (0x1<<0) // Enables programmable tx det rx pulse
31851 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
31853 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
31855 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
31857 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
31859 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
31861 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
31863 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
31865 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
31868 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
31870 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
31872 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
31874 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
31876 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
31878 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
31880 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
31882 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
31885 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
31887 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
31889 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
31891 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
31893 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
31895 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
31897 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
31899 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
31902 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
31904 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
31906 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
31908 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
31911 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
31913 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
31915 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
31917 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
31919 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
31921 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
31923 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
31925 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
31928 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
31930 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
31932 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
31934 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
31936 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
31938 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
31940 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
31942 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
31945 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
31947 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
31949 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
31951 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
31953 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
31955 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
31957 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
31959 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
31962 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
31964 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
31966 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
31968 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
31971 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
31973 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
31975 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
31977 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
31979 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
31981 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
31983 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
31985 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
31988 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
31990 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
31992 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
31994 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
31996 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
31998 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
32000 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
32002 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
32005 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
32007 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
32009 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
32011 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
32013 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
32015 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
32017 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
32019 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
32022 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
32024 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
32026 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
32028 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
32031 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
32033 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
32035 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
32037 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
32039 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
32041 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
32043 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
32045 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
32048 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
32050 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
32052 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
32054 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
32056 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
32058 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
32060 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
32062 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
32065 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
32067 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
32069 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
32071 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
32073 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
32075 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
32077 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
32079 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
32082 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
32084 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
32086 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
32088 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
32091 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
32093 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
32095 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
32097 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
32099 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
32101 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
32103 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
32105 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
32108 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
32110 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
32112 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
32114 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
32116 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
32118 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
32120 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
32122 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
32125 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
32127 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
32129 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
32131 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
32133 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
32135 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
32137 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
32139 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
32142 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
32144 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
32146 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
32148 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
32158 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8 (0x1<<0) // OOB detector COMINIT maximum idle length.
32162 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8 (0x1<<0) // OOB detector COMINIT maximum idle length.
32166 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8 (0x1<<0) // OOB detector COMWAKE minimum idle length.
32170 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8 (0x1<<0) // OOB detector COMWAKE maximum idle length.
32174 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8 (0x1<<0) // OOB detector COMSAS maximum idle length.
32178 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8 (0x1<<0) // OOB detector COMSAS maximum idle length.
32258 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_PREEM_1LSB_MODE (0x1<<0) // TX 1lsb mode
32260 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_MASTER_PREEM_1LSB_MODE_OVR (0x1<<1) // TX master 1lsb mode overrides.
32271 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_OVR_EN_O (0x1<<6) // Tx control master override enable
32319 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O (0x1<<6) // Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed
32321 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O (0x1<<7) // Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed
32332 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O (0x1<<6) // Enable phase detector during CDR VCO calibration
32337 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O (0x1<<4) // Assertion causes repeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are selected by rxeq_recal_o[6:0]/rxeq_rate2_recal_o[6:0].
32339 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O (0x1<<6) // Set all DFE calibration values to mid-scale instead of using start values at start of calibration
32353 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O (0x1<<0) // Repeat calibration whenever exiting RX electrical idle. Calibrations performed are selected by rxeq_recal_o[6:0]/rxeq_lane2_recal_o[6:0]
32388 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O (0x1<<0) // comparator offset override enable
32395 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
32402 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for boost
32406 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap1
32410 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap2
32414 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap3
32418 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap4
32422 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for DFE tap5
32427 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O (0x1<<6) // RXEQ ctrl_test mode enable
32429 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O (0x1<<7) // Step calibration in test mode, rising edge triggers step
32434 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O (0x1<<7) // Take the floor of the calibration result
32445 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O (0x1<<5) // Reverse order of tap power down signals
32450 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O (0x1<<5) // By pass comparator DC offset calibration
32452 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O (0x1<<6) // Changes the dfe tap offset cal direction
32456 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for boost in rate2
32460 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8 (0x1<<0) // Training pattern for boost in rate3
32474 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL (0x1<<7) // DFE shadow offset read select
32503 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
32509 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8 (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
32511 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1 (0x1<<1) // Initiate TXEQ adaptation for Gen3 rate
32515 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_TXEQ_TRAINING_PATT_O_8 (0x1<<0) // TX Equalizer Training Pattern select
32519 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_TXEQ_DONT_CARE_O_8 (0x1<<0) // TX Equalizer Training Pattern mask during Link Training
32690 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN (0x1<<0) //
32692 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN (0x1<<1) //
32740 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN (0x1<<6) //
32750 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O (0x1<<7) //
32763 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O (0x1<<3) //
32767 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32769 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32771 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32773 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32775 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32777 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32779 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32781 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32784 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32786 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32788 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32790 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32792 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32794 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32796 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32798 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32801 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32803 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32805 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32807 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32809 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32811 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32813 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32815 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32818 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32820 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32822 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32824 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32827 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32829 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32831 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32833 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32835 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32837 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32839 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32841 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32844 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32846 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32848 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32850 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32852 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32854 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32856 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32858 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32861 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32863 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32865 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32867 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32869 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32871 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32873 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32875 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32878 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32880 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32882 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32884 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32887 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32889 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32891 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32893 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32895 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32897 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32899 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32901 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32904 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32906 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32908 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32910 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32912 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32914 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32916 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32918 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32921 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32923 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32925 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32927 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32929 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32931 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32933 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32935 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32938 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32940 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32942 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32944 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32947 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32949 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32951 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32953 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32955 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32957 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32959 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32961 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32964 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32966 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32968 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32970 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32972 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32974 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32976 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32978 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32981 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32983 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32985 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32987 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32989 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32991 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32993 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32995 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
32998 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
33000 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
33002 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
33004 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
33013 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O (0x1<<0) // Lane0 master reset
33015 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O (0x1<<1) // Lane1 master reset
33017 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O (0x1<<2) // Lane2 master reset
33019 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O (0x1<<3) // Lane3 master reset
33022 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O (0x1<<0) // fast_sim_register
33034 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0 (0x1<<3) // CMU OK Status
33036 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1 (0x1<<4) // CMU1 OK Status
33039 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0 (0x1<<0) // Lane 0 Signal Detect Valid Status
33041 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1 (0x1<<1) // Lane 1 Signal Detect Valid Status
33043 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2 (0x1<<2) // Lane 2 Signal Detect Valid Status
33045 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3 (0x1<<3) // Lane 3 Signal Detect Valid Status
33047 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4 (0x1<<4) // Lane 0 OK Status
33049 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5 (0x1<<5) // Lane 1 OK Status
33051 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6 (0x1<<6) // Lane 2 OK Status
33053 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7 (0x1<<7) // Lane 3 OK Status
33065 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_EI_GLUE_EN_O (0x1<<0) // Unused
33068 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_GEN12_ONLY_O (0x1<<0) // Newly added for PCIe3 1CMU
33070 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RESETN_RESET_CMU_EN_O (0x1<<1) // Newly added for PCIe3 1CMU
33072 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_EN_O (0x1<<2) // Newly added for PCIe3 1CMU
33074 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_O (0x1<<3) // Newly added for PCIe3 1CMU
33076 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_EN_O (0x1<<4) // Newly added for PCIe3 1CMU
33078 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_O (0x1<<5) // Newly added for PCIe3 1CMU
33080 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_EN_O (0x1<<6) // Newly added for PCIe3 1CMU
33082 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_O (0x1<<7) // Newly added for PCIe3 1CMU
33087 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_EN_O (0x1<<4) // Newly added for PCIe3 1CMU
33089 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_O (0x1<<5) // Newly added for PCIe3 1CMU
33228 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33230 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33232 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33234 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33236 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33238 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33240 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33242 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33245 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33247 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33249 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33251 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33253 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33255 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33257 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33259 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33262 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33264 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33266 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33268 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33270 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33272 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33274 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33276 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33279 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33281 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33283 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33285 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33288 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33290 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33292 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33294 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33296 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33298 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33300 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33302 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33305 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33307 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33309 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33311 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33313 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33315 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33317 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33319 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33322 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33324 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33326 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33328 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33330 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33332 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33334 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33336 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33339 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33341 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33343 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33345 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33348 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33350 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33352 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33354 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33356 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33358 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33360 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33362 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33365 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33367 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33369 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33371 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33373 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33375 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33377 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33379 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33382 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33384 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33386 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33388 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33390 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33392 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33394 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33396 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33399 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33401 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33403 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33405 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
33427 #define MISC_REG_INT_STS 0x008180UL //Access:R DataWidth:0x1 // Multi Field Register.
33428 #define MISC_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
33430 #define MISC_REG_INT_MASK 0x008184UL //Access:RW DataWidth:0x1 // Multi Field Register.
33431 #define MISC_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MISC_REG_INT_STS.ADDRESS_ERROR .
33433 #define MISC_REG_INT_STS_WR 0x008188UL //Access:WR DataWidth:0x1 // Multi Field Register.
33434 #define MISC_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
33436 #define MISC_REG_INT_STS_CLR 0x00818cUL //Access:RC DataWidth:0x1 // Multi Field Register.
33437 #define MISC_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
33439 #define MISC_REG_AEU_GENERAL_ATTN_0 0x008400UL //Access:RW DataWidth:0x1 // Set/clr general attention 0; this will set/clr bit 48 in AEU vector.
33440 #define MISC_REG_AEU_GENERAL_ATTN_1 0x008404UL //Access:RW DataWidth:0x1 // Set/clr general attention 1; this will set/clr bit 49 in AEU vector.
33441 #define MISC_REG_AEU_GENERAL_ATTN_2 0x008408UL //Access:RW DataWidth:0x1 // Set/clr general attention 2; this will set/clr bit 50 in AEU vector.
33442 #define MISC_REG_AEU_GENERAL_ATTN_3 0x00840cUL //Access:RW DataWidth:0x1 // Set/clr general attention 3; this will set/clr bit 51 in AEU vector.
33443 #define MISC_REG_AEU_GENERAL_ATTN_4 0x008410UL //Access:RW DataWidth:0x1 // Set/clr general attention 4; this will set/clr bit 52 in AEU vector.
33444 #define MISC_REG_AEU_GENERAL_ATTN_5 0x008414UL //Access:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
33445 #define MISC_REG_AEU_GENERAL_ATTN_6 0x008418UL //Access:RW DataWidth:0x1 // Set/clr general attention 6; this will set/clr bit 54 in AEU vector.
33446 #define MISC_REG_AEU_GENERAL_ATTN_7 0x00841cUL //Access:RW DataWidth:0x1 // Set/clr general attention 7; this will set/clr bit 55 in AEU vector.
33447 #define MISC_REG_AEU_GENERAL_ATTN_8 0x008420UL //Access:RW DataWidth:0x1 // Set/clr general attention 8; this will set/clr bit 56 in AEU vector.
33448 #define MISC_REG_AEU_GENERAL_ATTN_9 0x008424UL //Access:RW DataWidth:0x1 // Set/clr general attention 9; this will set/clr bit 57 in AEU vector.
33449 #define MISC_REG_AEU_GENERAL_ATTN_10 0x008428UL //Access:RW DataWidth:0x1 // Set/clr general attention 10; this will set/clr bit 58 in AEU vector.
33450 #define MISC_REG_AEU_GENERAL_ATTN_11 0x00842cUL //Access:RW DataWidth:0x1 // Set/clr general attention 11; this will set/clr bit 59 in AEU vector.
33451 #define MISC_REG_AEU_GENERAL_ATTN_12 0x008430UL //Access:RW DataWidth:0x1 // Set/clr general attention 12; this will set/clr bit 60 in AEU vector.
33452 #define MISC_REG_AEU_GENERAL_ATTN_13 0x008434UL //Access:RW DataWidth:0x1 // Set/clr general attention 13; this will set/clr bit 61 in AEU vector.
33453 #define MISC_REG_AEU_GENERAL_ATTN_14 0x008438UL //Access:RW DataWidth:0x1 // Set/clr general attention 14; this will set/clr bit 62 in AEU vector.
33454 #define MISC_REG_AEU_GENERAL_ATTN_15 0x00843cUL //Access:RW DataWidth:0x1 // Set/clr general attention 15; this will set/clr bit 63 in AEU vector.
33455 #define MISC_REG_AEU_GENERAL_ATTN_16 0x008440UL //Access:RW DataWidth:0x1 // Set/clr general attention 16; this will set/clr bit 64 in AEU vector.
33456 #define MISC_REG_AEU_GENERAL_ATTN_17 0x008444UL //Access:RW DataWidth:0x1 // Set/clr general attention 17; this will set/clr bit 65 in AEU vector.
33457 #define MISC_REG_AEU_GENERAL_ATTN_18 0x008448UL //Access:RW DataWidth:0x1 // Set/clr general attention 18; this will set/clr bit 66 in AEU vector.
33458 #define MISC_REG_AEU_GENERAL_ATTN_19 0x00844cUL //Access:RW DataWidth:0x1 // Set/clr general attention 19; this will set/clr bit 67 in AEU vector.
33459 #define MISC_REG_AEU_GENERAL_ATTN_20 0x008450UL //Access:RW DataWidth:0x1 // Set/clr general attention 20; this will set/clr bit 68 in AEU vector.
33460 #define MISC_REG_AEU_GENERAL_ATTN_21 0x008454UL //Access:RW DataWidth:0x1 // Set/clr general attention 21; this will set/clr bit 69 in AEU vector.
33461 #define MISC_REG_AEU_GENERAL_ATTN_22 0x008458UL //Access:RW DataWidth:0x1 // Set/clr general attention 22; this will set/clr bit 70 in AEU vector.
33462 #define MISC_REG_AEU_GENERAL_ATTN_23 0x00845cUL //Access:RW DataWidth:0x1 // Set/clr general attention 23; this will set/clr bit 71 in AEU vector.
33463 #define MISC_REG_AEU_GENERAL_ATTN_24 0x008460UL //Access:RW DataWidth:0x1 // Set/clr general attention 24; this will set/clr bit 72 in AEU vector.
33464 #define MISC_REG_AEU_GENERAL_ATTN_25 0x008464UL //Access:RW DataWidth:0x1 // Set/clr general attention 25; this will set/clr bit 73 in AEU vector.
33465 #define MISC_REG_AEU_GENERAL_ATTN_26 0x008468UL //Access:RW DataWidth:0x1 // Set/clr general attention 26; this will set/clr bit 74 in AEU vector.
33466 #define MISC_REG_AEU_GENERAL_ATTN_27 0x00846cUL //Access:RW DataWidth:0x1 // Set/clr general attention 27; this will set/clr bit 75 in AEU vector.
33467 #define MISC_REG_AEU_GENERAL_ATTN_28 0x008470UL //Access:RW DataWidth:0x1 // Set/clr general attention 28; this will set/clr bit 76 in AEU vector.
33468 #define MISC_REG_AEU_GENERAL_ATTN_29 0x008474UL //Access:RW DataWidth:0x1 // Set/clr general attention 29; this will set/clr bit 77 in AEU vector.
33469 #define MISC_REG_AEU_GENERAL_ATTN_30 0x008478UL //Access:RW DataWidth:0x1 // Set/clr general attention 30; this will set/clr bit 78 in AEU vector.
33470 #define MISC_REG_AEU_GENERAL_ATTN_31 0x00847cUL //Access:RW DataWidth:0x1 // Set/clr general attention 31; this will set/clr bit 79 in AEU vector.
33471 #define MISC_REG_AEU_GENERAL_ATTN_32 0x008480UL //Access:RW DataWidth:0x1 // Set/clr general attention 32; this will set/clr bit 80 in AEU vector.
33472 #define MISC_REG_AEU_GENERAL_ATTN_33 0x008484UL //Access:RW DataWidth:0x1 // Set/clr general attention 33; this will set/clr bit 81 in AEU vector.
33473 #define MISC_REG_AEU_GENERAL_ATTN_34 0x008488UL //Access:RW DataWidth:0x1 // Set/clr general attention 34; this will set/clr bit 82 in AEU vector.
33474 #define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL //Access:RW DataWidth:0x1 // Set/clr general attention 35; this will set/clr bit 83 in AEU vector.
33475 #define MISC_REG_AEU_EVENT_ENABLE 0x008490UL //Access:RW DataWidth:0x1 // Event_enable control; when this bit is clear the event enable toward the MCP is masked.
33694 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0x0087fcUL //Access:RW DataWidth:0x1 // If set a system kill occurred. Reset on POR reset.
33695 #define MISC_REG_AEU_SYS_KILL_BEHAVIOR 0x008800UL //Access:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Reset on POR reset.
33706 #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK (0x1<<0) // Pxp close the gate mask bit; 0 = masked; 1 = unmasked.
33708 #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK (0x1<<1) // Nig close the gate mask bit; 0 = masked; 1 = unmasked.
33710 #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK (0x1<<2) // System kill mask bit; 0 = masked; 1 = unmasked.
33712 #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK (0x1<<3) // Global uncorrectable error mask bit; 0 = masked; 1 = unmasked.
33722 #define MISC_REG_OPTE_MODE 0x008c0cUL //Access:RW DataWidth:0x1 // 0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs.
33724 #define MISC_REG_BLOCK_256B_EN 0x008c14UL //Access:RW DataWidth:0x1 // This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset.
33725 #define MISC_REG_PERST_STATUS 0x008c18UL //Access:R DataWidth:0x1 // PERST_B status.
33769 #define MISCS_REG_BLOCK_256B_EN 0x009074UL //Access:RW DataWidth:0x1 // This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset.
33823 #define MISCS_REG_MEMCTRL_WR_RD_N 0x009160UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
33827 #define MISCS_REG_BSC_SMBIO_ENABLE_GLITCH_FILTER 0x009170UL //Access:RW DataWidth:0x1 // When set enables the deglitching circuit for the SMBus inputs per I2C requirement.
33829 #define MISCS_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
33831 #define MISCS_REG_INT_STS_0_GENERIC_SW (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
33833 #define MISCS_REG_INT_STS_0_CNIG_INTERRUPT (0x1<<2) // CNIG HW interrupt.
33836 #define MISCS_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.ADDRESS_ERROR .
33838 #define MISCS_REG_INT_MASK_0_GENERIC_SW (0x1<<1) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.GENERIC_SW .
33840 #define MISCS_REG_INT_MASK_0_CNIG_INTERRUPT (0x1<<2) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.CNIG_INTERRUPT .
33843 #define MISCS_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
33845 #define MISCS_REG_INT_STS_WR_0_GENERIC_SW (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
33847 #define MISCS_REG_INT_STS_WR_0_CNIG_INTERRUPT (0x1<<2) // CNIG HW interrupt.
33850 #define MISCS_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
33852 #define MISCS_REG_INT_STS_CLR_0_GENERIC_SW (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
33854 #define MISCS_REG_INT_STS_CLR_0_CNIG_INTERRUPT (0x1<<2) // CNIG HW interrupt.
33857 #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG1 (0x1<<0) // DORQ FIFO error interrupt for engine 1
33859 #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG0 (0x1<<1) // DORQ FIFO error interrupt for engine 0
33861 #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG1 (0x1<<2) // DBG FIFO error interrupt for engine 1
33863 #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG0 (0x1<<3) // DBG FIFO error interrupt for engine 0
33865 #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG1 (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
33867 #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG0 (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
33869 #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG1 (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
33871 #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG0 (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
33873 #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG1 (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
33875 #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG0 (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
33877 #define MISCS_REG_INT_STS_1_OPTE_STORM_FIFO_ERR_ENG0 (0x1<<10) // STORM FIFO error interrupt
33880 #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG1 (0x1<<0) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DORQ_FIFO_ERR_ENG1 .
33882 #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG0 (0x1<<1) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DORQ_FIFO_ERR_ENG0 .
33884 #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG1 (0x1<<2) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DBG_FIFO_ERR_ENG1 .
33886 #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG0 (0x1<<3) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DBG_FIFO_ERR_ENG0 .
33888 #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG1 (0x1<<4) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF1_FIFO_ERR_ENG1 .
33890 #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG0 (0x1<<5) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF1_FIFO_ERR_ENG0 .
33892 #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG1 (0x1<<6) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF0_FIFO_ERR_ENG1 .
33894 #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG0 (0x1<<7) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF0_FIFO_ERR_ENG0 .
33896 #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG1 (0x1<<8) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_SOP_FIFO_ERR_ENG1 .
33898 #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG0 (0x1<<9) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_SOP_FIFO_ERR_ENG0 .
33900 #define MISCS_REG_INT_MASK_1_OPTE_STORM_FIFO_ERR_ENG0 (0x1<<10) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_STORM_FIFO_ERR_ENG0 .
33903 #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG1 (0x1<<0) // DORQ FIFO error interrupt for engine 1
33905 #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG0 (0x1<<1) // DORQ FIFO error interrupt for engine 0
33907 #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG1 (0x1<<2) // DBG FIFO error interrupt for engine 1
33909 #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG0 (0x1<<3) // DBG FIFO error interrupt for engine 0
33911 #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1 (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
33913 #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0 (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
33915 #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1 (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
33917 #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0 (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
33919 #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1 (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
33921 #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0 (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
33923 #define MISCS_REG_INT_STS_WR_1_OPTE_STORM_FIFO_ERR_ENG0 (0x1<<10) // STORM FIFO error interrupt
33926 #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG1 (0x1<<0) // DORQ FIFO error interrupt for engine 1
33928 #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG0 (0x1<<1) // DORQ FIFO error interrupt for engine 0
33930 #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG1 (0x1<<2) // DBG FIFO error interrupt for engine 1
33932 #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG0 (0x1<<3) // DBG FIFO error interrupt for engine 0
33934 #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1 (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
33936 #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0 (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
33938 #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1 (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
33940 #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0 (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
33942 #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1 (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
33944 #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0 (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
33946 #define MISCS_REG_INT_STS_CLR_1_OPTE_STORM_FIFO_ERR_ENG0 (0x1<<10) // STORM FIFO error interrupt
33948 #define MISCS_REG_PRTY_MASK_0 0x0091a4UL //Access:RW DataWidth:0x1 // Multi Field Register.
33949 #define MISCS_REG_PRTY_MASK_0_CNIG_PARITY (0x1<<0) // This bit masks, when set, the Parity bit: MISCS_REG_PRTY_STS_0.CNIG_PARITY .
33951 #define MISCS_REG_PCIE_LINK_UP_STATE 0x0093c0UL //Access:R DataWidth:0x1 // Indicates the current state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the beginning of PCIe link up.
33952 #define MISCS_REG_PCIE_HOT_RESET_STATE 0x0093c4UL //Access:R DataWidth:0x1 // Indicates the current state of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the beginning of PCIe hot reset.
33956 #define MISCS_REG_MAIN_PLL_STATUS 0x0093d4UL //Access:RW DataWidth:0x1 // Set to 1 when main PLL lock indication is de-asserted when hard reset is de-asserted. Reset to 0 by FW. Is reset on POR reset.
34107 #define MISCS_REG_PCIE_CORE_RST_N_STATUS 0x00965cUL //Access:RW DataWidth:0x1 // When 0, indicated PCIE EP controller is in reset, except for PMC module. Refer to PCIE EP controller databook.
34108 #define MISCS_REG_PCIE_PHY_RST_N_STATUS 0x009660UL //Access:RW DataWidth:0x1 // When 0, indicated PCIE PHY is in reset Refer to PCIE PHY user manual.
34109 #define MISCS_REG_CORE_RST_N_STATUS 0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
34111 #define MISCS_REG_LINK_HOLDOFF_REQ 0x0096c0UL //Access:RW DataWidth:0x1 // This bit is written to a '1' to request that the PCIE link not begin training yet. Software should set this bit; and then check the MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_STATUS register. Pulling may be required till one of the fields is set: If MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_SUCCESS is set; configure the PCIE link and then clear this bit. If MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_FAILURE is set; the PCIE link has already begun training so it's too late to do any configuration. Clear this bit.
34121 #define MISCS_REG_ISOLATION_LOGIC 0x0096e8UL //Access:R DataWidth:0x1 // The isolation between Vaux and Vmain read value.
34124 #define MISCS_REG_PWR_ATTN 0x0096f4UL //Access:RW DataWidth:0x1 // This bit indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Reset on hard reset.
34125 #define MISCS_REG_SMBIO_ENABLE_GLITCH_FILTER 0x0096f8UL //Access:RW DataWidth:0x1 // When set enables the deglitching circuit for the SMBus inputs per I2C requirement.
34126 #define MISCS_REG_PCIE_HOT_RESET 0x0096fcUL //Access:RC DataWidth:0x1 // If set indicate that the pcie_rst_b was asserted without perst assertion.
34127 #define MISCS_REG_FUNC_HIDE_PIN 0x009700UL //Access:R DataWidth:0x1 // Synchronised value of ifmux_misc_func_hide.
34128 #define MISCS_REG_NIG_DBG_VECTOR 0x009704UL //Access:RW DataWidth:0x1 // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 - NIG1 debug vector is output to IFMUX.
34129 #define MISCS_REG_FOUR_PORT_SHARED_MDIO_EN 0x009708UL //Access:RW DataWidth:0x1 // When set this will allow any of the four emacs MDIO masters to initiate MDIO transactions to access XGXS0 or the four external GPHYs. Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode.
34130 #define MISCS_REG_SEL_DBG_IFMUX_TEST 0x00970cUL //Access:RW DataWidth:0x1 // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by NIG; If 1 - path1 gmii/mii emac debug outputs are selected by NIG. Drives output misc_cnig_sel_dbg_ifmux_test.
34132 #define MISCS_REG_PCIE_DIS 0x009714UL //Access:RW DataWidth:0x1 // PCIE disable register bit. PCIE DIS. Has same functionality as the external IO PCIE_DIS: Internal PCIE DIS = external IO PCIE DIS or MISCS_REG_PCIE_DIS.
34133 #define MISCS_REG_CLK_NW_MAC_FAST_MODE 0x009718UL //Access:RW DataWidth:0x1 // When set to 1, HiGig is supported on 40G and the nw mac clock frequency is higher than the main clock frequency. When set to 0, HiGig is not supported on 40G and the nw mac clock frequency is identical to the main clock frequency. Applicable only for K2.
34135 #define MISCS_REG_ISOLATE_PATH 0x009720UL //Access:RW DataWidth:0x1 // This bit will be set by the MCP when the device works in PDA mode. The value of this register also drives the isolate_path output of the MISC block.
34136 #define MISCS_REG_MDIO_OVERRIDE 0x009724UL //Access:RW DataWidth:0x1 // MDIO Override. Enables the values on MISC_REGISTERS_MDIO_SUBSCRIPTION.MDIO_SUBSCRIPTION to override the hardware mode defined defaults. Global register. Reset on Hard reset.
34138 #define MISCS_REG_HOT_RESET_UNPREPARED 0x00972cUL //Access:RW DataWidth:0x1 // Set to 1 when pcie_rst_n is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state. Reset to 0 by the FW. Reset on por reset.
34140 #define MISCS_REG_PARITY_MODE 0x009734UL //Access:RW DataWidth:0x1 // Debug only : parity mode to MCP. Setting this bit changes the parity checking on the memories from even to odd parity. Global register.
34141 #define MISCS_REG_IPOR_CMD_REG 0x009738UL //Access:RW DataWidth:0x1 // Writing this bit as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is not protection for this request and it may cause any current PCI cycle to lock up. Reset on hard reset.
34144 #define MISCS_REG_UNCOND_ENTER_PLAY_DEAD 0x009744UL //Access:RW DataWidth:0x1 // Writing to this register results in resetting entire chip via the play dead mechanism.
34145 #define MISCS_REG_COND_ENTER_PLAY_DEAD 0x009748UL //Access:RW DataWidth:0x1 // Writing to this register result with resetting entire chip via the play dead mechanism if PERST is asserted.
34147 #define MISCS_REG_PLL_STORM_CTRL_4 0x009750UL //Access:RW DataWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select external clock; Reset on POR reset.
34148 #define MISCS_REG_UNPREPARED 0x009754UL //Access:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
34149 #define MISCS_REG_UNPREPARED_FW 0x009758UL //Access:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
34150 #define MISCS_REG_UNPREPARED_DR 0x00975cUL //Access:RW DataWidth:0x1 // Set by the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.
34151 #define MISCS_REG_VAUX_PRESENT 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present; 1 - VAUX is present.
34158 #define MISCS_REG_LINK_IN_L23 0x00977cUL //Access:R DataWidth:0x1 // When this bit is 1 it indicates that the link is down and PCIE is prepared for operation off of VAUX.
34159 #define MISCS_REG_PCIE_DIS_IO 0x009780UL //Access:R DataWidth:0x1 // This bit reports the current state of the PCIE_DIS pin. If this bit is 1 it means that the LOM design has been strapped to support management only. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode.
34160 #define MISCS_REG_INTERNAL_PERST_N 0x009784UL //Access:R DataWidth:0x1 // The status of the internal perst_n control (active low) that goes to the PCIE CORE.
34170 #define MISCS_REG_HOT_RESET_EN 0x0097acUL //Access:RW DataWidth:0x1 // When =1, when pcie_rst_n is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state, hard reset is asserted. When =0, when pcie_rst_n is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state, hard reset is not asserted. Reset on por reset.
34171 #define MISCS_REG_PCIE_RST_N 0x0097b0UL //Access:R DataWidth:0x1 // Indicates the current state of the pcie_rst_n control which is driven by the PCIE CORE. Active low control.
34190 #define DBU_REG_CMD_ENABLE (0x1<<0) // This bit will always read '1', as it is not possible to disable the dbu block.
34192 #define DBU_REG_CMD_RX_ERROR (0x1<<1) // This bit will read '1' if a byte has been received with a framing error. It will continue to read as a '1' until the command register is written with a '1' in this bit position.
34194 #define DBU_REG_CMD_RX_OVERFLOW (0x1<<2) // This bit will read '1' of a receive overflow has occurred. It will continue to read as a '1' until the command register is written with a '1' in this bit position.
34197 #define DBU_REG_STATUS_RXDATA_VALID (0x1<<0) // This bit will read '1' if there is a valid byte to read in dbu_rxdata. Once dbu_rxdata is read, this bit will automatically clear.
34199 #define DBU_REG_STATUS_TXDATA_OCCUPIED (0x1<<1) // This bit will read '1' if there is data pending to be transmitted in the txdata register. The bit will automatically clear when the txdata register is emptied.
34202 #define DBU_REG_CONFIG_TIMING_OVERRIDE (0x1<<0) // When this bit is set, the UART timing will be determined by the values in the dbu_timing register. When the bit is clear, the UART timing will be determined by the timing_select inputs to the block.
34204 #define DBU_REG_CONFIG_DEBUGSM_ENABLE (0x1<<1) // When this bit is set, the debug state machine shall respond to received characters by performing GRC master transactions and returning received data.
34206 #define DBU_REG_CONFIG_CRLF_ENABLE (0x1<<2) // When this bit is set, all line feeds shall be preceded by a carriage return. Note that this bit has no impact on carriage returns transmitted by a GRC master via the txdata register.
34220 #define DBU_REG_VFID_CFG_VFID_VALID (0x1<<16) // The vfid_value bits are valid only if this bit is set. If this bit is cleared, PF registers will be accessed
34222 #define DBU_REG_VFID_CFG_PATHID (0x1<<20) // Set the path ID if the access is forced as indicated by bit 31.
34224 #define DBU_REG_VFID_CFG_PATH_FORCE (0x1<<31) // When 0, the path selection is done by PFID[0]. When 1, the path selection is done by the PATHID field in this register.
34226 #define DMAE_REG_INIT 0x00c000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
34227 #define DMAE_REG_PCI_IFEN 0x00c040UL //Access:RW DataWidth:0x1 // DMAE PCI Interface (Request;Read;Write) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all other signals are treated as usual; if 1 - normal activity.
34228 #define DMAE_REG_GRC_IFEN 0x00c044UL //Access:RW DataWidth:0x1 // DMAE GRC Interface (Target;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
34229 #define DMAE_REG_GO_C0 0x00c048UL //Access:RW DataWidth:0x1 // Command 0 go.
34230 #define DMAE_REG_GO_C1 0x00c04cUL //Access:RW DataWidth:0x1 // Command 1 go.
34231 #define DMAE_REG_GO_C2 0x00c050UL //Access:RW DataWidth:0x1 // Command 2 go.
34232 #define DMAE_REG_GO_C3 0x00c054UL //Access:RW DataWidth:0x1 // Command 3 go.
34233 #define DMAE_REG_GO_C4 0x00c058UL //Access:RW DataWidth:0x1 // Command 4 go.
34234 #define DMAE_REG_GO_C5 0x00c05cUL //Access:RW DataWidth:0x1 // Command 5 go.
34235 #define DMAE_REG_GO_C6 0x00c060UL //Access:RW DataWidth:0x1 // Command 6 go.
34236 #define DMAE_REG_GO_C7 0x00c064UL //Access:RW DataWidth:0x1 // Command 7 go.
34237 #define DMAE_REG_GO_C8 0x00c068UL //Access:RW DataWidth:0x1 // Command 8 go.
34238 #define DMAE_REG_GO_C9 0x00c06cUL //Access:RW DataWidth:0x1 // Command 9 go.
34239 #define DMAE_REG_GO_C10 0x00c070UL //Access:RW DataWidth:0x1 // Command 10 go.
34240 #define DMAE_REG_GO_C11 0x00c074UL //Access:RW DataWidth:0x1 // Command 11 go.
34241 #define DMAE_REG_GO_C12 0x00c078UL //Access:RW DataWidth:0x1 // Command 12 go.
34242 #define DMAE_REG_GO_C13 0x00c07cUL //Access:RW DataWidth:0x1 // Command 13 go.
34243 #define DMAE_REG_GO_C14 0x00c080UL //Access:RW DataWidth:0x1 // Command 14 go.
34244 #define DMAE_REG_GO_C15 0x00c084UL //Access:RW DataWidth:0x1 // Command 15 go.
34245 #define DMAE_REG_GO_C16 0x00c088UL //Access:RW DataWidth:0x1 // Command 16 go.
34246 #define DMAE_REG_GO_C17 0x00c08cUL //Access:RW DataWidth:0x1 // Command 17 go.
34247 #define DMAE_REG_GO_C18 0x00c090UL //Access:RW DataWidth:0x1 // Command 18 go.
34248 #define DMAE_REG_GO_C19 0x00c094UL //Access:RW DataWidth:0x1 // Command 19 go.
34249 #define DMAE_REG_GO_C20 0x00c098UL //Access:RW DataWidth:0x1 // Command 20 go.
34250 #define DMAE_REG_GO_C21 0x00c09cUL //Access:RW DataWidth:0x1 // Command 21 go.
34251 #define DMAE_REG_GO_C22 0x00c0a0UL //Access:RW DataWidth:0x1 // Command 22 go.
34252 #define DMAE_REG_GO_C23 0x00c0a4UL //Access:RW DataWidth:0x1 // Command 23 go.
34253 #define DMAE_REG_GO_C24 0x00c0a8UL //Access:RW DataWidth:0x1 // Command 24 go.
34254 #define DMAE_REG_GO_C25 0x00c0acUL //Access:RW DataWidth:0x1 // Command 25 go.
34255 #define DMAE_REG_GO_C26 0x00c0b0UL //Access:RW DataWidth:0x1 // Command 26 go.
34256 #define DMAE_REG_GO_C27 0x00c0b4UL //Access:RW DataWidth:0x1 // Command 27 go.
34257 #define DMAE_REG_GO_C28 0x00c0b8UL //Access:RW DataWidth:0x1 // Command 28 go.
34258 #define DMAE_REG_GO_C29 0x00c0bcUL //Access:RW DataWidth:0x1 // Command 29 go.
34259 #define DMAE_REG_GO_C30 0x00c0c0UL //Access:RW DataWidth:0x1 // Command 30 go.
34260 #define DMAE_REG_GO_C31 0x00c0c4UL //Access:RW DataWidth:0x1 // Command 31 go.
34262 #define DMAE_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
34264 #define DMAE_REG_INT_STS_PCI_RD_BUF_ERR (0x1<<1) // PCI read buffer error.
34267 #define DMAE_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: DMAE_REG_INT_STS.ADDRESS_ERROR .
34269 #define DMAE_REG_INT_MASK_PCI_RD_BUF_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: DMAE_REG_INT_STS.PCI_RD_BUF_ERR .
34272 #define DMAE_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
34274 #define DMAE_REG_INT_STS_WR_PCI_RD_BUF_ERR (0x1<<1) // PCI read buffer error.
34277 #define DMAE_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
34279 #define DMAE_REG_INT_STS_CLR_PCI_RD_BUF_ERR (0x1<<1) // PCI read buffer error.
34282 #define DMAE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
34284 #define DMAE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
34286 #define DMAE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
34290 #define DMAE_REG_RLXD_ORDR 0x00c404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X relaxed ordering is enabled.
34291 #define DMAE_REG_NO_SNOOP 0x00c408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;1-system isn't required to cause processor cache snoop for coherency.
34292 #define DMAE_REG_CRC16I_INIT 0x00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - the CRC-16 initial value is all ones.
34293 #define DMAE_REG_CRC16_BSWAP 0x00c410UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 final calculation result isn't byte swapped; if 1 - the CRC-16 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
34294 #define DMAE_REG_CRC16C_INIT 0x00c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c initial value is all ones.
34295 #define DMAE_REG_CRC16T10_INIT 0x00c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the CRC-16 T10 initial value is all ones.
34296 #define DMAE_REG_CRC32I_INIT 0x00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - the CRC-32 initial value is all ones.
34297 #define DMAE_REG_CRC32I_BSWAP 0x00c420UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
34298 #define DMAE_REG_CRC32C_INIT 0x00c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - the CRC-32c initial value is all ones.
34299 #define DMAE_REG_CRC32C_BSWAP 0x00c428UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c final calculation result isn't byte swapped; if 1 - the CRC-32c final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
34300 #define DMAE_REG_CHKSUM0_FIX 0x00c42cUL //Access:RW DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if 1 - the final checksum equal 0 will be fixed to all ones.
34303 #define DMAE_REG_PCI_ERR_DISCARD_EN 0x00c438UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI transaction read in case there is PCI error.
34310 #define DMAE_REG_TPH_FLAGS_TPH_VALID (0x1<<11) // TPH valid.
34315 #define DMAE_REG_MEMCTRL_WR_RD_N 0x00c500UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
34333 #define DBG_REG_OUTPUT_ENABLE_PCI_REQ_ENABLE (0x1<<0) // Debug only: This bit is an enable to PCI output request interface; This bit should be enabled/disabled together along with DBG_REGISTERS_OUTPUT_ENABLE.PCI_DATA_ENABLE . When DBG_REGISTERS_OUTPUT_ENABLE.NIG_ENABLE is enabled this register must be disabled.
34335 #define DBG_REG_OUTPUT_ENABLE_PCI_DATA_ENABLE (0x1<<1) // Debug only: This bit is an enable to PCI output data interface; This bit should be enabled/disabled together along with DBG_REGISTERS_OUTPUT_ENABLE.PCI_REQ_ENABLE . When DBG_REGISTERS_OUTPUT_ENABLE.NIG_ENABLE is enabled this register must be disabled.
34337 #define DBG_REG_OUTPUT_ENABLE_NIG_ENABLE (0x1<<2) // Debug only: This bit is an enable to NIG output data interface. When DBG_REGISTERS_OUTPUT_ENABLE.PCI_REQ_ENABLE and DBG_REGISTERS_OUTPUT_ENABLE.PCI_DATA_ENABLE are enabled this bit should be disabled.
34359 #define DBG_REG_FULL_MODE 0x010060UL //Access:RW DataWidth:0x1 // Debug only: This bit indicates whether data will be wrapped (oldest data is thrown) or overflowed-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer): 1- wrap internal buffer; 0 - One Shot; b) When DBG_REGISTERS_DEBUG_TARGET =1 (NIG): 1 - constant send; 0 - One Shot; c) When DBG_REGISTERS_DEBUG_TARGET =2 (PXP): 1 - wrap host memory in PXP; 0 - One Shot;.
34360 #define DBG_REG_INT_STS 0x010180UL //Access:R DataWidth:0x1 // Multi Field Register.
34361 #define DBG_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
34363 #define DBG_REG_INT_MASK 0x010184UL //Access:RW DataWidth:0x1 // Multi Field Register.
34364 #define DBG_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: DBG_REG_INT_STS.ADDRESS_ERROR .
34366 #define DBG_REG_INT_STS_WR 0x010188UL //Access:WR DataWidth:0x1 // Multi Field Register.
34367 #define DBG_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
34369 #define DBG_REG_INT_STS_CLR 0x01018cUL //Access:RC DataWidth:0x1 // Multi Field Register.
34370 #define DBG_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
34372 #define DBG_REG_PRTY_MASK_H_0 0x010204UL //Access:RW DataWidth:0x1 // Multi Field Register.
34373 #define DBG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: DBG_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
34382 #define DBG_REG_WRAP_ON_INT_BUFFER 0x010418UL //Access:R DataWidth:0x1 // Debug only: This bit indicates wheter the internal buffer was wrapped (oldest data was thrown) Relevant only when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer).
34383 #define DBG_REG_WRAP_ON_EXT_BUFFER 0x01041cUL //Access:R DataWidth:0x1 // Debug only: This bit indicates wheter indicates that external buffer was wrapped (oldest data was thrown); Relevant only when DBG_REGISTERS_DEBUG_TARGET =2 (PCI) & DBG_REGISTERS_FULL_MODE =1 (wrap);.
34384 #define DBG_REG_OVL_ON_INT_BUFFER 0x010420UL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the internal buffer was overflowed (newest data was thrown); Not relevant if DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) & DBG_REGISTERS_FULL_MODE =1 (wrap);.
34385 #define DBG_REG_OVL_ON_EXT_BUFFER 0x010424UL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the external buffer was overflowed (newest data was thrown); Relevant only for (a) DBG_REGISTERS_DEBUG_TARGET =2 (PCI) & DBG_REGISTERS_FULL_MODE =0 (one shot); or (b) DBG_REGISTERS_DEBUG_TARGET =1 (NIG) & DBG_REGISTERS_FULL_MODE =0 (one shot).
34386 #define DBG_REG_FULL_ON_INT_BUFFER 0x010428UL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the internal buffer was filled.
34387 #define DBG_REG_FULL_ON_EXT_BUFFER 0x01042cUL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the external buffer was filled; Relevant only when DBG_REGISTERS_FULL_MODE =0 (one shot).
34395 #define DBG_REG_CPU_DEBUG_FRAME 0x01044cUL //Access:RW DataWidth:0x1 // Debug only: This bit indicate the frame signal of the debug data that arrives from the CPU. Must be configured before cpu_debug_data is configured.
34396 #define DBG_REG_CPU_TIMEOUT 0x010450UL //Access:RW DataWidth:0x1 // Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty.
34397 #define DBG_REG_DBG_BLOCK_ON 0x010454UL //Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;.
34398 #define DBG_REG_NO_GRANT_ON_FULL 0x010458UL //Access:RW DataWidth:0x1 // Debug only: This bit indicate whether grant will be issued by the dbg block towards the storms in case the internal buffer is almost full as follows: (a) 1 - no grants will be made to the storms when the internal buffer is almost full. When the buffer will be partialy freed (enough for a complete data chunk) then grant is resumed; b) 0 - grant is supplied every time the matching storms's slot is chosen disregarding the volume status of the internal buffer.
34400 #define DBG_REG_PCI_LOGIC_ADDR 0x010460UL //Access:RW DataWidth:0x1 // Debug only: This bit indicates logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical address;.
34408 #define DBG_REG_PATTERN_RECOGNITION_DISABLE 0x010540UL //Access:RW DataWidth:0x1 // Debug only: For pattern recognition usage: This bit indicates whether the pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;.
34409 #define DBG_REG_PATTERN_RECOGNITION_STORAGE_MODE 0x010544UL //Access:RW DataWidth:0x1 // Debug only: For pattern recognition usage: This bit indicates the trigger behavior of the pattern recognition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially recognized; (b) 0 - start debug data storage when the expected pattern is initially recognized. When pattern_recognition_filter=0 then this register must be 0
34410 #define DBG_REG_PATTERN_RECOGNITION_FILTER 0x010548UL //Access:RW DataWidth:0x1 // Debug only: For pattern recognition usage: This bit indicates whether data is continously stored in the dbg block until/from pattern recognition initial event; or stored only in cycles of a pattern recognition event occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pattern recognition; (b) 0 - enable data storage only in cycles of a pttern recognition event occurence.
34411 #define DBG_REG_TRIGGER_ENABLE 0x01054cUL //Access:RW DataWidth:0x1 // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode.
34412 #define DBG_REG_TRIGGER_INTERLEAVED_ENABLE 0x010550UL //Access:RW DataWidth:0x1 // (a) 0 - triggering interleaved messages is disabled. (b) 1 - triggering interleaved messages is enabled; will be used for triggering on recorded handler messages. NOTE: (1) triggering is possible on one level depth of interleaved messages; i.e. if message B is interleaved within message A then it is ok; However if message C is interleaved within message B and message B is interleaved within message A this scenario is NOT supported. (2) when triggering interleaved messages is enabled, set trigger_enable=1 and filter_enable>0, and trigger_id_num not equal with filter_id_num (because filtering machine does not support interleaving)
34416 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_0 0x010560UL //Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
34417 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_1 0x010564UL //Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
34418 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_2 0x010568UL //Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
34455 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0 0x0105fcUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34456 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_1 0x010600UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34457 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_2 0x010604UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34458 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_3 0x010608UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34459 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_4 0x01060cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34460 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_5 0x010610UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34461 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_6 0x010614UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34462 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_7 0x010618UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34463 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_8 0x01061cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34464 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_9 0x010620UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34465 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_10 0x010624UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34466 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_11 0x010628UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34467 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_12 0x01062cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34468 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_13 0x010630UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34469 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_14 0x010634UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34470 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_15 0x010638UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34471 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_16 0x01063cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34472 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_17 0x010640UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34473 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_18 0x010644UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34474 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_19 0x010648UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34475 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_20 0x01064cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34476 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_21 0x010650UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34477 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_22 0x010654UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34478 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_23 0x010658UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.
34503 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34504 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_1 0x0106c0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34505 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_2 0x0106c4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34506 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_3 0x0106c8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34507 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_4 0x0106ccUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34508 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_5 0x0106d0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34509 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_6 0x0106d4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34510 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_7 0x0106d8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34511 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_8 0x0106dcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34512 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_9 0x0106e0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34513 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_10 0x0106e4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34514 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_11 0x0106e8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34515 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_12 0x0106ecUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34516 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_13 0x0106f0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34517 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_14 0x0106f4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34518 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_15 0x0106f8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34519 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_16 0x0106fcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34520 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_17 0x010700UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34521 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_18 0x010704UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34522 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_19 0x010708UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34523 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_20 0x01070cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34524 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_21 0x010710UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34525 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_22 0x010714UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34526 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_23 0x010718UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34695 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0 0x01083cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34696 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_1 0x010840UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34697 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_2 0x010844UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34698 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_3 0x010848UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34699 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_4 0x01084cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34700 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_5 0x010850UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34701 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_6 0x010854UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34702 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_7 0x010858UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34703 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_8 0x01085cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34704 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_9 0x010860UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34705 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_10 0x010864UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34706 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_11 0x010868UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34707 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_12 0x01086cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34708 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_13 0x010870UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34709 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_14 0x010874UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34710 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_15 0x010878UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34711 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_16 0x01087cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34712 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_17 0x010880UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34713 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_18 0x010884UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34714 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_19 0x010888UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34715 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_20 0x01088cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34716 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_21 0x010890UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34717 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_22 0x010894UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34718 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_23 0x010898UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34743 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0 0x0108fcUL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34744 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_1 0x010900UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34745 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_2 0x010904UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34746 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_3 0x010908UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34747 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_4 0x01090cUL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34748 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_5 0x010910UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34749 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_6 0x010914UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34750 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_7 0x010918UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34751 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_8 0x01091cUL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34752 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_9 0x010920UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34753 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_10 0x010924UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34754 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_11 0x010928UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34755 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_12 0x01092cUL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34756 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_13 0x010930UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34757 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_14 0x010934UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34758 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_15 0x010938UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34759 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_16 0x01093cUL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34760 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_17 0x010940UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34761 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_18 0x010944UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34762 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_19 0x010948UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34763 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_20 0x01094cUL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34764 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_21 0x010950UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34765 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_22 0x010954UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34766 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_23 0x010958UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34767 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 0x01095cUL //Access:RW DataWidth:0x1 // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use masking according to trigger_state_id only.
34768 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_1 0x010960UL //Access:RW DataWidth:0x1 // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use masking according to trigger_state_id only.
34769 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_2 0x010964UL //Access:RW DataWidth:0x1 // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use masking according to trigger_state_id only.
34773 #define DBG_REG_TRIGGER_EVENT 0x010974UL //Access:R DataWidth:0x1 // Configured messages sequencing was identified.
34802 #define DBG_REG_FILTER_CNSTR_FRAME_0 0x0109e8UL //Access:RW DataWidth:0x1 // The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.
34803 #define DBG_REG_FILTER_CNSTR_FRAME_1 0x0109ecUL //Access:RW DataWidth:0x1 // The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.
34804 #define DBG_REG_FILTER_CNSTR_FRAME_2 0x0109f0UL //Access:RW DataWidth:0x1 // The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.
34805 #define DBG_REG_FILTER_CNSTR_FRAME_3 0x0109f4UL //Access:RW DataWidth:0x1 // The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.
34810 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_0 0x010a08UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34811 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_1 0x010a0cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34812 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_2 0x010a10UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34813 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_3 0x010a14UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.
34842 #define DBG_REG_FILTER_CNSTR_MUST_0 0x010a48UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34843 #define DBG_REG_FILTER_CNSTR_MUST_1 0x010a4cUL //Access:RW DataWidth:0x1 // (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34844 #define DBG_REG_FILTER_CNSTR_MUST_2 0x010a50UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34845 #define DBG_REG_FILTER_CNSTR_MUST_3 0x010a54UL //Access:RW DataWidth:0x1 // (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
34850 #define DBG_REG_FILTER_CNSTR_CYCLIC_0 0x010a68UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34851 #define DBG_REG_FILTER_CNSTR_CYCLIC_1 0x010a6cUL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34852 #define DBG_REG_FILTER_CNSTR_CYCLIC_2 0x010a70UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34853 #define DBG_REG_FILTER_CNSTR_CYCLIC_3 0x010a74UL //Access:RW DataWidth:0x1 // Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (filter_cnstr_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).
34854 #define DBG_REG_FILTER_MSG_LENGTH_ENABLE 0x010a78UL //Access:RW DataWidth:0x1 // (a) 1: use filter_msg_length to determine message boundary. (b) 0: use the frame bit to determine message boundary.
34856 #define DBG_REG_FILTER_PARTIAL_RECORD_EN 0x010a80UL //Access:RW DataWidth:0x1 // When set that enables of partial message record. Other way record is done for whole message (when message is filtered). Note: (a) When filter_enable = 1 (Filter on prior to trigger_event) the messages are partially recorded not only before the trigger_event but also after trigger_event (for the messages that are not filtered). (b) when filter_enable = 2 (Filter on upon trigger_event) the messages are partially recorded not only after the trigger_event, but also before trigger_event (for the messages that are not filtered).
34859 #define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE 0x010a8cUL //Access:RW DataWidth:0x1 // Recording mode upon trigger event: (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_num_cycles valid cycles upon the event; (b) 1 - disable recording data upon triggering event. NOTE: applicable only if trigger_enable=1.
34871 #define DBG_REG_DBG_DRIVER_TRIGGER 0x010abcUL //Access:RW DataWidth:0x1 // Used for triggering on driver assertions. For example this can be used in Emulation when The driver identifies an error and write to the for triggerig purpose
34894 #define DBG_REG_NW_PACKET_COUNTER_EN 0x010b40UL //Access:RW DataWidth:0x1 // When 1 enables inserting packet counter at the output to NIG between Ethernet header and data.
34915 #define DBG_REG_MEMCTRL_WR_RD_N 0x010b94UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
34920 #define DBG_REG_FILTER_MODE 0x010ba8UL //Access:RW DataWidth:0x1 // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_ID_NUM is logged. When set to 1 - the client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_ID_NUM is filtered, while other clients are passed as as is without filtering.
34924 #define IPC_REG_MDIO_VOLTAGE_SEL 0x020200UL //Access:RW DataWidth:0x1 // Select line for MDIO Voltage Select 0 : MDIO VDDIO is 1.8V or below. 1 : MDIO VDDIO is 1.8+V or above.
34931 #define IPC_REG_PLL_MAIN_BYPASS 0x020210UL //Access:RW DataWidth:0x1 // pll bypass signal
34933 #define IPC_REG_PLL_MAIN_LOCK 0x020214UL //Access:R DataWidth:0x1 // pll lock signal
34935 #define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS 0x020218UL //Access:R DataWidth:0x1 // pll lock detected filter status
34936 #define IPC_REG_OSC_E28_XCORE_BIAS_OVERRIDE 0x020218UL //Access:RW DataWidth:0x1 // XCORE_BIAS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_xcore_bias Global Register, Reset on POR
34937 #define IPC_REG_PLL_MAIN_NEWDIV 0x02021cUL //Access:RW DataWidth:0x1 // Divider input control
34938 #define IPC_REG_OSC_E28_HIPASS 0x02021cUL //Access:RW DataWidth:0x1 // XTAL core Highpass Filter Corner Frequency control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 1. Global Register, Reset on POR
34939 #define IPC_REG_PLL_MAIN_DIVACK 0x020220UL //Access:R DataWidth:0x1 // Divider handshake signal
34940 #define IPC_REG_OSC_E28_HIPASS_OVERRIDE 0x020220UL //Access:RW DataWidth:0x1 // HIPASS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_hipass Global Register, Reset on POR
34942 #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET (0x1<<0) // 1 : Reset the PLL. The reset is active high.
34944 #define IPC_REG_PLL_MAIN_RESET_OVERRIDE (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
34947 #define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED 0x020228UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
34948 #define IPC_REG_OSC_E28_CML_CUR 0x020228UL //Access:RW DataWidth:0x1 // CML Current Control Global Register, Reset on POR
34952 #define IPC_REG_OSC_E28_DIV2_SEL 0x020230UL //Access:RW DataWidth:0x1 // Divide by 2 Selection for pad_op/n_cml output 0=XTAL Freq. 1=XTAL Freq. / 2 Global Register, Reset on POR
34956 #define IPC_REG_OSC_E28_CMOS_EN_ALL 0x020238UL //Access:RW DataWidth:0x1 // ENABLE All CMOS Outputs 0=o_xtal_ck[5:0] depends on i_resetb and i_cmos_en_ch[5:0] 1=o_xtal_ck[5:0] ALL ON Global Register, Reset on POR
34957 #define IPC_REG_PLL_NWM_RESET 0x02023cUL //Access:RW DataWidth:0x1 // pll reset signal
34959 #define IPC_REG_PLL_NWM_BYPASS 0x020240UL //Access:RW DataWidth:0x1 // pll bypass signal
34961 #define IPC_REG_PLL_NWM_LOCK 0x020244UL //Access:R DataWidth:0x1 // pll lock signal
34962 #define IPC_REG_OSC_E28_PD_DRV 0x020244UL //Access:RW DataWidth:0x1 // 50ohm Driver Power Down 0=Driver ENABLED 1=Driver DISABLED Global Register, Reset on POR
34963 #define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS 0x020248UL //Access:R DataWidth:0x1 // pll lock detected filter status
34965 #define IPC_REG_OSC_E28_MISC_OSC_E28_POWER_SAVE (0x1<<0) // Future Use
34969 #define IPC_REG_OSC_E28_MISC_OSC_E28_XCORE_CM_SEL (0x1<<4) // Future Use
34971 #define IPC_REG_PLL_NWM_NEWDIV 0x02024cUL //Access:RW DataWidth:0x1 // Divider input control
34972 #define IPC_REG_PLL_MAIN_E28_PWRDN 0x02024cUL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
34973 #define IPC_REG_PLL_NWM_DIVACK 0x020250UL //Access:R DataWidth:0x1 // Divider handshake signal
34975 #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO (0x1<<0) // 1 : Reset the VCO of the PLL. The reset is active high. Global Register, Reset on POR
34977 #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_OVERRIDE (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
34979 #define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED 0x020254UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
34981 #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST (0x1<<0) // 1 : Reset the Post Divider of the PLL. The reset is active high. Global Register, Reset on POR
34983 #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_OVERRIDE (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
34993 #define IPC_REG_PLL_STORM_RESET 0x020268UL //Access:RW DataWidth:0x1 // pll reset signal
34995 #define IPC_REG_PLL_STORM_BYPASS 0x02026cUL //Access:RW DataWidth:0x1 // pll bypass signal
34997 #define IPC_REG_PLL_STORM_LOCK 0x020270UL //Access:R DataWidth:0x1 // pll lock signal
34999 #define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS 0x020274UL //Access:R DataWidth:0x1 // pll lock detected filter status
35001 #define IPC_REG_PLL_STORM_NEWDIV 0x020278UL //Access:RW DataWidth:0x1 // Divider input control
35003 #define IPC_REG_PLL_STORM_DIVACK 0x02027cUL //Access:R DataWidth:0x1 // Divider handshake signal
35005 #define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED 0x020280UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.
35015 #define IPC_REG_SGMII_RSTB_MDIOREGS 0x020294UL //Access:RW DataWidth:0x1 // reset of sgmii mdio registers. This is an active high reset. The name "rstb" is mistakenly suggest an active low reset.
35017 #define IPC_REG_FREQ_CAPTURE 0x0204a4UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW clocks. This is a self clearing bit.
35022 #define IPC_REG_FREQ_MAIN_CNT_VALID (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
35028 #define IPC_REG_FREQ_STORM_CNT_VALID (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
35034 #define IPC_REG_FREQ_NWM_CNT_VALID (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
35038 #define IPC_REG_PLL_MAIN_E28_LOCK 0x0202a8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
35042 #define IPC_REG_PLL_NW_E28_PWRDN 0x0202b0UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
35044 #define IPC_REG_PLL_NW_E28_RESET_VCO 0x0202b4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High
35046 #define IPC_REG_PLL_NW_E28_RESET_POST 0x0202b8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High
35047 #define IPC_REG_VMAIN_POR_STATUS 0x0204c8UL //Access:R DataWidth:0x1 // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
35053 #define IPC_REG_PERST_POR_STATUS 0x0204d4UL //Access:R DataWidth:0x1 // This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted
35068 #define IPC_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
35070 #define IPC_REG_INT_STS_0_VMAIN_POR_ASSERT (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
35072 #define IPC_REG_INT_STS_0_VMAIN_POR_DEASSERT (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
35074 #define IPC_REG_INT_STS_0_PERST_ASSERT (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
35076 #define IPC_REG_INT_STS_0_PERST_DEASSERT (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
35078 #define IPC_REG_INT_STS_0_OTP_ECC_DED_0 (0x1<<8) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted.
35080 #define IPC_REG_INT_STS_0_OTP_ECC_DED_1 (0x1<<9) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 1 is asserted.
35082 #define IPC_REG_INT_STS_0_OTP_ECC_DED_2 (0x1<<10) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 2 is asserted.
35084 #define IPC_REG_INT_STS_0_OTP_ECC_DED_3 (0x1<<11) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 3 is asserted.
35086 #define IPC_REG_INT_STS_0_OTP_ECC_DED_4 (0x1<<12) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 4 is asserted.
35088 #define IPC_REG_INT_STS_0_OTP_ECC_DED_5 (0x1<<13) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 5 is asserted.
35090 #define IPC_REG_INT_STS_0_OTP_ECC_DED_6 (0x1<<14) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 6 is asserted.
35092 #define IPC_REG_INT_STS_0_OTP_ECC_DED_7 (0x1<<15) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted.
35096 #define IPC_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.ADDRESS_ERROR .
35098 #define IPC_REG_INT_MASK_0_VMAIN_POR_ASSERT (0x1<<4) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.VMAIN_POR_ASSERT .
35100 #define IPC_REG_INT_MASK_0_VMAIN_POR_DEASSERT (0x1<<5) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.VMAIN_POR_DEASSERT .
35102 #define IPC_REG_INT_MASK_0_PERST_ASSERT (0x1<<6) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.PERST_ASSERT .
35104 #define IPC_REG_INT_MASK_0_PERST_DEASSERT (0x1<<7) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.PERST_DEASSERT .
35106 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_0 (0x1<<8) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_0 .
35108 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_1 (0x1<<9) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_1 .
35110 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_2 (0x1<<10) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_2 .
35112 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_3 (0x1<<11) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_3 .
35114 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_4 (0x1<<12) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_4 .
35116 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_5 (0x1<<13) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_5 .
35118 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_6 (0x1<<14) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_6 .
35120 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_7 (0x1<<15) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_7 .
35124 #define IPC_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
35126 #define IPC_REG_INT_STS_WR_0_VMAIN_POR_ASSERT (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
35128 #define IPC_REG_INT_STS_WR_0_VMAIN_POR_DEASSERT (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
35130 #define IPC_REG_INT_STS_WR_0_PERST_ASSERT (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
35132 #define IPC_REG_INT_STS_WR_0_PERST_DEASSERT (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
35134 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_0 (0x1<<8) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted.
35136 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_1 (0x1<<9) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 1 is asserted.
35138 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_2 (0x1<<10) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 2 is asserted.
35140 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_3 (0x1<<11) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 3 is asserted.
35142 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_4 (0x1<<12) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 4 is asserted.
35144 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_5 (0x1<<13) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 5 is asserted.
35146 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_6 (0x1<<14) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 6 is asserted.
35148 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_7 (0x1<<15) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted.
35152 #define IPC_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
35154 #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_ASSERT (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
35156 #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_DEASSERT (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
35158 #define IPC_REG_INT_STS_CLR_0_PERST_ASSERT (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
35160 #define IPC_REG_INT_STS_CLR_0_PERST_DEASSERT (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
35162 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_0 (0x1<<8) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted.
35164 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_1 (0x1<<9) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 1 is asserted.
35166 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_2 (0x1<<10) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 2 is asserted.
35168 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_3 (0x1<<11) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 3 is asserted.
35170 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_4 (0x1<<12) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 4 is asserted.
35172 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_5 (0x1<<13) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 5 is asserted.
35174 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_6 (0x1<<14) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 6 is asserted.
35176 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_7 (0x1<<15) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted.
35178 #define IPC_REG_PLL_NW_E28_LOCK 0x0202e8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
35182 #define IPC_REG_JTAG_COMPLIANCE_OVERRIDE (0x1<<4) // Set this bit to override the pins on the chip with bits[1:0]
35185 #define IPC_REG_TCAM_BIST_REGISTER_OR_EXTERNAL_SELECT 0x0202f0UL //Access:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - control of the tcam bist is from the external pins. by default these pins are gurenteed to be zero so tcam bist will not start running.
35186 #define IPC_REG_PLL_STORM_E28_PWRDN 0x0202f0UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
35188 #define IPC_REG_PLL_STORM_E28_RESET_VCO 0x0202f4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High
35190 #define IPC_REG_PLL_STORM_E28_RESET_POST 0x0202f8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High
35214 #define IPC_REG_PLL_STORM_E28_LOCK 0x020328UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
35218 #define IPC_REG_LCPLL_E28_PWRDN 0x020330UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR
35220 #define IPC_REG_LCPLL_E28_RESET_VCO 0x020334UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High
35222 #define IPC_REG_LCPLL_E28_RESET_POST 0x020338UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High
35246 #define IPC_REG_LCPLL_E28_LOCK 0x020368UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.
35250 #define IPC_REG_PMFC_DVT_EN 0x020370UL //Access:RW DataWidth:0x1 // Enable the MAC SERDES
35252 #define IPC_REG_PMFC_DVT_IDDQ 0x020374UL //Access:RW DataWidth:0x1 // MAC SERDES IDDQ
35253 #define IPC_REG_PMFC_DVT_PWRDWN 0x020378UL //Access:RW DataWidth:0x1 // MAC SERDES Power Down
35254 #define IPC_REG_PMFC_DVT_REFIN_EN 0x02037cUL //Access:RW DataWidth:0x1 //
35255 #define IPC_REG_PMFC_DVT_REFOUT_EN 0x020380UL //Access:RW DataWidth:0x1 //
35256 #define IPC_REG_PMFC_DVT_TSC_RESET 0x020384UL //Access:RW DataWidth:0x1 //
35257 #define IPC_REG_PMFC_DVT_MDIO_FAST_MODE 0x020388UL //Access:RW DataWidth:0x1 //
35259 #define IPC_REG_PMFC_TX_DRV_HV_DISABLE 0x020390UL //Access:RW DataWidth:0x1 // 1 : Disable high voltage for Tx Driver
35261 #define IPC_REG_PMFC_PLL_LOCK 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.
35263 #define IPC_REG_PMEG_DVT_EN 0x0203a0UL //Access:RW DataWidth:0x1 // Enable the MAC SERDES
35264 #define IPC_REG_PMEG_DVT_IDDQ 0x0203a4UL //Access:RW DataWidth:0x1 // MAC SERDES IDDQ
35265 #define IPC_REG_PMEG_DVT_PWRDWN 0x0203a8UL //Access:RW DataWidth:0x1 // MAC SERDES Power Down
35266 #define IPC_REG_PMEG_DVT_REFIN_EN 0x0203acUL //Access:RW DataWidth:0x1 //
35267 #define IPC_REG_PMEG_DVT_REFOUT_EN 0x0203b0UL //Access:RW DataWidth:0x1 //
35268 #define IPC_REG_PMEG_DVT_TSC_RESET 0x0203b4UL //Access:RW DataWidth:0x1 //
35269 #define IPC_REG_PMEG_DVT_MDIO_FAST_MODE 0x0203b8UL //Access:RW DataWidth:0x1 //
35272 #define IPC_REG_PMEG_PLL_LOCK 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.
35275 #define IPC_REG_PCIES_PIPE_IDDQ 0x0203d0UL //Access:RW DataWidth:0x1 //
35276 #define IPC_REG_PCIES_RESETMDIO_N 0x0203d4UL //Access:RW DataWidth:0x1 //
35277 #define IPC_REG_PCIES_ALT_CLK_SELECT 0x0203d8UL //Access:RW DataWidth:0x1 //
35279 #define IPC_REG_SGMII_RESETS_SGMII_RST_HW (0x1<<0) // 1 : Reset the entire SGMII Core. Global Register, Reset on POR
35281 #define IPC_REG_SGMII_RESETS_SGMII_RST_MDIO (0x1<<1) // 1 : Reset the MDIO Registers. Global Register, Reset on POR
35283 #define IPC_REG_SGMII_RESETS_SGMII_RST_PLL (0x1<<2) // 1 : Resets the PLL and digital logic.. Global Register, Reset on POR
35286 #define IPC_REG_SGMII_MD_ST 0x0203e4UL //Access:RW DataWidth:0x1 // 0 : CL22 1 : CL45 Global Register, Reset on POR
35288 #define IPC_REG_SGMII_PWRDWN 0x0203ecUL //Access:RW DataWidth:0x1 // 1 : powers down for the analog front end and turns off all clocks except refclk. MDIO is operational Global Register, Reset on POR
35289 #define IPC_REG_SGMII_IDDQ 0x0203f0UL //Access:RW DataWidth:0x1 // 1 : iddq enable, powers down analog and turns off all clocks. MDIO is not operational Global Register, Reset on POR
35292 #define IPC_REG_SGMII_STATUS_SGMII_LINK_STATUS (0x1<<0) // Link Status 1: Link has been achieve Global Register, Reset on POR
35294 #define IPC_REG_SGMII_STATUS_SGMII_RX_SIGDET (0x1<<1) // Signal Detect Global Register, Reset on POR
35296 #define IPC_REG_SGMII_STATUS_SGMII_RX_SEQDONE1G (0x1<<2) // 1: Bit Alignment Done Global Register, Reset on POR
35298 #define IPC_REG_SGMII_STATUS_SGMII_SYNC_STATUS (0x1<<3) // 1: Symbol Alignment Global Register, Reset on POR
35300 #define IPC_REG_SGMII_STATUS_SGMII_SPEED_10 (0x1<<4) // 1: Speed is 10M Global Register, Reset on POR
35302 #define IPC_REG_SGMII_STATUS_SGMII_SPEED_100 (0x1<<5) // 1: Speed is 100M Global Register, Reset on POR
35304 #define IPC_REG_SGMII_STATUS_SGMII_SPEED_1000 (0x1<<6) // 1: Speed is 1G Global Register, Reset on POR
35306 #define IPC_REG_SGMII_STATUS_SGMII_TXPLL_LOCK (0x1<<8) // 1: PLL is locked Global Register, Reset on POR
35308 #define IPC_REG_SGMII_STATUS_SGMII_MODE (0x1<<12) // 1: Running in SGMII mode. Global Register, Reset on POR
35312 #define IPC_REG_PM_TMON_ENA_PM_TMON_RESET (0x1<<0) // 1 : Reset the VTMON registers.
35314 #define IPC_REG_PM_TMON_ENA_PM_TMON_PWRDN (0x1<<1) // 1 : Hold the VTMON in powerdown state.
35316 #define IPC_REG_PM_TMON_HOLD 0x020404UL //Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.
35320 #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_RESET (0x1<<0) // 1 : Reset the VTMON registers.
35322 #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_PWRDN (0x1<<1) // 1 : Hold the VTMON in powerdown state.
35324 #define IPC_REG_PCIE_TMON_HOLD 0x020414UL //Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.
35326 #define IPC_REG_RESCAL_E28_PWRDN 0x02041cUL //Access:RW DataWidth:0x1 // Powerdown the Rescal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibration Global Register, Reset on POR
35327 #define IPC_REG_RESCAL_E28_RST 0x020420UL //Access:RW DataWidth:0x1 // Reset the RESCAL block 0: Normal Operation Mode 1: Reset the RESCAL block Global Register, Reset on POR
35328 #define IPC_REG_RESCAL_E28_OVERRIDE 0x020424UL //Access:RW DataWidth:0x1 // By Setting this bit, FW takes control of the RESCAL block manitpulates the pwrdn and reset signals to start its own calibration. 0: Normal Operation Mode 1: FW override Global Register, Reset on POR
35329 #define IPC_REG_RESCAL_E28_RESTART_CALIBRATION 0x020428UL //Access:RW DataWidth:0x1 // Setting this bit starts the HW based calibration engine to recalibrate the rescal block. 0: Normal Operation Mode 1: Restart the calibration Global Register, Reset on POR
35330 #define IPC_REG_RESCAL_E28_DIAG_ON 0x02042cUL //Access:RW DataWidth:0x1 // 0: Normal Operation Mode 1: Freeze Internal Digital ciruit Global Register, Reset on POR
35333 #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_CALIB_DONE (0x1<<0) // Indicates if the calibraion operation is done. 0: Calibration in progress 1: Calibration Done Global Register, Reset on POR
35335 #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_VALID (0x1<<1) // Indicates if the pon data is valid when calib_done is set 0: Data is invalid 1: Data is valid Global Register, Reset on POR
35340 #define IPC_REG_RESCAL_E28_COMP 0x020444UL //Access:R DataWidth:0x1 // RESCAL Comp Value Global Register, Reset on POR
35344 #define IPC_REG_SWREG_VMGMT_E28_PWRDN 0x020454UL //Access:RW DataWidth:0x1 // Powerdown the VManagement Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
35345 #define IPC_REG_SWREG_VMGMT_E28_REG_RESET 0x020458UL //Access:RW DataWidth:0x1 // Reset the Registers in VManagement Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
35346 #define IPC_REG_SWREG_VMGMT_E28_STABLE 0x02045cUL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
35347 #define IPC_REG_SWREG_VMAIN_E28_PWRDN 0x020460UL //Access:RW DataWidth:0x1 // Powerdown the VMain Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
35348 #define IPC_REG_SWREG_VMAIN_E28_REG_RESET 0x020464UL //Access:RW DataWidth:0x1 // Reset the Registers in VMain Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
35349 #define IPC_REG_SWREG_VMAIN_E28_STABLE 0x020468UL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
35350 #define IPC_REG_SWREG_VANALOG_E28_PWRDN 0x02046cUL //Access:RW DataWidth:0x1 // Powerdown the VAnalog Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
35351 #define IPC_REG_SWREG_VANALOG_E28_REG_RESET 0x020470UL //Access:RW DataWidth:0x1 // Reset the Registers in VAnalog Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
35352 #define IPC_REG_SWREG_VANALOG_E28_STABLE 0x020474UL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
35353 #define IPC_REG_SWREG_V1P8_E28_PWRDN 0x020478UL //Access:RW DataWidth:0x1 // Powerdown the V1p8 Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR
35354 #define IPC_REG_SWREG_V1P8_E28_REG_RESET 0x02047cUL //Access:RW DataWidth:0x1 // Reset the Registers in V1p8 Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR
35355 #define IPC_REG_SWREG_V1P8_E28_STABLE 0x020480UL //Access:R DataWidth:0x1 // 1: PMU is stable Global Register, Reset on POR
35356 #define IPC_REG_SWREG_SYNC_CLK_SELECT 0x020484UL //Access:RW DataWidth:0x1 // All three SWREG with external FETs are sync'ed such that they are running on different phases of alternate clock. This lowers the overall power consumption. 1: Select 1Mhz Clock 0: Select 500Khz Clock Global Register, Reset on POR
35357 #define IPC_REG_SWREG_SYNC_CLK_EN 0x020488UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will enable the phase shift logic betweent the three swreg to start working. Global Register, Reset on POR
35364 #define IPC_REG_FREQ_NW_CNT_VALID (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
35374 #define IPC_REG_PRTY_MASK 0x020520UL //Access:RW DataWidth:0x1 // Multi Field Register.
35375 #define IPC_REG_PRTY_MASK_FAKE_PAR_ERR (0x1<<0) // This bit masks, when set, the Parity bit: IPC_REG_PRTY_STS.FAKE_PAR_ERR .
35377 #define IPC_REG_LCPLL_REFCLK_SEL 0x02052cUL //Access:RW DataWidth:0x1 // Selects the reference clock for the PLL 0= CMOS Reference clock, output of the differential oscillator 1= CML reference clock, from the chip pins Global register. Reset on POR reset.
35382 #define CPMU_REG_LPI_MODE_CONFIG 0x030200UL //Access:RW DataWidth:0x1 // 0 : LPI is not enabled. 1 : LPI is enabled, LPI_REQ will be generated by the transmitter.
35383 #define CPMU_REG_LPI_BNB_MODE 0x030204UL //Access:RW DataWidth:0x1 // Setting this bit will enable a special Batch and Burst mode in the LPI request logic. When this mode is enabled, CPMU will not exit LPI at the earliest indication (L1 exit or DORQ event for ex) but rather wait for BTB to be filled with a certain threshold bytes and then exit LPI. This allows for the system to not wake up just to send a single packet for ex and go back to LPI state. In this mode, the LPI exit can also happen after a programmable time tha the first packet is in the Tx Pipeline.
35387 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of LPI request generation logic. 1 : PBF Empty is part of LPI request generation logic.
35389 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_QM_EMPTY_EN (0x1<<1) // 0 : QM Empty is not part of LPI request generation logic. 1 : QM Empty is part of LPI request generation logic. QM Empty only includes Network traffic for that port. Loopback traffic is not part of the LPI equation.
35391 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_ALL_SQ_EMPTY_EN (0x1<<2) // 0 : All Send Queue Empty is not part of LPI request generation logic. 1 : All Send Queue Empty is part of LPI request generation logic.
35393 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_MGMT_EMPTY_EN (0x1<<3) // 0 : Management Traffic is not part of LPI request generation logic. 1 : Management Traffic is part of LPI request generation logic.
35395 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_RX_LPI_STATUS_EN (0x1<<4) // 0 : LPI receive status is not part of LPI request generation logic. 1 : LPI receive status is part of LPI request generation logic.
35397 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_OBFF_STATE_EN (0x1<<5) // 0 : OBFF State (non CPU_ACTIVE) is not part of LPI request generation logic. 1 : OBFF State (non CPU_ACTIVE) is part of LPI request generation logic.
35399 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PCIE_IN_D3_EN (0x1<<6) // 0 : PCIe in D3 State is not part of LPI request generation logic. 1 : PCIe in D3 State is part of LPI request generation logic.
35401 #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_NIG_TX_EMPTY_EN (0x1<<7) // 0 : NIG Tx is empty is not part of LPI request generation logic. 1 : NIG Tx is empty is part of LPI request generation logic.
35404 #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_DORQ_EVENT_EN (0x1<<0) // 0 : DORQ Event is not part of the equation to exit LPI. 1 : DORQ Event is part of the equation to exit LPI.
35406 #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_NCSI_EVENT_EN (0x1<<1) // 0 : NCSI Event is not part of the equation to exit LPI. 1 : NCSI Event is part of the equation to exit LPI.
35408 #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PCIE_L1_EXIT_EN (0x1<<2) // 0 : PCIe L1 exit is not part of the equation to exit LPI. 1 : PCIe L1 exit is part of the equation to exit LPI.
35410 #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PBF_ALMOST_FULL_EN (0x1<<3) // This bit will be used in the Batch and Burst mode. In this mode, 0 : pbf almost full is not part of the equation to exit LPI. 1 : pbf almost full is part of the equation to exit LPI.
35412 #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_BMB_ALMOST_FULL_EN (0x1<<4) // This bit will be used in the Batch and Burst mode. In this mode, 0 : BMB almost full is not part of the equation to exit LPI. 1 : BMB almost full is part of the equation to exit LPI.
35414 #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_SQ_EARLY_EXIT_EN (0x1<<5) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the LPI exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, LPI will exit.
35416 #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_RX_LPI_STATUS_EXIT_EN (0x1<<6) // 0 : LPI receive status is not part of LPI request exit logic. 1 : LPI receive status is part of LPI request exit logic.
35418 #define CPMU_REG_SW_FORCE_LPI 0x030218UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force an LPI request on the interface. Clearing this bit will not automatically guarantee an exit from LPI if other elements in the LPI equation is causing an LPI request to go out. To do a forceful exit, SW needs to assert the sw_lpi_exit register.
35419 #define CPMU_REG_SW_LPI_EXIT 0x03021cUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indication to exit LPI state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
35420 #define CPMU_REG_OBFF_MODE_CONFIG 0x030220UL //Access:RW DataWidth:0x1 // 0 : OBFF is not enabled. 1 : OBFF is enabled, DMA master requests could be stalled based on OBFF state machine.
35422 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_FORCE (0x1<<0) // Reserved.
35424 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_ENGINE_IDLE_EN (0x1<<1) // 0: Engine IDLE is not part of the OBFF state logic. 1: Engine IDLE is part of the OBFF state logic.
35426 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_DEVICE_IDLE_FORCE (0x1<<2) // Setting this bit forces the CPMU to force the device IDLE condition for OBFF operations.
35428 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_IGU_PENDING_INTERRUPT_EN (0x1<<3) // 0 : IGU Pending Interrupt is not part of OBFF logic w.r.t. IGU requests. 1 : IGU Pending Interrupt is part of OBFF logic w.r.t. IGU requests.
35430 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_VOQ_IGU_REQUESTS_EN (0x1<<4) // 0 : VOQ for IGU requests is not part of OBFF logic w.r.t. IGU requests. 1 : VOQ for IGU requests is part of OBFF logic w.r.t. IGU requests.
35432 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_INTERRUPTS_EN (0x1<<5) // 0 : Interrupts are not part of OBFF logic w.r.t. IGU requests. 1 : Interrupts are part of OBFF logic w.r.t. IGU requests.
35436 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_MEM_SET_VQ_EN (0x1<<8) // 0 : For the FSM that drives stall_mem control, the control set logic is not conditioned with VOQ empty. 1 : For the FSM that drives stall_mem control, the control set logic is conditioned with VOQ empty.
35438 #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_INT_SET_INT_EN (0x1<<9) // 0 : For the FSM that drives stall_int control, the control set logic is not conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt. 1 : For the FSM that drives stall_int control, the control set logic is conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt.
35440 #define CPMU_REG_SW_OBFF_EXIT 0x030228UL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to force an exit from the OBFF related stalls. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
35451 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of OBFF logic. 1 : PBF Empty is not part of OBFF logic.
35453 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_TX_EN (0x1<<1) // 0 : QM Tx Empty is not part of OBFF logic. 1 : QM Tx Empty is part of OBFF logic.
35455 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_GLOBAL_EN (0x1<<2) // 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is part of main clock slowdown generation logic.
35457 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Queue Empty is not part of OBFF logic. 1 : All Send Queue Empty is part of OBFF logic.
35459 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MGMT_EMPTY_EN (0x1<<4) // 0 : Management Traffic is not part of OBFF logic. 1 : Management Traffic is part of OBFF logic.
35461 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_BRB_EMPTY_EN (0x1<<5) // 0 : BRB empty is not part of OBFF logic. 1 : BRB empty is part of OBFF logic.
35463 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PXP_EMPTY_EN (0x1<<6) // 0 : PXP empty is not part of OBFF logic. 1 : PXP empty is part of OBFF logic.
35465 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is not part of OBFF logic. 1 : CAU IDLE is part of OBFF logic.
35467 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan status is not part of OBFF logic. 1 : Timer Scan status is part of OBFF logic.
35469 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_OBFF_STATE_EN (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of OBFF logic. 1 : OBFF State (non CPU_ACTIVE) is part of OBFF logic.
35471 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TSEM_IDLE_EN (0x1<<10) // 0 : TSEM IDLE is not part of OBFF logic. 1 : TSEM IDLE is part of OBFF logic.
35473 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MSEM_IDLE_EN (0x1<<11) // 0 : MSEM IDLE is not part of OBFF logic. 1 : MSEM IDLE is part of OBFF logic.
35475 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_USEM_IDLE_EN (0x1<<12) // 0 : USEM IDLE is not part of OBFF logic. 1 : USEM IDLE is part of OBFF logic.
35477 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_XSEM_IDLE_EN (0x1<<13) // 0 : XSEM IDLE is not part of OBFF logic. 1 : XSEM IDLE is part of OBFF logic.
35479 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_YSEM_IDLE_EN (0x1<<14) // 0 : YSEM IDLE is not part of OBFF logic. 1 : YSEM IDLE is part of OBFF logic.
35481 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PSEM_IDLE_EN (0x1<<15) // 0 : PSEM IDLE is not part of OBFF logic. 1 : PSEM IDLE is part of OBFF logic.
35483 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_RX_LPI_STATUS_EN (0x1<<16) // 0 : LPI receive status is not part of OBFF logic. 1 : LPI receive status is part of OBFF logic.
35485 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NW_LINKDOWN_EN (0x1<<17) // 0 : Network Link Down is not part of OBFF logic. 1 : Network Link Down is part of OBFF logic.
35487 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_RX_EMPTY_EN (0x1<<18) // 0 : NIG Rx Empty is not part of OBFF logic. 1 : NIG Rx Empty is part of OBFF logic.
35489 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_TX_EMPTY_EN (0x1<<19) // 0 : NIG Tx Empty is not part of OBFF logic. 1 : NIG Tx Empty is part of OBFF logic.
35491 #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_LB_EMPTY_EN (0x1<<20) // 0 : NIG lb Empty is not part of OBFF logic. 1 : NIG lb Empty is part of OBFF logic.
35494 #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_PCIE_L1_EXIT_EN (0x1<<0) // 0 : PCIe L1 exit is not part of exit from OBFF logic 1 : PCIe L1 exit is part of exit from OBFF logic
35496 #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_DORQ_EVENT_EN (0x1<<1) // 0 : DORQ Event is not part of exit from OBFF logic 1 : DORQ Event is part of exit from OBFF logic
35498 #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_SQ_EARLY_EXIT_EN (0x1<<2) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the OBFF exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, OBFF will exit.
35503 #define CPMU_REG_L1_MODE_CONFIG 0x030264UL //Access:RW DataWidth:0x1 // 0 : Entry to PCIe L1 is not enabled. 1 : Entry to PCIe L1 is enabled. This reflects the CPMU output and it is in addition to PCIE CORE register which controls entry to L1.
35506 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of L1 request generation logic. 1 : PBF Empty is part of L1 request generation logic.
35508 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_TX_EN (0x1<<1) // 0 : QM Tx Empty is not part of L1 request generation logic. 1 : QM Tx Empty is part of L1 request generation logic.
35510 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_GLOBAL_EN (0x1<<2) // 0 : QM Global Empty is not part of L1 request generation logic. 1 : QM Global Empty is part of L1 request generation logic.
35512 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Queue Empty is not part of L1 request generation logic. 1 : All Send Queue Empty is part of L1 request generation logic.
35514 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_MGMT_EMPTY_EN (0x1<<4) // 0 : Management Traffic is not part of L1 request generation logic. 1 : Management Traffic is part of L1 request generation logic.
35516 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_BRB_EMPTY_EN (0x1<<5) // 0 : BRB empty is not part of L1 request generation logic. 1 : BRB empty is part of L1 request generation logic.
35518 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PXP_EMPTY_EN (0x1<<6) // 0 : PXP empty is not part of L1 request generation logic. 1 : PXP empty is part of L1 request generation logic.
35520 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PGL_EMPTY_EN (0x1<<7) // 0 : PGL empty is not part of L1 request generation logic. 1 : PGL empty is part of L1 request generation logic.
35522 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_CAU_IDLE_EN (0x1<<8) // 0 : CAU IDLE is not part of L1 request generation logic. 1 : CAU IDLE is part of L1 request generation logic.
35524 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_TM_SCAN_EN (0x1<<9) // 0 : Timer Scan status is not part of L1 request generation logic. 1 : Timer Scan status is part of L1 request generation logic.
35526 #define CPMU_REG_L1_MODE_ENTRY_EN_L1_RX_LPI_STATUS_EN (0x1<<10) // 0 : LPI receive status is not part of L1 request generation logic. 1 : LPI receive status is part of L1 request generation logic.
35529 #define CPMU_REG_L1_MODE_EXIT_EN_L1_RX_LPI_STATUS_EXIT_EN (0x1<<0) // 0 : LPI recive status is not part of the L1 exit. 1 : LPI recive status is part of the L1 exit.
35531 #define CPMU_REG_L1_MODE_EXIT_EN_L1_SQ_EARLY_EXIT_EN (0x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the L1 exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, L1 will exit.
35533 #define CPMU_REG_SW_FORCE_L1 0x030274UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force an L1 request on the interface. Clearing this bit will not automatically guarantee an exit from L1 if other elements in the L1 equation is causing an L1 request to go out. To do a forceful exit, SW needs to assert the sw_l1_exit register.
35534 #define CPMU_REG_SW_L1_EXIT 0x030278UL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indication to exit L1 state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
35535 #define CPMU_REG_LTR_MODE_CONFIG 0x03027cUL //Access:RW DataWidth:0x1 // 0 : Entry to PCIe LTR is not enabled. 1 : Entry to PCIe LTR is enabled
35538 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of LTR request generation logic. 1 : PBF Empty is part of LTR request generation logic.
35540 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_TX_EN (0x1<<1) // 0 : QM Tx Empty is not part of LTR request generation logic. 1 : QM Tx Empty is part of LTR request generation logic.
35542 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_GLOBAL_EN (0x1<<2) // 0 : QM Global Empty is not part of LTR request generation logic. 1 : QM Global Empty is part of LTR request generation logic.
35544 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Queue Empty is not part of LTR request generation logic. 1 : All Send Queue Empty is part of LTR request generation logic.
35546 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_MGMT_EMPTY_EN (0x1<<4) // 0 : Management Traffic is not part of LTR request generation logic. 1 : Management Traffic is part of LTR request generation logic.
35548 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_BRB_CHECK_EN (0x1<<5) // 0 : BRB above threshold is not part of LTR request generation logic. 1 : BRB above threshold is part of LTR request generation logic.
35550 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PXP_EMPTY_EN (0x1<<6) // 0 : PXP empty is not part of LTR request generation logic. 1 : PXP empty is part of LTR request generation logic.
35552 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PGL_EMPTY_EN (0x1<<7) // 0 : PGL empty is not part of LTR request generation logic. 1 : PGL empty is part of LTR request generation logic.
35554 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_CAU_IDLE_EN (0x1<<8) // 0 : CAU IDLE is not part of LTR request generation logic. 1 : CAU IDLE is part of LTR request generation logic.
35556 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_TM_SCAN_EN (0x1<<9) // 0 : Timer Scan status is not part of LTR request generation logic. 1 : Timer Scan status is part of LTR request generation logic.
35558 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_RX_LPI_STATUS_EN (0x1<<10) // 0 : LPI receive status is not part of LTR request generation logic. 1 : LPI receive status is part of LTR request generation logic.
35560 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_MEM_STALL_EN (0x1<<11) // 0 : OBFF Memory access stall is not part of LTR request generation logic. 1 : OBFF Memory access stall is part of LTR request generation logic.
35562 #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_INT_STALL_EN (0x1<<12) // 0 : OBFF interrupt access stall is not part of LTR request generation logic. 1 : OBFF interrupt access stall is part of LTR request generation logic.
35565 #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_RX_LPI_STATUS_EXIT_EN (0x1<<0) // 0 : LPI recive status is not part of the LTR exit. 1 : LPI recive status is part of the LTR exit.
35567 #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_SQ_EARLY_EXIT_EN (0x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the LTR exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, LTR will exit.
35569 #define CPMU_REG_SW_FORCE_LTR 0x03028cUL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force an LTR request on the interface. Clearing this bit will not automatically guarantee an exit from LTR if other elements in the LTR equation is causing an LTR request to go out. To do a forceful exit, SW needs to assert the sw_ltr_exit register.
35570 #define CPMU_REG_SW_LTR_EXIT 0x030290UL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indication to exit LTR state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.
35572 #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E0_EN (0x1<<0) // 0 : Shutdown Main Clock to Path 0 1 : Enable Main Clock to Path 0
35574 #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E1_EN (0x1<<1) // 0 : Shutdown Main Clock to Path 1 1 : Enable Main Clock to Path 1
35576 #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E0_EN (0x1<<2) // 0 : Shutdown Main Clock to Path 0 on the Network side 1 : Enable Main Clock to Path 0 on the Network side
35578 #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E1_EN (0x1<<3) // 0 : Shutdown Main Clock to Path 1 on the Network side 1 : Enable Main Clock to Path 1 on the Network side
35580 #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NMC_EN (0x1<<4) // 0 : Shutdown Main Clock to Common Logic on the Network side 1 : Enable Main Clock to Common Logic on the Network side
35582 #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_HOST_EN (0x1<<5) // 0 : Shutdown Main Clock to Common Logic on the Host side 1 : Enable Main Clock to Common Logic on the Host side
35584 #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E0_EN (0x1<<6) // 0 : Shutdown STORM Clock to Path 0 1 : Enable STORM Clock to Path 0
35586 #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E1_EN (0x1<<7) // 0 : Shutdown STORM Clock to Path 1 1 : Enable STORM Clock to Path 1
35588 #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E0_EN (0x1<<8) // 0 : Shutdown Network Clock to Path 0 1 : Enable Network Clock to Path 0
35590 #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E1_EN (0x1<<9) // 0 : Shutdown Network Clock to Path 1 1 : Enable Network Clock to Path 1
35592 #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_CMN_EN (0x1<<10) // 0 : Shutdown Network Clock to Common logic 1 : Enable Network Clock to Common logic
35594 #define CPMU_REG_CLK_EN_CONFIG_CFG_CLK_EN (0x1<<11) // 0 : Shutdown Configuration Clock to PCIe Core 1 : Enable Configuration Clock to PCIe Core
35596 #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E0_EN (0x1<<12) // 0 : Shutdown PCI Clock to Path 0 1 : Enable PCI clock to Path 0
35598 #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E1_EN (0x1<<13) // 0 : Shutdown PCI Clock to Path 1 1 : Enable PCI clock to Path 1
35600 #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_HOST_EN (0x1<<14) // 0 : Shutdown PCI Clock to Common logic on the host side 1 : Enable PCI clock to Common logic on the host side
35602 #define CPMU_REG_CLK_EN_CONFIG_PMFC_CLK_EN (0x1<<15) // 0 : Shutdown all clocks to the Falcon based Port Macro 1 : Enable all clocks to the Falcon based Port Macro
35604 #define CPMU_REG_CLK_EN_CONFIG_PMEG_CLK_EN (0x1<<16) // 0 : Shutdown all clocks to the Eagle based Port Macro 1 : Enable all clocks to the Eagle based Port Macro
35606 #define CPMU_REG_CLK_EN_CONFIG_NWM_CLK_EN (0x1<<17) // 0 : Shutdown NWM clock to the NW MAC 1 : Enable NWM clock to the NW MAC
35608 #define CPMU_REG_CLK_EN_CONFIG_BMB_CLK_EN (0x1<<18) // 0 : Shutdown Main Clock to the BMB PD 1 : Enable Main Clock to the BMB PD
35610 #define CPMU_REG_CLK_EN_CONFIG_BMB_NW_CLK_EN (0x1<<19) // 0 : Shutdown Network Clock to the BMB PD 1 : Enable Network Clock to the BMB PD
35612 #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_EN (0x1<<20) // 0 : Shutdown Main Clock to the NW PD 1 : Enable Main Clock to the NW PD
35614 #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_CLK_EN (0x1<<21) // 0 : Shutdown Main Clock to the NMC PD 1 : Enable Main Clock to the NMC PD
35616 #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_NW_CLK_EN (0x1<<22) // 0 : Shutdown Network Clock to the NMC PD 1 : Enable Network Clock to the NMC PD
35618 #define CPMU_REG_CLK_EN_CONFIG_NMC_AHB_CLK_EN (0x1<<23) // 0 : Shutdown AHB Clock to the NMC PD 1 : Enable AHB Clock to the NMC PD
35620 #define CPMU_REG_CLK_EN_CONFIG_TOP_CLK_EN (0x1<<24) // 0 : Shutdown Main Clock to the TOP 1 : Enable Main Clock to the TOP
35623 #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_MAIN_CLK_EN (0x1<<0) // 0 : Slowdown of Main Clock is not enabled. 1 : Slowdown of Main Clock is enabled
35625 #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_STORM_CLK_EN (0x1<<1) // 0 : Slowdown of STORM Clock is not enabled. 1 : Slowdown of STORM Clock is enabled
35627 #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_NW_CLK_EN (0x1<<2) // 0 : Slowdown of Network Clock is not enabled. 1 : Slowdown of Network Clock is enabled
35629 #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_PCI_CLK_EN (0x1<<3) // 0 : Slowdown of PCI Clock is not enabled. 1 : Slowdown of PCI Clock is enabled
35632 #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_MAIN_CLK_CMN_EN (0x1<<0) // 0 : Slowdown of Main Clock for common logic is not enabled. 1 : Slowdown of Main Clock for common logic is enabled
35634 #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_NW_CLK_CMN_EN (0x1<<1) // 0 : Slowdown of Network Clock for common logic is not enabled. 1 : Slowdown of Network Clock for common logic is enabled
35636 #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_PCI_CLK_CMN_EN (0x1<<2) // 0 : Slowdown of PCI Clock for common logic is not enabled. 1 : Slowdown of PCI Clock for common logic is enabled
35647 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of main clock slowdown logic. 1 : PBF Empty is not part of main clock slowdown logic.
35649 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_TX_EN (0x1<<1) // 0 : QM Tx Empty is not part of main clock slowdown generation logic. 1 : QM Tx Empty is part of main clock slowdown generation logic.
35651 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_GLOBAL_EN (0x1<<2) // 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is part of main clock slowdown generation logic.
35653 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Queue Empty is not part of Main Clock slowdown logic. 1 : All Send Queue Empty is part of Main Clock slowdown logic.
35655 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MGMT_EMPTY_EN (0x1<<4) // 0 : Management Traffic is not part of Main Clock slowdown logic. 1 : Management Traffic is part of Main Clock slowdown logic.
35657 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_BRB_EMPTY_EN (0x1<<5) // 0 : BRB empty is not part of Main Clock slowdown logic. 1 : BRB empty is part of Main Clock slowdown logic.
35659 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PXP_EMPTY_EN (0x1<<6) // 0 : PXP empty is not part of Main Clock slowdown logic. 1 : PXP empty is part of Main Clock slowdown logic.
35661 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is not part of Main Clock slowdown logic. 1 : CAU IDLE is part of Main Clock slowdown logic.
35663 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan status is not part of Main Clock slowdown logic. 1 : Timer Scan status is part of Main Clock slowdown logic.
35665 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_OBFF_STATE_EN (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Main Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Main Clock slowdown logic.
35667 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TSEM_IDLE_EN (0x1<<10) // 0 : TSEM IDLE is not part of Main Clock slowdown logic. 1 : TSEM IDLE is part of Main Clock slowdown logic.
35669 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MSEM_IDLE_EN (0x1<<11) // 0 : MSEM IDLE is not part of Main Clock slowdown logic. 1 : MSEM IDLE is part of Main Clock slowdown logic.
35671 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_USEM_IDLE_EN (0x1<<12) // 0 : USEM IDLE is not part of Main Clock slowdown logic. 1 : USEM IDLE is part of Main Clock slowdown logic.
35673 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_XSEM_IDLE_EN (0x1<<13) // 0 : XSEM IDLE is not part of Main Clock slowdown logic. 1 : XSEM IDLE is part of Main Clock slowdown logic.
35675 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_YSEM_IDLE_EN (0x1<<14) // 0 : YSEM IDLE is not part of Main Clock slowdown logic. 1 : YSEM IDLE is part of Main Clock slowdown logic.
35677 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PSEM_IDLE_EN (0x1<<15) // 0 : PSEM IDLE is not part of Main Clock slowdown logic. 1 : PSEM IDLE is part of Main Clock slowdown logic.
35679 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_RX_LPI_STATUS_EN (0x1<<16) // 0 : LPI receive status is not part of Main Clock slowdown logic. 1 : LPI receive status is part of Main Clock slowdown logic.
35681 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NW_LINKDOWN_EN (0x1<<17) // 0 : Network Link Down is not part of Main Clock slowdown logic. 1 : Network Link Down is part of Main Clock slowdown logic.
35683 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_RX_EMPTY_EN (0x1<<18) // 0 : NIG Rx Empty is not part of Main Clock slowdown logic. 1 : NIG Rx Empty is part of Main Clock slowdown logic.
35685 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_TX_EMPTY_EN (0x1<<19) // 0 : NIG Tx Empty is not part of Main Clock slowdown logic. 1 : NIG Tx Empty is part of Main Clock slowdown logic.
35687 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_LB_EMPTY_EN (0x1<<20) // 0 : NIG Loopback Empty is not part of Main Clock slowdown logic. 1 : NIG Loopback Empty is part of Main Clock slowdown logic.
35689 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PCIE_IN_D3_EN (0x1<<21) // 0 : PCIE in D3 is not part of Main Clock slowdown logic. 1 : PCIE in D3 is part of Main Clock slowdown logic.
35692 #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_PCIE_L1_EXIT_EN (0x1<<0) // 0 : PCIe L1 exit is not part of exit from main clock slowdown logic 1 : PCIe L1 exit is part of exit from main clock slowdown logic
35694 #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_DORQ_EVENT_EN (0x1<<1) // 0 : DORQ Event is not part of exit from main clock slowdown logic 1 : DORQ Event is part of exit from main clock slowdown logic
35696 #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_NCSI_EVENT_EN (0x1<<2) // 0 : NCSI Event is not part of exit from main clock slowdown logic 1 : NCSI Event is part of exit from main clock slowdown logic
35698 #define CPMU_REG_SW_FORCE_MAIN_CLK_SLOWDOWN 0x0302c8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force slowdown of main clock for the corresponding path.
35699 #define CPMU_REG_SW_FORCE_MAIN_CLK_EXIT 0x0302ccUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indication to exit main clock slowdown.
35701 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of storm clock slowdown logic. 1 : PBF Empty is not part of storm clock slowdown logic.
35703 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_TX_EN (0x1<<1) // 0 : QM Tx Empty is not part of storm clock slowdown generation logic. 1 : QM Tx Empty is part of storm clock slowdown generation logic.
35705 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_GLOBAL_EN (0x1<<2) // 0 : QM Global Empty is not part of storm clock slowdown generation logic. 1 : QM Global Empty is part of storm clock slowdown generation logic.
35707 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Queue Empty is not part of Storm Clock slowdown logic. 1 : All Send Queue Empty is part of Storm Clock slowdown logic.
35709 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MGMT_EMPTY_EN (0x1<<4) // 0 : Management Traffic is not part of Storm Clock slowdown logic. 1 : Management Traffic is part of Storm Clock slowdown logic.
35711 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_BRB_EMPTY_EN (0x1<<5) // 0 : BRB empty is not part of Storm Clock slowdown logic. 1 : BRB empty is part of Storm Clock slowdown logic.
35713 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PXP_EMPTY_EN (0x1<<6) // 0 : PXP empty is not part of Storm Clock slowdown logic. 1 : PXP empty is part of Storm Clock slowdown logic.
35715 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is not part of Storm Clock slowdown logic. 1 : CAU IDLE is part of Storm Clock slowdown logic.
35717 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan status is not part of Storm Clock slowdown logic. 1 : Timer Scan status is part of Storm Clock slowdown logic.
35719 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_OBFF_STATE_EN (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Storm Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Storm Clock slowdown logic.
35721 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TSEM_IDLE_EN (0x1<<10) // 0 : TSEM IDLE is not part of Storm Clock slowdown logic. 1 : TSEM IDLE is part of Storm Clock slowdown logic.
35723 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MSEM_IDLE_EN (0x1<<11) // 0 : MSEM IDLE is not part of Storm Clock slowdown logic. 1 : MSEM IDLE is part of Storm Clock slowdown logic.
35725 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_USEM_IDLE_EN (0x1<<12) // 0 : USEM IDLE is not part of Storm Clock slowdown logic. 1 : USEM IDLE is part of Storm Clock slowdown logic.
35727 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_XSEM_IDLE_EN (0x1<<13) // 0 : XSEM IDLE is not part of Storm Clock slowdown logic. 1 : XSEM IDLE is part of Storm Clock slowdown logic.
35729 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_YSEM_IDLE_EN (0x1<<14) // 0 : YSEM IDLE is not part of Storm Clock slowdown logic. 1 : YSEM IDLE is part of Storm Clock slowdown logic.
35731 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PSEM_IDLE_EN (0x1<<15) // 0 : PSEM IDLE is not part of Storm Clock slowdown logic. 1 : PSEM IDLE is part of Storm Clock slowdown logic.
35733 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_RX_LPI_STATUS_EN (0x1<<16) // 0 : LPI receive status is not part of Storm Clock slowdown logic. 1 : LPI receive status is part of Storm Clock slowdown logic.
35735 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NW_LINKDOWN_EN (0x1<<17) // 0 : Network Link Down is not part of Storm Clock slowdown logic. 1 : Network Link Down is part of Storm Clock slowdown logic.
35737 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_RX_EMPTY_EN (0x1<<18) // 0 : NIG Rx Empty is not part of Storm Clock slowdown logic. 1 : NIG Rx Empty is part of Storm Clock slowdown logic.
35739 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_TX_EMPTY_EN (0x1<<19) // 0 : NIG Tx Empty is not part of Storm Clock slowdown logic. 1 : NIG Tx Empty is part of Storm Clock slowdown logic.
35741 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_LB_EMPTY_EN (0x1<<20) // 0 : NIG Loopback Empty is not part of Storm Clock slowdown logic. 1 : NIG Loopback Empty is part of Storm Clock slowdown logic.
35743 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PCIE_IN_D3_EN (0x1<<21) // 0 : PCIE in D3 is not part of Storm Clock slowdown logic. 1 : PCIE in D3 is part of Storm Clock slowdown logic.
35746 #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_PCIE_L1_EXIT_EN (0x1<<0) // 0 : PCIe L1 exit is not part of exit from storm clock slowdown logic 1 : PCIe L1 exit is part of exit from storm clock slowdown logic
35748 #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_DORQ_EVENT_EN (0x1<<1) // 0 : DORQ Event is not part of exit from storm clock slowdown logic 1 : DORQ Event is part of exit from storm clock slowdown logic
35750 #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_NCSI_EVENT_EN (0x1<<2) // 0 : NCSI Event is not part of exit from storm clock slowdown logic 1 : NCSI Event is part of exit from storm clock slowdown logic
35752 #define CPMU_REG_SW_FORCE_STORM_CLK_SLOWDOWN 0x0302d8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force slowdown of storm clock for the corresponding path.
35753 #define CPMU_REG_SW_FORCE_STORM_CLK_EXIT 0x0302dcUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indication to exit storm clock slowdown.
35755 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of nw clock slowdown logic. 1 : PBF Empty is not part of nw clock slowdown logic.
35757 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_TX_EN (0x1<<1) // 0 : QM Tx Empty is not part of nw clock slowdown generation logic. 1 : QM Tx Empty is part of nw clock slowdown generation logic.
35759 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_GLOBAL_EN (0x1<<2) // 0 : QM Global Empty is not part of nw clock slowdown generation logic. 1 : QM Global Empty is part of nw clock slowdown generation logic.
35761 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Queue Empty is not part of Nw Clock slowdown logic. 1 : All Send Queue Empty is part of Nw Clock slowdown logic.
35763 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MGMT_EMPTY_EN (0x1<<4) // 0 : Management Traffic is not part of Nw Clock slowdown logic. 1 : Management Traffic is part of Nw Clock slowdown logic.
35765 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_BRB_EMPTY_EN (0x1<<5) // 0 : BRB empty is not part of Nw Clock slowdown logic. 1 : BRB empty is part of Nw Clock slowdown logic.
35767 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PXP_EMPTY_EN (0x1<<6) // 0 : PXP empty is not part of Nw Clock slowdown logic. 1 : PXP empty is part of Nw Clock slowdown logic.
35769 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is not part of Nw Clock slowdown logic. 1 : CAU IDLE is part of Nw Clock slowdown logic.
35771 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan status is not part of Nw Clock slowdown logic. 1 : Timer Scan status is part of Nw Clock slowdown logic.
35773 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_OBFF_STATE_EN (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Nw Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Nw Clock slowdown logic.
35775 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TSEM_IDLE_EN (0x1<<10) // 0 : TSEM IDLE is not part of Nw Clock slowdown logic. 1 : TSEM IDLE is part of Nw Clock slowdown logic.
35777 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MSEM_IDLE_EN (0x1<<11) // 0 : MSEM IDLE is not part of Nw Clock slowdown logic. 1 : MSEM IDLE is part of Nw Clock slowdown logic.
35779 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_USEM_IDLE_EN (0x1<<12) // 0 : USEM IDLE is not part of Nw Clock slowdown logic. 1 : USEM IDLE is part of Nw Clock slowdown logic.
35781 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_XSEM_IDLE_EN (0x1<<13) // 0 : XSEM IDLE is not part of Nw Clock slowdown logic. 1 : XSEM IDLE is part of Nw Clock slowdown logic.
35783 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_YSEM_IDLE_EN (0x1<<14) // 0 : YSEM IDLE is not part of Nw Clock slowdown logic. 1 : YSEM IDLE is part of Nw Clock slowdown logic.
35785 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PSEM_IDLE_EN (0x1<<15) // 0 : PSEM IDLE is not part of Nw Clock slowdown logic. 1 : PSEM IDLE is part of Nw Clock slowdown logic.
35787 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_RX_LPI_STATUS_EN (0x1<<16) // 0 : LPI receive status is not part of Nw Clock slowdown logic. 1 : LPI receive status is part of Nw Clock slowdown logic.
35789 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NW_LINKDOWN_EN (0x1<<17) // 0 : Network Link Down is not part of Nw Clock slowdown logic. 1 : Network Link Down is part of Nw Clock slowdown logic.
35791 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_RX_EMPTY_EN (0x1<<18) // 0 : NIG Rx Empty is not part of Nw Clock slowdown logic. 1 : NIG Rx Empty is part of Nw Clock slowdown logic.
35793 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_TX_EMPTY_EN (0x1<<19) // 0 : NIG Tx Empty is not part of Nw Clock slowdown logic. 1 : NIG Tx Empty is part of Nw Clock slowdown logic.
35795 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_LB_EMPTY_EN (0x1<<20) // 0 : NIG Loopback Empty is not part of Nw Clock slowdown logic. 1 : NIG Loopback Empty is part of Nw Clock slowdown logic.
35797 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PCIE_IN_D3_EN (0x1<<21) // 0 : PCIE in D3 is not part of NW Clock slowdown logic. 1 : PCIE in D3 is part of NW Clock slowdown logic.
35800 #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_PCIE_L1_EXIT_EN (0x1<<0) // 0 : PCIe L1 exit is not part of exit from nw clock slowdown logic 1 : PCIe L1 exit is part of exit from nw clock slowdown logic
35802 #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_DORQ_EVENT_EN (0x1<<1) // 0 : DORQ Event is not part of exit from nw clock slowdown logic 1 : DORQ Event is part of exit from nw clock slowdown logic
35804 #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_NCSI_EVENT_EN (0x1<<2) // 0 : NCSI Event is not part of exit from nw clock slowdown logic 1 : NCSI Event is part of exit from nw clock slowdown logic
35806 #define CPMU_REG_SW_FORCE_NW_CLK_SLOWDOWN 0x0302e8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force slowdown of nw clock for the corresponding path.
35807 #define CPMU_REG_SW_FORCE_NW_CLK_EXIT 0x0302ecUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indication to exit nw clock slowdown.
35809 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PBF_EMPTY_EN (0x1<<0) // 0 : PBF Empty is not part of pci clock slowdown logic. 1 : PBF Empty is not part of pci clock slowdown logic.
35811 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_TX_EN (0x1<<1) // 0 : QM Tx Empty is not part of pci clock slowdown generation logic. 1 : QM Tx Empty is part of pci clock slowdown generation logic.
35813 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_GLOBAL_EN (0x1<<2) // 0 : QM Global Empty is not part of pci clock slowdown generation logic. 1 : QM Global Empty is part of pci clock slowdown generation logic.
35815 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Queue Empty is not part of PCI Clock slowdown logic. 1 : All Send Queue Empty is part of PCI Clock slowdown logic.
35817 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MGMT_EMPTY_EN (0x1<<4) // 0 : Management Traffic is not part of PCI Clock slowdown logic. 1 : Management Traffic is part of PCI Clock slowdown logic.
35819 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_BRB_EMPTY_EN (0x1<<5) // 0 : BRB empty is not part of PCI Clock slowdown logic. 1 : BRB empty is part of PCI Clock slowdown logic.
35821 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PXP_EMPTY_EN (0x1<<6) // 0 : PXP empty is not part of PCI Clock slowdown logic. 1 : PXP empty is part of PCI Clock slowdown logic.
35823 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_CAU_IDLE_EN (0x1<<7) // 0 : CAU IDLE is not part of PCI Clock slowdown logic. 1 : CAU IDLE is part of PCI Clock slowdown logic.
35825 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TM_SCAN_EN (0x1<<8) // 0 : Timer Scan status is not part of PCI Clock slowdown logic. 1 : Timer Scan status is part of PCI Clock slowdown logic.
35827 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_OBFF_STATE_EN (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of PCI Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of PCI Clock slowdown logic.
35829 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TSEM_IDLE_EN (0x1<<10) // 0 : TSEM IDLE is not part of PCI Clock slowdown logic. 1 : TSEM IDLE is part of PCI Clock slowdown logic.
35831 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MSEM_IDLE_EN (0x1<<11) // 0 : MSEM IDLE is not part of PCI Clock slowdown logic. 1 : MSEM IDLE is part of PCI Clock slowdown logic.
35833 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_USEM_IDLE_EN (0x1<<12) // 0 : USEM IDLE is not part of PCI Clock slowdown logic. 1 : USEM IDLE is part of PCI Clock slowdown logic.
35835 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_XSEM_IDLE_EN (0x1<<13) // 0 : XSEM IDLE is not part of PCI Clock slowdown logic. 1 : XSEM IDLE is part of PCI Clock slowdown logic.
35837 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_YSEM_IDLE_EN (0x1<<14) // 0 : YSEM IDLE is not part of PCI Clock slowdown logic. 1 : YSEM IDLE is part of PCI Clock slowdown logic.
35839 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PSEM_IDLE_EN (0x1<<15) // 0 : PSEM IDLE is not part of PCI Clock slowdown logic. 1 : PSEM IDLE is part of PCI Clock slowdown logic.
35841 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_RX_LPI_STATUS_EN (0x1<<16) // 0 : LPI receive status is not part of PCI Clock slowdown logic. 1 : LPI receive status is part of PCI Clock slowdown logic.
35843 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NW_LINKDOWN_EN (0x1<<17) // 0 : Network Link Down is not part of PCI Clock slowdown logic. 1 : Network Link Down is part of PCI Clock slowdown logic.
35845 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_RX_EMPTY_EN (0x1<<18) // 0 : NIG Rx Empty is not part of PCI Clock slowdown logic. 1 : NIG Rx Empty is part of PCI Clock slowdown logic.
35847 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_TX_EMPTY_EN (0x1<<19) // 0 : NIG Tx Empty is not part of PCI Clock slowdown logic. 1 : NIG Tx Empty is part of PCI Clock slowdown logic.
35849 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_LB_EMPTY_EN (0x1<<20) // 0 : NIG Loopback Empty is not part of PCI Clock slowdown logic. 1 : NIG Loopback Empty is part of PCI Clock slowdown logic.
35851 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PCIE_IN_D3_EN (0x1<<21) // 0 : PCIE in D3 is not part of PCI Clock slowdown logic. 1 : PCIE in D3 is part of PCI Clock slowdown logic.
35854 #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_PCIE_L1_EXIT_EN (0x1<<0) // 0 : PCIe L1 exit is not part of exit from pci clock slowdown logic 1 : PCIe L1 exit is part of exit from pci clock slowdown logic
35856 #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_DORQ_EVENT_EN (0x1<<1) // 0 : DORQ Event is not part of exit from pci clock slowdown logic 1 : DORQ Event is part of exit from pci clock slowdown logic
35858 #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_NCSI_EVENT_EN (0x1<<2) // 0 : NCSI Event is not part of exit from pci clock slowdown logic 1 : NCSI Event is part of exit from pci clock slowdown logic
35860 #define CPMU_REG_SW_FORCE_PCI_CLK_SLOWDOWN 0x0302f8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force slowdown of pci clock for the corresponding path.
35861 #define CPMU_REG_SW_FORCE_PCI_CLK_EXIT 0x0302fcUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indication to exit pci clock slowdown.
35869 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PATH_EMPTY_ISIG_STATUS (0x1<<4) // Current status of bmb_path_empty
35877 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E0_ISIG_STATUS (0x1<<13) // Current status of brb_path_empty_e0
35879 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E1_ISIG_STATUS (0x1<<14) // Current status of brb_path_empty_e1
35885 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E0_ISIG_STATUS (0x1<<19) // Current status of btb_path_empty_e0
35887 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E1_ISIG_STATUS (0x1<<20) // Current status of btb_path_empty_e1
35893 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E0_ISIG_STATUS (0x1<<25) // Current status of cau_path_idle_e0
35895 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E1_ISIG_STATUS (0x1<<26) // Current status of cau_path_idle_e1
35897 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E0_ISIG_STATUS (0x1<<27) // Current status of cnig_link_down_p0_e0
35899 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E1_ISIG_STATUS (0x1<<28) // Current status of cnig_link_down_p0_e1
35901 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E0_ISIG_STATUS (0x1<<29) // Current status of cnig_link_down_p1_e0
35903 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E1_ISIG_STATUS (0x1<<30) // Current status of cnig_link_down_p1_e1
35905 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_RX_LPI_P0_E0_ISIG_STATUS (0x1<<31) // Current status of cnig_rx_lpi_p0_e0
35908 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P0_E1_ISIG_STATUS (0x1<<0) // Current status of cnig_rx_lpi_p0_e1
35910 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E0_ISIG_STATUS (0x1<<1) // Current status of cnig_rx_lpi_p1_e0
35912 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E1_ISIG_STATUS (0x1<<2) // Current status of cnig_rx_lpi_p1_e1
35918 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<7) // Current status of msem_sem_idle_e0
35920 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<8) // Current status of msem_sem_idle_e1
35922 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NCSI_RX_EVENT_ISIG_STATUS (0x1<<9) // Current status of ncsi_rx_event
35924 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E0_ISIG_STATUS (0x1<<10) // Current status of nig_lb_empty_p0_e0
35926 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E1_ISIG_STATUS (0x1<<11) // Current status of nig_lb_empty_p0_e1
35928 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E0_ISIG_STATUS (0x1<<12) // Current status of nig_lb_empty_p1_e0
35930 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E1_ISIG_STATUS (0x1<<13) // Current status of nig_lb_empty_p1_e1
35932 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E0_ISIG_STATUS (0x1<<14) // Current status of nig_rx_empty_p0_e0
35934 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E1_ISIG_STATUS (0x1<<15) // Current status of nig_rx_empty_p0_e1
35936 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E0_ISIG_STATUS (0x1<<16) // Current status of nig_rx_empty_p1_e0
35938 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E1_ISIG_STATUS (0x1<<17) // Current status of nig_rx_empty_p1_e1
35940 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E0_ISIG_STATUS (0x1<<18) // Current status of nig_tx_empty_p0_e0
35942 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E1_ISIG_STATUS (0x1<<19) // Current status of nig_tx_empty_p0_e1
35944 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E0_ISIG_STATUS (0x1<<20) // Current status of nig_tx_empty_p1_e0
35946 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E1_ISIG_STATUS (0x1<<21) // Current status of nig_tx_empty_p1_e1
35948 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E0_ISIG_STATUS (0x1<<22) // Current status of pbf_path_empty_e0
35950 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E1_ISIG_STATUS (0x1<<23) // Current status of pbf_path_empty_e1
35957 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E0_ISIG_STATUS (0x1<<0) // Current status of pglue_int_deassert_e0
35959 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E1_ISIG_STATUS (0x1<<1) // Current status of pglue_int_deassert_e1
35963 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E0_ISIG_STATUS (0x1<<6) // Current status of pglue_path_in_d3_e0
35965 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E1_ISIG_STATUS (0x1<<7) // Current status of pglue_path_in_d3_e1
35967 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PGL_EMPTY_ISIG_STATUS (0x1<<8) // Current status of pglue_pgl_empty
35969 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<9) // Current status of psem_sem_idle_e0
35971 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<10) // Current status of psem_sem_idle_e1
35973 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E0_ISIG_STATUS (0x1<<11) // Current status of pxp_master_path_empty_e0
35975 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E1_ISIG_STATUS (0x1<<12) // Current status of pxp_master_path_empty_e1
35977 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E0_ISIG_STATUS (0x1<<13) // Current status of pxp_target_path_empty_e0
35979 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E1_ISIG_STATUS (0x1<<14) // Current status of pxp_target_path_empty_e1
35981 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E0_ISIG_STATUS (0x1<<15) // Current status of qm_global_empty_e0
35983 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E1_ISIG_STATUS (0x1<<16) // Current status of qm_global_empty_e1
35989 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E0_ISIG_STATUS (0x1<<25) // Current status of qm_tx_empty_e0
35991 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E1_ISIG_STATUS (0x1<<26) // Current status of qm_tx_empty_e1
35993 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E0_ISIG_STATUS (0x1<<27) // Current status of tm_during_scan_e0
35995 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E1_ISIG_STATUS (0x1<<28) // Current status of tm_during_scan_e1
35997 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<29) // Current status of tsem_sem_idle_e0
35999 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<30) // Current status of tsem_sem_idle_e1
36001 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_USEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<31) // Current status of usem_sem_idle_e0
36004 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_USEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<0) // Current status of usem_sem_idle_e1
36006 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<1) // Current status of xsem_sem_idle_e0
36008 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<2) // Current status of xsem_sem_idle_e1
36010 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<3) // Current status of ysem_sem_idle_e0
36012 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E1_ISIG_STATUS (0x1<<4) // Current status of ysem_sem_idle_e1
36014 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_PCIE_LINK_IN_L1_ISIG_STATUS (0x1<<5) // Current status of pcie_link_in_l1
36016 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E0_ISIG_STATUS (0x1<<6) // Current status of igu_cpmu_eee_pending_interrupt_e0
36018 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E1_ISIG_STATUS (0x1<<7) // Current status of igu_cpmu_eee_pending_interrupt_e1
36020 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P2_E0_ISIG_STATUS (0x1<<8) // Current status of nig_tx_empty_p2_e0
36022 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P3_E0_ISIG_STATUS (0x1<<9) // Current status of nig_tx_empty_p3_e0
36024 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P2_E0_ISIG_STATUS (0x1<<10) // Current status of nig_rx_empty_p2_e0
36026 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P3_E0_ISIG_STATUS (0x1<<11) // Current status of nig_rx_empty_p3_e0
36028 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P2_E0_ISIG_STATUS (0x1<<12) // Current status of nig_lb_empty_p2_e0
36030 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P3_E0_ISIG_STATUS (0x1<<13) // Current status of nig_lb_empty_p3_e0
36032 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P2_E0_ISIG_STATUS (0x1<<14) // Current status of cnig_link_down_p2_e0
36034 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P3_E0_ISIG_STATUS (0x1<<15) // Current status of cnig_link_down_p3_e0
36036 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P2_E0_ISIG_STATUS (0x1<<16) // Current status of cnig_rx_lpi_p2_e0
36038 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P3_E0_ISIG_STATUS (0x1<<17) // Current status of cnig_rx_lpi_p3_e0
36041 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E0_OSIG_STATUS (0x1<<0) // Current status of cnig_lpi_req_p0_e0
36043 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E1_OSIG_STATUS (0x1<<1) // Current status of cnig_lpi_req_p0_e1
36045 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E0_OSIG_STATUS (0x1<<2) // Current status of cnig_lpi_req_p1_e0
36047 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E1_OSIG_STATUS (0x1<<3) // Current status of cnig_lpi_req_p1_e1
36049 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_CMN_OSIG_STATUS (0x1<<4) // Current status of erstclk_main_clk_slowdown_cmn
36051 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E0_OSIG_STATUS (0x1<<5) // Current status of erstclk_main_clk_slowdown_e0
36053 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E1_OSIG_STATUS (0x1<<6) // Current status of erstclk_main_clk_slowdown_e1
36055 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_CMN_OSIG_STATUS (0x1<<7) // Current status of erstclk_nw_clk_slowdown_cmn
36057 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E0_OSIG_STATUS (0x1<<8) // Current status of erstclk_nw_clk_slowdown_e0
36059 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E1_OSIG_STATUS (0x1<<9) // Current status of erstclk_nw_clk_slowdown_e1
36061 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_CMN_OSIG_STATUS (0x1<<10) // Current status of erstclk_pci_clk_slowdown_cmn
36063 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E0_OSIG_STATUS (0x1<<11) // Current status of erstclk_pci_clk_slowdown_e0
36065 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E1_OSIG_STATUS (0x1<<12) // Current status of erstclk_pci_clk_slowdown_e1
36067 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E0_OSIG_STATUS (0x1<<13) // Current status of erstclk_storm_clk_slowdown_e0
36069 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E1_OSIG_STATUS (0x1<<14) // Current status of erstclk_storm_clk_slowdown_e1
36071 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E0_OSIG_STATUS (0x1<<15) // Current status of igu_stall_int_e0
36073 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E1_OSIG_STATUS (0x1<<16) // Current status of igu_stall_int_e1
36075 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PCIE_EARLY_L1_EXIT_OSIG_STATUS (0x1<<17) // Current status of pcie_early_l1_exit
36077 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PGLUE_SEND_LTR2_OSIG_STATUS (0x1<<18) // Current status of pglue_send_ltr2
36079 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E0_OSIG_STATUS (0x1<<19) // Current status of pxp_stall_mem_e0
36081 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E1_OSIG_STATUS (0x1<<20) // Current status of pxp_stall_mem_e1
36083 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P2_E0_OSIG_STATUS (0x1<<21) // Current status of cnig_lpi_req_p2_e0
36085 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P3_E0_OSIG_STATUS (0x1<<22) // Current status of cnig_lpi_req_p3_e0
36134 #define CPMU_REG_INT_STS_0 0x0303e0UL //Access:R DataWidth:0x1 // Multi Field Register.
36135 #define CPMU_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36137 #define CPMU_REG_INT_MASK_0 0x0303e4UL //Access:RW DataWidth:0x1 // Multi Field Register.
36138 #define CPMU_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: CPMU_REG_INT_STS_0.ADDRESS_ERROR .
36140 #define CPMU_REG_INT_STS_WR_0 0x0303e8UL //Access:WR DataWidth:0x1 // Multi Field Register.
36141 #define CPMU_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36143 #define CPMU_REG_INT_STS_CLR_0 0x0303ecUL //Access:RC DataWidth:0x1 // Multi Field Register.
36144 #define CPMU_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36152 #define NCSI_REG_PRTY_MASK_H_0 0x040004UL //Access:RW DataWidth:0x1 // Multi Field Register.
36153 #define NCSI_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NCSI_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
36157 #define NCSI_REG_CONFIG_PROMISCOUS (0x1<<0) // Setting this bit to a '1' will result in all packets received from BMC to be routed to MCP.
36159 #define NCSI_REG_CONFIG_ALL_MCP (0x1<<1) // Setting this bit to a '1' will result in all packets received from BMC that meet the matching of Source MAC address of the packet to the stored channel MAC address criteria to be routed to MCP.
36161 #define NCSI_REG_CONFIG_FWD_BCAST_TO_MCP (0x1<<2) // 0 -> Send all broadcast packets to the appropriate network port. 1 -> Send all broadcast packets to MCP
36163 #define NCSI_REG_CONFIG_FWD_MCAST_TO_MCP (0x1<<3) // 0 -> Send all multicast packets to the appropriate network port. 1 -> Send all multicast packets to MCP
36165 #define NCSI_REG_CONFIG_USE_VLAN_FOR_COMP (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2BMC traffic. 1 -> MAC and VLAN are used for comparision to detect Host2BMC traffic.
36167 #define NCSI_REG_CONFIG_SA_LEARNING_EN (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from Host to BMC. 1 -> Enable source MAC address learning for packets from Host to BMC.
36169 #define NCSI_REG_CONFIG_INVALIDATE_AGED_ENTRIES (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they are aged. 1 -> Entries in SA Learning Cache become invalid after they are aged.
36171 #define NCSI_REG_CONFIG_FLOW_CONTROL_EN (0x1<<7) // Setting this bit to a '1' will result in enabling flow control towards the BMC.
36173 #define NCSI_REG_CONFIG_SW_PAUSE (0x1<<8) // Setting this bit to a '1' will result in XOFF to be sent out to BMC. Clearing this register after it was set to '1' will cause an XON to be sent out.
36175 #define NCSI_REG_CONFIG_HOST2BMC_EN (0x1<<9) // Setting this bit to a '1' tells the HW that Host2BMC traffic is enabled.
36177 #define NCSI_REG_CONFIG_MII_SEL (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port 1 -> Select SGMII MII interface as the MII port
36179 #define NCSI_REG_CONFIG_MGMT_SRC_SEL (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Port 1 -> Select Proprietary SGMII interface as the Management port
36181 #define NCSI_REG_CONFIG_DROP_ALL_PKTS_WHEN_FULL (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the packets 0 -> Drop packets destined only to the particular TC when the TC specific full is asserted. Note: When global BMB Full condition is asserted, all the packets will be dropped irrespective of the settings of this register.
36183 #define NCSI_REG_CONFIG_ALL_PASS_THRU_TO_HOST (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to host, if HOST2BMC is enabled. 0 -> When not set, packets will follow the normal decision tree.
36185 #define NCSI_REG_PKT_ETHERTYPE_VALID 0x040204UL //Access:RW DataWidth:0x1 // When set, this bit indicates that the value in pkt_ethertype register is valid.
36187 #define NCSI_REG_BMC_MAC_VALID_FLAG_0 0x04020cUL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36188 #define NCSI_REG_BMC_MAC_VALID_FLAG_1 0x040210UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36189 #define NCSI_REG_BMC_MAC_VALID_FLAG_2 0x040214UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36190 #define NCSI_REG_BMC_MAC_VALID_FLAG_3 0x040218UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36203 #define NCSI_REG_SA_STATIC_VALID_FLAG_0 0x04024cUL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36204 #define NCSI_REG_SA_STATIC_VALID_FLAG_1 0x040250UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36205 #define NCSI_REG_SA_STATIC_VALID_FLAG_2 0x040254UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36206 #define NCSI_REG_SA_STATIC_VALID_FLAG_3 0x040258UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36207 #define NCSI_REG_SA_STATIC_VALID_FLAG_4 0x04025cUL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36208 #define NCSI_REG_SA_STATIC_VALID_FLAG_5 0x040260UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36209 #define NCSI_REG_SA_STATIC_VALID_FLAG_6 0x040264UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36210 #define NCSI_REG_SA_STATIC_VALID_FLAG_7 0x040268UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36211 #define NCSI_REG_SA_STATIC_VALID_FLAG_8 0x04026cUL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36212 #define NCSI_REG_SA_STATIC_VALID_FLAG_9 0x040270UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36213 #define NCSI_REG_SA_STATIC_VALID_FLAG_10 0x040274UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36214 #define NCSI_REG_SA_STATIC_VALID_FLAG_11 0x040278UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36215 #define NCSI_REG_SA_STATIC_VALID_FLAG_12 0x04027cUL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36216 #define NCSI_REG_SA_STATIC_VALID_FLAG_13 0x040280UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36217 #define NCSI_REG_SA_STATIC_VALID_FLAG_14 0x040284UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36218 #define NCSI_REG_SA_STATIC_VALID_FLAG_15 0x040288UL //Access:RW DataWidth:0x1 // This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36267 #define NCSI_REG_SA_CACHE_VALID_FLAG_0 0x04034cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36268 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_0 0x040350UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36269 #define NCSI_REG_SA_CACHE_VALID_FLAG_1 0x040354UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36270 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_1 0x040358UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36271 #define NCSI_REG_SA_CACHE_VALID_FLAG_2 0x04035cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36272 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_2 0x040360UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36273 #define NCSI_REG_SA_CACHE_VALID_FLAG_3 0x040364UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36274 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_3 0x040368UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36275 #define NCSI_REG_SA_CACHE_VALID_FLAG_4 0x04036cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36276 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_4 0x040370UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36277 #define NCSI_REG_SA_CACHE_VALID_FLAG_5 0x040374UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36278 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_5 0x040378UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36279 #define NCSI_REG_SA_CACHE_VALID_FLAG_6 0x04037cUL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36280 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_6 0x040380UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36281 #define NCSI_REG_SA_CACHE_VALID_FLAG_7 0x040384UL //Access:RW DataWidth:0x1 // This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag
36282 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_7 0x040388UL //Access:RW DataWidth:0x1 // This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.
36316 #define NCSI_REG_SA_CACHE_CLR 0x040410UL //Access:RW DataWidth:0x1 // When this bit is set, all the entries in the cache will be cleared.
36318 #define NCSI_REG_TAG_RM_CONFIG_PROP_HEADER_RM (0x1<<0) // Setting this bit to "1" will result in removing proprietary headers from all packets.
36332 #define NCSI_REG_TAG_INS_CONFIG_INSERT_PROP_HEADER (0x1<<0) // Tells HW to set the INS_PROP_HEADER flag in the SOP descriptor for a BMC to Network packet
36334 #define NCSI_REG_TAG_INS_CONFIG_INSERT_OUTER_TAG (0x1<<1) // Tells HW to set the INS_OUTER_TAG flag in the SOP descriptor for a BMC to Network packet
36336 #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN (0x1<<2) // Tells HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is non-zero
36338 #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_IF_NO_VLAN (0x1<<3) // Tells HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is zero or Set the INS_INNER_VLAN flag if there is no VLAN header in the packet. In this case even the priority is inserted
36340 #define NCSI_REG_TAG_INS_CONFIG_FORCE_PRIORITY (0x1<<4) // Tells HW to set the OVRRIDE_PRIORITY flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet
36345 #define NCSI_REG_SIDEBAND_ARB_UNUSED0 (0x1<<3) // Unused
36347 #define NCSI_REG_SIDEBAND_ARB_ARB_DISABLE (0x1<<4) // Setting this field to '1' causes the hardware arbitration scheme to be disabled. This bit should be set when there is only one NCSI port on the board and tokens need not be passed out.
36349 #define NCSI_REG_SIDEBAND_ARB_ARB_START (0x1<<5) // Setting this field to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
36351 #define NCSI_REG_SIDEBAND_ARB_ARB_BYPASS (0x1<<6) // Setting this field to '1' the HW arbitration logic to function in bypass mode. This allows NCSI ports that don't have the firmware running to be automatically bypassed. Firmware should also set this bit when there is nothing to send. This will reduce the latency of the token around the loop.
36353 #define NCSI_REG_SIDEBAND_ARB_ARB_AUTO_BYPASS (0x1<<7) // Setting this field to '1' causes the NCSI port to cut latency when forwarding a token.
36357 #define NCSI_REG_SIDEBAND_ARB_UNUSED1 (0x1<<13) // unused
36359 #define NCSI_REG_SIDEBAND_ARB_ARB_FC_DISABLE (0x1<<14) // Setting this bit disables the feature to send XOFF/XON ordered sets on the arbiter interface. This feature is enabled by default and allows a NCSI port that wants to send a XOFF/XON frame to use the sideband interface to accelerate sending the command on the MII bus. This helps reducing the size of the Rx FIFO needed when multiple NCSI ports are connected to the BMC.
36361 #define NCSI_REG_SIDEBAND_ARB_ARB_UPDATE (0x1<<15) // Toggle this bit to update this register. Write "1" and then write "0".
36365 #define NCSI_REG_ARB_TOKEN_VALID 0x04043cUL //Access:R DataWidth:0x1 // This bit indicates if the arbiter has a valid token.
36368 #define NCSI_REG_NCSI_RESET_EGRESS_RESET (0x1<<0) // Setting this bit will create an asychronous reset to the egress logic. Should be used only incase where the logic is stuck
36370 #define NCSI_REG_NCSI_RESET_INGRESS_RESET (0x1<<1) // Setting this bit will create an asychronous reset to the ingress logic. Should be used only incase where the logic is stuck
36393 #define NCSI_REG_INT_STS_0 0x0404ccUL //Access:R DataWidth:0x1 // Multi Field Register.
36394 #define NCSI_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36396 #define NCSI_REG_INT_MASK_0 0x0404d0UL //Access:RW DataWidth:0x1 // Multi Field Register.
36397 #define NCSI_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NCSI_REG_INT_STS_0.ADDRESS_ERROR .
36399 #define NCSI_REG_INT_STS_WR_0 0x0404d4UL //Access:WR DataWidth:0x1 // Multi Field Register.
36400 #define NCSI_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36402 #define NCSI_REG_INT_STS_CLR_0 0x0404d8UL //Access:RC DataWidth:0x1 // Multi Field Register.
36403 #define NCSI_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36405 #define GRC_REG_OVERRIDE_WINDOW_MEM_SELF_INIT_START 0x050000UL //Access:RW DataWidth:0x1 // Reset the protection override window memory. When set to 1, protection override window memory self init starts.
36406 #define GRC_REG_OVERRIDE_WINDOW_MEM_SELF_INIT_DONE 0x050004UL //Access:R DataWidth:0x1 // When = 1, the self init for the protection override window memory is done.
36409 #define GRC_REG_RSV_ATTN_ACCESS_VALID 0x050048UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the rsv_attn_access_data_0 and rsv_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
36412 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
36415 #define GRC_REG_PATH_ISOLATION_ERROR_VALID 0x050060UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the path_isolation_error_data_0 and path_isolation_error_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
36416 #define GRC_REG_TRACE_FIFO_VALID_DATA 0x050064UL //Access:R DataWidth:0x1 // If = 1, indicates that the trace FIFO contains at least one valid data. If = 0, indicates that the trace FIFO doeasn't contain any valid data. This register should be read before reading the GRC_REGISTERS_TRACE_FIFO, and only if the read value is 1, one read from the GRC_REGISTERS_TRACE_FIFO can be done.
36419 #define GRC_REG_TRACE_FIFO_ENABLE 0x050070UL //Access:RW DataWidth:0x1 // If = 1, the trace fifo feature is enabled and write of GRC wr/rd accesses to the FIFO is done based on the different trace FIFO configurtaions. If = 0, the trace fifo feature is disabled and no writes are done to the FIFO. It is recommended to disable this feature before reading from the GRC_REGISTERS_TRACE_FIFO.
36424 #define GRC_REG_TRACE_FIFO_VF_SEL 0x050084UL //Access:RW DataWidth:0x1 // If = 1, selects only the VF in GRC_REG_TRACE_FIFO_VF for the accesses that are written to the trace FIFO. If = 0, accesses with all VFs are written to the trace FIFO.
36431 #define GRC_REG_TRACE_FIFO_MODE 0x0500a0UL //Access:RW DataWidth:0x1 // Trace FIFO mode. If = 0, keeps the first 32 GRC accesses. When the FIFO is full new accesses are dropped. If = 1, keeps the last 32 GRC accesses. When the FIFO is full a new access overrides the first access.
36444 #define GRC_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36446 #define GRC_REG_INT_STS_0_TIMEOUT_EVENT (0x1<<1) // Timeout event
36448 #define GRC_REG_INT_STS_0_GLOBAL_RESERVED_ADDRESS (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
36450 #define GRC_REG_INT_STS_0_PATH_ISOLATION_ERROR (0x1<<3) // Path Isolation error.
36452 #define GRC_REG_INT_STS_0_TRACE_FIFO_VALID_DATA (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
36455 #define GRC_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.ADDRESS_ERROR .
36457 #define GRC_REG_INT_MASK_0_TIMEOUT_EVENT (0x1<<1) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.TIMEOUT_EVENT .
36459 #define GRC_REG_INT_MASK_0_GLOBAL_RESERVED_ADDRESS (0x1<<2) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.GLOBAL_RESERVED_ADDRESS .
36461 #define GRC_REG_INT_MASK_0_PATH_ISOLATION_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.PATH_ISOLATION_ERROR .
36463 #define GRC_REG_INT_MASK_0_TRACE_FIFO_VALID_DATA (0x1<<4) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.TRACE_FIFO_VALID_DATA .
36466 #define GRC_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36468 #define GRC_REG_INT_STS_WR_0_TIMEOUT_EVENT (0x1<<1) // Timeout event
36470 #define GRC_REG_INT_STS_WR_0_GLOBAL_RESERVED_ADDRESS (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
36472 #define GRC_REG_INT_STS_WR_0_PATH_ISOLATION_ERROR (0x1<<3) // Path Isolation error.
36474 #define GRC_REG_INT_STS_WR_0_TRACE_FIFO_VALID_DATA (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
36477 #define GRC_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36479 #define GRC_REG_INT_STS_CLR_0_TIMEOUT_EVENT (0x1<<1) // Timeout event
36481 #define GRC_REG_INT_STS_CLR_0_GLOBAL_RESERVED_ADDRESS (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
36483 #define GRC_REG_INT_STS_CLR_0_PATH_ISOLATION_ERROR (0x1<<3) // Path Isolation error.
36485 #define GRC_REG_INT_STS_CLR_0_TRACE_FIFO_VALID_DATA (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
36488 #define GRC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
36490 #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
36494 #define GRC_REG_TIMEOUT_EN 0x050404UL //Access:RW DataWidth:0x1 // Setting this bit enables a timer in the GRC block to timeout any access that does not finish within GRC_REGISTERS_TIMOUT_VAL.TIMEOUT_VAL cycles. When this bit is cleared the timeout is disabled.
36497 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW 0x050500UL //Access:WB DataWidth:0x37 // A protection override window that enables to override the protection levels of a range of GRC addresses. There are 20 windows. Each valid window can be applicable for rd access, wr access, or both. Each window contains the following fields: Bits [22:0]: Base address 4 bytes resolution). The GRC address which the window starts at. Bits [46:23]: Window size. The size of the window in the GRC space (for a window of one address needs to write value of 0x1). Bit [47]: Rd access. If = 1, the window is applicable for rd access. If = 0, the window is not applicable for rd access. Bit [48]: Wr access. If = 1, the window is applicable for wr access. If = 1, the window is not applicable for wr access. Bits [51:49]: Protection value rd access. The new protection value assigned to the range in rd access (if Rd access = 1). Bits [54:52]: Protection value wr access. The new protection value assigned to the range in wr access (if Wr access = 1).
36501 #define UMAC_REG_COMMAND_CONFIG_PORT_ENB_SYS (0x1<<0) // Enable/Disable MAC path for data packets.
36505 #define UMAC_REG_COMMAND_CONFIG_PCRCE (0x1<<5) // globally pad frame, and append CRC.
36507 #define UMAC_REG_COMMAND_CONFIG_CRCE (0x1<<6) // globally append CRC.
36509 #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_TX (0x1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
36511 #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_RX (0x1<<19) // When set, frames received by the PHY are transmitted. Received packet by the PHY are Transmitted by the PHY (remote loopback); when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
36513 #define UMAC_REG_COMMAND_CONFIG_TX_ENA (0x1<<0) // Enable/Disable MAC transmit path for data packets & pause/pfc packets sent in the normal data path. Pause/pfc packets generated internally are allowed if ignore_tx_pause is not set. When set to '0' (Reset value); the MAC transmit function is disable. When set to '1'; the MAC transmit function is enabled.
36515 #define UMAC_REG_COMMAND_CONFIG_RX_ENA (0x1<<1) // Enable/Disable MAC receive path. When set to '0' (Reset value); the MAC receive function is disable. When set to '1'; the MAC receive function is enabled.
36519 #define UMAC_REG_COMMAND_CONFIG_PROMIS_EN (0x1<<4) // Enable/Disable MAC promiscuous operation. When asserted (Set to '1'); all frames are received without Unicast address filtering.
36521 #define UMAC_REG_COMMAND_CONFIG_PAD_EN (0x1<<5) // Enable/Disable Frame Padding. If enabled (Set to '1'); then padding is removed from the received frame before it is transmitted to the user application. If disabled (set to reset value '0'); then no padding is removed on receive by the MAC. This bit has no effect on Tx padding and hence Transmit always pad runts to guarantee a minimum frame size of 64 octets.
36523 #define UMAC_REG_COMMAND_CONFIG_CRC_FWD (0x1<<6) // Terminate/Forward Received CRC. If enabled (1) the CRC field of received frames are transmitted to the user application. If disabled (Set to reset value '0') the CRC field is stripped from the frame. Note: If padding function (Bit PAD_EN set to '1') is enabled. CRC_FWD is ignored and the CRC field is checked and always terminated and removed.
36525 #define UMAC_REG_COMMAND_CONFIG_PAUSE_FWD (0x1<<7) // Terminate/Forward Pause Frames. If enabled (Set to '1') pause frames are forwarded to the user application. If disabled (Set to reset value '0'); pause frames are terminated and discarded in the MAC.
36527 #define UMAC_REG_COMMAND_CONFIG_PAUSE_IGNORE (0x1<<8) // Ignore Pause Frame Quanta. If enabled (Set to '1') received pause frames are ignored by the MAC. When disabled (Set to reset value '0') the transmit process is stopped for the amount of time specified in the pause quanta received within the pause frame.
36529 #define UMAC_REG_COMMAND_CONFIG_TX_ADDR_INS (0x1<<9) // Set MAC address on transmit. If enabled (Set to '1') the MAC overwrites the source MAC address with the programmed MAC address in registers MAC_0 and MAC_1. If disabled (Set to reset value '0'); the source MAC address received from the transmit application transmitted is not modified by the MAC.
36531 #define UMAC_REG_COMMAND_CONFIG_HD_ENA (0x1<<10) // Half duplex enable. When set to '1'; enables half duplex mode; when set to '0'; the MAC operates in full duplex mode. Ignored at ethernet speeds 1G/2.5G or when the register ENA_EXT_CONFIG is set to '1'.
36533 #define UMAC_REG_COMMAND_CONFIG_RX_LOW_LATENCY_EN (0x1<<11) // This works only when runt filter is disabled. It reduces the receive latency by 48 MAC clock time.
36535 #define UMAC_REG_COMMAND_CONFIG_OVERFLOW_EN (0x1<<12) // If set; enables Rx FIFO overflow logic. In this case; the RXFIFO_STAT[1] register bit is not operational (always set to 0). If cleared; disables RX FIFO overflow logic. In this case; the RXFIFO_STAT[1] register bit is operational (Sticky set when overrun occurs; clearable only by SW_Reset).
36537 #define UMAC_REG_COMMAND_CONFIG_SW_RESET (0x1<<13) // Software Reset Command. When asserted; the TX and RX are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
36539 #define UMAC_REG_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN (0x1<<14) // Corrupt Tx FCS; on underrun; when set to '1'; No FCS corruption when set to '0' (Reset value).
36541 #define UMAC_REG_COMMAND_CONFIG_LOOP_ENA (0x1<<15) // Enable GMII/MII loopback when set to '1'; normal operation when set to '0' (Reset value).
36543 #define UMAC_REG_COMMAND_CONFIG_MAC_LOOP_CON (0x1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
36545 #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_TX (0x1<<17) // If set; enables the SW programmed Tx pause capability config bits to overwrite the auto negotiated Tx pause capabilities when ena_ext_config (autoconfig) is set. If cleared; and when ena_ext_config (autoconfig) is set; then SW programmed Tx pause capability config bits has no effect over auto negotiated capabilities.
36547 #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_RX (0x1<<18) // If set; enables the SW programmed Rx pause capability config bits to overwrite the auto negotiated Rx pause capabilities when ena_ext_config (autoconfig) is set. If cleared; and when ena_ext_config (autoconfig) is set; then SW programmed Rx pause capability config bits has no effect over auto negotiated capabilities.
36549 #define UMAC_REG_COMMAND_CONFIG_EN_INTERNAL_TX_CRS (0x1<<21) // If enabled; then CRS input to Unimac is ORed with tds[8] (tx data valid output). This is helpful when TX CRS is disabled inside PHY.
36551 #define UMAC_REG_COMMAND_CONFIG_ENA_EXT_CONFIG (0x1<<22) // Enable Configuration with External Pins. When set to '0' (Reset value) the Core speed and Mode is programmed with the register bits ETH_SPEED(1:0) and HD_ENA. When set to '1'; the Core is configured with the pins set_speed(1:0) and set_duplex.
36553 #define UMAC_REG_COMMAND_CONFIG_CNTL_FRM_ENA (0x1<<23) // MAC Control Frame Enable. When set to '1'; MAC Control frames with any Opcode other than 0x0001 are accepted and forward to the Client interface. When set to '0' (Reset value); MAC Control frames with any Opcode other than 0x0001 are silently discarded.
36555 #define UMAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK (0x1<<24) // Payload Length Check Disable. When set to '0'; the Core checks the frame's payload length with the Frame Length/Type field; when set to '1'(Reset value); the payload length check is disabled.
36557 #define UMAC_REG_COMMAND_CONFIG_LINE_LOOPBACK (0x1<<25) // Enable Line Loopback i.e. MAC FIFO side loopback; when set to '1'; normal operation when set to '0' (Reset value).
36559 #define UMAC_REG_COMMAND_CONFIG_RX_ERR_DISC (0x1<<26) // Receive Errored Frame Discard Enable. When set to '1'; any frame received with an error is discarded in the Core and not forwarded to the Client interface. When set to '0'; errored Frames are forwarded to the Client interface with ff_rx_err asserted. It is recommended to set RX_ERR_DISC to '1' only when Store and Forward operation is enabled on the Core Receive FIFO Receive FIFO Section full threshold set to 0).
36561 #define UMAC_REG_COMMAND_CONFIG_PRBL_ENA (0x1<<27) // Reserved.
36563 #define UMAC_REG_COMMAND_CONFIG_IGNORE_TX_PAUSE (0x1<<28) // Ignores the back pressure signaling from the system and hence no Tx pause generation; when set.
36565 #define UMAC_REG_COMMAND_CONFIG_OOB_EFC_EN (0x1<<29) // If set then out-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is enabled then data frame trasmission is stopped; whereas Pause & PFC frames are transmitted normally. This operation is similar to halting the transmit datapath due to the reception of a Pause Frame with non-zero timer value; and is used in applications where the flow control information is exchanged out of band. Enabling or disabling this bit has no effect on regular Rx_pause pkt based egress flow control.
36567 #define UMAC_REG_COMMAND_CONFIG_RUNT_FILTER_DIS (0x1<<30) // When set; disable runt filtering.
36575 #define UMAC_REG_MAC_MODE_PAUSE_RX_EN (0x1<<3) // Rx Flow. Setting this bit will cause the receive MAC control to detect and act on PAUSE flow control frames. Clearing this bit causes the receive MAC control to ignore PAUSE flow control frames.
36577 #define UMAC_REG_MAC_MODE_PAUSE_TX_EN (0x1<<4) // Tx Flow. Setting this bit will allow the transmit MAC control to send PAUSE flow control frames when requested by the system. Clearing this bit prevents the transmit MAC control from sending flow control frames.
36581 #define UMAC_REG_MAC_MODE_MAC_DUPLEX (0x1<<2) // MAC Duplex. 0: Full Duplex Mode enabled 1: Half Duplex Mode enabled.
36583 #define UMAC_REG_MAC_MODE_MAC_RX_PAUSE (0x1<<3) // MAC Pause Enabled in Receive. 0: MAC Pause Disabled in Receive 1: MAC Pause Enabled in Receive.
36585 #define UMAC_REG_MAC_MODE_MAC_TX_PAUSE (0x1<<4) // MAC Pause Enabled in Transmit. 0: MAC Pause Disabled in Transmit 1: MAC Pause Enabled in Transmit.
36587 #define UMAC_REG_MAC_MODE_LINK_STATUS (0x1<<5) // Link Status Indication. Set to '0'; when link_status input is low. Set to '1'; when link_status input is High.
36592 #define UMAC_REG_TAG_0_CONFIG_OUTER_TPID_ENABLE (0x1<<16) // If cleared then disable outer TPID detection.
36597 #define UMAC_REG_TAG_1_CONFIG_INNER_TPID_ENABLE (0x1<<16) // If cleared then disable inner TPID detection.
36602 #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL (0x1<<16) // If clear; then subtract the scale_value from the received pause quanta. If set; then add the scale_value from the received pause quanta.
36604 #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_FIX (0x1<<17) // If set; then receive pause quanta is ignored and a fixed quanta value programmed in SCALE_VALUE is loaded into the pause timer. If set; then SCALE_CONTROL is ignored. If cleared; then SCALE_CONTROL takes into effect.
36610 #define UMAC_REG_UMAC_EEE_CTRL_EEE_EN (0x1<<3) // If set; the TX LPI policy control engine is enabled and the MAC inserts LPI_idle codes if the link is idle. The rx_lpi_detect assertion is independent of this configuration. Reset default depends on EEE_en_strap input; which if tied to 1; defaults to enabled; otherwise if tied to 0; defaults to disabled.
36612 #define UMAC_REG_UMAC_EEE_CTRL_RX_FIFO_CHECK (0x1<<4) // If enabled; lpi_rx_detect is set whenever the LPI_IDLES are being received on the RX line and Unimac Rx FIFO is empty. By default; lpi_rx_detect is set only when whenever the LPI_IDLES are being received on the RX line.
36614 #define UMAC_REG_UMAC_EEE_CTRL_EEE_TXCLK_DIS (0x1<<5) // If enabled; UNIMAC will shut down TXCLK to PHY; when in LPI state.
36616 #define UMAC_REG_UMAC_EEE_CTRL_DIS_EEE_10M (0x1<<6) // When this bit is set and link is established at 10Mbps; LPI is not supported (saving is achieved by reduced PHY's output swing). UNIMAC ignores EEE feature on both Tx & Rx in 10Mbps. When cleared; Unimac doesn't differentiate between speeds for EEE feature.
36618 #define UMAC_REG_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE (0x1<<7) // When set to 1; enables LP_IDLE Prediction. When set to 0; disables LP_IDLE Prediction.
36623 #define UMAC_REG_UMAC_RX_PKT_DROP_STATUS 0x051078UL //Access:RW DataWidth:0x1 // Debug status; set if MAC receives an IPG less than programmed RX IPG or less than four bytes. Sticky bit. Clears when SW writes 0 into the field or by sw_reset.
36650 #define UMAC_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36652 #define UMAC_REG_INT_STS_TX_OVERFLOW (0x1<<1) // TX fifo overflow
36655 #define UMAC_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: UMAC_REG_INT_STS.ADDRESS_ERROR .
36657 #define UMAC_REG_INT_MASK_TX_OVERFLOW (0x1<<1) // This bit masks, when set, the Interrupt bit: UMAC_REG_INT_STS.TX_OVERFLOW .
36660 #define UMAC_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36662 #define UMAC_REG_INT_STS_WR_TX_OVERFLOW (0x1<<1) // TX fifo overflow
36665 #define UMAC_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
36667 #define UMAC_REG_INT_STS_CLR_TX_OVERFLOW (0x1<<1) // TX fifo overflow
36680 #define UMAC_REG_MACSEC_CNTRL_TX_LAUNCH_EN (0x1<<0) // Set the bit 0 (Tx_Launch_en) logic 0; if the tx_launch function is to be disabled. If set; then the launch_enable signal assertion/deassertion causes the packet transmit enabled/disabled. The launch_enable is per packet basis.
36682 #define UMAC_REG_MACSEC_CNTRL_TX_CRC_CORUPT_EN (0x1<<1) // Setting this field enables the CRC corruption on the transmitted packets. The options of how to corrupt; depends on the field 2 of this register (TX_CRC_PROGRAM). The CRC corruption happens only on the frames for which TXCRCER is asserted by the system.
36684 #define UMAC_REG_MACSEC_CNTRL_TX_CRC_PROGRAM (0x1<<2) // If CRC corruption feature in enabled (TX_CRC_CORUPT_EN set); then in case where this bit when set; replaces the transmitted FCS with the programmed FCS. When cleared; corrupts the CRC of the transmitted packet internally.
36686 #define UMAC_REG_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG (0x1<<3) // When this bit is 1; IPG between pause and data frame is as per the original design; i.e.; 13B or 12B; fixed. It should be noted; that as number of preamble bytes reduces from 7; the IPG also increases. When this bit is 0; IPG between pause and data frame is variable and equals programmed IPG or programmed IPG + 1.
36690 #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_FULL (0x1<<0) // Read-only field assertion shows that the transmit timestamp FIFO is full.
36692 #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY (0x1<<1) // Read-only field assertion shows that the transmit timestamp FIFO is empty.
36701 #define UMAC_REG_PAUSE_CONTROL_TIME_NRESUME (0x1<<17) // If set and a Pause frame is being forced, send a Pause frame with the Pause Time Field specified in rf_omac_pause_time. If this bit is cleared send a Pause frame with the zero pause time.
36703 #define UMAC_REG_PAUSE_CONTROL_PAUSE_MODE (0x1<<18) // Pause mode 0 = Standard Pause, 1 = PFC Pause.
36705 #define UMAC_REG_PAUSE_CONTROL_FORCE_STD_PAUSE (0x1<<23) // Force sending a Standard Pause Frame. The value of the Pause time is defined by rf_omac_time_nresume. If rf_omac_time_nresume is set, the chip should continue to send Standard Pause frames at periodic intervals until rf_omac_time_nresume is cleared. If rf_omac_time_nresume is cleared, after sending a single Standard Pause frame the internal timer should be cleared.
36711 #define UMAC_REG_PAUSE_CONTROL_ENABLE (0x1<<17) // Enable Extra Pause Frames.
36714 #define UMAC_REG_FLUSH_CONTROL 0x051334UL //Access:RW DataWidth:0x1 // Flush enable bit to drop out all packets in Tx FIFO without egressing any packets when set.
36717 #define UMAC_REG_RXFIFO_STAT_RXFIFO_UNDERRUN (0x1<<0) // RXFIFO Underrun occurred. Cleared by only reset.
36719 #define UMAC_REG_RXFIFO_STAT_RXFIFO_OVERRUN (0x1<<1) // RXFIFO Overrun occurred. Cleared by only reset.
36723 #define UMAC_REG_TXFIFO_STAT_TXFIFO_UNDERRUN (0x1<<0) // TXFIFO Underrun occurred. Cleared by only reset.
36725 #define UMAC_REG_TXFIFO_STAT_TXFIFO_OVERRUN (0x1<<1) // TXFIFO Overrun occurred. Cleared by only reset.
36728 #define UMAC_REG_MAC_PFC_CTRL_PFC_TX_ENBL (0x1<<0) // Enables the PPP-Tx functionality.
36730 #define UMAC_REG_MAC_PFC_CTRL_PFC_RX_ENBL (0x1<<1) // Enables the PPP-Rx functionality.
36732 #define UMAC_REG_MAC_PFC_CTRL_FORCE_PFC_XON (0x1<<2) // Instructs MAC to send Xon message to all classes of service.
36734 #define UMAC_REG_MAC_PFC_CTRL_RX_PASS_PFC_FRM (0x1<<4) // When set; MAC pass PFC frame to the system. Otherwise; PFC frame is discarded.
36736 #define UMAC_REG_MAC_PFC_CTRL_PFC_STATS_EN (0x1<<5) // When clear; none of PFC related counters should increment. Otherwise; PFC counters is in full function. Note: it is programming requirement to set this bit when PFC function is enable.
36739 #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN (0x1<<0) // Enables the PPP refresh functionality on the Tx side. When enabled; the MAC sends Xoff message on refresh counter becoming 0.
36743 #define MCP2_REG_PRTY_MASK 0x052044UL //Access:RW DataWidth:0x1 // Multi Field Register.
36744 #define MCP2_REG_PRTY_MASK_ROM_PARITY (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS.ROM_PARITY .
36748 #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
36750 #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
36752 #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
36754 #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_2_RF_INT .
36756 #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_3_RF_INT .
36758 #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
36760 #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
36762 #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
36764 #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
36766 #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
36768 #define MCP2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
36770 #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
36777 #define MCP2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
36779 #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem
36781 #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem
36783 #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN (0x1<<3) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem
36785 #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_3_EN (0x1<<4) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem
36787 #define MCP2_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem
36790 #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
36792 #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem
36794 #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem
36796 #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY (0x1<<3) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem
36798 #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_3_PRTY (0x1<<4) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem
36800 #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem
36803 #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer
36805 #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem
36807 #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem
36809 #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem
36811 #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_3_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem
36813 #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem
36826 #define OPTE_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
36828 #define OPTE_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
36830 #define OPTE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
36832 #define OPTE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
36834 #define OPTE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
36836 #define OPTE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
36838 #define OPTE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
36840 #define OPTE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
36842 #define OPTE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
36844 #define OPTE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
36846 #define OPTE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
36851 #define OPTE_REG_PRTY_MASK 0x05320cUL //Access:RW DataWidth:0x1 // Multi Field Register.
36852 #define OPTE_REG_PRTY_MASK_DATAPATH_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS.DATAPATH_PARITY_ERROR .
36855 #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
36857 #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
36859 #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
36861 #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
36863 #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
36865 #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
36867 #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
36869 #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
36871 #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
36873 #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
36875 #define PCIE_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
36877 #define PCIE_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
36879 #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
36881 #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0 (0x1<<8) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
36883 #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1 (0x1<<9) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
36885 #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2 (0x1<<10) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_2 .
36887 #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_3 (0x1<<11) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_3 .
36889 #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_1 (0x1<<12) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY_1 .
36891 #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_2 (0x1<<13) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY_2 .
36893 #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1 (0x1<<14) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
36895 #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2 (0x1<<15) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
36898 #define PCIE_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_mem_e4
36900 #define PCIE_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
36902 #define PCIE_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
36904 #define PCIE_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_mem_e4
36906 #define PCIE_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem_e4
36908 #define PCIE_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem_e4
36910 #define PCIE_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
36913 #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_mem_e4
36915 #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
36917 #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
36919 #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_mem_e4
36921 #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem_e4
36923 #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem_e4
36925 #define PCIE_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
36928 #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_debug_mem.i_ecc in module pcie_debug_mem_e4
36930 #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.i_ram_2p_sotbuf.i_ecc in module ram_2p_sotbuf
36932 #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_d2t_fifo.i_ecc in module d2t_fifo_e4
36934 #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_header_mem.i_ecc in module header_log_mem_e4
36936 #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_tlda_mem.i_ecc in module pcie_tlda_mem_e4
36938 #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_tlda2_mem.i_ecc in module pcie_tlda_mem_e4
36940 #define PCIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance pcie_top_wrapper.u_replay_data_mem.i_ecc in module pcie_replay_e4
36945 #define PCIE_REG_PCIE_CONTROL_BITS_USER_L1_ENTER (0x1<<2) // Set to enter L1 state.
36947 #define PCIE_REG_PCIE_CONTROL_BITS_USER_L23_REQ (0x1<<3) // Set to request entry to L23 state.
36949 #define PCIE_REG_PCIE_CONTROL_BITS_USER_SEND_LTR1 (0x1<<4) // Set to send LTR1.
36951 #define PCIE_REG_PCIE_CONTROL_BITS_USER_RC_MODE (0x1<<0) // Set to enter Root Controller Mode.
36953 #define PCIE_REG_PCIE_CONTROL_BITS_USER_ALLOW_GEN3 (0x1<<1) // Set to allow Gen3 mode.
36955 #define PCIE_REG_PCIE_CONTROL_BITS_USER_STOP_L1SUB (0x1<<5) // Stop L1Sub control bit.
36958 #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L0 (0x1<<1) // Link in L0 Status bit.
36960 #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L23 (0x1<<4) // Link in L23 Status bit.
36962 #define PCIE_REG_PCIE_STATUS_BITS_PTM_ATTN (0x1<<0) // Timesynch Data is ready in PCIE FIFO.
36964 #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L11 (0x1<<2) // Link in L11 Status bit.
36966 #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L12 (0x1<<3) // Link in L12 Status bit.
36970 #define PCIE_REG_PCIE_STATUS_BITS_PHY_PLL_LOCK (0x1<<8) // PLL Lock status bit.
36973 #define PCIE_REG_PCIE_DEBUG_BITS_SPLITTBL_TL_PERR (0x1<<0) // Force Parity Error on Split Table memory.
36975 #define PCIE_REG_PCIE_DEBUG_BITS_TIMERTBL_TL_PERR (0x1<<1) // Force Parity Error on Timer Table memory.
36978 #define PCIE_REG_SOFT_RESET_CONTROL_APP_INIT_RST (0x1<<0) //
36980 #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_WAKE_REF_RST_N (0x1<<1) //
36982 #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_SQUELCH_RST_N (0x1<<2) //
36984 #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_STICKY_RST_N (0x1<<3) //
36986 #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_NON_STICKY_RST_N (0x1<<4) //
36988 #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_CORE_RST_N (0x1<<5) //
36990 #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_PIPE_RST_N (0x1<<6) //
36993 #define PCIE_REG_OBFF_CONTROL_1_RECEIVEDREQUEST (0x1<<0) //
36995 #define PCIE_REG_OBFF_CONTROL_1_OBFFSIGNALENABLE (0x1<<1) // This bit is set by firmware when host system sets OBFF Enable to 2'b11. Firmware must clear this bit when the host changes OBFF Enable from 2'b11 to any other value
36997 #define PCIE_REG_OBFF_CONTROL_1_OBFFWAKEPOLARITY (0x1<<2) // Set to 1 to indicate that the pcore WakeIn input is active high. This bit should only be set in the event a workaround is required.
36999 #define PCIE_REG_OBFF_CONTROL_1_DISABLECPUACTIVEFORCING (0x1<<3) // Set to 1 to prevent incoming Request TLPs from forcing the OBFF state to CPU Active.
37009 #define PCIE_REG_OBFF_STATUS_1_RXOBFFUPDATE (0x1<<0) //
37013 #define PCIE_REG_OBFF_STATUS_1_RXOBFFEXCEPTION (0x1<<5) //
37017 #define PCIE_REG_OBFF_STATUS_1_MINIMUMWAKEFALLINGEDGEVALID (0x1<<11) //
37019 #define PCIE_REG_OBFF_STATUS_1_MAXIMUMPULSEWIDTHEXPIRE (0x1<<12) //
37021 #define PCIE_REG_OBFF_STATUS_1_MINIMUMPULSEWIDTHREADY (0x1<<13) //
37023 #define PCIE_REG_OBFF_STATUS_1_RESTARTWAKEPULSEWIDTHTIMER (0x1<<14) //
37025 #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGE (0x1<<15) //
37027 #define PCIE_REG_OBFF_STATUS_1_WAKERISINGEDGE (0x1<<16) //
37029 #define PCIE_REG_OBFF_STATUS_1_WAKEINSYNC (0x1<<17) //
37042 #define PCIE_REG_LTR_STATUS 0x054234UL //Access:R DataWidth:0x1 //
37044 #define PCIE_REG_SII_LANE_FLIP_CONTROL_RX_LANE_FLIP_EN (0x1<<0) // Performs manual lane reversal for receive lanes.
37046 #define PCIE_REG_SII_LANE_FLIP_CONTROL_TX_LANE_FLIP_EN (0x1<<1) // Performs manual lane reversal for transmit lanes.
37048 #define PCIE_REG_APP_LTSSM_ENABLE 0x05423cUL //Access:RW DataWidth:0x1 // Driven low by your application after cold, warm or hot reset to hold the LTSSM in the Detect state until your application is ready for the link training to begin. When your application has finished reprogramming the core configuration registers using the DBI, it asserts app_ltssm_enable to allow the LTSSM to continue link establishment. Can also be used to delay hot resetting of the core until you have read out any register status.
37050 #define PCIE_REG_HW_INIT_CONFIG_APP_LTSSM_ENABLE_OVR (0x1<<0) // When set to 0, HWInit controls app_ltssm_enable
37052 #define PCIE_REG_HW_INIT_CONFIG_HOT_RESET_PRE_DELAY_ENABLE (0x1<<1) // When set to 1, HW delay asserting internal reset to allow FW access to internal registers
37054 #define PCIE_REG_SII_CORE_CONTROL 0x054244UL //Access:RW DataWidth:0x1 //
37056 #define PCIE_REG_CLK_RST_APM_CONTROL_APP_CLK_REQ_N (0x1<<0) // Indicates that the application logic is ready to have reference clock removed.
37058 #define PCIE_REG_CLK_RST_APM_CONTROL_PHY_CLK_REQ_N (0x1<<1) // Acknowledge from the PHY that it is ready to have reference clock removed.
37060 #define PCIE_REG_CLK_RST_APM_CONTROL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running external clock.
37063 #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_CLK_REQ_N (0x1<<0) // Indicates to the PHY that MAC and application is ready to remove the clock. PHY can decide whether or not it will allow reference clock removal if it supports this feature
37065 #define PCIE_REG_CLK_RST_APM_STATUS_CLK_REQ_N (0x1<<1) // Clock Turnoff request. Allows your application clock generation module to turn off core_clk based the current power management state
37067 #define PCIE_REG_CLK_RST_APM_STATUS_LOCAL_REF_CLK_REQ_N (0x1<<2) //
37072 #define PCIE_REG_PTM_CONTROL_PTM_AUTO_UPDATE_SIGNAL (0x1<<0) //
37074 #define PCIE_REG_PTM_CONTROL_PTM_MANUAL_UPDATE_PULSE (0x1<<1) // Indicates that the core should update the PTM Requester Context and Clock now. FW must clear this bit after setting this bit to 1.
37077 #define PCIE_REG_PTM_STATUS_PTM_CONTEXT_VALID (0x1<<0) //
37079 #define PCIE_REG_PTM_STATUS_PTM_CLOCK_UPDATED (0x1<<1) //
37088 #define PCIE_REG_RESET_STATUS_1_WAKE_REF_RST_N (0x1<<0) //
37090 #define PCIE_REG_RESET_STATUS_1_SQUELCH_RST_N (0x1<<1) //
37092 #define PCIE_REG_RESET_STATUS_1_STICKY_RST_N (0x1<<2) //
37094 #define PCIE_REG_RESET_STATUS_1_NON_STICKY_RST_N (0x1<<3) //
37096 #define PCIE_REG_RESET_STATUS_1_PIPE_RST_N (0x1<<4) //
37098 #define PCIE_REG_RESET_STATUS_1_SMLH_REQ_RST_NOT (0x1<<5) // Early version of the link_req_rst_not signal. For more details, see the 'Warm and Hot Resets' section in the Architecture chapter of the Databook.
37100 #define PCIE_REG_RESET_STATUS_1_LINK_REQ_RST_NOT (0x1<<6) //
37102 #define PCIE_REG_RESET_STATUS_1_TRAINING_RST_N (0x1<<7) //
37105 #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LINK_UP (0x1<<0) //
37107 #define PCIE_REG_LINK_DEBUG_STATUS_RDLH_LINK_UP (0x1<<1) //
37111 #define PCIE_REG_LINK_DEBUG_STATUS_RADM_Q_NOT_EMPTY (0x1<<8) // Level indicating that the receive queues contain TLP header/data.There is a 1 bit indication for each virtual channel.
37115 #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_RCVRY_EQ (0x1<<16) // This status signal is asserted during all Recovery Equalization states
37117 #define PCIE_REG_LINK_DEBUG_STATUS_CFG_HW_AUTO_SP_DIS (0x1<<17) // Autonomous speed disable. Used in downstream ports only.
37122 #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_MSG_UNLOCK (0x1<<16) // One-cycle pulse that indicates that the core received an Unlock message
37124 #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_PM_TURNOFF (0x1<<17) // One-clock-cycle pulse that indicates that the core received a PME Turnoff message
37137 #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_XTLH_BLOCK_TLP (0x1<<0) // WARNING: this bit should not be used by firmware due to a bug filed in CQ85027. Indicates that your application must stop generating new outgoing request TLPs due to the current power management state.
37141 #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L0S (0x1<<17) // Power management is in L0s state
37143 #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L2 (0x1<<18) // Power management is in L2 state.
37145 #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_L2_EXIT (0x1<<19) // Power management is exiting L2 state.
37150 #define PCIE_REG_SII_CONFIG_INFO_CFG_LTR_M_EN (0x1<<16) // The LTR Mechanism Enable field of the Device Control 2 register of function 0
37212 #define PCIE_REG_DBG_FW_TRIGGER_ENABLE 0x05436cUL //Access:RW DataWidth:0x1 //
37214 #define PCIE_REG_DBG_AUX_CORE_CLK_SWITCH_TRIGGER_ENABLE 0x054374UL //Access:RW DataWidth:0x1 //
37215 #define PCIE_REG_DBG_LTSSM_MATCH_TRIGGER_ENABLE 0x054378UL //Access:RW DataWidth:0x1 //
37217 #define PCIE_REG_DBG_RX_ALIGN_LOSS_TRIGGER_ENABLE 0x054380UL //Access:RW DataWidth:0x1 //
37218 #define PCIE_REG_DBG_EI_ENTRY_TRIGGER_ENABLE 0x054384UL //Access:RW DataWidth:0x1 //
37219 #define PCIE_REG_DBG_EI_EXIT_TRIGGER_ENABLE 0x054388UL //Access:RW DataWidth:0x1 //
37220 #define PCIE_REG_DBG_RATE_CHANGE_TRIGGER_ENABLE 0x05438cUL //Access:RW DataWidth:0x1 //
37221 #define PCIE_REG_DBG_LINK_WIDTH_CHANGE_TRIGGER_ENABLE 0x054390UL //Access:RW DataWidth:0x1 //
37222 #define PCIE_REG_DBG_CORRECTABLE_ERROR_TRIGGER_ENABLE 0x054394UL //Access:RW DataWidth:0x1 //
37229 #define PCIE_REG_MSIX_SYNCH_START 0x0543b0UL //Access:RW DataWidth:0x1 // Need to write on init to start MSIX synchronization.
37230 #define PCIE_REG_MSIX_SYNCH_STICKY 0x0543b4UL //Access:RC DataWidth:0x1 // Is set to 1 if at least 1 MSIX synchronization was performed completely.
37232 #define PCIE_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37234 #define PCIE_REG_INT_STS_LINK_DOWN_DETECT (0x1<<1) // Data Link Down detected.
37236 #define PCIE_REG_INT_STS_LINK_UP_DETECT (0x1<<2) // Data Link Up detected.
37238 #define PCIE_REG_INT_STS_CFG_LINK_EQ_REQ_INT (0x1<<3) // Link Equalization requested.
37240 #define PCIE_REG_INT_STS_PCIE_BANDWIDTH_CHANGE_DETECT (0x1<<4) // PCIe Bandwidth changed.
37242 #define PCIE_REG_INT_STS_EARLY_HOT_RESET_DETECT (0x1<<5) // Early Hot Reset detected.
37244 #define PCIE_REG_INT_STS_HOT_RESET_DETECT (0x1<<6) // Hot Reset detected.
37246 #define PCIE_REG_INT_STS_L1_ENTRY_DETECT (0x1<<7) // L1 Entry detected.
37248 #define PCIE_REG_INT_STS_L1_EXIT_DETECT (0x1<<8) // L1 Exit detected.
37250 #define PCIE_REG_INT_STS_LTSSM_STATE_MATCH_DETECT (0x1<<9) // LTSSM State matched.
37252 #define PCIE_REG_INT_STS_FC_TIMEOUT_DETECT (0x1<<10) // Do not use -- keep mask bit set to 1.
37254 #define PCIE_REG_INT_STS_PME_TURNOFF_MESSAGE_DETECT (0x1<<11) // PME Turnoff Message received.
37256 #define PCIE_REG_INT_STS_CFG_SEND_COR_ERR (0x1<<12) // Correctable Error Message sent.
37258 #define PCIE_REG_INT_STS_CFG_SEND_NF_ERR (0x1<<13) // Non-Fatal Error Message sent.
37260 #define PCIE_REG_INT_STS_CFG_SEND_F_ERR (0x1<<14) // Fatal Error Message sent.
37262 #define PCIE_REG_INT_STS_QOVERFLOW_DETECT (0x1<<15) // Queue Overflow detected.
37264 #define PCIE_REG_INT_STS_VDM_DETECT (0x1<<16) // Vendor-Defined Message received.
37267 #define PCIE_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.ADDRESS_ERROR .
37269 #define PCIE_REG_INT_MASK_LINK_DOWN_DETECT (0x1<<1) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LINK_DOWN_DETECT .
37271 #define PCIE_REG_INT_MASK_LINK_UP_DETECT (0x1<<2) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LINK_UP_DETECT .
37273 #define PCIE_REG_INT_MASK_CFG_LINK_EQ_REQ_INT (0x1<<3) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_LINK_EQ_REQ_INT .
37275 #define PCIE_REG_INT_MASK_PCIE_BANDWIDTH_CHANGE_DETECT (0x1<<4) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.PCIE_BANDWIDTH_CHANGE_DETECT .
37277 #define PCIE_REG_INT_MASK_EARLY_HOT_RESET_DETECT (0x1<<5) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.EARLY_HOT_RESET_DETECT .
37279 #define PCIE_REG_INT_MASK_HOT_RESET_DETECT (0x1<<6) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.HOT_RESET_DETECT .
37281 #define PCIE_REG_INT_MASK_L1_ENTRY_DETECT (0x1<<7) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.L1_ENTRY_DETECT .
37283 #define PCIE_REG_INT_MASK_L1_EXIT_DETECT (0x1<<8) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.L1_EXIT_DETECT .
37285 #define PCIE_REG_INT_MASK_LTSSM_STATE_MATCH_DETECT (0x1<<9) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LTSSM_STATE_MATCH_DETECT .
37287 #define PCIE_REG_INT_MASK_FC_TIMEOUT_DETECT (0x1<<10) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.FC_TIMEOUT_DETECT .
37289 #define PCIE_REG_INT_MASK_PME_TURNOFF_MESSAGE_DETECT (0x1<<11) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.PME_TURNOFF_MESSAGE_DETECT .
37291 #define PCIE_REG_INT_MASK_CFG_SEND_COR_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_COR_ERR .
37293 #define PCIE_REG_INT_MASK_CFG_SEND_NF_ERR (0x1<<13) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_NF_ERR .
37295 #define PCIE_REG_INT_MASK_CFG_SEND_F_ERR (0x1<<14) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_F_ERR .
37297 #define PCIE_REG_INT_MASK_QOVERFLOW_DETECT (0x1<<15) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.QOVERFLOW_DETECT .
37299 #define PCIE_REG_INT_MASK_VDM_DETECT (0x1<<16) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.VDM_DETECT .
37302 #define PCIE_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37304 #define PCIE_REG_INT_STS_WR_LINK_DOWN_DETECT (0x1<<1) // Data Link Down detected.
37306 #define PCIE_REG_INT_STS_WR_LINK_UP_DETECT (0x1<<2) // Data Link Up detected.
37308 #define PCIE_REG_INT_STS_WR_CFG_LINK_EQ_REQ_INT (0x1<<3) // Link Equalization requested.
37310 #define PCIE_REG_INT_STS_WR_PCIE_BANDWIDTH_CHANGE_DETECT (0x1<<4) // PCIe Bandwidth changed.
37312 #define PCIE_REG_INT_STS_WR_EARLY_HOT_RESET_DETECT (0x1<<5) // Early Hot Reset detected.
37314 #define PCIE_REG_INT_STS_WR_HOT_RESET_DETECT (0x1<<6) // Hot Reset detected.
37316 #define PCIE_REG_INT_STS_WR_L1_ENTRY_DETECT (0x1<<7) // L1 Entry detected.
37318 #define PCIE_REG_INT_STS_WR_L1_EXIT_DETECT (0x1<<8) // L1 Exit detected.
37320 #define PCIE_REG_INT_STS_WR_LTSSM_STATE_MATCH_DETECT (0x1<<9) // LTSSM State matched.
37322 #define PCIE_REG_INT_STS_WR_FC_TIMEOUT_DETECT (0x1<<10) // Do not use -- keep mask bit set to 1.
37324 #define PCIE_REG_INT_STS_WR_PME_TURNOFF_MESSAGE_DETECT (0x1<<11) // PME Turnoff Message received.
37326 #define PCIE_REG_INT_STS_WR_CFG_SEND_COR_ERR (0x1<<12) // Correctable Error Message sent.
37328 #define PCIE_REG_INT_STS_WR_CFG_SEND_NF_ERR (0x1<<13) // Non-Fatal Error Message sent.
37330 #define PCIE_REG_INT_STS_WR_CFG_SEND_F_ERR (0x1<<14) // Fatal Error Message sent.
37332 #define PCIE_REG_INT_STS_WR_QOVERFLOW_DETECT (0x1<<15) // Queue Overflow detected.
37334 #define PCIE_REG_INT_STS_WR_VDM_DETECT (0x1<<16) // Vendor-Defined Message received.
37337 #define PCIE_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37339 #define PCIE_REG_INT_STS_CLR_LINK_DOWN_DETECT (0x1<<1) // Data Link Down detected.
37341 #define PCIE_REG_INT_STS_CLR_LINK_UP_DETECT (0x1<<2) // Data Link Up detected.
37343 #define PCIE_REG_INT_STS_CLR_CFG_LINK_EQ_REQ_INT (0x1<<3) // Link Equalization requested.
37345 #define PCIE_REG_INT_STS_CLR_PCIE_BANDWIDTH_CHANGE_DETECT (0x1<<4) // PCIe Bandwidth changed.
37347 #define PCIE_REG_INT_STS_CLR_EARLY_HOT_RESET_DETECT (0x1<<5) // Early Hot Reset detected.
37349 #define PCIE_REG_INT_STS_CLR_HOT_RESET_DETECT (0x1<<6) // Hot Reset detected.
37351 #define PCIE_REG_INT_STS_CLR_L1_ENTRY_DETECT (0x1<<7) // L1 Entry detected.
37353 #define PCIE_REG_INT_STS_CLR_L1_EXIT_DETECT (0x1<<8) // L1 Exit detected.
37355 #define PCIE_REG_INT_STS_CLR_LTSSM_STATE_MATCH_DETECT (0x1<<9) // LTSSM State matched.
37357 #define PCIE_REG_INT_STS_CLR_FC_TIMEOUT_DETECT (0x1<<10) // Do not use -- keep mask bit set to 1.
37359 #define PCIE_REG_INT_STS_CLR_PME_TURNOFF_MESSAGE_DETECT (0x1<<11) // PME Turnoff Message received.
37361 #define PCIE_REG_INT_STS_CLR_CFG_SEND_COR_ERR (0x1<<12) // Correctable Error Message sent.
37363 #define PCIE_REG_INT_STS_CLR_CFG_SEND_NF_ERR (0x1<<13) // Non-Fatal Error Message sent.
37365 #define PCIE_REG_INT_STS_CLR_CFG_SEND_F_ERR (0x1<<14) // Fatal Error Message sent.
37367 #define PCIE_REG_INT_STS_CLR_QOVERFLOW_DETECT (0x1<<15) // Queue Overflow detected.
37369 #define PCIE_REG_INT_STS_CLR_VDM_DETECT (0x1<<16) // Vendor-Defined Message received.
37372 #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_0 (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_0 .
37374 #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_1 (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_1 .
37376 #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_2 (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_2 .
37388 #define PCIE_REG_RESET_STATUS_2_PWR_RST_2 (0x1<<0) // Power-on reset occurred.
37390 #define PCIE_REG_RESET_STATUS_2_WAKE_REF_RST_2 (0x1<<1) // Wake Ref reset occurred.
37392 #define PCIE_REG_RESET_STATUS_2_PHY_RST_2 (0x1<<2) // Phy reset occurred.
37394 #define PCIE_REG_RESET_STATUS_2_SQUELCH_RST_2 (0x1<<3) // Squelch reset occurred.
37396 #define PCIE_REG_RESET_STATUS_2_STICKY_RST_2 (0x1<<4) // Sticky register reset occurred.
37398 #define PCIE_REG_RESET_STATUS_2_NON_STICKY_RST_2 (0x1<<5) // Non-sticky register reset occurred.
37400 #define PCIE_REG_RESET_STATUS_2_CORE_RST_2 (0x1<<6) // Core reset occurred.
37402 #define PCIE_REG_RESET_STATUS_2_PIPE_RST_2 (0x1<<7) // PIPE reset occurred.
37404 #define PCIE_REG_RESET_STATUS_2_PERST_2 (0x1<<8) // PERST occurred (raw version).
37406 #define PCIE_REG_RESET_STATUS_2_DATA_LINK_DOWN_2 (0x1<<9) // Data Link Down occurred.
37408 #define PCIE_REG_RESET_STATUS_2_DELAYED_PERST_2 (0x1<<10) // PERST occurred (delayed version).
37410 #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_11_2 (0x1<<11) // Spare status bit
37412 #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_12_2 (0x1<<12) // Spare status bit
37414 #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_13_2 (0x1<<13) // Spare status bit
37416 #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_14_2 (0x1<<14) // Spare status bit
37418 #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_15_2 (0x1<<15) // Spare status bit
37420 #define PCIE_REG_RESET_STATUS_2_SOFT_PWR_RST_2 (0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft power-on reset, because it self-clears within a short time following the event.
37422 #define PCIE_REG_RESET_STATUS_2_SOFT_WAKE_REF_RST_2 (0x1<<17) // Soft Wake Ref reset occurred.
37424 #define PCIE_REG_RESET_STATUS_2_SOFT_PHY_RST_2 (0x1<<18) // Soft phy reset occurred.
37426 #define PCIE_REG_RESET_STATUS_2_SOFT_SQUELCH_RST_2 (0x1<<19) // Soft squelch reset occurred.
37428 #define PCIE_REG_RESET_STATUS_2_SOFT_STICKY_RST_2 (0x1<<20) // Soft sticky register reset occurred.
37430 #define PCIE_REG_RESET_STATUS_2_SOFT_NON_STICKY_RST_2 (0x1<<21) // Soft non-sticky register reset occurred.
37432 #define PCIE_REG_RESET_STATUS_2_SOFT_CORE_RST_2 (0x1<<22) // Soft core reset occurred.
37434 #define PCIE_REG_RESET_STATUS_2_SOFT_PIPE_RST_2 (0x1<<23) // Soft PIPE reset occurred.
37437 #define DORQ_REG_INIT 0x100000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
37438 #define DORQ_REG_IFEN 0x100040UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
37440 #define DORQ_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37442 #define DORQ_REG_INT_STS_DB_DROP (0x1<<1) // Doorbell drop.
37444 #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1<<2) // DORQ FIFO overflow.
37446 #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1<<3) // DORQ FIFO almost full.
37448 #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
37450 #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR (0x1<<5) // CCFC load response returnes an error.
37452 #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
37454 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR (0x1<<7) // CFC load request FIFO overflow
37456 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR (0x1<<8) // CFC load request FIFO under-run
37459 #define DORQ_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.ADDRESS_ERROR .
37461 #define DORQ_REG_INT_MASK_DB_DROP (0x1<<1) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DB_DROP .
37463 #define DORQ_REG_INT_MASK_DORQ_FIFO_OVFL_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DORQ_FIFO_OVFL_ERR .
37465 #define DORQ_REG_INT_MASK_DORQ_FIFO_AFULL (0x1<<3) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DORQ_FIFO_AFULL .
37467 #define DORQ_REG_INT_MASK_CFC_BYP_VALIDATION_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_BYP_VALIDATION_ERR .
37469 #define DORQ_REG_INT_MASK_CFC_LD_RESP_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_RESP_ERR .
37471 #define DORQ_REG_INT_MASK_XCM_DONE_CNT_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.XCM_DONE_CNT_ERR .
37473 #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_REQ_FIFO_OVFL_ERR .
37475 #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_REQ_FIFO_UNDER_ERR .
37478 #define DORQ_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37480 #define DORQ_REG_INT_STS_WR_DB_DROP (0x1<<1) // Doorbell drop.
37482 #define DORQ_REG_INT_STS_WR_DORQ_FIFO_OVFL_ERR (0x1<<2) // DORQ FIFO overflow.
37484 #define DORQ_REG_INT_STS_WR_DORQ_FIFO_AFULL (0x1<<3) // DORQ FIFO almost full.
37486 #define DORQ_REG_INT_STS_WR_CFC_BYP_VALIDATION_ERR (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
37488 #define DORQ_REG_INT_STS_WR_CFC_LD_RESP_ERR (0x1<<5) // CCFC load response returnes an error.
37490 #define DORQ_REG_INT_STS_WR_XCM_DONE_CNT_ERR (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
37492 #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_OVFL_ERR (0x1<<7) // CFC load request FIFO overflow
37494 #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_UNDER_ERR (0x1<<8) // CFC load request FIFO under-run
37497 #define DORQ_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37499 #define DORQ_REG_INT_STS_CLR_DB_DROP (0x1<<1) // Doorbell drop.
37501 #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_OVFL_ERR (0x1<<2) // DORQ FIFO overflow.
37503 #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_AFULL (0x1<<3) // DORQ FIFO almost full.
37505 #define DORQ_REG_INT_STS_CLR_CFC_BYP_VALIDATION_ERR (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
37507 #define DORQ_REG_INT_STS_CLR_CFC_LD_RESP_ERR (0x1<<5) // CCFC load response returnes an error.
37509 #define DORQ_REG_INT_STS_CLR_XCM_DONE_CNT_ERR (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
37511 #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_OVFL_ERR (0x1<<7) // CFC load request FIFO overflow
37513 #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_UNDER_ERR (0x1<<8) // CFC load request FIFO under-run
37515 #define DORQ_REG_PRTY_MASK 0x100194UL //Access:RW DataWidth:0x1 // Multi Field Register.
37516 #define DORQ_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS.DATAPATH_REGISTERS .
37519 #define DORQ_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
37521 #define DORQ_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
37523 #define DORQ_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37525 #define DORQ_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
37527 #define DORQ_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
37529 #define DORQ_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37531 #define DORQ_REG_MEM_ECC_ENABLE_0 0x100210UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
37532 #define DORQ_REG_MEM_ECC_PARITY_ONLY_0 0x100214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
37533 #define DORQ_REG_MEM_ECC_ERROR_CORRECTED_0 0x100218UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance dorq.i_dorq_fifo_mem.i_ecc in module dorq_fifo_mem
37580 #define DORQ_REG_QM_EN_BYP_MASK_0 0x1004b4UL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 0.
37581 #define DORQ_REG_QM_EN_BYP_MASK_1 0x1004b8UL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 1.
37582 #define DORQ_REG_QM_EN_BYP_MASK_2 0x1004bcUL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 2.
37583 #define DORQ_REG_QM_EN_BYP_MASK_3 0x1004c0UL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 3.
37584 #define DORQ_REG_QM_EN_BYP_MASK_4 0x1004c4UL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 4.
37585 #define DORQ_REG_QM_EN_BYP_MASK_5 0x1004c8UL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 5.
37586 #define DORQ_REG_QM_EN_BYP_MASK_6 0x1004ccUL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 6.
37587 #define DORQ_REG_QM_EN_BYP_MASK_7 0x1004d0UL //Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 7.
37588 #define DORQ_REG_DPI_VAL_SUP_0 0x1004d4UL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 0.
37589 #define DORQ_REG_DPI_VAL_SUP_1 0x1004d8UL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 1.
37590 #define DORQ_REG_DPI_VAL_SUP_2 0x1004dcUL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 2.
37591 #define DORQ_REG_DPI_VAL_SUP_3 0x1004e0UL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 3.
37592 #define DORQ_REG_DPI_VAL_SUP_4 0x1004e4UL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 4.
37593 #define DORQ_REG_DPI_VAL_SUP_5 0x1004e8UL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 5.
37594 #define DORQ_REG_DPI_VAL_SUP_6 0x1004ecUL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 6.
37595 #define DORQ_REG_DPI_VAL_SUP_7 0x1004f0UL //Access:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 7.
37598 #define DORQ_REG_WAKE_MISC_EN 0x1004fcUL //Access:RW DataWidth:0x1 // Enables sending early wakeup indication towards MISC. This is per port configuration.
37600 #define DORQ_REG_PF_WAKE_ALL 0x100504UL //Access:RW DataWidth:0x1 // Indicates that a doorbell on this PF should send wakeup indication on all ports. This is a per PF per configuration. Should be set in case of coupled mode teaming. Otherwise should be clear.
37601 #define DORQ_REG_PF_DB_ENABLE 0x100508UL //Access:RW DataWidth:0x1 // Enable doorbells for this PF. In case not set the doorbell is silently dropped. This is a per PF configuration.
37602 #define DORQ_REG_VF_DB_ENABLE 0x10050cUL //Access:RW DataWidth:0x1 // Enable doorbells for this VF. In case not set the doorbell is silently dropped. This is a per VF configuration.
37603 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL //Access:RW DataWidth:0x1 // Enable DPM doorbells for this PF. In case not set the DPM doorbell is aborted. This is a per PF configuration.
37604 #define DORQ_REG_VF_DPM_ENABLE 0x100514UL //Access:RW DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set the DPM doorbell is aborted. This is a per PF configuration.
37670 #define DORQ_REG_XCM_SM_CTX_LD_ST_FLG_DPM 0x100708UL //Access:RW DataWidth:0x1 // The value of the SmCtxLdStFlg in XCM header in case of EDPM and legacy DPM.
37683 #define DORQ_REG_CFC_LOAD_MINI_CACHE_EN 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is enabled.
37687 #define DORQ_REG_MASK_XCM_EN 0x100824UL //Access:RW DataWidth:0x1 // If set, then XCM bypass enable bit will be masked (XCM bypass considered always asserted).
37688 #define DORQ_REG_MASK_QM_EN 0x100828UL //Access:RW DataWidth:0x1 // If set, then QM bypass enable bit will be masked (considered always asserted).
37689 #define DORQ_REG_MASK_PBF_ROCE_EN 0x10082cUL //Access:RW DataWidth:0x1 // If set, then PBF bypass enable bit will be masked (considered always asserted) for RoCE EDPM.
37690 #define DORQ_REG_MASK_PBF_L2_EN 0x100830UL //Access:RW DataWidth:0x1 // If set, then QM bypass enable bit will be masked (considered always asserted) for L2 for L2 EDPM.
37693 #define DORQ_REG_DQ_PXP_FULL_EN 0x10083cUL //Access:RW DataWidth:0x1 // If 1, then full is asserted towards PXP when DORQ FIFO fill level is equal or greater than dq_fifo_full_thr. If 0, then doorbell is discarded when DORQ FIFO is full.
37707 #define DORQ_REG_CRC32_BSWAP 0x1008b0UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
37720 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL //Access:RW DataWidth:0x1 // Indicates whether Ethernet over GRE header is expected in packet payload.
37721 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL //Access:RW DataWidth:0x1 // Indicates whether IP over GRE header is expected in packet payload.
37722 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL //Access:RW DataWidth:0x1 // Indicates whether VXLAN header is expected in packet payload.
37728 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL //Access:RW DataWidth:0x1 // Set to 1 if IP over NGE header is expected in the packet payload.
37729 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL //Access:RW DataWidth:0x1 // Set to 1 if Ethernet over NGE header is expected in the packet payload.
37738 #define DORQ_REG_PF_OVFL_STICKY 0x1009d0UL //Access:RW DataWidth:0x1 // If set, PF doorbell with corresponding PF is silently dropped at the entrance to DORQ FIFO. This is a per PF configuration. Is cleared by write of 0.
37739 #define DORQ_REG_VF_OVFL_STICKY 0x1009d4UL //Access:RW DataWidth:0x1 // If set, VF doorbell with corresponding VF, is silently dropped at the entrance to DORQ FIFO. This is a per VF configuration. Is cleared by write of 0.
37740 #define DORQ_REG_DPM_FORCE_ABORT 0x1009d8UL //Access:W DataWidth:0x1 // Aborts all the current DPM entries which are not FREE.
37742 #define DORQ_REG_AUTO_FREEZE_EN 0x1009e0UL //Access:RW DataWidth:0x1 // If set, DORQ enters freeze mode on the first doorbell drop due to DORQ FIFO overflow. The freeze mode means that DORQ stops sending CFC load requests. The freeze mode will remain until auto_drop_rel (Write Only) register is set.
37743 #define DORQ_REG_AUTO_FREEZE_ST 0x1009e4UL //Access:R DataWidth:0x1 // When set, auto freeze is active and doorbells are not being popped from the FIFO. Cleared when auto_freeze_rel is written.
37744 #define DORQ_REG_AUTO_FREEZE_REL 0x1009e8UL //Access:W DataWidth:0x1 // Release the freeze mode set by auto_freeze_en. Write only.
37745 #define DORQ_REG_AUTO_DROP_EN 0x1009ecUL //Access:RW DataWidth:0x1 // If set, DORQ enters auto drop mode on the first doorbell drop due to DORQ FIFO overflow. In this mode all incoming doorbells will be dropped even if the FIFO is not full anymore. The drop mode will remain until auto_drop_rel (Write Only) register is set.
37746 #define DORQ_REG_AUTO_DROP_ST 0x1009f0UL //Access:R DataWidth:0x1 // When set, auto discard mode is active and all doorbells are dropped at the entrance to DORQ FIFO. De-asserted when auto_discard_rel is written.
37747 #define DORQ_REG_AUTO_DROP_REL 0x1009f4UL //Access:W DataWidth:0x1 // Releases the auto_drop mode. Write only.
37760 #define DORQ_REG_DB_DROP_DETAILS_REL 0x100a28UL //Access:W DataWidth:0x1 // Clears db_drop_details and makes it ready for the next details capture. Write only.
37768 #define DORQ_REG_DPM_ABORT_DETAILS_REL 0x100a48UL //Access:W DataWidth:0x1 // Clears db_abort_details and makes it ready for the next details capture. Write only.
37793 #define DORQ_REG_MEMCTRL_WR_RD_N 0x100ac0UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
37814 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN (0x1<<0) // If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
37816 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN (0x1<<1) // If enabled the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
37818 #define IGU_REG_BLOCK_CONFIGURATION_RL_BYPASS_EN (0x1<<2) // If enabled the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
37821 #define IGU_REG_CAM_BIST_EN 0x180060UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
37826 #define IGU_REG_CAM_BIST_DBG_DATA_VALID 0x180074UL //Access:RW DataWidth:0x1 // For CAM bist usage.
37827 #define IGU_REG_CAM_BIST_DBG_COMPARE_EN 0x180078UL //Access:RW DataWidth:0x1 // For CAM bist usage.
37829 #define IGU_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37831 #define IGU_REG_INT_STS_CTRL_FIFO_ERROR_ERR (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
37833 #define IGU_REG_INT_STS_PXP_REQ_LENGTH_TOO_BIG (0x1<<2) // PXP write message length bigger then one.
37835 #define IGU_REG_INT_STS_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3) // Host write producer update command.
37837 #define IGU_REG_INT_STS_VF_TRIES2ACC_ATTN_CMD (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
37839 #define IGU_REG_INT_STS_MME_BIGGER_THEN_5 (0x1<<5) // MME value in MSI control is bigger than 5.
37841 #define IGU_REG_INT_STS_SB_INDEX_IS_NOT_VALID (0x1<<6) // Prod / Cons update command to invalid SB index, or FID + Vector Number not found in the mapping memory. The last error can happen in cases SB doesn�t exist for MSIX memory read/write command, Read during interrupt register commands (FID and vector 0 doesn�t exist), or in other SIMD searches, for example consumer/producer update command in SIMD mode (FID and vector 0 doesn�t exist).
37843 #define IGU_REG_INT_STS_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7) // During interrupt read from function that is not in SIMD mode.
37845 #define IGU_REG_INT_STS_CMD_FID_NOT_MATCH (0x1<<8) // Command FID not match mapping FID.
37847 #define IGU_REG_INT_STS_SEGMENT_ACCESS_INVALID (0x1<<9) // Removed.
37849 #define IGU_REG_INT_STS_ATTN_PROD_ACC (0x1<<10) // Update producer command to attention producer.
37852 #define IGU_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.ADDRESS_ERROR .
37854 #define IGU_REG_INT_MASK_CTRL_FIFO_ERROR_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.CTRL_FIFO_ERROR_ERR .
37856 #define IGU_REG_INT_MASK_PXP_REQ_LENGTH_TOO_BIG (0x1<<2) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.PXP_REQ_LENGTH_TOO_BIG .
37858 #define IGU_REG_INT_MASK_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.HOST_TRIES2ACCESS_PROD_UPD .
37860 #define IGU_REG_INT_MASK_VF_TRIES2ACC_ATTN_CMD (0x1<<4) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.VF_TRIES2ACC_ATTN_CMD .
37862 #define IGU_REG_INT_MASK_MME_BIGGER_THEN_5 (0x1<<5) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.MME_BIGGER_THEN_5 .
37864 #define IGU_REG_INT_MASK_SB_INDEX_IS_NOT_VALID (0x1<<6) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.SB_INDEX_IS_NOT_VALID .
37866 #define IGU_REG_INT_MASK_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.DURIN_INT_READ_WITH_SIMD_DIS .
37868 #define IGU_REG_INT_MASK_CMD_FID_NOT_MATCH (0x1<<8) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.CMD_FID_NOT_MATCH .
37870 #define IGU_REG_INT_MASK_SEGMENT_ACCESS_INVALID (0x1<<9) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.SEGMENT_ACCESS_INVALID .
37872 #define IGU_REG_INT_MASK_ATTN_PROD_ACC (0x1<<10) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.ATTN_PROD_ACC .
37875 #define IGU_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37877 #define IGU_REG_INT_STS_WR_CTRL_FIFO_ERROR_ERR (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
37879 #define IGU_REG_INT_STS_WR_PXP_REQ_LENGTH_TOO_BIG (0x1<<2) // PXP write message length bigger then one.
37881 #define IGU_REG_INT_STS_WR_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3) // Host write producer update command.
37883 #define IGU_REG_INT_STS_WR_VF_TRIES2ACC_ATTN_CMD (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
37885 #define IGU_REG_INT_STS_WR_MME_BIGGER_THEN_5 (0x1<<5) // MME value in MSI control is bigger than 5.
37887 #define IGU_REG_INT_STS_WR_SB_INDEX_IS_NOT_VALID (0x1<<6) // Prod / Cons update command to invalid SB index, or FID + Vector Number not found in the mapping memory. The last error can happen in cases SB doesn�t exist for MSIX memory read/write command, Read during interrupt register commands (FID and vector 0 doesn�t exist), or in other SIMD searches, for example consumer/producer update command in SIMD mode (FID and vector 0 doesn�t exist).
37889 #define IGU_REG_INT_STS_WR_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7) // During interrupt read from function that is not in SIMD mode.
37891 #define IGU_REG_INT_STS_WR_CMD_FID_NOT_MATCH (0x1<<8) // Command FID not match mapping FID.
37893 #define IGU_REG_INT_STS_WR_SEGMENT_ACCESS_INVALID (0x1<<9) // Removed.
37895 #define IGU_REG_INT_STS_WR_ATTN_PROD_ACC (0x1<<10) // Update producer command to attention producer.
37898 #define IGU_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37900 #define IGU_REG_INT_STS_CLR_CTRL_FIFO_ERROR_ERR (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
37902 #define IGU_REG_INT_STS_CLR_PXP_REQ_LENGTH_TOO_BIG (0x1<<2) // PXP write message length bigger then one.
37904 #define IGU_REG_INT_STS_CLR_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3) // Host write producer update command.
37906 #define IGU_REG_INT_STS_CLR_VF_TRIES2ACC_ATTN_CMD (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
37908 #define IGU_REG_INT_STS_CLR_MME_BIGGER_THEN_5 (0x1<<5) // MME value in MSI control is bigger than 5.
37910 #define IGU_REG_INT_STS_CLR_SB_INDEX_IS_NOT_VALID (0x1<<6) // Prod / Cons update command to invalid SB index, or FID + Vector Number not found in the mapping memory. The last error can happen in cases SB doesn�t exist for MSIX memory read/write command, Read during interrupt register commands (FID and vector 0 doesn�t exist), or in other SIMD searches, for example consumer/producer update command in SIMD mode (FID and vector 0 doesn�t exist).
37912 #define IGU_REG_INT_STS_CLR_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7) // During interrupt read from function that is not in SIMD mode.
37914 #define IGU_REG_INT_STS_CLR_CMD_FID_NOT_MATCH (0x1<<8) // Command FID not match mapping FID.
37916 #define IGU_REG_INT_STS_CLR_SEGMENT_ACCESS_INVALID (0x1<<9) // Removed.
37918 #define IGU_REG_INT_STS_CLR_ATTN_PROD_ACC (0x1<<10) // Update producer command to attention producer.
37920 #define IGU_REG_PRTY_MASK 0x180194UL //Access:RW DataWidth:0x1 // Multi Field Register.
37921 #define IGU_REG_PRTY_MASK_CAM_PARITY (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS.CAM_PARITY .
37924 #define IGU_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
37926 #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
37928 #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
37930 #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
37932 #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
37934 #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
37936 #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
37938 #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0 (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
37940 #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1 (0x1<<8) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
37942 #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0 (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
37944 #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1 (0x1<<8) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
37946 #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2 (0x1<<11) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_2 .
37948 #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37950 #define IGU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
37952 #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_0 (0x1<<14) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY_0 .
37954 #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_1 (0x1<<15) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY_1 .
37956 #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0 (0x1<<14) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_0 .
37958 #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1 (0x1<<15) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_1 .
37960 #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_2 (0x1<<18) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_2 .
37962 #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
37964 #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0 (0x1<<20) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 .
37966 #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1 (0x1<<21) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_1 .
37968 #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0 (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_0 .
37970 #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1 (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
37972 #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2 (0x1<<28) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
37974 #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
37976 #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
37978 #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
37980 #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
37982 #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0 (0x1<<9) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
37984 #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1 (0x1<<10) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
37986 #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_2 (0x1<<11) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_2 .
37988 #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
37990 #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0 (0x1<<16) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
37992 #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1 (0x1<<17) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
37994 #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2 (0x1<<18) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_2 .
37996 #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37998 #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_2 (0x1<<22) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_2 .
38000 #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_3 (0x1<<23) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_3 .
38002 #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_0 (0x1<<24) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY_0 .
38004 #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_1 (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY_1 .
38006 #define IGU_REG_MEM_ECC_ENABLE_0 0x180220UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem
38007 #define IGU_REG_MEM_ECC_PARITY_ONLY_0 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem
38008 #define IGU_REG_PRTY_MASK_H_1 0x180214UL //Access:RW DataWidth:0x1 // Multi Field Register.
38009 #define IGU_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
38011 #define IGU_REG_MEM_ECC_ERROR_CORRECTED_0 0x180228UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem
38021 #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM_MASK_EN (0x1<<9) // Debug: if set the counter is active.
38027 #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM_MASK_EN (0x1<<9) // Debug: if set the counter is active.
38033 #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM_MASK_EN (0x1<<9) // Debug: if set th counter is active.
38046 #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_RO (0x1<<8) // RO for MSI and MSIX messages.
38048 #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_NS (0x1<<9) // NS for MSI and MSIX messages.
38050 #define IGU_REG_MESSAGE_FIELDS_MSIX_WRITE_DONE_TYPE (0x1<<10) // Write done type for MSI and MSIX message.
38058 #define IGU_REG_MESSAGE_FIELDS_ATTN_RO (0x1<<23) // RO for attention messages.
38060 #define IGU_REG_MESSAGE_FIELDS_ATTN_NS (0x1<<24) // NS for attention messages.
38062 #define IGU_REG_MESSAGE_FIELDS_ATTN_WRITE_DONE_TYPE (0x1<<25) // Write done type for attention message.
38066 #define IGU_REG_PCI_PF_MSI_EN 0x18080cUL //Access:RW DataWidth:0x1 // PF MSI enable status. Shadow of PCI config register.
38067 #define IGU_REG_PCI_PF_MSIX_EN 0x180810UL //Access:RW DataWidth:0x1 // PF MSIX enable status. Shadow of PCI config register.
38068 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x180814UL //Access:RW DataWidth:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
38069 #define IGU_REG_PCI_VF_MSIX_EN 0x180818UL //Access:RW DataWidth:0x1 // VF MSIX enable status. Shadow of PCI config register.
38070 #define IGU_REG_PCI_VF_MSIX_FUNC_MASK 0x18081cUL //Access:RW DataWidth:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
38082 #define IGU_REG_STATISTIC_EN 0x18084cUL //Access:RW DataWidth:0x1 // Enable to collect data in the statistic_num_vf_msg_sent memory and statistic_num_pf_msg_sent memory.
38086 #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_HIT_EN (0x1<<0) // IF = 1, hit scrubbing is enabled. When hit scrubbing is enabled, the match address of the hit response is used to perform a two-cycle read at the CAM hit location and (as usual) parity is checked during this read.
38088 #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_MISS_EN (0x1<<1) // IF = 1, miss scrubbing is enabled. When miss scrubbing is enabled, each time there is a search that results in a miss, a read of the entire CAM will be started (or re-started). This will end when the entire CAM has been read. Parity is checked during this read.
38090 #define IGU_REG_RATE_LIMITER_STATISTICS_EN 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
38153 #define IGU_REG_VF_FUNCTIONAL_CLEANUP 0x18120cUL //Access:W DataWidth:0x1 // Writing 1 to this register will clear the VF statistics.
38154 #define IGU_REG_PF_FUNCTIONAL_CLEANUP 0x181210UL //Access:W DataWidth:0x1 // Writing 1 to this register will clear the PF statistics and clean also attn bit, attn ack and attn index registers.
38169 #define IGU_REG_COMMAND_DEBUG 0x181518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command.
38173 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x181530UL //Access:R DataWidth:0x1 // Data available for error memory. If this bit is clear do not read from error_handling_memory.
38187 #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_EN (0x1<<9) // Debug: if set the debug information is collected for SB index equal or above debug_record_mask_min_sb_idx. Applicable for PROD/CONS UPD, CLEANUP, and MSIX RD/WR commands. This field is ignored for error cases and for all other commands.
38192 #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_EN (0x1<<9) // Debug: if set the debug information is collected for SB index equal or below debug_record_mask_max_sb_idx. Applicable for PROD/CONS UPD, CLEANUP, and MSIX RD/WR commands. This field is ignored for error cases and for all other commands.
38197 #define IGU_REG_DEBUG_RECORD_MASK_FID_EN (0x1<<9) // Debug: if set the debug information is collected for FID specified in debug_record_mask_fid_num according to debug_record_mask_fid_exclude field.
38199 #define IGU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE (0x1<<10) // Debug: if clear the debug information is collected for FID equal to debug_record_mask_fid_num. if set the debug information is collected for FID not equal to debug_record_mask_fid_num.
38204 #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_EN (0x1<<4) // Debug: if set the debug information is collected for source equal to debug_record_mask_source_idx.
38209 #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN (0x1<<6) // Debug: if set the debug information is collected for the marked commands only according to debug_record_mask_cmd_type_idx.
38212 #define IGU_REG_CAU_DISCARD_STATUS 0x181574UL //Access:R DataWidth:0x1 // The discard signal status from the CAU.
38231 #define CAU_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
38233 #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_RD_CMD (0x1<<1) // PXP read request arrived.
38235 #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_LENGTH_CMD (0x1<<2) // PXP write request without CQA and with length >1 arrived.
38237 #define CAU_REG_INT_STS_PXP_SB_ADDRESS_ERROR (0x1<<3) // SB index > CAU_NUM_SB or SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
38239 #define CAU_REG_INT_STS_PXP_PI_NUMBER_ERROR (0x1<<4) // PI relative number > num_pi_per_sb.
38241 #define CAU_REG_INT_STS_CLEANUP_REG_SB_IDX_ERROR (0x1<<5) // SB index > CAU_SB_NUM or SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
38243 #define CAU_REG_INT_STS_FSM_INVALID_LINE (0x1<<6) // The FSM arrived to an invalid line.
38245 #define CAU_REG_INT_STS_CQE_FIFO_ERR (0x1<<7) // Write to full FIFO or read from empty FIFO.
38247 #define CAU_REG_INT_STS_IGU_WDATA_FIFO_ERR (0x1<<8) // Write to full FIFO or read from empty FIFO.
38249 #define CAU_REG_INT_STS_IGU_REQ_FIFO_ERR (0x1<<9) // Write to full FIFO or read from empty FIFO.
38251 #define CAU_REG_INT_STS_IGU_CMD_FIFO_ERR (0x1<<10) // Write to full FIFO or read from empty FIFO.
38254 #define CAU_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
38256 #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_RD_CMD (0x1<<1) // PXP read request arrived.
38258 #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_LENGTH_CMD (0x1<<2) // PXP write request without CQA and with length >1 arrived.
38260 #define CAU_REG_INT_STS_CLR_PXP_SB_ADDRESS_ERROR (0x1<<3) // SB index > CAU_NUM_SB or SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
38262 #define CAU_REG_INT_STS_CLR_PXP_PI_NUMBER_ERROR (0x1<<4) // PI relative number > num_pi_per_sb.
38264 #define CAU_REG_INT_STS_CLR_CLEANUP_REG_SB_IDX_ERROR (0x1<<5) // SB index > CAU_SB_NUM or SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
38266 #define CAU_REG_INT_STS_CLR_FSM_INVALID_LINE (0x1<<6) // The FSM arrived to an invalid line.
38268 #define CAU_REG_INT_STS_CLR_CQE_FIFO_ERR (0x1<<7) // Write to full FIFO or read from empty FIFO.
38270 #define CAU_REG_INT_STS_CLR_IGU_WDATA_FIFO_ERR (0x1<<8) // Write to full FIFO or read from empty FIFO.
38272 #define CAU_REG_INT_STS_CLR_IGU_REQ_FIFO_ERR (0x1<<9) // Write to full FIFO or read from empty FIFO.
38274 #define CAU_REG_INT_STS_CLR_IGU_CMD_FIFO_ERR (0x1<<10) // Write to full FIFO or read from empty FIFO.
38277 #define CAU_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
38279 #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_RD_CMD (0x1<<1) // PXP read request arrived.
38281 #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_LENGTH_CMD (0x1<<2) // PXP write request without CQA and with length >1 arrived.
38283 #define CAU_REG_INT_STS_WR_PXP_SB_ADDRESS_ERROR (0x1<<3) // SB index > CAU_NUM_SB or SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
38285 #define CAU_REG_INT_STS_WR_PXP_PI_NUMBER_ERROR (0x1<<4) // PI relative number > num_pi_per_sb.
38287 #define CAU_REG_INT_STS_WR_CLEANUP_REG_SB_IDX_ERROR (0x1<<5) // SB index > CAU_SB_NUM or SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
38289 #define CAU_REG_INT_STS_WR_FSM_INVALID_LINE (0x1<<6) // The FSM arrived to an invalid line.
38291 #define CAU_REG_INT_STS_WR_CQE_FIFO_ERR (0x1<<7) // Write to full FIFO or read from empty FIFO.
38293 #define CAU_REG_INT_STS_WR_IGU_WDATA_FIFO_ERR (0x1<<8) // Write to full FIFO or read from empty FIFO.
38295 #define CAU_REG_INT_STS_WR_IGU_REQ_FIFO_ERR (0x1<<9) // Write to full FIFO or read from empty FIFO.
38297 #define CAU_REG_INT_STS_WR_IGU_CMD_FIFO_ERR (0x1<<10) // Write to full FIFO or read from empty FIFO.
38300 #define CAU_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.ADDRESS_ERROR .
38302 #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_RD_CMD (0x1<<1) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.UNAUTHORIZED_PXP_RD_CMD .
38304 #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_LENGTH_CMD (0x1<<2) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.UNAUTHORIZED_PXP_LENGTH_CMD .
38306 #define CAU_REG_INT_MASK_PXP_SB_ADDRESS_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.PXP_SB_ADDRESS_ERROR .
38308 #define CAU_REG_INT_MASK_PXP_PI_NUMBER_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.PXP_PI_NUMBER_ERROR .
38310 #define CAU_REG_INT_MASK_CLEANUP_REG_SB_IDX_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.CLEANUP_REG_SB_IDX_ERROR .
38312 #define CAU_REG_INT_MASK_FSM_INVALID_LINE (0x1<<6) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.FSM_INVALID_LINE .
38314 #define CAU_REG_INT_MASK_CQE_FIFO_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.CQE_FIFO_ERR .
38316 #define CAU_REG_INT_MASK_IGU_WDATA_FIFO_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_WDATA_FIFO_ERR .
38318 #define CAU_REG_INT_MASK_IGU_REQ_FIFO_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_REQ_FIFO_ERR .
38320 #define CAU_REG_INT_MASK_IGU_CMD_FIFO_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_CMD_FIFO_ERR .
38323 #define CAU_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
38325 #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM001_I_ECC_0_RF_INT .
38327 #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM001_I_ECC_1_RF_INT .
38329 #define CAU_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
38331 #define CAU_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
38333 #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
38335 #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
38337 #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
38339 #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
38341 #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
38343 #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
38345 #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0 (0x1<<10) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
38347 #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1 (0x1<<11) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
38349 #define CAU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
38351 #define CAU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
38354 #define CAU_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_mem_128data
38356 #define CAU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance cau.cau_pi_mem_288sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_288sb
38358 #define CAU_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance cau.cau_pi_mem_288sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_288sb
38360 #define CAU_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_mem_368sb
38362 #define CAU_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_mem_368sb
38365 #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_mem_128data
38367 #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance cau.cau_pi_mem_288sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_288sb
38369 #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance cau.cau_pi_mem_288sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_288sb
38371 #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_mem_368sb
38373 #define CAU_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_mem_368sb
38376 #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance cau.i_cau_agg_unit_mem.i_ecc in module cau_agg_unit_mem_128data
38378 #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance cau.cau_pi_mem_288sb_IF.i_cau_pi_mem.i_ecc_0 in module cau_pi_mem_288sb
38380 #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance cau.cau_pi_mem_288sb_IF.i_cau_pi_mem.i_ecc_1 in module cau_pi_mem_288sb
38382 #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_ecc in module cau_sb_addr_mem_368sb
38384 #define CAU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_ecc in module cau_sb_var_mem_368sb
38395 #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_RO (0x1<<6) // The value of the Relax Ordering field in the PXP request.
38397 #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_NS (0x1<<7) // The value of the No Snoop field in the PXP request.
38401 #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_PAD2CACHE (0x1<<13) // The value of the Pad to Cache Line field in the SB DMA PXP request.
38403 #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_PAD2CACHE (0x1<<14) // The value of the Pad to Cache Line field in the CQE PXP request.
38407 #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_DONE_TYPE (0x1<<18) // The value of the done type in the PXP request.
38409 #define CAU_REG_PI_BYP_GRAY2_EN 0x1c0408UL //Access:RW DataWidth:0x1 // Enabling pi value of command N+2/N+1 as part of sb_dma message of command N (Cont00065605 related) When set, bypass can be implemented (i.e. bug not fixed) When reset, bypass cannot be implemented (i.e. bug fixed)
38413 #define CAU_REG_CLEANUP_COMMAND_DONE 0x1c0418UL //Access:R DataWidth:0x1 // When reading one from this register mean the cleanup was done. Reading it will clear its value.
38416 #define CAU_REG_CQE_SIZE 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
38418 #define CAU_REG_CQE_FLUSH_ALL 0x1c0608UL //Access:RW DataWidth:0x1 // Flush all command - will flush all the CQE AGG unit that are in dirty state and free all AGG units.
38419 #define CAU_REG_CQE_FLUSH_ALL_DONE 0x1c060cUL //Access:R DataWidth:0x1 // Read clear register. 1 means the the cqe_flush_all command was finished.
38424 #define CAU_REG_STOP_SCAN 0x1c070cUL //Access:RW DataWidth:0x1 // Setting this bit will disable the timer expiration mechanism. Should be used in close the gate only.
38431 #define CAU_REG_IGU_REQ_CREDIT_STATUS 0x1c0980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface credit. In idle should be 1.
38432 #define CAU_REG_IGU_CMD_CREDIT_STATUS 0x1c0984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface credit. In idle should be 1.
38436 #define CAU_REG_STAT_CTRL_SB_SELECT_EN (0x1<<9) // Statistic: enable SB index statistics.
38441 #define CAU_REG_STAT_CTRL_PROTOCOL_EN (0x1<<5) // Statistic: enable protocol statistics.
38446 #define CAU_REG_STAT_CTRL_CLIENT_EN (0x1<<4) // Statistic: enable client statistics.
38451 #define CAU_REG_STAT_CTRL_FSM0_LINE_EN (0x1<<8) // Statistic: enable FSM 0 line statistics.
38456 #define CAU_REG_STAT_CTRL_FSM1_LINE_EN (0x1<<8) // Statistic: enable FSM 1 line statistics.
38480 #define CAU_REG_PARITY_LATCH_STATUS 0x1c0c90UL //Access:R DataWidth:0x1 // Debug: If set a parity occurd and the CAU assert discard flag to the IGU from now on (until hard reset).
38482 #define CAU_REG_AGG_UNITS_STATE_READ_EN 0x1c0c98UL //Access:W DataWidth:0x1 // Debug: write only. Writing to this register will copy the aggregation unit status to the agg_unit_state registers.
38491 #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_EN (0x1<<9) // Debug: if set the debug information will be collected for SB index equal or above debug_record_mask_min_sb_idx.
38496 #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_EN (0x1<<9) // Debug: if set the debug information will be collected for SB index equal or below debug_record_mask_min_sb_idx.
38501 #define CAU_REG_DEBUG_RECORD_MASK_FID_EN (0x1<<9) // Debug: if set the debug information will be collected for FID specified in debug_record_mask_fid_num.
38503 #define CAU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE (0x1<<10) // Debug: if clear the debug information will be collected for FID equal to debug_record_mask_fid_num. if set he debug information will be collected for FID not equal to debug_record_mask_fid_num.
38508 #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_EN (0x1<<4) // Debug: if set the debug information will be collected for source equal to debug_record_mask_source_idx.
38513 #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN (0x1<<3) // Debug: if set the debug information will be collected for the marked commands only according to debug_record_mask_cmd_type_idx.
38556 #define PRS_REG_SOFT_RST 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
38557 #define PRS_REG_MAC_VLAN_CACHE_INIT 0x1f0004UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initialization.
38558 #define PRS_REG_MAC_VLAN_CACHE_INIT_DONE 0x1f0008UL //Access:R DataWidth:0x1 // Set when the cache initialization is complete.
38559 #define PRS_REG_CAM_SCRUB_HIT_EN 0x1f000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit parity scrubbing feature is enabled in the MAC/VLAN cache CAM.
38560 #define PRS_REG_CAM_SCRUB_MISS_EN 0x1f0010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss parity scrubbing feature is enabled in the MAC/VLAN cache CAM.
38562 #define PRS_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
38564 #define PRS_REG_INT_STS_0_LCID_VALIDATION_ERR (0x1<<1) // Load Request Mini-cache validation error
38567 #define PRS_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PRS_REG_INT_STS_0.ADDRESS_ERROR .
38569 #define PRS_REG_INT_MASK_0_LCID_VALIDATION_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: PRS_REG_INT_STS_0.LCID_VALIDATION_ERR .
38572 #define PRS_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
38574 #define PRS_REG_INT_STS_WR_0_LCID_VALIDATION_ERR (0x1<<1) // Load Request Mini-cache validation error
38577 #define PRS_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
38579 #define PRS_REG_INT_STS_CLR_0_LCID_VALIDATION_ERR (0x1<<1) // Load Request Mini-cache validation error
38582 #define PRS_REG_PRTY_MASK_CAM_PARITY (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS.CAM_PARITY .
38584 #define PRS_REG_PRTY_MASK_GFT_CAM_PARITY (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS.GFT_CAM_PARITY .
38622 #define PRS_REG_ROCE_SEPARATE_RX_TX_CID_FLG 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override of the CID LSb is enabled for RoCE packets.
38624 #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load request is sent for TCP, UDP, and RoCE packets receiving a search response result code of match L2 filter.
38625 #define PRS_REG_CFC_LOAD_MINI_CACHE_EN 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is enabled.
38626 #define PRS_REG_TARGET_INITIATOR_SELECT 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Exchange Context
38627 #define PRS_REG_FCOE_SEARCH_WITH_EXCHANGE_CONTEXT 0x1f01a4UL //Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is zero. 1-Exchange context field in the FCoE search request is taken from the F_CTL field of the FC header.
38630 #define PRS_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
38632 #define PRS_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
38634 #define PRS_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
38636 #define PRS_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
38638 #define PRS_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
38640 #define PRS_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
38642 #define PRS_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
38644 #define PRS_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT .
38646 #define PRS_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
38648 #define PRS_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
38650 #define PRS_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
38652 #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
38654 #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
38656 #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
38658 #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
38660 #define PRS_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
38662 #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
38664 #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
38666 #define PRS_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
38668 #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
38670 #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
38672 #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
38674 #define PRS_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
38676 #define PRS_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
38678 #define PRS_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
38680 #define PRS_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
38682 #define PRS_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
38684 #define PRS_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
38686 #define PRS_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
38688 #define PRS_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
38690 #define PRS_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
38692 #define PRS_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
38694 #define PRS_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
38696 #define PRS_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
38698 #define PRS_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
38700 #define PRS_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
38702 #define PRS_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
38704 #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
38706 #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
38708 #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
38710 #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
38712 #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
38714 #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
38716 #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
38718 #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
38720 #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
38722 #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
38724 #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
38726 #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
38728 #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
38730 #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
38732 #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
38734 #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
38737 #define PRS_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
38739 #define PRS_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
38741 #define PRS_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
38743 #define PRS_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
38745 #define PRS_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
38747 #define PRS_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
38749 #define PRS_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
38751 #define PRS_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
38753 #define PRS_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
38755 #define PRS_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
38757 #define PRS_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
38759 #define PRS_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
38761 #define PRS_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
38763 #define PRS_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
38765 #define PRS_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
38767 #define PRS_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
38769 #define PRS_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
38771 #define PRS_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
38773 #define PRS_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
38775 #define PRS_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
38777 #define PRS_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
38779 #define PRS_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
38781 #define PRS_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
38783 #define PRS_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
38785 #define PRS_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
38787 #define PRS_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
38789 #define PRS_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
38791 #define PRS_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
38793 #define PRS_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
38795 #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
38797 #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
38799 #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
38801 #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
38803 #define PRS_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
38806 #define PRS_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38808 #define PRS_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38810 #define PRS_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38812 #define PRS_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38814 #define PRS_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38816 #define PRS_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38818 #define PRS_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN (0x1<<6) // Enable ECC for memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38820 #define PRS_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN (0x1<<7) // Enable ECC for memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38822 #define PRS_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38824 #define PRS_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38826 #define PRS_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38828 #define PRS_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38831 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38833 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38835 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38837 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38839 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38841 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38843 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY (0x1<<6) // Set parity only for memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38845 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY (0x1<<7) // Set parity only for memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38847 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38849 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38851 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38853 #define PRS_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38856 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38858 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38860 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38862 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38864 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38866 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38868 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38870 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38872 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38874 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38876 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38878 #define PRS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_ecc in module prs_main_fifo_mem
38881 #define PRS_REG_SEARCH_TCP 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling searches for tcp protocol.
38882 #define PRS_REG_SEARCH_UDP 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling searches for udp protocol.
38883 #define PRS_REG_SEARCH_FCOE 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling searches for fcoe protocol.
38884 #define PRS_REG_SEARCH_ROCE 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling searches for roce protocol.
38885 #define PRS_REG_SEARCH_TCP_FIRST_FRAG 0x1f0410UL //Access:RW DataWidth:0x1 // Enables sending messages to CFC on received first TCP fragmented packets.
38887 #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4 (0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the TCP search request.
38889 #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6 (0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the TCP search request.
38891 #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4 (0x1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the TCP search request.
38893 #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6 (0x1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the TCP search request.
38895 #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_DEST_PORT (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the TCP search request.
38897 #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_SOURCE_PORT (0x1<<5) // If this bit is 0, the tcp_source_port field will be masked in the TCP search request.
38899 #define PRS_REG_TCP_SEARCH_KEY_MASK_IP_VERSION (0x1<<6) // If this bit is 0, the ip_version field will be masked in the TCP search request.
38902 #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4 (0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the UDP search request.
38904 #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6 (0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the UDP search request.
38906 #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4 (0x1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the UDP search request.
38908 #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6 (0x1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the UDP search request.
38910 #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_DEST_PORT (0x1<<4) // If this bit is 0, the udp_dest_port field will be masked in the UDP search request.
38912 #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_SOURCE_PORT (0x1<<5) // If this bit is 0, the udp_source_port field will be masked in the UDP search request.
38914 #define PRS_REG_UDP_SEARCH_KEY_MASK_IP_VERSION (0x1<<6) // If this bit is 0, the ip_version field will be masked in the UDP search request.
38916 #define PRS_REG_SEARCH_FCOE_W_SRC_MAC 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search requests on FCoE packets are only sent if source MAC address compare matches.
38917 #define PRS_REG_SEARCH_FCOE_W_VFT 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if it exists) to be sent in search requests for FCoE packets.
38918 #define PRS_REG_ROCE_BUILD_CID_WO_SEARCH 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load request for RoCE pkts to be sent even though a search request was not sent
38922 #define PRS_REG_SEARCH_OPENFLOW 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for all packet types.
38923 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW 0x1f0438UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP packets. Only valid if search_openflow is also set.
38924 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP 0x1f043cUL //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-protocol field of Openflow search is only valid for SCTP, TCP, and UDP headers.
38926 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_SOURCE_PORT (0x1<<0) // If this bit is 0, the tcp_source_port field will be masked in the Openflow search request.
38928 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_SOURCE_PORT (0x1<<1) // If this bit is 0, the udp_source_port field will be masked in the Openflow search request.
38930 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_SOURCE_PORT (0x1<<2) // If this bit is 0, the sctp_source_port field will be masked in the Openflow search request.
38932 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_TYPE (0x1<<3) // If this bit is 0, the icmp_type field will be masked in the Openflow search request.
38934 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_DEST_PORT (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the Openflow search request.
38936 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_DEST_PORT (0x1<<5) // If this bit is 0, the udp_dest_port field will be masked in the Openflow search request.
38938 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_DEST_PORT (0x1<<6) // If this bit is 0, the sctp_dest_port field will be masked in the Openflow search request.
38940 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_CODE (0x1<<7) // If this bit is 0, the icmp_code field will be masked in the Openflow search request.
38942 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_PRIORITY (0x1<<8) // If this bit is 0, the priority field will be masked in the Openflow search request.
38944 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_FRAG_TYPE (0x1<<9) // If this bit is 0, the ipv4_frag_type field will be masked in the Openflow search request.
38946 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_MAC_ADDRESS (0x1<<10) // If this bit is 0, the dest_mac_address field will be masked in the Openflow search request.
38948 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_OVER_IPV4_PROTOCOL (0x1<<11) // If this bit is 0, the over_ipv4_protocol field will be masked in the Openflow search request.
38950 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ARP_OPCODE (0x1<<12) // If this bit is 0, the arp_opcode field will be masked in the Openflow search request.
38952 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_DSCP (0x1<<13) // If this bit is 0, the ipv4_dscp field will be masked in the Openflow search request.
38954 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_MAC_ADDRESS (0x1<<14) // If this bit is 0, the source_mac_address field will be masked in the Openflow search request.
38956 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4 (0x1<<15) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the Openflow search request.
38958 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_ARP (0x1<<16) // If this bit is 0, the source_ip_address_arp field will be masked in the Openflow search request.
38960 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4 (0x1<<17) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the Openflow search request.
38962 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_ARP (0x1<<18) // If this bit is 0, the dest_ip_address_arp field will be masked in the Openflow search request.
38964 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ETHERTYPE (0x1<<19) // If this bit is 0, the ethertype field will be masked in the Openflow search request.
38983 #define PRS_REG_PORTS_ARB_SCHEME 0x1f0500UL //Access:RW DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
38984 #define PRS_REG_MAIN_LB_ARB_SCHEME 0x1f0504UL //Access:RW DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
38994 #define PRS_REG_ETS_ARB_PSEUDO_RR_EN 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin arbitration.
39166 #define PRS_REG_RROCE_ENABLE 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling RRoCE.
39167 #define PRS_REG_NGE_COMP_VER 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compare the value of nge version to 2'b00. 0 - don't compare 1 - compare.
39241 #define PRS_REG_OVERRIDE_PFID_IF_NO_MATCH 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for no-match packets.
39251 #define PRS_REG_USE_LIGHT_L2 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF classification succeeds, use light_l2_tbit_eventid
39276 #define PRS_REG_SORT_SACK 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK blocks will be sorted and various compares performed.
39277 #define PRS_REG_SACK_BLK_OVERRIDE 0x1f09d4UL //Access:RW DataWidth:0x1 // If set, RoCE building block data is FIFOed on all non-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specific bits of this block will still show default values on non-RoCE packets.
39287 #define PRS_REG_RDMA_SYN_COOKIE_EN 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cookie hash function.
39288 #define PRS_REG_IWARP_EN 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables iWarp.
39289 #define PRS_REG_PKT_LEN_STAT_ADD_CRC 0x1f0a04UL //Access:RW DataWidth:0x1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For pkts where classification failed, the per-port version of this register is used.
39292 #define PRS_REG_CLASSIFY_FAILED_PKT_LEN_STAT_ADD_CRC 0x1f0a10UL //Access:RW DataWidth:0x1 // Per-Port: If set and classification failed, 4B for Ethernet CRC is included in Packet Length for Statistics field.
39333 #define PRS_REG_STOP_PARSING_STATUS 0x1f0b5cUL //Access:R DataWidth:0x1 // Debug only: BRB has asserted Stop Parsing indication to PRS.
39363 #define PRS_REG_CCFC_LOAD_CURRENT_CREDIT 0x1f0f18UL //Access:R DataWidth:0x1 // Debug only: CCFC load request current credit. Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK.
39364 #define PRS_REG_TCFC_LOAD_CURRENT_CREDIT 0x1f0f1cUL //Access:R DataWidth:0x1 // Debug only: TCFC load request current credit. Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK.
39371 #define PRS_REG_CAM_BIST_EN 0x1f0f80UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
39376 #define PRS_REG_CAM_BIST_DBG_DATA_VALID 0x1f0f94UL //Access:RW DataWidth:0x1 // For CAM bist usage.
39377 #define PRS_REG_CAM_BIST_DBG_COMPARE_EN 0x1f0f98UL //Access:RW DataWidth:0x1 // For CAM bist usage.
39395 #define PRS_REG_GFT_INNER_VLAN_SELECT 0x1f11b4UL //Access:RW DataWidth:0x1 // used to build the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN priority
39396 #define PRS_REG_GFT_TUNNEL_VLAN_SELECT 0x1f11b8UL //Access:RW DataWidth:0x1 // used to build the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN priority
39397 #define PRS_REG_SEARCH_GFT 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for all packet types.
39398 #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP packets. Only valid if search_gft is also set.
39405 #define PRS_REG_GFT_CAM_SCRUB_HIT_EN 0x1f11ccUL //Access:RW DataWidth:0x1 // When set to 1 the gft cam hit parity scrubbing feature is enabled.
39406 #define PRS_REG_GFT_CAM_SCRUB_MISS_EN 0x1f11d0UL //Access:RW DataWidth:0x1 // When set to 1 the gft cam miss parity scrubbing feature is enabled.
39408 #define XMAC_REG_CTRL_TX_EN (0x1<<0) // Transmit enable.
39410 #define XMAC_REG_CTRL_RX_EN (0x1<<1) // Receive enable.
39412 #define XMAC_REG_CTRL_LINE_LOCAL_LPBK (0x1<<2) // Local loopback from TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pipeline stage to the first RX pipeline stage.
39414 #define XMAC_REG_CTRL_CORE_LOCAL_LPBK (0x1<<3) // Local loopback from TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pipeline stage to the last RX pipeline stage.
39416 #define XMAC_REG_CTRL_LINE_REMOTE_LPBK (0x1<<4) // Remote loopback from RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pipeline stage to the last TX pipeline stage.
39418 #define XMAC_REG_CTRL_CORE_REMOTE_LPBK (0x1<<5) // Remote loopback from RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pipeline stage to the first TX pipeline stage.
39420 #define XMAC_REG_CTRL_SOFT_RESET (0x1<<6) // Resets the MAC logic annd status registers only.
39422 #define XMAC_REG_CTRL_XLGMII_ALIGN_ENB (0x1<<7) // Enables SOP; SOM & Sequence alignment to 8 byte boundaries; as defined in 40G mode.
39424 #define XMAC_REG_CTRL_LOCAL_LPBK_LEAK_ENB (0x1<<8) // If set; during either of the local loopback modes; the transmit packets are also sent to the TX Warpcore interface; apart from the loopback operation.
39426 #define XMAC_REG_CTRL_REMOTE_LPBK_LEAK_ENB (0x1<<9) // If set; during either of the remote loopback modes; the received packets are also sent to the RX Port interface; apart from the loopback operation.
39428 #define XMAC_REG_CTRL_RS_SOFT_RESET (0x1<<10) // Resets the RS layer functionality - fault handling.
39430 #define XMAC_REG_CTRL_XGMII_IPG_CHECK_DISABLE (0x1<<11) // If set; this will override the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporting 1 byte IPG in XGMII mode.
39432 #define XMAC_REG_CTRL_SW_LINK_STATUS (0x1<<12) // Link status indication from Software. If set; indicates that link is active. When this transitions from 0 to 1; EEE FSM waits for 1 second before it starts its operation.
39434 #define XMAC_REG_CTRL_LINK_STATUS_SELECT (0x1<<13) // This is the link status mux select signal to choose between link status indication from software or the link status indication from the strap pin. If reset; it selects the software link status which is also the default value.
39439 #define XMAC_REG_MODE_NO_SOP_FOR_CRC_HG (0x1<<3) // If set; exclude the SOP byte for CRC calculation in HG modes.
39448 #define XMAC_REG_TX_CTRL_LO_DISCARD (0x1<<2) // Accept packets from the host but do not transmit.
39450 #define XMAC_REG_TX_CTRL_LO_TX_ANY_START (0x1<<3) // Don't force the first byte of a packet to be /Start.
39452 #define XMAC_REG_TX_CTRL_LO_PAD_EN (0x1<<4) // Enable XMAC to pad runt packets on the Tx.
39463 #define XMAC_REG_TX_CTRL_HI_THROT_DENOM_HI (0x1<<0) // Upper 8 bits of throt_denom register. Number of bytes to transmite before adding txThrotNumer bytes to the IPG.
39467 #define XMAC_REG_TX_CTRL_HI_TX_64BYTE_BUFFER_EN (0x1<<5) // If enabled; XMAC buffers 64 bytes per packet; before starting transmission of the packet on the line side; helps to prevent underflow issues.
39472 #define XMAC_REG_RX_CTRL_RX_PASS_CTRL (0x1<<0) // Mac Control packets are passed to the system.
39474 #define XMAC_REG_RX_CTRL_RX_ANY_START (0x1<<1) // True to allow any non-Idle character to start a packet.
39476 #define XMAC_REG_RX_CTRL_STRIP_CRC (0x1<<2) // CRC is checked; then stripped from the received packet.
39478 #define XMAC_REG_RX_CTRL_STRICT_PREAMBLE (0x1<<3) // If set; the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD character - if this sequence is missing it is treated as an errored packet.
39482 #define XMAC_REG_RX_CTRL_RECEIVE_18_BYTE_PKTS (0x1<<11) // If set; the minimum receive packet size is reduced to 18 bytes from the default 33 bytes - Should be used in MACSEC chips with IEEE mode only.
39484 #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1<<12) // If set; the MAC parses the frame from K.SOP onwards to look for the SFD character and then processes the packet. If disabled; treats the first 8 bytes of packet as preamble.
39495 #define XMAC_REG_RX_VLAN_TAG_HI_INNER_VLAN_TAG_ENABLE (0x1<<0) // Enables VLAN tag detection using the INNER_VLAN_TAG.
39497 #define XMAC_REG_RX_VLAN_TAG_HI_OUTER_VLAN_TAG_ENABLE (0x1<<1) // Enables VLAN tag detection using the OUTER_VLAN_TAG.
39500 #define XMAC_REG_RX_LSS_CTRL_LOCAL_FAULT_DISABLE (0x1<<0) // True to disable enable processing of LSS message type: Local Fault. When clear and a local fault LSS message is received; a continuous stream of 'Remote Fault' LSS messages will be transmitted to the link partner.
39502 #define XMAC_REG_RX_LSS_CTRL_REMOTE_FAULT_DISABLE (0x1<<1) // True to disable processing of LSS message type: Remote Fault. When clear and a remote fault LSS message is received; a continuous stream of IDLES will be transmitted to the link partner.
39504 #define XMAC_REG_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX (0x1<<2) // If set; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used by MACSEC PHY chips.
39506 #define XMAC_REG_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE (0x1<<3) // True to disable processing of LSS message type: Link Interruption. When clear and a Link Interruption LSS message is received; a continuous stream of IDLES will be transmitted to the link partner.
39508 #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT (0x1<<4) // If set; the transmit data is dropped on detection of local fault on the receive side. If reset; transmit data is stalled on detection of local fault.
39510 #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT (0x1<<5) // If set; the transmit data is dropped on detection of remote fault on the receive side. If reset; transmit data is stalled on detection of remote fault.
39512 #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT (0x1<<6) // If set; the transmit data is dropped on detection of link interruption on the receive side. If reset; transmit data is stalled on detection of link interruption.
39514 #define XMAC_REG_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN (0x1<<7) // If set; the Receive LPause; PFC & LLFC timers are reset whenever the link status is down; or we receive local or remote faults.
39517 #define XMAC_REG_RX_LSS_STATUS_LOCAL_FAULT_STATUS (0x1<<0) // True while 'local fault' LSS messages are being received.
39519 #define XMAC_REG_RX_LSS_STATUS_REMOTE_FAULT_STATUS (0x1<<1) // True while 'remote fault' LSS messages are being received.
39521 #define XMAC_REG_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS (0x1<<2) // True while 'Link Interruption' LSS messages are being received.
39524 #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky LOCAL_FAULT_STATUS bit.
39526 #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky REMOTE_FAULT_STATUS bit.
39528 #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky LINK_INTERRUPTION_STATUS bit.
39533 #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_EN (0x1<<16) // If set; enables the pause regen functionality.
39535 #define XMAC_REG_PAUSE_CTRL_LO_TX_PAUSE_EN (0x1<<17) // Send PAUSE packets whenever TxPause input is true.
39537 #define XMAC_REG_PAUSE_CTRL_LO_RX_PAUSE_EN (0x1<<18) // Process PAUSE Frames in the receive direction.
39539 #define XMAC_REG_PAUSE_CTRL_LO_RX_PASS_PAUSE (0x1<<19) // Send PAUSE frames to the system side.
39541 #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_GMII_ON_TX_LINE_SIDE (0x1<<20) // If set; the recive pause is used to stop the frame transmission in the GMII convertor block; to reduce the Pause commencement latency.
39552 #define XMAC_REG_PFC_CTRL_HI_PFC_REFRESH_EN (0x1<<0) // Enable automatic re-send of PFC packet after a period time determined by PFC_REFRESH_TIMER.
39554 #define XMAC_REG_PFC_CTRL_HI_FORCE_PFC_XON (0x1<<1) // Instructs the MAC to send XON for all Classes of Service.
39556 #define XMAC_REG_PFC_CTRL_HI_RX_PASS_PFC (0x1<<2) // Set to pass RX PFC frame to core I/F.
39558 #define XMAC_REG_PFC_CTRL_HI_PFC_STATS_EN (0x1<<3) // Set to enable incrementing IRXPP and ITXPP.
39560 #define XMAC_REG_PFC_CTRL_HI_RX_PFC_EN (0x1<<4) // PFC RX enable.
39562 #define XMAC_REG_PFC_CTRL_HI_TX_PFC_EN (0x1<<5) // PFC TX enable.
39569 #define XMAC_REG_LLFC_CTRL_TX_LLFC_EN (0x1<<0) // This bit enables llfc for Tx path in XMAC; works with llfc_en in xport.
39571 #define XMAC_REG_LLFC_CTRL_RX_LLFC_EN (0x1<<1) // This bit enables llfc for Rx path in XMAC; works with llfc_en in xport.
39573 #define XMAC_REG_LLFC_CTRL_LLFC_IN_IPG_ONLY (0x1<<2) // When set; LLFC is inserted only during IPG.
39575 #define XMAC_REG_LLFC_CTRL_LLFC_CUT_THROUGH_MODE (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
39577 #define XMAC_REG_LLFC_CTRL_LLFC_CRC_IGNORE (0x1<<4) // This bit if set to 1; disables the crc check for incoming llfc messages.
39579 #define XMAC_REG_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC (0x1<<5) // When set; LLFC crc calculation does not involve SOM.
39600 #define XMAC_REG_HCFC_CTRL_TX_HCFC_EN (0x1<<0) // This bit enables HCFC for Tx path in XMAC.
39602 #define XMAC_REG_HCFC_CTRL_RX_HCFC_EN (0x1<<1) // This bit enables HCFC for Rx path in XMAC.
39604 #define XMAC_REG_HCFC_CTRL_HCFC_CRC_IGNORE (0x1<<2) // The crc check for HCFC messages is ignored if this bit is set.
39606 #define XMAC_REG_HCFC_CTRL_NO_SOM_FOR_CRC_HCFC (0x1<<3) // When set; HCFC CRC calculation does not involve SOM.
39608 #define XMAC_REG_HCFC_CTRL_HCFC_IN_IPG_ONLY (0x1<<4) // If 1; the HCFC packets are sent during IPG; else sent preemptively.
39615 #define XMAC_REG_FIFO_STATUS_RX_PKT_OVERFLOW (0x1<<0) // Indicates rx packet fifo overflow.
39617 #define XMAC_REG_FIFO_STATUS_RX_MSG_OVERFLOW (0x1<<1) // Indicates rx message fifo overflow.
39619 #define XMAC_REG_FIFO_STATUS_TX_PKT_UNDERFLOW (0x1<<2) // Indicates tx packet fifo underflow.
39621 #define XMAC_REG_FIFO_STATUS_TX_PKT_OVERFLOW (0x1<<3) // Indicates tx packet fifo overflow.
39623 #define XMAC_REG_FIFO_STATUS_TX_HCFC_MSG_OVERFLOW (0x1<<4) // Indicates tx HCFC message fifo overflow.
39625 #define XMAC_REG_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW (0x1<<5) // Indicates tx LLFC message fifo overflow.
39627 #define XMAC_REG_FIFO_STATUS_LINK_STATUS (0x1<<7) // This bit indicates the link status used by XMAC EEE. This is continuously updated. If set; indicates that link is active.
39630 #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky RX_PKT_OVERFLOW status bit.
39632 #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky RX_MSG_OVERFLOW status bit.
39634 #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_UNDERFLOW status bit.
39636 #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW (0x1<<3) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_OVERFLOW status bit.
39638 #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_HCFC_MSG_OVERFLOW (0x1<<4) // A rising edge on this register bit (0->1); clears the sticky TX_HCFC_MSG_OVERFLOW status bit.
39640 #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW (0x1<<5) // A rising edge on this register bit (0->1); clears the sticky TX_LLFC_MSG_OVERFLOW status bit.
39642 #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW (0x1<<6) // A rising edge on this register bit (0->1); clears the sticky TX_TS_FIFO_OVERFLOW status bit.
39652 #define XMAC_REG_EEE_CTRL_EEE_EN (0x1<<0) // EEE Enable.
39654 #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PAUSE_XOFF (0x1<<1) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state and Refresh Pause frame generation is enabled.
39656 #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PFC_XOFF (0x1<<2) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state per PFC implementation and Refresh PFC frame generation is enabled.
39658 #define XMAC_REG_EEE_CTRL_EEE_DISABLE_RX_PAUSE_ACTIVE (0x1<<3) // If set; EEE FSM can go to EMPTY state even when Receive Pause is active.
39670 #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN (0x1<<16) // When set to 1; enables LP_IDLE Prediction. When set to 0; disables LP_IDLE Prediction.
39672 #define XMAC_REG_GMII_EEE_CTRL_GMII_TXCLK_DIS (0x1<<17) // When set to 1; GMII interface will shut down TXCLK to PHY; when in LPI state.
39675 #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_LAUNCH_EN (0x1<<0) // If set; each data frame is transmitted only after the corresponding launch_en signal is asserted.
39677 #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPT_EN (0x1<<1) // Setting this field enables the CRC corruption on the transmitted packets.
39679 #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPTION_MODE (0x1<<2) // In CRC corruption mode; if this bit is set; replaces computed CRC with XXX; else computed CRC is inverted.
39702 #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0 (0x1<<0) // 0: NIG port inactive 1: NIG prot active
39708 #define CNIG_REG_NIG_PORT0_CONF_CRC_REMOVE_EN_0 (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
39710 #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_EN_0 (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append CRC field at the end of the packet.
39712 #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_EN_0 (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39714 #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_ON_ERROR_0 (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39716 #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ENABLE_0 (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
39722 #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_ENABLE_1 (0x1<<0) // 0: NIG port inactive 1: NIG prot active
39728 #define CNIG_REG_NIG_PORT1_CONF_CRC_REMOVE_EN_1 (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
39730 #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_EN_1 (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append CRC field at the end of the packet.
39732 #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_EN_1 (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39734 #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_ON_ERROR_1 (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39736 #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ENABLE_1 (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
39740 #define CNIG_REG_NW_SERDES_SWAP 0x218204UL //Access:RW DataWidth:0x1 // This register allows swapping the SERDES instances 0 : 4x25 SERDES connects to Engine 0 and 4x10 SERDES connects to Engine 1 1 : 4x25 SERDES connects to Engine 1 and 4x10 SERDES connects to Engine 0
39742 #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_ENABLE_2 (0x1<<0) // 0: NIG port inactive 1: NIG prot active
39748 #define CNIG_REG_NIG_PORT2_CONF_CRC_REMOVE_EN_2 (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
39750 #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_EN_2 (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append CRC field at the end of the packet.
39752 #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_EN_2 (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39754 #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_ON_ERROR_2 (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39756 #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ENABLE_2 (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
39761 #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_TYPE (0x1<<0) // 1 : Memory Access 0 : Register Access
39763 #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC (0x1<<1) // Setting this bit to 1 tells the interface logic auto increment the address based on the programmed byte count.
39771 #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_RESET_FSM (0x1<<16) // Reset the Register interface state machine
39774 #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_ENABLE_3 (0x1<<0) // 0: NIG port inactive 1: NIG prot active
39780 #define CNIG_REG_NIG_PORT3_CONF_CRC_REMOVE_EN_3 (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
39782 #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_EN_3 (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append CRC field at the end of the packet.
39784 #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_EN_3 (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39786 #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_ON_ERROR_3 (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
39788 #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ENABLE_3 (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
39793 #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_BUSY (0x1<<0) // 1 : State Machine is busy
39795 #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_DONE (0x1<<1) // 1 : State Machine has completed operation.
39797 #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_ERROR (0x1<<2) // 1 : Last transaction resulted in an error
39800 #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_ENABLE (0x1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback active
39802 #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_MODE (0x1<<1) // 0: mode0 is used with the following loopback mapping: NIG TX port 0 => NIG RX port 0 NIG TX port 1 => NIG RX port 1 NIG TX port 2 => NIG RX port 2 NIG TX port 3 => NIG RX port 3 1: mode1 is used with the following loopback mapping: NIG TX port 0 => NIG RX port 1 NIG TX port 1 => NIG RX port 0 NIG TX port 2 => NIG RX port 3 NIG TX port 3 => NIG RX port 2
39806 #define CNIG_REG_NWM_ERROR_MASK_LENGTH (0x1<<0) // Set to 1 for masking invlaid legth fram error.
39808 #define CNIG_REG_NWM_ERROR_MASK_CRC (0x1<<1) // Set to 1 for masking crc error.
39810 #define CNIG_REG_NWM_ERROR_MASK_DEC (0x1<<2) // Set to 1 for masking decoding error.
39812 #define CNIG_REG_NWM_ERROR_MASK_SHORT_FRAME (0x1<<3) // Set to 1 for masking fifo overflow error.
39814 #define CNIG_REG_NWM_ERROR_MASK_REMOTE (0x1<<4) // Set to 1 for masking remote error.
39816 #define CNIG_REG_NWM_ERROR_MASK_VLAN_TAG (0x1<<5) // Set to 1 for masking vlan tag error.
39818 #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_TRASMIT (0x1<<6) // Set to 1 for masking vlan transmit error.
39820 #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_VLAN (0x1<<7) // Set to 1 for masking vlan error.
39824 #define CNIG_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
39826 #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0 (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
39828 #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT1 (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
39830 #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2 (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
39832 #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT3 (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
39834 #define CNIG_REG_INT_STS_TDM_LANE_0_BANDWITH_EXCEED (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
39836 #define CNIG_REG_INT_STS_TDM_LANE_1_BANDWITH_EXCEED (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
39838 #define CNIG_REG_INT_STS_PMEG_INTR (0x1<<1) // Interrupt from PMEG.
39840 #define CNIG_REG_INT_STS_PMFC_INTR (0x1<<2) // Interrupt from PMFC.
39842 #define CNIG_REG_INT_STS_FIFO_ERROR (0x1<<3) // Error from an Interface FIFO.
39846 #define CNIG_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.ADDRESS_ERROR .
39848 #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0 (0x1<<4) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT0 .
39850 #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT1 (0x1<<2) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT1 .
39852 #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2 (0x1<<5) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT2 .
39854 #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT3 (0x1<<4) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT3 .
39856 #define CNIG_REG_INT_MASK_TDM_LANE_0_BANDWITH_EXCEED (0x1<<5) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TDM_LANE_0_BANDWITH_EXCEED .
39858 #define CNIG_REG_INT_MASK_TDM_LANE_1_BANDWITH_EXCEED (0x1<<6) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TDM_LANE_1_BANDWITH_EXCEED .
39860 #define CNIG_REG_INT_MASK_PMEG_INTR (0x1<<1) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.PMEG_INTR .
39862 #define CNIG_REG_INT_MASK_PMFC_INTR (0x1<<2) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.PMFC_INTR .
39864 #define CNIG_REG_INT_MASK_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.FIFO_ERROR .
39867 #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_TYPE (0x1<<0) // 1 : Memory Access 0 : Register Access
39869 #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC (0x1<<1) // Setting this bit to 1 tells the interface logic auto increment the address based on the programmed byte count.
39877 #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_RESET_FSM (0x1<<16) // Reset the Register interface state machine
39880 #define CNIG_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
39882 #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0 (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
39884 #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT1 (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
39886 #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2 (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
39888 #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT3 (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
39890 #define CNIG_REG_INT_STS_WR_TDM_LANE_0_BANDWITH_EXCEED (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
39892 #define CNIG_REG_INT_STS_WR_TDM_LANE_1_BANDWITH_EXCEED (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
39894 #define CNIG_REG_INT_STS_WR_PMEG_INTR (0x1<<1) // Interrupt from PMEG.
39896 #define CNIG_REG_INT_STS_WR_PMFC_INTR (0x1<<2) // Interrupt from PMFC.
39898 #define CNIG_REG_INT_STS_WR_FIFO_ERROR (0x1<<3) // Error from an Interface FIFO.
39901 #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_BUSY (0x1<<0) // 1 : State Machine is busy
39903 #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_DONE (0x1<<1) // 1 : State Machine has completed operation.
39905 #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_ERROR (0x1<<2) // 1 : Last transaction resulted in an error
39908 #define CNIG_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
39910 #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0 (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
39912 #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT1 (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
39914 #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2 (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
39916 #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT3 (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP + Byte Valid > 28" without inserting an "empty" transaction in between.
39918 #define CNIG_REG_INT_STS_CLR_TDM_LANE_0_BANDWITH_EXCEED (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
39920 #define CNIG_REG_INT_STS_CLR_TDM_LANE_1_BANDWITH_EXCEED (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
39922 #define CNIG_REG_INT_STS_CLR_PMEG_INTR (0x1<<1) // Interrupt from PMEG.
39924 #define CNIG_REG_INT_STS_CLR_PMFC_INTR (0x1<<2) // Interrupt from PMFC.
39926 #define CNIG_REG_INT_STS_CLR_FIFO_ERROR (0x1<<3) // Error from an Interface FIFO.
39929 #define CNIG_REG_NWM_LPI_DEFUALT_VALUE 0x218228UL //Access:RW DataWidth:0x1 // This register is used to set the value of NWM lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the NWM NIG mapping.
39933 #define CNIG_REG_PRTY_MASK_DATAPATH_TX (0x1<<1) // This bit masks, when set, the Parity bit: CNIG_REG_PRTY_STS.DATAPATH_TX .
39935 #define CNIG_REG_PRTY_MASK_DATAPATH_RX (0x1<<0) // This bit masks, when set, the Parity bit: CNIG_REG_PRTY_STS.DATAPATH_RX .
39940 #define CNIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC And LED_CONTROL_BLINK_TRAFFIC
39942 #define CNIG_REG_LED_CONTROL_TRAFFIC (0x1<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
39944 #define CNIG_REG_LED_CONTROL_BLINK_TRAFFIC (0x1<<8) // Port0: If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
39946 #define CNIG_REG_LED_CONTROL_BLINK_RATE_ENA (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field defined below. If this bit is cleared; then the blink rate will be about 16Hz.
39980 #define CNIG_REG_PMIF_OVERRIDE_ENABLE 0x218278UL //Access:RW DataWidth:0x1 // When set, PMIF block uses values in following registers to configure NIG - PM interface
40045 #define CNIG_REG_PMEG_SIGN_EXT 0x218320UL //Access:RW DataWidth:0x1 // This register is used to set the value of cnig_pmeg_sign_ext output signal.
40046 #define CNIG_REG_PMFC_SIGN_EXT 0x218324UL //Access:RW DataWidth:0x1 // This register is used to set the value of cnig_pmfc_sign_ext output signal.
40047 #define CNIG_REG_PMFC_LPI_DEFUALT_VALUE 0x218328UL //Access:RW DataWidth:0x1 // This register is used to set the value of PMFC lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the Port Macro NIG mapping.
40048 #define CNIG_REG_PMEG_LPI_DEFUALT_VALUE 0x21832cUL //Access:RW DataWidth:0x1 // This register is used to set the value of PMEG lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the Port Macro NIG mapping.
40049 #define CNIG_REG_PMEG_TS_RESET_N 0x218330UL //Access:RW DataWidth:0x1 // PMEG timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of reset.
40050 #define CNIG_REG_PMFC_TS_RESET_N 0x218334UL //Access:RW DataWidth:0x1 // PMFC timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of reset.
40055 #define PRM_REG_DISABLE_PRM 0x230000UL //Access:RW DataWidth:0x1 // Used to disable the PRM from processing any new commands.
40056 #define PRM_REG_BRB_DATA_IN_EN 0x230004UL //Access:RW DataWidth:0x1 // Enables data to be received on the BRB data interface.
40057 #define PRM_REG_BRB_FULL_OUT_EN 0x230008UL //Access:RW DataWidth:0x1 // Enables the BRB full output to be asserted by the PRM.
40058 #define PRM_REG_PXP_ACK_IN_EN 0x23000cUL //Access:RW DataWidth:0x1 // Enables the PXP request acknowledge to be received by the PRM.
40059 #define PRM_REG_DISABLE_INPUTS 0x230010UL //Access:RW DataWidth:0x1 // Used to disable all PRM block inputs for test purposes.
40060 #define PRM_REG_DISABLE_OUTPUTS 0x230014UL //Access:RW DataWidth:0x1 // Used to disable all PRM block outputs for test purposes.
40062 #define PRM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40064 #define PRM_REG_INT_STS_IFIFO_ERROR (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
40066 #define PRM_REG_INT_STS_IMMED_FIFO_ERROR (0x1<<2) // Overrun/underrun error for the immediate FIFO.
40068 #define PRM_REG_INT_STS_OFST_PEND_ERROR (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
40070 #define PRM_REG_INT_STS_PAD_PEND_ERROR (0x1<<4) // Overrun/underrun error for pad pending FIFO.
40072 #define PRM_REG_INT_STS_PBINP_PEND_ERROR (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
40074 #define PRM_REG_INT_STS_TAG_PEND_ERROR (0x1<<6) // Overrun/underrun error for tag pending FIFO.
40076 #define PRM_REG_INT_STS_MSTORM_EOP_ERR (0x1<<7) // End of packet error on M-Storm command interface.
40078 #define PRM_REG_INT_STS_USTORM_EOP_ERR (0x1<<8) // End of packet error on U-Storm command interface.
40080 #define PRM_REG_INT_STS_MSTORM_QUE_ERR (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
40082 #define PRM_REG_INT_STS_USTORM_QUE_ERR (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
40085 #define PRM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.ADDRESS_ERROR .
40087 #define PRM_REG_INT_MASK_IFIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.IFIFO_ERROR .
40089 #define PRM_REG_INT_MASK_IMMED_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.IMMED_FIFO_ERROR .
40091 #define PRM_REG_INT_MASK_OFST_PEND_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.OFST_PEND_ERROR .
40093 #define PRM_REG_INT_MASK_PAD_PEND_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.PAD_PEND_ERROR .
40095 #define PRM_REG_INT_MASK_PBINP_PEND_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.PBINP_PEND_ERROR .
40097 #define PRM_REG_INT_MASK_TAG_PEND_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.TAG_PEND_ERROR .
40099 #define PRM_REG_INT_MASK_MSTORM_EOP_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.MSTORM_EOP_ERR .
40101 #define PRM_REG_INT_MASK_USTORM_EOP_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.USTORM_EOP_ERR .
40103 #define PRM_REG_INT_MASK_MSTORM_QUE_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.MSTORM_QUE_ERR .
40105 #define PRM_REG_INT_MASK_USTORM_QUE_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.USTORM_QUE_ERR .
40108 #define PRM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40110 #define PRM_REG_INT_STS_WR_IFIFO_ERROR (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
40112 #define PRM_REG_INT_STS_WR_IMMED_FIFO_ERROR (0x1<<2) // Overrun/underrun error for the immediate FIFO.
40114 #define PRM_REG_INT_STS_WR_OFST_PEND_ERROR (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
40116 #define PRM_REG_INT_STS_WR_PAD_PEND_ERROR (0x1<<4) // Overrun/underrun error for pad pending FIFO.
40118 #define PRM_REG_INT_STS_WR_PBINP_PEND_ERROR (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
40120 #define PRM_REG_INT_STS_WR_TAG_PEND_ERROR (0x1<<6) // Overrun/underrun error for tag pending FIFO.
40122 #define PRM_REG_INT_STS_WR_MSTORM_EOP_ERR (0x1<<7) // End of packet error on M-Storm command interface.
40124 #define PRM_REG_INT_STS_WR_USTORM_EOP_ERR (0x1<<8) // End of packet error on U-Storm command interface.
40126 #define PRM_REG_INT_STS_WR_MSTORM_QUE_ERR (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
40128 #define PRM_REG_INT_STS_WR_USTORM_QUE_ERR (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
40131 #define PRM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40133 #define PRM_REG_INT_STS_CLR_IFIFO_ERROR (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
40135 #define PRM_REG_INT_STS_CLR_IMMED_FIFO_ERROR (0x1<<2) // Overrun/underrun error for the immediate FIFO.
40137 #define PRM_REG_INT_STS_CLR_OFST_PEND_ERROR (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
40139 #define PRM_REG_INT_STS_CLR_PAD_PEND_ERROR (0x1<<4) // Overrun/underrun error for pad pending FIFO.
40141 #define PRM_REG_INT_STS_CLR_PBINP_PEND_ERROR (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
40143 #define PRM_REG_INT_STS_CLR_TAG_PEND_ERROR (0x1<<6) // Overrun/underrun error for tag pending FIFO.
40145 #define PRM_REG_INT_STS_CLR_MSTORM_EOP_ERR (0x1<<7) // End of packet error on M-Storm command interface.
40147 #define PRM_REG_INT_STS_CLR_USTORM_EOP_ERR (0x1<<8) // End of packet error on U-Storm command interface.
40149 #define PRM_REG_INT_STS_CLR_MSTORM_QUE_ERR (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
40151 #define PRM_REG_INT_STS_CLR_USTORM_QUE_ERR (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
40153 #define PRM_REG_PRTY_MASK 0x230054UL //Access:RW DataWidth:0x1 // Multi Field Register.
40154 #define PRM_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS.DATAPATH_REGISTERS .
40157 #define PRM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
40159 #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
40161 #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
40163 #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT .
40165 #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
40167 #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
40169 #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
40171 #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
40173 #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
40175 #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
40177 #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
40179 #define PRM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
40181 #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
40183 #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
40185 #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
40187 #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
40189 #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
40191 #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
40193 #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
40195 #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
40197 #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
40199 #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
40201 #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
40203 #define PRM_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
40205 #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
40207 #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
40209 #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
40211 #define PRM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
40213 #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
40220 #define PRM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
40222 #define PRM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
40224 #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
40226 #define PRM_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
40228 #define PRM_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
40230 #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
40233 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
40235 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
40237 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
40239 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
40241 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
40243 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
40246 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
40248 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem
40250 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_ecc in module rdif_l1_sector1_mem
40252 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
40254 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem
40256 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram
40262 #define PRM_REG_PAD_FROM_DBG 0x230424UL //Access:RW DataWidth:0x1 // When set, this bit enables the pad insertion logic to use BRB debug field from the PRM command to define the value of the inserted pad; otherwise the pad_data configuration is used.
40302 #define PRM_REG_NOP_WITHOUT_COMPLETION_FIX_DISABLE 0x236000UL //Access:RW DataWidth:0x1 // Chicken Bit for the NOP without completion fix
40308 #define SRC_REG_CTRL_VLAN_HASH_ENABLE (0x1<<16) // Enable for VLAN in Hash Address. !!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is illegal !!!
40310 #define SRC_REG_CTRL_VLAN_MATCH_DISABLE (0x1<<17) // Disable VLAN and VLAN Promiscuous Mode (vpf) matching logic.!!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is illegal !!!
40312 #define SRC_REG_CTRL_STRING_MATCH_DISABLE (0x1<<18) // Disable String Matching Logic.
40314 #define SRC_REG_CTRL_ALLOWSHORTCUT (0x1<<19) // If set; same search shortcut is allowed.
40316 #define SRC_REG_CTRL_ALLOWEMPTYSHORTCUT (0x1<<20) // If set; search return no match on empty shortcut is allowed.
40318 #define SRC_REG_CTRL_TENANT_ID_DISABLE (0x1<<21) // Disable Tenant ID Matching Logic.NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is illegal !!!
40320 #define SRC_REG_CTRL_TENANT_ID_IN_HASH_EN (0x1<<22) // Enables the use of the tenant_id value in Hash address calculation.!!! NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is illegal !!!
40322 #define SRC_REG_INT_STS 0x2381d8UL //Access:R DataWidth:0x1 // Multi Field Register.
40323 #define SRC_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40325 #define SRC_REG_INT_STS_CLR 0x2381dcUL //Access:RC DataWidth:0x1 // Multi Field Register.
40326 #define SRC_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40328 #define SRC_REG_INT_STS_WR 0x2381e0UL //Access:WR DataWidth:0x1 // Multi Field Register.
40329 #define SRC_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40331 #define SRC_REG_INT_MASK 0x2381e4UL //Access:RW DataWidth:0x1 // Multi Field Register.
40332 #define SRC_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: SRC_REG_INT_STS.ADDRESS_ERROR .
40347 #define SRC_REG_IF_STAT_ENABLED 0x238488UL //Access:RW DataWidth:0x1 // IF Stats Enable Bit. IF Stat Counters only count when this bit is set. This bit is cleared when any IF Stat Counter is read to ensure coherency. Setting this bit clears all IF Stat Counters.
40362 #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T1 (0x1<<3) // Controls PXP Request TPH Valid field for Table1.
40366 #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T2 (0x1<<7) // Controls PXP Request TPH Valid field for Table2.
40368 #define SRC_REG_PXP_CTRL_PXP_DONETYPE (0x1<<8) // Controls PXP Request DonType Field.
40384 #define RSS_REG_RSS_INIT_EN 0x238804UL //Access:RW DataWidth:0x1 // Write to this register will initialize all rows of RSS memory to zeros.It will be be set to 0 when init will be finished.
40385 #define RSS_REG_RSS_INIT_DONE 0x238808UL //Access:R DataWidth:0x1 // This register will be set when init procedure of RSS memory is finished.
40387 #define RSS_REG_IF_ENABLE_TMLD_INP_EN (0x1<<0) // TM loader input interface enable register.
40389 #define RSS_REG_IF_ENABLE_RGFS_INP_EN (0x1<<1) // RGFS input interface enable register.
40391 #define RSS_REG_IF_ENABLE_TMLD_OUT_EN (0x1<<2) // TM loader output interface enable register.
40393 #define RSS_REG_IF_ENABLE_RGFS_OUT_EN (0x1<<3) // RGFS output interface enable register.
40395 #define RSS_REG_IF_ENABLE_TSEM_INP_EN (0x1<<1) // TSEM input interface enable register.
40397 #define RSS_REG_IF_ENABLE_TSEM_OUT_EN (0x1<<3) // TSEM output interface enable register.
40400 #define RSS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40402 #define RSS_REG_INT_STS_CMD_FIFO_ERROR (0x1<<8) // RSS command FIFO overflow or underflow.
40404 #define RSS_REG_INT_STS_RSP_FIFO_ERROR (0x1<<10) // Response FIFO overflow or underflow.
40406 #define RSS_REG_INT_STS_HDR_FIFO_ERROR (0x1<<11) // Header FIFO overflow or underflow.
40408 #define RSS_REG_INT_STS_INFO_FIFO_ERROR (0x1<<12) // Info FIFO overflow or underflow.
40410 #define RSS_REG_INT_STS_KEY_LOW_FIFO_ERROR (0x1<<13) // Key Low FIFO overflow or underflow.
40412 #define RSS_REG_INT_STS_KEY_MID_FIFO_ERROR (0x1<<14) // Key Mid FIFO overflow or underflow.
40414 #define RSS_REG_INT_STS_KEY_HIGH_FIFO_ERROR (0x1<<15) // Key High FIFO overflow or underflow.
40416 #define RSS_REG_INT_STS_TUPLE_FIFO_ERROR (0x1<<16) // Tuple FIFO overflow or underflow.
40418 #define RSS_REG_INT_STS_HASH_FIFO_ERROR (0x1<<17) // Hash FIFO overflow or underflow.
40420 #define RSS_REG_INT_STS_HASH_TUPLE_FIFO_ERROR (0x1<<18) // Hash Tuple FIFO overflow or underflow.
40422 #define RSS_REG_INT_STS_IND_HASH_FIFO_ERROR (0x1<<19) // Indirect Hash FIFO overflow or underflow.
40424 #define RSS_REG_INT_STS_F4TUPLE_OFFSET_ZERO (0x1<<20) // Received RSS hash command where f4tuple_offset field was 0.
40426 #define RSS_REG_INT_STS_F4TUPLE_OFFSET_IN_TMLD (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
40428 #define RSS_REG_INT_STS_MSG_INP_CNT_ERROR (0x1<<1) // Number of cycles in CM message from TSEM is 63.
40430 #define RSS_REG_INT_STS_MSG_OUT_CNT_ERROR (0x1<<2) // Number of cycles in CM message to TM loader is 63.
40432 #define RSS_REG_INT_STS_INP_STATE_ERROR (0x1<<3) // Input state machine reached error state.
40434 #define RSS_REG_INT_STS_OUT_STATE_ERROR (0x1<<4) // Output state machine reached error state.
40436 #define RSS_REG_INT_STS_MAIN_STATE_ERROR (0x1<<5) // Main state machine in RSS calculation block reached error state.
40438 #define RSS_REG_INT_STS_CALC_STATE_ERROR (0x1<<6) // CALC state machine in RSS calculation block reached error state.
40440 #define RSS_REG_INT_STS_INP_FIFO_ERROR (0x1<<7) // Input FIFO overflow or underflow.
40442 #define RSS_REG_INT_STS_MSG_FIFO_ERROR (0x1<<9) // Message FIFO overflow or underflow.
40445 #define RSS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.ADDRESS_ERROR .
40447 #define RSS_REG_INT_MASK_CMD_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.CMD_FIFO_ERROR .
40449 #define RSS_REG_INT_MASK_RSP_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.RSP_FIFO_ERROR .
40451 #define RSS_REG_INT_MASK_HDR_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.HDR_FIFO_ERROR .
40453 #define RSS_REG_INT_MASK_INFO_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INFO_FIFO_ERROR .
40455 #define RSS_REG_INT_MASK_KEY_LOW_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.KEY_LOW_FIFO_ERROR .
40457 #define RSS_REG_INT_MASK_KEY_MID_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.KEY_MID_FIFO_ERROR .
40459 #define RSS_REG_INT_MASK_KEY_HIGH_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.KEY_HIGH_FIFO_ERROR .
40461 #define RSS_REG_INT_MASK_TUPLE_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.TUPLE_FIFO_ERROR .
40463 #define RSS_REG_INT_MASK_HASH_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.HASH_FIFO_ERROR .
40465 #define RSS_REG_INT_MASK_HASH_TUPLE_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.HASH_TUPLE_FIFO_ERROR .
40467 #define RSS_REG_INT_MASK_IND_HASH_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.IND_HASH_FIFO_ERROR .
40469 #define RSS_REG_INT_MASK_F4TUPLE_OFFSET_ZERO (0x1<<20) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.F4TUPLE_OFFSET_ZERO .
40471 #define RSS_REG_INT_MASK_F4TUPLE_OFFSET_IN_TMLD (0x1<<21) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.F4TUPLE_OFFSET_IN_TMLD .
40473 #define RSS_REG_INT_MASK_MSG_INP_CNT_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_INP_CNT_ERROR .
40475 #define RSS_REG_INT_MASK_MSG_OUT_CNT_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_OUT_CNT_ERROR .
40477 #define RSS_REG_INT_MASK_INP_STATE_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INP_STATE_ERROR .
40479 #define RSS_REG_INT_MASK_OUT_STATE_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.OUT_STATE_ERROR .
40481 #define RSS_REG_INT_MASK_MAIN_STATE_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MAIN_STATE_ERROR .
40483 #define RSS_REG_INT_MASK_CALC_STATE_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.CALC_STATE_ERROR .
40485 #define RSS_REG_INT_MASK_INP_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INP_FIFO_ERROR .
40487 #define RSS_REG_INT_MASK_MSG_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_FIFO_ERROR .
40490 #define RSS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40492 #define RSS_REG_INT_STS_WR_CMD_FIFO_ERROR (0x1<<8) // RSS command FIFO overflow or underflow.
40494 #define RSS_REG_INT_STS_WR_RSP_FIFO_ERROR (0x1<<10) // Response FIFO overflow or underflow.
40496 #define RSS_REG_INT_STS_WR_HDR_FIFO_ERROR (0x1<<11) // Header FIFO overflow or underflow.
40498 #define RSS_REG_INT_STS_WR_INFO_FIFO_ERROR (0x1<<12) // Info FIFO overflow or underflow.
40500 #define RSS_REG_INT_STS_WR_KEY_LOW_FIFO_ERROR (0x1<<13) // Key Low FIFO overflow or underflow.
40502 #define RSS_REG_INT_STS_WR_KEY_MID_FIFO_ERROR (0x1<<14) // Key Mid FIFO overflow or underflow.
40504 #define RSS_REG_INT_STS_WR_KEY_HIGH_FIFO_ERROR (0x1<<15) // Key High FIFO overflow or underflow.
40506 #define RSS_REG_INT_STS_WR_TUPLE_FIFO_ERROR (0x1<<16) // Tuple FIFO overflow or underflow.
40508 #define RSS_REG_INT_STS_WR_HASH_FIFO_ERROR (0x1<<17) // Hash FIFO overflow or underflow.
40510 #define RSS_REG_INT_STS_WR_HASH_TUPLE_FIFO_ERROR (0x1<<18) // Hash Tuple FIFO overflow or underflow.
40512 #define RSS_REG_INT_STS_WR_IND_HASH_FIFO_ERROR (0x1<<19) // Indirect Hash FIFO overflow or underflow.
40514 #define RSS_REG_INT_STS_WR_F4TUPLE_OFFSET_ZERO (0x1<<20) // Received RSS hash command where f4tuple_offset field was 0.
40516 #define RSS_REG_INT_STS_WR_F4TUPLE_OFFSET_IN_TMLD (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
40518 #define RSS_REG_INT_STS_WR_MSG_INP_CNT_ERROR (0x1<<1) // Number of cycles in CM message from TSEM is 63.
40520 #define RSS_REG_INT_STS_WR_MSG_OUT_CNT_ERROR (0x1<<2) // Number of cycles in CM message to TM loader is 63.
40522 #define RSS_REG_INT_STS_WR_INP_STATE_ERROR (0x1<<3) // Input state machine reached error state.
40524 #define RSS_REG_INT_STS_WR_OUT_STATE_ERROR (0x1<<4) // Output state machine reached error state.
40526 #define RSS_REG_INT_STS_WR_MAIN_STATE_ERROR (0x1<<5) // Main state machine in RSS calculation block reached error state.
40528 #define RSS_REG_INT_STS_WR_CALC_STATE_ERROR (0x1<<6) // CALC state machine in RSS calculation block reached error state.
40530 #define RSS_REG_INT_STS_WR_INP_FIFO_ERROR (0x1<<7) // Input FIFO overflow or underflow.
40532 #define RSS_REG_INT_STS_WR_MSG_FIFO_ERROR (0x1<<9) // Message FIFO overflow or underflow.
40535 #define RSS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40537 #define RSS_REG_INT_STS_CLR_CMD_FIFO_ERROR (0x1<<8) // RSS command FIFO overflow or underflow.
40539 #define RSS_REG_INT_STS_CLR_RSP_FIFO_ERROR (0x1<<10) // Response FIFO overflow or underflow.
40541 #define RSS_REG_INT_STS_CLR_HDR_FIFO_ERROR (0x1<<11) // Header FIFO overflow or underflow.
40543 #define RSS_REG_INT_STS_CLR_INFO_FIFO_ERROR (0x1<<12) // Info FIFO overflow or underflow.
40545 #define RSS_REG_INT_STS_CLR_KEY_LOW_FIFO_ERROR (0x1<<13) // Key Low FIFO overflow or underflow.
40547 #define RSS_REG_INT_STS_CLR_KEY_MID_FIFO_ERROR (0x1<<14) // Key Mid FIFO overflow or underflow.
40549 #define RSS_REG_INT_STS_CLR_KEY_HIGH_FIFO_ERROR (0x1<<15) // Key High FIFO overflow or underflow.
40551 #define RSS_REG_INT_STS_CLR_TUPLE_FIFO_ERROR (0x1<<16) // Tuple FIFO overflow or underflow.
40553 #define RSS_REG_INT_STS_CLR_HASH_FIFO_ERROR (0x1<<17) // Hash FIFO overflow or underflow.
40555 #define RSS_REG_INT_STS_CLR_HASH_TUPLE_FIFO_ERROR (0x1<<18) // Hash Tuple FIFO overflow or underflow.
40557 #define RSS_REG_INT_STS_CLR_IND_HASH_FIFO_ERROR (0x1<<19) // Indirect Hash FIFO overflow or underflow.
40559 #define RSS_REG_INT_STS_CLR_F4TUPLE_OFFSET_ZERO (0x1<<20) // Received RSS hash command where f4tuple_offset field was 0.
40561 #define RSS_REG_INT_STS_CLR_F4TUPLE_OFFSET_IN_TMLD (0x1<<21) // Received RSS hash command where f4tuple_offset field puts f4tuple in the tmld header.
40563 #define RSS_REG_INT_STS_CLR_MSG_INP_CNT_ERROR (0x1<<1) // Number of cycles in CM message from TSEM is 63.
40565 #define RSS_REG_INT_STS_CLR_MSG_OUT_CNT_ERROR (0x1<<2) // Number of cycles in CM message to TM loader is 63.
40567 #define RSS_REG_INT_STS_CLR_INP_STATE_ERROR (0x1<<3) // Input state machine reached error state.
40569 #define RSS_REG_INT_STS_CLR_OUT_STATE_ERROR (0x1<<4) // Output state machine reached error state.
40571 #define RSS_REG_INT_STS_CLR_MAIN_STATE_ERROR (0x1<<5) // Main state machine in RSS calculation block reached error state.
40573 #define RSS_REG_INT_STS_CLR_CALC_STATE_ERROR (0x1<<6) // CALC state machine in RSS calculation block reached error state.
40575 #define RSS_REG_INT_STS_CLR_INP_FIFO_ERROR (0x1<<7) // Input FIFO overflow or underflow.
40577 #define RSS_REG_INT_STS_CLR_MSG_FIFO_ERROR (0x1<<9) // Message FIFO overflow or underflow.
40580 #define RSS_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
40582 #define RSS_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
40584 #define RSS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
40586 #define RSS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
40589 #define RSS_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance rss.RSS_MEM_BB_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_2port_ram
40591 #define RSS_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance rss.RSS_IND_BB_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_2port_ram
40594 #define RSS_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance rss.RSS_MEM_BB_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_2port_ram
40596 #define RSS_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance rss.RSS_IND_BB_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_2port_ram
40599 #define RSS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance rss.RSS_MEM_BB_GEN_IF.i_rss_mem_ram.i_ecc in module rss_mem_2port_ram
40601 #define RSS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance rss.RSS_IND_BB_GEN_IF.i_rss_ind_ram.i_ecc in module rss_ind_2port_ram
40626 #define RSS_REG_MEMCTRL_WR_RD_N 0x238c88UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
40631 #define RSS_REG_FIFO_FULL_STATUS1_RSP_FIFO_FULL (0x1<<0) // The rsp fifio is empty.
40633 #define RSS_REG_FIFO_FULL_STATUS1_IND_HASH_FIFO_FULL (0x1<<1) // The ind_hash fifo is full.
40635 #define RSS_REG_FIFO_FULL_STATUS1_HASH_TUPLE_FIFO_FULL (0x1<<2) // The hash_tuple fifo is full.
40637 #define RSS_REG_FIFO_FULL_STATUS1_HASH_FIFO_FULL (0x1<<3) // The hash fifo is full.
40639 #define RSS_REG_FIFO_FULL_STATUS1_TUPLE_FIFO_FULL (0x1<<4) // The tuple fifo is full.
40641 #define RSS_REG_FIFO_FULL_STATUS1_KEY_HIGH_FIFO_FULL (0x1<<5) // The key_high fifo is full.
40643 #define RSS_REG_FIFO_FULL_STATUS1_KEY_MID_FIFO_FULL (0x1<<6) // The key_mid fifo is full.
40645 #define RSS_REG_FIFO_FULL_STATUS1_KEY_LOW_FIFO_FULL (0x1<<7) // The key_low fifo is full.
40647 #define RSS_REG_FIFO_FULL_STATUS1_INFO_FIFO_FULL (0x1<<8) // The info fifo is full.
40649 #define RSS_REG_FIFO_FULL_STATUS1_HEADER_FIFO_FULL (0x1<<9) // The header fifo is full.
40651 #define RSS_REG_FIFO_FULL_STATUS1_CMD_FIFO_FULL (0x1<<10) // The cmd fifo is full.
40653 #define RSS_REG_FIFO_FULL_STATUS1_MSG_FIFO_FULL (0x1<<11) // The msg fifo is full.
40655 #define RSS_REG_FIFO_FULL_STATUS1_INP_FIFO_FULL (0x1<<12) // The inp fifo is full.
40658 #define RSS_REG_FIFO_EMPTY_STATUS1_RSP_FIFO_EMPTY (0x1<<0) // The rsp fifio is empty.
40660 #define RSS_REG_FIFO_EMPTY_STATUS1_IND_HASH_FIFO_EMPTY (0x1<<1) // The ind_hash fifo is empty.
40662 #define RSS_REG_FIFO_EMPTY_STATUS1_HASH_TUPLE_FIFO_EMPTY (0x1<<2) // The hash_tuple fifo is empty.
40664 #define RSS_REG_FIFO_EMPTY_STATUS1_HASH_FIFO_EMPTY (0x1<<3) // The hash fifo is empty.
40666 #define RSS_REG_FIFO_EMPTY_STATUS1_TUPLE_FIFO_EMPTY (0x1<<4) // The tuple fifo is empty.
40668 #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_HIGH_FIFO_EMPTY (0x1<<5) // The key_high fifo is empty.
40670 #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_MID_FIFO_EMPTY (0x1<<6) // The key_mid fifo is empty.
40672 #define RSS_REG_FIFO_EMPTY_STATUS1_KEY_LOW_FIFO_EMPTY (0x1<<7) // The key_low fifo is empty.
40674 #define RSS_REG_FIFO_EMPTY_STATUS1_INFO_FIFO_EMPTY (0x1<<8) // The info fifo is empty.
40676 #define RSS_REG_FIFO_EMPTY_STATUS1_HEADER_FIFO_EMPTY (0x1<<9) // The header fifo is empty.
40678 #define RSS_REG_FIFO_EMPTY_STATUS1_CMD_FIFO_EMPTY (0x1<<10) // The cmd fifo is empty.
40680 #define RSS_REG_FIFO_EMPTY_STATUS1_MSG_FIFO_EMPTY (0x1<<11) // The msg fifo is empty.
40682 #define RSS_REG_FIFO_EMPTY_STATUS1_INP_FIFO_EMPTY (0x1<<12) // The inp fifo is empty.
40725 #define RPB_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40727 #define RPB_REG_INT_STS_EOP_ERROR (0x1<<1) // EOP check error.
40729 #define RPB_REG_INT_STS_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
40731 #define RPB_REG_INT_STS_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
40733 #define RPB_REG_INT_STS_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
40735 #define RPB_REG_INT_STS_TH_EXEC_ERROR (0x1<<5) //
40737 #define RPB_REG_INT_STS_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
40739 #define RPB_REG_INT_STS_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
40741 #define RPB_REG_INT_STS_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
40744 #define RPB_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
40746 #define RPB_REG_INT_MASK_EOP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
40748 #define RPB_REG_INT_MASK_IFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
40750 #define RPB_REG_INT_MASK_PFIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
40752 #define RPB_REG_INT_MASK_DB_BUF_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
40754 #define RPB_REG_INT_MASK_TH_EXEC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
40756 #define RPB_REG_INT_MASK_TQ_ERROR_WR (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
40758 #define RPB_REG_INT_MASK_TQ_ERROR_RD_TH (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
40760 #define RPB_REG_INT_MASK_TQ_ERROR_RD_IH (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
40763 #define RPB_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40765 #define RPB_REG_INT_STS_WR_EOP_ERROR (0x1<<1) // EOP check error.
40767 #define RPB_REG_INT_STS_WR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
40769 #define RPB_REG_INT_STS_WR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
40771 #define RPB_REG_INT_STS_WR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
40773 #define RPB_REG_INT_STS_WR_TH_EXEC_ERROR (0x1<<5) //
40775 #define RPB_REG_INT_STS_WR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
40777 #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
40779 #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
40782 #define RPB_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40784 #define RPB_REG_INT_STS_CLR_EOP_ERROR (0x1<<1) // EOP check error.
40786 #define RPB_REG_INT_STS_CLR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
40788 #define RPB_REG_INT_STS_CLR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
40790 #define RPB_REG_INT_STS_CLR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
40792 #define RPB_REG_INT_STS_CLR_TH_EXEC_ERROR (0x1<<5) //
40794 #define RPB_REG_INT_STS_CLR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
40796 #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
40798 #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
40800 #define RPB_REG_PRTY_MASK 0x23c054UL //Access:RW DataWidth:0x1 // Multi Field Register.
40801 #define RPB_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
40804 #define RPB_REG_CONTROL_BYTE_ORDER_SWITCH (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
40806 #define RPB_REG_CONTROL_DB_IGNORE_ERROR (0x1<<1) // Indicates if to ignore the input error indication.
40808 #define RPB_REG_CONTROL_DONT_PASS_ERROR (0x1<<2) // Masks error on output of pb.
40810 #define RPB_REG_CONTROL_EOP_CHECK_DISABLE (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
40812 #define RPB_REG_CONTROL_CRC_COMPARE_DISABLE (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
40814 #define RPB_REG_CONTROL_EN_INPUTS (0x1<<5) // Enable inputs.
40816 #define RPB_REG_CONTROL_DISABLE_PB (0x1<<6) // Debug only: Disable PB.
40820 #define RPB_REG_CONTROL_RELAX_TH (0x1<<11) // Dbug only.
40822 #define RPB_REG_CONTROL_DUMMY_ERR_ALLOW (0x1<<12) // Dummy ingress error allow. When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
40836 #define RPB_REG_DB_EMPTY 0x23c500UL //Access:R DataWidth:0x1 // Data Buffer empty status.
40837 #define RPB_REG_DB_FULL 0x23c504UL //Access:R DataWidth:0x1 // Data Buffer full status.
40838 #define RPB_REG_TQ_EMPTY 0x23c508UL //Access:R DataWidth:0x1 // Task Queue empty status.
40839 #define RPB_REG_TQ_FULL 0x23c50cUL //Access:R DataWidth:0x1 // Task Queue full status.
40840 #define RPB_REG_IFIFO_EMPTY 0x23c510UL //Access:R DataWidth:0x1 // Instruction FIFO empty status.
40841 #define RPB_REG_IFIFO_FULL 0x23c514UL //Access:R DataWidth:0x1 // Instruction FIFO full status.
40842 #define RPB_REG_PFIFO_EMPTY 0x23c518UL //Access:R DataWidth:0x1 // Parameter FIFO empty status.
40843 #define RPB_REG_PFIFO_FULL 0x23c51cUL //Access:R DataWidth:0x1 // Parameter FIFO full status.
40844 #define RPB_REG_TQ_TH_EMPTY 0x23c520UL //Access:R DataWidth:0x1 // Task Queue empty status for task handler.
40864 #define PSWRQ2_REG_RBC_DONE 0x240000UL //Access:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the PSWRQ block to start initializing internal memories.
40865 #define PSWRQ2_REG_CFG_DONE 0x240004UL //Access:R DataWidth:0x1 // PSWRQ internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to rbc_done register.
40866 #define PSWRQ2_REG_RESET_STT 0x240008UL //Access:RW DataWidth:0x1 // MCP writes '1' to this bit to indicate PSWRQ to initialize Steering Tag Table with zeros. PSWRQ clears this bit when the initialization is done. MCP can use this register the same as it uses IGU reset_memories register.
40921 #define PSWRQ2_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40923 #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
40925 #define PSWRQ2_REG_INT_STS_WDFIFO_OVERFLOW (0x1<<2) // Overflow in src write done fifo.
40927 #define PSWRQ2_REG_INT_STS_PHYADDR_FIFO_OF (0x1<<3) // Overflow of phy addr fifo - removed in E4.
40929 #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
40931 #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
40933 #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
40935 #define PSWRQ2_REG_INT_STS_ELT_ADDR (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
40937 #define PSWRQ2_REG_INT_STS_L2P_VF_ERR (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
40939 #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
40941 #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo.
40943 #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo.
40945 #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo.
40947 #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo.
40949 #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed.
40952 #define PSWRQ2_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ADDRESS_ERROR .
40954 #define PSWRQ2_REG_INT_MASK_L2P_FIFO_OVERFLOW (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_FIFO_OVERFLOW .
40956 #define PSWRQ2_REG_INT_MASK_WDFIFO_OVERFLOW (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.WDFIFO_OVERFLOW .
40958 #define PSWRQ2_REG_INT_MASK_PHYADDR_FIFO_OF (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.PHYADDR_FIFO_OF .
40960 #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_1 (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VIOLATION_1 .
40962 #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_2 (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VIOLATION_2 .
40964 #define PSWRQ2_REG_INT_MASK_FREE_LIST_EMPTY (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.FREE_LIST_EMPTY .
40966 #define PSWRQ2_REG_INT_MASK_ELT_ADDR (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ELT_ADDR .
40968 #define PSWRQ2_REG_INT_MASK_L2P_VF_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VF_ERR .
40970 #define PSWRQ2_REG_INT_MASK_CORE_WDONE_OVERFLOW (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.CORE_WDONE_OVERFLOW .
40972 #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_UNDERFLOW (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.TREQ_FIFO_UNDERFLOW .
40974 #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_OVERFLOW (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.TREQ_FIFO_OVERFLOW .
40976 #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_UNDERFLOW (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ICPL_FIFO_UNDERFLOW .
40978 #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_OVERFLOW (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ICPL_FIFO_OVERFLOW .
40980 #define PSWRQ2_REG_INT_MASK_BACK2BACK_ATC_RESPONSE (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.BACK2BACK_ATC_RESPONSE .
40983 #define PSWRQ2_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
40985 #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
40987 #define PSWRQ2_REG_INT_STS_WR_WDFIFO_OVERFLOW (0x1<<2) // Overflow in src write done fifo.
40989 #define PSWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF (0x1<<3) // Overflow of phy addr fifo - removed in E4.
40991 #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
40993 #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
40995 #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
40997 #define PSWRQ2_REG_INT_STS_WR_ELT_ADDR (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
40999 #define PSWRQ2_REG_INT_STS_WR_L2P_VF_ERR (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
41001 #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
41003 #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo.
41005 #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo.
41007 #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo.
41009 #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo.
41011 #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed.
41014 #define PSWRQ2_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
41016 #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
41018 #define PSWRQ2_REG_INT_STS_CLR_WDFIFO_OVERFLOW (0x1<<2) // Overflow in src write done fifo.
41020 #define PSWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF (0x1<<3) // Overflow of phy addr fifo - removed in E4.
41022 #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
41024 #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
41026 #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
41028 #define PSWRQ2_REG_INT_STS_CLR_ELT_ADDR (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
41030 #define PSWRQ2_REG_INT_STS_CLR_L2P_VF_ERR (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
41032 #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
41034 #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo.
41036 #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo.
41038 #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo.
41040 #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo.
41042 #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed.
41045 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
41047 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
41049 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
41051 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
41053 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
41055 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
41057 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
41059 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
41061 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
41063 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
41065 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
41070 #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table
41072 #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table
41074 #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
41077 #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table
41079 #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table
41081 #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
41084 #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table
41086 #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table
41088 #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1
41094 #define PSWRQ2_REG_DISABLE_INPUTS 0x24040cUL //Access:RW DataWidth:0x1 // When '1'; requests will enter input buffers but wont get out towards the glue.
41182 #define PSWRQ2_REG_QM_PCI_ATTR_QM_RELAXED (0x1<<0) // Relaxed oredering attribute for qm.
41184 #define PSWRQ2_REG_QM_PCI_ATTR_QM_NOSNOOP (0x1<<1) // Nosnoop attribute for qm.
41187 #define PSWRQ2_REG_TM_PCI_ATTR_TM_RELAXED (0x1<<0) // Relaxed oredering attribute for tm.
41189 #define PSWRQ2_REG_TM_PCI_ATTR_TM_NOSNOOP (0x1<<1) // Nosnoop attribute for tm.
41192 #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_RELAXED (0x1<<0) // Relaxed oredering attribute for src.
41194 #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_NOSNOOP (0x1<<1) // Nosnoop attribute for src.
41197 #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_RELAXED (0x1<<0) // Relaxed oredering attribute for cdu. Removed in E4B0, PXP request flag is used.
41199 #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_NOSNOOP (0x1<<1) // Nosnoop attribute for cdu. Removed in E4B0, PXP request flag is used.
41202 #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_RELAXED (0x1<<0) // Relaxed oredering attribute for dbg.
41204 #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_NOSNOOP (0x1<<1) // Nosnoop attribute for dbg.
41207 #define PSWRQ2_REG_HC_PCI_ATTR_HC_RELAXED (0x1<<0) // Relaxed oredering attribute for hc.
41209 #define PSWRQ2_REG_HC_PCI_ATTR_HC_NOSNOOP (0x1<<1) // Nosnoop attribute for hc.
41212 #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_RELAXED (0x1<<0) // Relaxed oredering attribute for dmae.
41214 #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_NOSNOOP (0x1<<1) // Nosnoop attribute for dmae.
41486 #define PSWRQ2_REG_L2P_MODE 0x24072cUL //Access:RW DataWidth:0x1 // Will determine how the logical address is calculated; 0: as in E1; 1:with new algorithm.
41487 #define PSWRQ2_REG_DRAM_ALIGN_SEL 0x240730UL //Access:RW DataWidth:0x1 // When set the new alignment method (E2) will be applied; when reset the original alignment method (E1 E1H) will be applied.
41538 #define PSWRQ2_REG_ATC_GLOBAL_ENABLE 0x2407fcUL //Access:RW DataWidth:0x1 // Global ATC enable bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be the same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
41548 #define PSWRQ2_REG_ASSERT_IF_ILT_FAIL 0x240824UL //Access:RW DataWidth:0x1 // When set - assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail due to overflow on vah_plus_1st signal (Cont00041628). If reset - interrupt will not assert.
41550 #define PSWRQ2_REG_HOQ_RAM_RD_EN 0x24082cUL //Access:RW DataWidth:0x1 // FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is disabled (i.e. rq_hoq_ram_rd_req will not have any affect).
41551 #define PSWRQ2_REG_HOQ_RAM_RD_STATUS 0x240830UL //Access:R DataWidth:0x1 // FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed).
41570 #define PSWRQ2_REG_SR_CNT_WINDOW_MODE 0x24087cUL //Access:RW DataWidth:0x1 // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by the user through GRC. 1 - configured window: counting occurs according to configured window size.
41573 #define PSWRQ2_REG_SR_CNT_MANUAL_CMD 0x240888UL //Access:W DataWidth:0x1 // Write Only register. The manual window command sent by the user. Valid when working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start counting.
41574 #define PSWRQ2_REG_SR_CNT_RST 0x24088cUL //Access:W DataWidth:0x1 // Write Only register. RBC write command to this reg (any value) will reset the SR counters & the global window counter. In addition it'll move the Sr_cnt_status to idle state.
41575 #define PSWRQ2_REG_SR_CNT_START_MODE 0x240890UL //Access:RW DataWidth:0x1 // Determines the trigger for start counting (for both SR counters & global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start counting upon first PBF/USDM-DP SR that is sent to the PGLUE.
41576 #define PSWRQ2_REG_SR_CNT_ENABLE 0x240894UL //Access:RW DataWidth:0x1 // Enables the SR counting mechanism.
41595 #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_RELAXED (0x1<<0) // Relaxed oredering attribute for ptu.
41597 #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP (0x1<<1) // Nosnoop attribute for ptu.
41601 #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_RELAXED (0x1<<0) // Relaxed oredering attribute for m2p.
41603 #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_NOSNOOP (0x1<<1) // Nosnoop attribute for m2p.
41606 #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_RELAXED (0x1<<0) // Relaxed oredering attribute for muld.
41608 #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP (0x1<<1) // Nosnoop attribute for muld.
41612 #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_RELAXED (0x1<<0) // Relaxed oredering attribute for xyld.
41614 #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP (0x1<<1) // Nosnoop attribute for xyld.
41621 #define PSWRQ2_REG_RMM_ENABLE 0x240908UL //Access:RW DataWidth:0x1 // Debug only. Writing this register from 0 to 1 enables the roundtrip measurement mechanism and resets the registers latest_rtt ,max_hold_rtt, min_hold_rtt, num_of_measurements.
41633 #define PSWRQ2_REG_L2P_ERR_DETAILS_CLR 0x240938UL //Access:W DataWidth:0x1 // Writing to this register clears rq_l2p_err registers and enables logging new error details.
41797 #define PSWRQ2_REG_L2P_CLOSE_GATE_STS 0x240bc8UL //Access:RW DataWidth:0x1 // L2P error close the gate status register.
41798 #define PSWRQ2_REG_MISC_CLOSE_GATE_STS 0x240bccUL //Access:R DataWidth:0x1 // MISC close the gate status register. 1 indicates the gates are closed.
41799 #define PSWRQ2_REG_MISC_STALL_MEM_STS 0x240bd0UL //Access:R DataWidth:0x1 // MISC stall mem status register. 1 indicates stall mem is active.
41800 #define PSWRQ2_REG_GARB_STRICT_PRIORITY_FOR_READS 0x240bd4UL //Access:RW DataWidth:0x1 // GARB config: 1 indicates read SRs have strict priority over write SRs in RW arbiter.
41801 #define PSWRQ2_REG_GARB_NEGATIVE_BWC_MODE 0x240bd8UL //Access:RW DataWidth:0x1 // GARB config: 1 indicates BWCs can become negative. Clients with negative BWCs are not chosen. Default value: 1.
41802 #define PSWRQ2_REG_GARB_GNT_ABOVE_LIMIT_ONLY_MODE 0x240bdcUL //Access:RW DataWidth:0x1 // GARB config: 1 indicates that only clients with BWC greater or equal to Li are chosen. 0 indicates that clients with BWC greater or equal to 0 can be chosen if no BWC is greater or equal to Li. Default value: 0. This is a chicken bit in case there are problems/bugs when choosing clients with BWC less than Li.
41821 #define PSWRQ2_REG_CREDIT_WR_STS 0x240c28UL //Access:R DataWidth:0x1 // The status of the PSWRQ-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for wr SR-s (i.e. more write SR-s can be sent to the PGLUE).
41822 #define PSWRQ2_REG_CREDIT_RD_STS 0x240c2cUL //Access:R DataWidth:0x1 // The status of the PSWRQ-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for rd SR-s (i.e. more read SR-s can be sent to the PGLUE).
41831 #define PSWRQ2_REG_L2P_VALIDATE_VFID 0x240c50UL //Access:RW DataWidth:0x1 // Enables VFID validate check
41847 #define PSWRQ_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
41849 #define PSWRQ_REG_INT_STS_PBF_FIFO_OVERFLOW (0x1<<1) // Overflow in pbf request input fifo.
41851 #define PSWRQ_REG_INT_STS_SRC_FIFO_OVERFLOW (0x1<<2) // Overflow in src request input fifo.
41853 #define PSWRQ_REG_INT_STS_QM_FIFO_OVERFLOW (0x1<<3) // Overflow in qm request input fifo.
41855 #define PSWRQ_REG_INT_STS_TM_FIFO_OVERFLOW (0x1<<4) // Overflow in tm request fifo.
41857 #define PSWRQ_REG_INT_STS_USDM_FIFO_OVERFLOW (0x1<<5) // Overflow in usdm request input fifo.
41859 #define PSWRQ_REG_INT_STS_M2P_FIFO_OVERFLOW (0x1<<6) // Overflow in m2p request input fifo.
41861 #define PSWRQ_REG_INT_STS_XSDM_FIFO_OVERFLOW (0x1<<7) // Overflow in xsdm request input fifo.
41863 #define PSWRQ_REG_INT_STS_TSDM_FIFO_OVERFLOW (0x1<<8) // Overflow in tsdm request input fifo.
41865 #define PSWRQ_REG_INT_STS_PTU_FIFO_OVERFLOW (0x1<<9) // Overflow in ptu request input fifo.
41867 #define PSWRQ_REG_INT_STS_CDUWR_FIFO_OVERFLOW (0x1<<10) // Overflow in cduwr request input fifo.
41869 #define PSWRQ_REG_INT_STS_CDURD_FIFO_OVERFLOW (0x1<<11) // Overflow in cdurd request input fifo.
41871 #define PSWRQ_REG_INT_STS_DMAE_FIFO_OVERFLOW (0x1<<12) // Overflow in dmae request input fifo.
41873 #define PSWRQ_REG_INT_STS_HC_FIFO_OVERFLOW (0x1<<13) // Overflow in hc request input fifo.
41875 #define PSWRQ_REG_INT_STS_DBG_FIFO_OVERFLOW (0x1<<14) // Overflow in dbg request input fifo.
41877 #define PSWRQ_REG_INT_STS_MSDM_FIFO_OVERFLOW (0x1<<15) // Overflow in msdm request input fifo.
41879 #define PSWRQ_REG_INT_STS_YSDM_FIFO_OVERFLOW (0x1<<16) // Overflow in ysdm request input fifo.
41881 #define PSWRQ_REG_INT_STS_PSDM_FIFO_OVERFLOW (0x1<<17) // Overflow in psdm request input fifo.
41883 #define PSWRQ_REG_INT_STS_PRM_FIFO_OVERFLOW (0x1<<18) // Overflow in prm request input fifo.
41885 #define PSWRQ_REG_INT_STS_MULD_FIFO_OVERFLOW (0x1<<19) // Overflow in muld request input fifo.
41887 #define PSWRQ_REG_INT_STS_XYLD_FIFO_OVERFLOW (0x1<<20) // Overflow in muld request input fifo.
41889 #define PSWRQ_REG_INT_STS_TGFS_FIFO_OVERFLOW (0x1<<21) // Overflow in tgfs request input fifo.
41891 #define PSWRQ_REG_INT_STS_RGFS_FIFO_OVERFLOW (0x1<<22) // Overflow in rgfs request input fifo.
41894 #define PSWRQ_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.ADDRESS_ERROR .
41896 #define PSWRQ_REG_INT_MASK_PBF_FIFO_OVERFLOW (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PBF_FIFO_OVERFLOW .
41898 #define PSWRQ_REG_INT_MASK_SRC_FIFO_OVERFLOW (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.SRC_FIFO_OVERFLOW .
41900 #define PSWRQ_REG_INT_MASK_QM_FIFO_OVERFLOW (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.QM_FIFO_OVERFLOW .
41902 #define PSWRQ_REG_INT_MASK_TM_FIFO_OVERFLOW (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TM_FIFO_OVERFLOW .
41904 #define PSWRQ_REG_INT_MASK_USDM_FIFO_OVERFLOW (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.USDM_FIFO_OVERFLOW .
41906 #define PSWRQ_REG_INT_MASK_M2P_FIFO_OVERFLOW (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.M2P_FIFO_OVERFLOW .
41908 #define PSWRQ_REG_INT_MASK_XSDM_FIFO_OVERFLOW (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.XSDM_FIFO_OVERFLOW .
41910 #define PSWRQ_REG_INT_MASK_TSDM_FIFO_OVERFLOW (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TSDM_FIFO_OVERFLOW .
41912 #define PSWRQ_REG_INT_MASK_PTU_FIFO_OVERFLOW (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PTU_FIFO_OVERFLOW .
41914 #define PSWRQ_REG_INT_MASK_CDUWR_FIFO_OVERFLOW (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.CDUWR_FIFO_OVERFLOW .
41916 #define PSWRQ_REG_INT_MASK_CDURD_FIFO_OVERFLOW (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.CDURD_FIFO_OVERFLOW .
41918 #define PSWRQ_REG_INT_MASK_DMAE_FIFO_OVERFLOW (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.DMAE_FIFO_OVERFLOW .
41920 #define PSWRQ_REG_INT_MASK_HC_FIFO_OVERFLOW (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.HC_FIFO_OVERFLOW .
41922 #define PSWRQ_REG_INT_MASK_DBG_FIFO_OVERFLOW (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.DBG_FIFO_OVERFLOW .
41924 #define PSWRQ_REG_INT_MASK_MSDM_FIFO_OVERFLOW (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.MSDM_FIFO_OVERFLOW .
41926 #define PSWRQ_REG_INT_MASK_YSDM_FIFO_OVERFLOW (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.YSDM_FIFO_OVERFLOW .
41928 #define PSWRQ_REG_INT_MASK_PSDM_FIFO_OVERFLOW (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PSDM_FIFO_OVERFLOW .
41930 #define PSWRQ_REG_INT_MASK_PRM_FIFO_OVERFLOW (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PRM_FIFO_OVERFLOW .
41932 #define PSWRQ_REG_INT_MASK_MULD_FIFO_OVERFLOW (0x1<<19) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.MULD_FIFO_OVERFLOW .
41934 #define PSWRQ_REG_INT_MASK_XYLD_FIFO_OVERFLOW (0x1<<20) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.XYLD_FIFO_OVERFLOW .
41936 #define PSWRQ_REG_INT_MASK_TGFS_FIFO_OVERFLOW (0x1<<21) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TGFS_FIFO_OVERFLOW .
41938 #define PSWRQ_REG_INT_MASK_RGFS_FIFO_OVERFLOW (0x1<<22) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.RGFS_FIFO_OVERFLOW .
41941 #define PSWRQ_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
41943 #define PSWRQ_REG_INT_STS_WR_PBF_FIFO_OVERFLOW (0x1<<1) // Overflow in pbf request input fifo.
41945 #define PSWRQ_REG_INT_STS_WR_SRC_FIFO_OVERFLOW (0x1<<2) // Overflow in src request input fifo.
41947 #define PSWRQ_REG_INT_STS_WR_QM_FIFO_OVERFLOW (0x1<<3) // Overflow in qm request input fifo.
41949 #define PSWRQ_REG_INT_STS_WR_TM_FIFO_OVERFLOW (0x1<<4) // Overflow in tm request fifo.
41951 #define PSWRQ_REG_INT_STS_WR_USDM_FIFO_OVERFLOW (0x1<<5) // Overflow in usdm request input fifo.
41953 #define PSWRQ_REG_INT_STS_WR_M2P_FIFO_OVERFLOW (0x1<<6) // Overflow in m2p request input fifo.
41955 #define PSWRQ_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW (0x1<<7) // Overflow in xsdm request input fifo.
41957 #define PSWRQ_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW (0x1<<8) // Overflow in tsdm request input fifo.
41959 #define PSWRQ_REG_INT_STS_WR_PTU_FIFO_OVERFLOW (0x1<<9) // Overflow in ptu request input fifo.
41961 #define PSWRQ_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW (0x1<<10) // Overflow in cduwr request input fifo.
41963 #define PSWRQ_REG_INT_STS_WR_CDURD_FIFO_OVERFLOW (0x1<<11) // Overflow in cdurd request input fifo.
41965 #define PSWRQ_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW (0x1<<12) // Overflow in dmae request input fifo.
41967 #define PSWRQ_REG_INT_STS_WR_HC_FIFO_OVERFLOW (0x1<<13) // Overflow in hc request input fifo.
41969 #define PSWRQ_REG_INT_STS_WR_DBG_FIFO_OVERFLOW (0x1<<14) // Overflow in dbg request input fifo.
41971 #define PSWRQ_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW (0x1<<15) // Overflow in msdm request input fifo.
41973 #define PSWRQ_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW (0x1<<16) // Overflow in ysdm request input fifo.
41975 #define PSWRQ_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW (0x1<<17) // Overflow in psdm request input fifo.
41977 #define PSWRQ_REG_INT_STS_WR_PRM_FIFO_OVERFLOW (0x1<<18) // Overflow in prm request input fifo.
41979 #define PSWRQ_REG_INT_STS_WR_MULD_FIFO_OVERFLOW (0x1<<19) // Overflow in muld request input fifo.
41981 #define PSWRQ_REG_INT_STS_WR_XYLD_FIFO_OVERFLOW (0x1<<20) // Overflow in muld request input fifo.
41983 #define PSWRQ_REG_INT_STS_WR_TGFS_FIFO_OVERFLOW (0x1<<21) // Overflow in tgfs request input fifo.
41985 #define PSWRQ_REG_INT_STS_WR_RGFS_FIFO_OVERFLOW (0x1<<22) // Overflow in rgfs request input fifo.
41988 #define PSWRQ_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
41990 #define PSWRQ_REG_INT_STS_CLR_PBF_FIFO_OVERFLOW (0x1<<1) // Overflow in pbf request input fifo.
41992 #define PSWRQ_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW (0x1<<2) // Overflow in src request input fifo.
41994 #define PSWRQ_REG_INT_STS_CLR_QM_FIFO_OVERFLOW (0x1<<3) // Overflow in qm request input fifo.
41996 #define PSWRQ_REG_INT_STS_CLR_TM_FIFO_OVERFLOW (0x1<<4) // Overflow in tm request fifo.
41998 #define PSWRQ_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW (0x1<<5) // Overflow in usdm request input fifo.
42000 #define PSWRQ_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW (0x1<<6) // Overflow in m2p request input fifo.
42002 #define PSWRQ_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW (0x1<<7) // Overflow in xsdm request input fifo.
42004 #define PSWRQ_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW (0x1<<8) // Overflow in tsdm request input fifo.
42006 #define PSWRQ_REG_INT_STS_CLR_PTU_FIFO_OVERFLOW (0x1<<9) // Overflow in ptu request input fifo.
42008 #define PSWRQ_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW (0x1<<10) // Overflow in cduwr request input fifo.
42010 #define PSWRQ_REG_INT_STS_CLR_CDURD_FIFO_OVERFLOW (0x1<<11) // Overflow in cdurd request input fifo.
42012 #define PSWRQ_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW (0x1<<12) // Overflow in dmae request input fifo.
42014 #define PSWRQ_REG_INT_STS_CLR_HC_FIFO_OVERFLOW (0x1<<13) // Overflow in hc request input fifo.
42016 #define PSWRQ_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW (0x1<<14) // Overflow in dbg request input fifo.
42018 #define PSWRQ_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW (0x1<<15) // Overflow in msdm request input fifo.
42020 #define PSWRQ_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW (0x1<<16) // Overflow in ysdm request input fifo.
42022 #define PSWRQ_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW (0x1<<17) // Overflow in psdm request input fifo.
42024 #define PSWRQ_REG_INT_STS_CLR_PRM_FIFO_OVERFLOW (0x1<<18) // Overflow in prm request input fifo.
42026 #define PSWRQ_REG_INT_STS_CLR_MULD_FIFO_OVERFLOW (0x1<<19) // Overflow in muld request input fifo.
42028 #define PSWRQ_REG_INT_STS_CLR_XYLD_FIFO_OVERFLOW (0x1<<20) // Overflow in muld request input fifo.
42030 #define PSWRQ_REG_INT_STS_CLR_TGFS_FIFO_OVERFLOW (0x1<<21) // Overflow in tgfs request input fifo.
42032 #define PSWRQ_REG_INT_STS_CLR_RGFS_FIFO_OVERFLOW (0x1<<22) // Overflow in rgfs request input fifo.
42034 #define PSWRQ_REG_PRTY_MASK 0x280194UL //Access:RW DataWidth:0x1 // Multi Field Register.
42035 #define PSWRQ_REG_PRTY_MASK_PXP_BUSIP_PARITY (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ_REG_PRTY_STS.PXP_BUSIP_PARITY .
42068 #define PSWWR_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42070 #define PSWWR_REG_INT_STS_SRC_FIFO_OVERFLOW (0x1<<1) // Overflow in src input fifo.
42072 #define PSWWR_REG_INT_STS_QM_FIFO_OVERFLOW (0x1<<2) // Overflow in qm input fifo.
42074 #define PSWWR_REG_INT_STS_TM_FIFO_OVERFLOW (0x1<<3) // Overflow in tm fifo.
42076 #define PSWWR_REG_INT_STS_USDM_FIFO_OVERFLOW (0x1<<4) // Overflow in usdm input fifo.
42078 #define PSWWR_REG_INT_STS_USDMDP_FIFO_OVERFLOW (0x1<<5) // Overflow in usdmdp input fifo.
42080 #define PSWWR_REG_INT_STS_XSDM_FIFO_OVERFLOW (0x1<<6) // Overflow in xsdm input fifo.
42082 #define PSWWR_REG_INT_STS_TSDM_FIFO_OVERFLOW (0x1<<7) // Overflow in tsdm input fifo.
42084 #define PSWWR_REG_INT_STS_CDUWR_FIFO_OVERFLOW (0x1<<8) // Overflow in cduwr input fifo.
42086 #define PSWWR_REG_INT_STS_DBG_FIFO_OVERFLOW (0x1<<9) // Overflow in dbg input fifo.
42088 #define PSWWR_REG_INT_STS_DMAE_FIFO_OVERFLOW (0x1<<10) // Overflow in dmae input fifo.
42090 #define PSWWR_REG_INT_STS_HC_FIFO_OVERFLOW (0x1<<11) // Overflow in hc input fifo.
42092 #define PSWWR_REG_INT_STS_MSDM_FIFO_OVERFLOW (0x1<<12) // Overflow in msdm write input fifo.
42094 #define PSWWR_REG_INT_STS_YSDM_FIFO_OVERFLOW (0x1<<13) // Overflow in ysdm write input fifo.
42096 #define PSWWR_REG_INT_STS_PSDM_FIFO_OVERFLOW (0x1<<14) // Overflow in psdm write input fifo.
42098 #define PSWWR_REG_INT_STS_M2P_FIFO_OVERFLOW (0x1<<15) // Overflow in M2P input fifo.
42100 #define PSWWR_REG_INT_STS_PRM_SEC_FIFO_OVERFLOW (0x1<<16) // Overflow in PRM Secondary input fifo.
42102 #define PSWWR_REG_INT_STS_RGFS_FIFO_OVERFLOW (0x1<<17) // Overflow in RGFS input fifo.
42104 #define PSWWR_REG_INT_STS_TGFS_FIFO_OVERFLOW (0x1<<18) // Overflow in TGFS input fifo.
42107 #define PSWWR_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.ADDRESS_ERROR .
42109 #define PSWWR_REG_INT_MASK_SRC_FIFO_OVERFLOW (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.SRC_FIFO_OVERFLOW .
42111 #define PSWWR_REG_INT_MASK_QM_FIFO_OVERFLOW (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.QM_FIFO_OVERFLOW .
42113 #define PSWWR_REG_INT_MASK_TM_FIFO_OVERFLOW (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TM_FIFO_OVERFLOW .
42115 #define PSWWR_REG_INT_MASK_USDM_FIFO_OVERFLOW (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.USDM_FIFO_OVERFLOW .
42117 #define PSWWR_REG_INT_MASK_USDMDP_FIFO_OVERFLOW (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.USDMDP_FIFO_OVERFLOW .
42119 #define PSWWR_REG_INT_MASK_XSDM_FIFO_OVERFLOW (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.XSDM_FIFO_OVERFLOW .
42121 #define PSWWR_REG_INT_MASK_TSDM_FIFO_OVERFLOW (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TSDM_FIFO_OVERFLOW .
42123 #define PSWWR_REG_INT_MASK_CDUWR_FIFO_OVERFLOW (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.CDUWR_FIFO_OVERFLOW .
42125 #define PSWWR_REG_INT_MASK_DBG_FIFO_OVERFLOW (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.DBG_FIFO_OVERFLOW .
42127 #define PSWWR_REG_INT_MASK_DMAE_FIFO_OVERFLOW (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.DMAE_FIFO_OVERFLOW .
42129 #define PSWWR_REG_INT_MASK_HC_FIFO_OVERFLOW (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.HC_FIFO_OVERFLOW .
42131 #define PSWWR_REG_INT_MASK_MSDM_FIFO_OVERFLOW (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.MSDM_FIFO_OVERFLOW .
42133 #define PSWWR_REG_INT_MASK_YSDM_FIFO_OVERFLOW (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.YSDM_FIFO_OVERFLOW .
42135 #define PSWWR_REG_INT_MASK_PSDM_FIFO_OVERFLOW (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.PSDM_FIFO_OVERFLOW .
42137 #define PSWWR_REG_INT_MASK_M2P_FIFO_OVERFLOW (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.M2P_FIFO_OVERFLOW .
42139 #define PSWWR_REG_INT_MASK_PRM_SEC_FIFO_OVERFLOW (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.PRM_SEC_FIFO_OVERFLOW .
42141 #define PSWWR_REG_INT_MASK_RGFS_FIFO_OVERFLOW (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.RGFS_FIFO_OVERFLOW .
42143 #define PSWWR_REG_INT_MASK_TGFS_FIFO_OVERFLOW (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TGFS_FIFO_OVERFLOW .
42146 #define PSWWR_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42148 #define PSWWR_REG_INT_STS_WR_SRC_FIFO_OVERFLOW (0x1<<1) // Overflow in src input fifo.
42150 #define PSWWR_REG_INT_STS_WR_QM_FIFO_OVERFLOW (0x1<<2) // Overflow in qm input fifo.
42152 #define PSWWR_REG_INT_STS_WR_TM_FIFO_OVERFLOW (0x1<<3) // Overflow in tm fifo.
42154 #define PSWWR_REG_INT_STS_WR_USDM_FIFO_OVERFLOW (0x1<<4) // Overflow in usdm input fifo.
42156 #define PSWWR_REG_INT_STS_WR_USDMDP_FIFO_OVERFLOW (0x1<<5) // Overflow in usdmdp input fifo.
42158 #define PSWWR_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW (0x1<<6) // Overflow in xsdm input fifo.
42160 #define PSWWR_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW (0x1<<7) // Overflow in tsdm input fifo.
42162 #define PSWWR_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW (0x1<<8) // Overflow in cduwr input fifo.
42164 #define PSWWR_REG_INT_STS_WR_DBG_FIFO_OVERFLOW (0x1<<9) // Overflow in dbg input fifo.
42166 #define PSWWR_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW (0x1<<10) // Overflow in dmae input fifo.
42168 #define PSWWR_REG_INT_STS_WR_HC_FIFO_OVERFLOW (0x1<<11) // Overflow in hc input fifo.
42170 #define PSWWR_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW (0x1<<12) // Overflow in msdm write input fifo.
42172 #define PSWWR_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW (0x1<<13) // Overflow in ysdm write input fifo.
42174 #define PSWWR_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW (0x1<<14) // Overflow in psdm write input fifo.
42176 #define PSWWR_REG_INT_STS_WR_M2P_FIFO_OVERFLOW (0x1<<15) // Overflow in M2P input fifo.
42178 #define PSWWR_REG_INT_STS_WR_PRM_SEC_FIFO_OVERFLOW (0x1<<16) // Overflow in PRM Secondary input fifo.
42180 #define PSWWR_REG_INT_STS_WR_RGFS_FIFO_OVERFLOW (0x1<<17) // Overflow in RGFS input fifo.
42182 #define PSWWR_REG_INT_STS_WR_TGFS_FIFO_OVERFLOW (0x1<<18) // Overflow in TGFS input fifo.
42185 #define PSWWR_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42187 #define PSWWR_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW (0x1<<1) // Overflow in src input fifo.
42189 #define PSWWR_REG_INT_STS_CLR_QM_FIFO_OVERFLOW (0x1<<2) // Overflow in qm input fifo.
42191 #define PSWWR_REG_INT_STS_CLR_TM_FIFO_OVERFLOW (0x1<<3) // Overflow in tm fifo.
42193 #define PSWWR_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW (0x1<<4) // Overflow in usdm input fifo.
42195 #define PSWWR_REG_INT_STS_CLR_USDMDP_FIFO_OVERFLOW (0x1<<5) // Overflow in usdmdp input fifo.
42197 #define PSWWR_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW (0x1<<6) // Overflow in xsdm input fifo.
42199 #define PSWWR_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW (0x1<<7) // Overflow in tsdm input fifo.
42201 #define PSWWR_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW (0x1<<8) // Overflow in cduwr input fifo.
42203 #define PSWWR_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW (0x1<<9) // Overflow in dbg input fifo.
42205 #define PSWWR_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW (0x1<<10) // Overflow in dmae input fifo.
42207 #define PSWWR_REG_INT_STS_CLR_HC_FIFO_OVERFLOW (0x1<<11) // Overflow in hc input fifo.
42209 #define PSWWR_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW (0x1<<12) // Overflow in msdm write input fifo.
42211 #define PSWWR_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW (0x1<<13) // Overflow in ysdm write input fifo.
42213 #define PSWWR_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW (0x1<<14) // Overflow in psdm write input fifo.
42215 #define PSWWR_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW (0x1<<15) // Overflow in M2P input fifo.
42217 #define PSWWR_REG_INT_STS_CLR_PRM_SEC_FIFO_OVERFLOW (0x1<<16) // Overflow in PRM Secondary input fifo.
42219 #define PSWWR_REG_INT_STS_CLR_RGFS_FIFO_OVERFLOW (0x1<<17) // Overflow in RGFS input fifo.
42221 #define PSWWR_REG_INT_STS_CLR_TGFS_FIFO_OVERFLOW (0x1<<18) // Overflow in TGFS input fifo.
42223 #define PSWWR_REG_PRTY_MASK 0x29a194UL //Access:RW DataWidth:0x1 // Multi Field Register.
42224 #define PSWWR_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR_REG_PRTY_STS.DATAPATH_REGISTERS .
42229 #define PSWWR2_REG_PGLUE_EOP_ERR_DETAILS_CLR 0x29b04cUL //Access:W DataWidth:0x1 // Writing to this register clears pglue_eop_err_details and enables logging new error details.
42237 #define PSWWR2_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42239 #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
42241 #define PSWWR2_REG_INT_STS_PGLUE_LSR_ERROR (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
42243 #define PSWWR2_REG_INT_STS_TM_UNDERFLOW (0x1<<3) // Underflow in the tm fifo.
42245 #define PSWWR2_REG_INT_STS_QM_UNDERFLOW (0x1<<4) // Underflow in the qm fifo.
42247 #define PSWWR2_REG_INT_STS_SRC_UNDERFLOW (0x1<<5) // Underflow in the src fifo.
42249 #define PSWWR2_REG_INT_STS_USDM_UNDERFLOW (0x1<<6) // Underflow in the usdm fifo.
42251 #define PSWWR2_REG_INT_STS_TSDM_UNDERFLOW (0x1<<7) // Underflow in the tsdm fifo.
42253 #define PSWWR2_REG_INT_STS_XSDM_UNDERFLOW (0x1<<8) // Underflow in the xsdm fifo.
42255 #define PSWWR2_REG_INT_STS_USDMDP_UNDERFLOW (0x1<<9) // Underflow in the usdmdp fifo.
42257 #define PSWWR2_REG_INT_STS_CDU_UNDERFLOW (0x1<<10) // Underflow in the cdu fifo.
42259 #define PSWWR2_REG_INT_STS_DBG_UNDERFLOW (0x1<<11) // Underflow in the dbg fifo.
42261 #define PSWWR2_REG_INT_STS_DMAE_UNDERFLOW (0x1<<12) // Underflow in the dmae fifo.
42263 #define PSWWR2_REG_INT_STS_HC_UNDERFLOW (0x1<<13) // Underflow in the hc fifo.
42265 #define PSWWR2_REG_INT_STS_MSDM_UNDERFLOW (0x1<<14) // Underflow in the msdm fifo.
42267 #define PSWWR2_REG_INT_STS_YSDM_UNDERFLOW (0x1<<15) // Underflow in the ysdm fifo.
42269 #define PSWWR2_REG_INT_STS_PSDM_UNDERFLOW (0x1<<16) // Underflow in the psdm fifo.
42271 #define PSWWR2_REG_INT_STS_M2P_UNDERFLOW (0x1<<17) // Underflow in the M2P fifo.
42273 #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR_IN_LINE (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
42275 #define PSWWR2_REG_INT_STS_PRM_SEC_UNDERFLOW (0x1<<19) // Underflow in the PRM Secondary fifo.
42277 #define PSWWR2_REG_INT_STS_RGFS_UNDERFLOW (0x1<<20) // Underflow in the RGFS fifo.
42279 #define PSWWR2_REG_INT_STS_TGFS_UNDERFLOW (0x1<<21) // Underflow in the TGFS fifo.
42282 #define PSWWR2_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.ADDRESS_ERROR .
42284 #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_EOP_ERROR .
42286 #define PSWWR2_REG_INT_MASK_PGLUE_LSR_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_LSR_ERROR .
42288 #define PSWWR2_REG_INT_MASK_TM_UNDERFLOW (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TM_UNDERFLOW .
42290 #define PSWWR2_REG_INT_MASK_QM_UNDERFLOW (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.QM_UNDERFLOW .
42292 #define PSWWR2_REG_INT_MASK_SRC_UNDERFLOW (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.SRC_UNDERFLOW .
42294 #define PSWWR2_REG_INT_MASK_USDM_UNDERFLOW (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.USDM_UNDERFLOW .
42296 #define PSWWR2_REG_INT_MASK_TSDM_UNDERFLOW (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TSDM_UNDERFLOW .
42298 #define PSWWR2_REG_INT_MASK_XSDM_UNDERFLOW (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.XSDM_UNDERFLOW .
42300 #define PSWWR2_REG_INT_MASK_USDMDP_UNDERFLOW (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.USDMDP_UNDERFLOW .
42302 #define PSWWR2_REG_INT_MASK_CDU_UNDERFLOW (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.CDU_UNDERFLOW .
42304 #define PSWWR2_REG_INT_MASK_DBG_UNDERFLOW (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.DBG_UNDERFLOW .
42306 #define PSWWR2_REG_INT_MASK_DMAE_UNDERFLOW (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.DMAE_UNDERFLOW .
42308 #define PSWWR2_REG_INT_MASK_HC_UNDERFLOW (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.HC_UNDERFLOW .
42310 #define PSWWR2_REG_INT_MASK_MSDM_UNDERFLOW (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.MSDM_UNDERFLOW .
42312 #define PSWWR2_REG_INT_MASK_YSDM_UNDERFLOW (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.YSDM_UNDERFLOW .
42314 #define PSWWR2_REG_INT_MASK_PSDM_UNDERFLOW (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PSDM_UNDERFLOW .
42316 #define PSWWR2_REG_INT_MASK_M2P_UNDERFLOW (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.M2P_UNDERFLOW .
42318 #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_IN_LINE (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_EOP_ERROR_IN_LINE .
42320 #define PSWWR2_REG_INT_MASK_PRM_SEC_UNDERFLOW (0x1<<19) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PRM_SEC_UNDERFLOW .
42322 #define PSWWR2_REG_INT_MASK_RGFS_UNDERFLOW (0x1<<20) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.RGFS_UNDERFLOW .
42324 #define PSWWR2_REG_INT_MASK_TGFS_UNDERFLOW (0x1<<21) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TGFS_UNDERFLOW .
42327 #define PSWWR2_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42329 #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
42331 #define PSWWR2_REG_INT_STS_WR_PGLUE_LSR_ERROR (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
42333 #define PSWWR2_REG_INT_STS_WR_TM_UNDERFLOW (0x1<<3) // Underflow in the tm fifo.
42335 #define PSWWR2_REG_INT_STS_WR_QM_UNDERFLOW (0x1<<4) // Underflow in the qm fifo.
42337 #define PSWWR2_REG_INT_STS_WR_SRC_UNDERFLOW (0x1<<5) // Underflow in the src fifo.
42339 #define PSWWR2_REG_INT_STS_WR_USDM_UNDERFLOW (0x1<<6) // Underflow in the usdm fifo.
42341 #define PSWWR2_REG_INT_STS_WR_TSDM_UNDERFLOW (0x1<<7) // Underflow in the tsdm fifo.
42343 #define PSWWR2_REG_INT_STS_WR_XSDM_UNDERFLOW (0x1<<8) // Underflow in the xsdm fifo.
42345 #define PSWWR2_REG_INT_STS_WR_USDMDP_UNDERFLOW (0x1<<9) // Underflow in the usdmdp fifo.
42347 #define PSWWR2_REG_INT_STS_WR_CDU_UNDERFLOW (0x1<<10) // Underflow in the cdu fifo.
42349 #define PSWWR2_REG_INT_STS_WR_DBG_UNDERFLOW (0x1<<11) // Underflow in the dbg fifo.
42351 #define PSWWR2_REG_INT_STS_WR_DMAE_UNDERFLOW (0x1<<12) // Underflow in the dmae fifo.
42353 #define PSWWR2_REG_INT_STS_WR_HC_UNDERFLOW (0x1<<13) // Underflow in the hc fifo.
42355 #define PSWWR2_REG_INT_STS_WR_MSDM_UNDERFLOW (0x1<<14) // Underflow in the msdm fifo.
42357 #define PSWWR2_REG_INT_STS_WR_YSDM_UNDERFLOW (0x1<<15) // Underflow in the ysdm fifo.
42359 #define PSWWR2_REG_INT_STS_WR_PSDM_UNDERFLOW (0x1<<16) // Underflow in the psdm fifo.
42361 #define PSWWR2_REG_INT_STS_WR_M2P_UNDERFLOW (0x1<<17) // Underflow in the M2P fifo.
42363 #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_IN_LINE (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
42365 #define PSWWR2_REG_INT_STS_WR_PRM_SEC_UNDERFLOW (0x1<<19) // Underflow in the PRM Secondary fifo.
42367 #define PSWWR2_REG_INT_STS_WR_RGFS_UNDERFLOW (0x1<<20) // Underflow in the RGFS fifo.
42369 #define PSWWR2_REG_INT_STS_WR_TGFS_UNDERFLOW (0x1<<21) // Underflow in the TGFS fifo.
42372 #define PSWWR2_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42374 #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
42376 #define PSWWR2_REG_INT_STS_CLR_PGLUE_LSR_ERROR (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
42378 #define PSWWR2_REG_INT_STS_CLR_TM_UNDERFLOW (0x1<<3) // Underflow in the tm fifo.
42380 #define PSWWR2_REG_INT_STS_CLR_QM_UNDERFLOW (0x1<<4) // Underflow in the qm fifo.
42382 #define PSWWR2_REG_INT_STS_CLR_SRC_UNDERFLOW (0x1<<5) // Underflow in the src fifo.
42384 #define PSWWR2_REG_INT_STS_CLR_USDM_UNDERFLOW (0x1<<6) // Underflow in the usdm fifo.
42386 #define PSWWR2_REG_INT_STS_CLR_TSDM_UNDERFLOW (0x1<<7) // Underflow in the tsdm fifo.
42388 #define PSWWR2_REG_INT_STS_CLR_XSDM_UNDERFLOW (0x1<<8) // Underflow in the xsdm fifo.
42390 #define PSWWR2_REG_INT_STS_CLR_USDMDP_UNDERFLOW (0x1<<9) // Underflow in the usdmdp fifo.
42392 #define PSWWR2_REG_INT_STS_CLR_CDU_UNDERFLOW (0x1<<10) // Underflow in the cdu fifo.
42394 #define PSWWR2_REG_INT_STS_CLR_DBG_UNDERFLOW (0x1<<11) // Underflow in the dbg fifo.
42396 #define PSWWR2_REG_INT_STS_CLR_DMAE_UNDERFLOW (0x1<<12) // Underflow in the dmae fifo.
42398 #define PSWWR2_REG_INT_STS_CLR_HC_UNDERFLOW (0x1<<13) // Underflow in the hc fifo.
42400 #define PSWWR2_REG_INT_STS_CLR_MSDM_UNDERFLOW (0x1<<14) // Underflow in the msdm fifo.
42402 #define PSWWR2_REG_INT_STS_CLR_YSDM_UNDERFLOW (0x1<<15) // Underflow in the ysdm fifo.
42404 #define PSWWR2_REG_INT_STS_CLR_PSDM_UNDERFLOW (0x1<<16) // Underflow in the psdm fifo.
42406 #define PSWWR2_REG_INT_STS_CLR_M2P_UNDERFLOW (0x1<<17) // Underflow in the M2P fifo.
42408 #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_IN_LINE (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
42410 #define PSWWR2_REG_INT_STS_CLR_PRM_SEC_UNDERFLOW (0x1<<19) // Underflow in the PRM Secondary fifo.
42412 #define PSWWR2_REG_INT_STS_CLR_RGFS_UNDERFLOW (0x1<<20) // Underflow in the RGFS fifo.
42414 #define PSWWR2_REG_INT_STS_CLR_TGFS_UNDERFLOW (0x1<<21) // Underflow in the TGFS fifo.
42416 #define PSWWR2_REG_PRTY_MASK 0x29b194UL //Access:RW DataWidth:0x1 // Multi Field Register.
42417 #define PSWWR2_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS.DATAPATH_REGISTERS .
42420 #define PSWWR2_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
42422 #define PSWWR2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
42424 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_0 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_0 .
42426 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_1 .
42428 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_2 .
42430 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_3 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_3 .
42432 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_4 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_4 .
42434 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_5 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_5 .
42436 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_6 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_6 .
42438 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_7 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_7 .
42440 #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_8 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_8 .
42442 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_0 .
42444 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1 (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_1 .
42446 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_2 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_2 .
42448 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_3 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_3 .
42450 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_4 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_4 .
42452 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_5 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_5 .
42454 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_6 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_6 .
42456 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_7 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_7 .
42458 #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_8 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_8 .
42460 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0 (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
42462 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1 (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
42464 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2 (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_2 .
42466 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_3 (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_3 .
42468 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_4 (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_4 .
42470 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_5 (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_5 .
42472 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_6 (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_6 .
42474 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_7 (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_7 .
42476 #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_8 (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_8 .
42478 #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_0 (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_0 .
42480 #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1 (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_1 .
42483 #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_2 (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_2 .
42485 #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_3 (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_3 .
42487 #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_4 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_4 .
42489 #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_5 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_5 .
42491 #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_6 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_6 .
42493 #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_7 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_7 .
42495 #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_8 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_8 .
42497 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_0 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_0 .
42499 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_1 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_1 .
42501 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_2 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_2 .
42503 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_3 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_3 .
42505 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_4 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_4 .
42507 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_5 (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_5 .
42509 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_6 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_6 .
42511 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_7 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_7 .
42513 #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_8 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_8 .
42515 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_0 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_0 .
42517 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_1 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_1 .
42519 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_2 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_2 .
42521 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_3 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_3 .
42523 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_4 (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_4 .
42525 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_5 (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_5 .
42527 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_6 (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_6 .
42529 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_7 (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_7 .
42531 #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_8 (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_8 .
42533 #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_0 (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_0 .
42535 #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_1 (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_1 .
42537 #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_2 (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_2 .
42539 #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_3 (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_3 .
42541 #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_4 (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_4 .
42543 #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_5 (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_5 .
42546 #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_6 (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_6 .
42548 #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_7 (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_7 .
42550 #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_8 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_8 .
42552 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_0 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_0 .
42554 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_1 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_1 .
42556 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_2 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_2 .
42558 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_3 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_3 .
42560 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_4 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_4 .
42562 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_5 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_5 .
42564 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_6 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_6 .
42566 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_7 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_7 .
42568 #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_8 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_8 .
42570 #define PSWWR2_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM012_I_MEM_PRTY .
42572 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_0 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_0 .
42574 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_1 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_1 .
42576 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_2 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_2 .
42578 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_3 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_3 .
42580 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_4 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_4 .
42582 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_5 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_5 .
42584 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_6 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_6 .
42586 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_7 (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_7 .
42588 #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_8 (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_8 .
42590 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_0 (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_0 .
42592 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_1 (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_1 .
42594 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_2 (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_2 .
42596 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_3 (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_3 .
42598 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_4 (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_4 .
42600 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_5 (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_5 .
42602 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_6 (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_6 .
42604 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_7 (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_7 .
42606 #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_8 (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_8 .
42609 #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_0 (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_0 .
42611 #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_1 (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_1 .
42613 #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_2 (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_2 .
42615 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_0 (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_0 .
42617 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_1 (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_1 .
42619 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_2 (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_2 .
42621 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_3 (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_3 .
42623 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_4 (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_4 .
42625 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_5 (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_5 .
42627 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_6 (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_6 .
42629 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_7 (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_7 .
42631 #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_8 (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_8 .
42633 #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_0 (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_0 .
42635 #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_1 (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_1 .
42637 #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_2 (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_2 .
42639 #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_3 (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_3 .
42641 #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_4 (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_4 .
42643 #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_0 (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_0 .
42645 #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_1 (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_1 .
42647 #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_2 (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_2 .
42650 #define PSWWR2_REG_MEM_ECC_ENABLE_0 0x29b244UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm_ififo
42651 #define PSWWR2_REG_MEM_ECC_PARITY_ONLY_0 0x29b248UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm_ififo
42652 #define PSWWR2_REG_MEM_ECC_ERROR_CORRECTED_0 0x29b24cUL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance pswwr.i_prm_fifo.i_ecc in module pswwr_mem_prm_ififo
42667 #define PSWRD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42669 #define PSWRD_REG_INT_STS_POP_ERROR (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
42671 #define PSWRD_REG_INT_STS_POP_PBF_ERROR (0x1<<2) // An error in the PBF FIFO pop interface.
42674 #define PSWRD_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.ADDRESS_ERROR .
42676 #define PSWRD_REG_INT_MASK_POP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.POP_ERROR .
42678 #define PSWRD_REG_INT_MASK_POP_PBF_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.POP_PBF_ERROR .
42681 #define PSWRD_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42683 #define PSWRD_REG_INT_STS_WR_POP_ERROR (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
42685 #define PSWRD_REG_INT_STS_WR_POP_PBF_ERROR (0x1<<2) // An error in the PBF FIFO pop interface.
42688 #define PSWRD_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42690 #define PSWRD_REG_INT_STS_CLR_POP_ERROR (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
42692 #define PSWRD_REG_INT_STS_CLR_POP_PBF_ERROR (0x1<<2) // An error in the PBF FIFO pop interface.
42694 #define PSWRD_REG_PRTY_MASK 0x29c194UL //Access:RW DataWidth:0x1 // Multi Field Register.
42695 #define PSWRD_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD_REG_PRTY_STS.DATAPATH_REGISTERS .
42697 #define PSWRD2_REG_START_INIT 0x29d000UL //Access:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the PSWRD block to start initializing internal memories.
42698 #define PSWRD2_REG_INIT_DONE 0x29d004UL //Access:R DataWidth:0x1 // PSWRD internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to start_init register.
42705 #define PSWRD2_REG_CONF11_OVERRIDE_DATA_WHEN_ERROR (0x1<<16) // 1 indicates to override the data to the client in case of an error and use the error pattern. 0 indicates not to override the data.
42707 #define PSWRD2_REG_CONF11_OVERRIDE_LAST_CYCLE_ONLY (0x1<<17) // Meaningful only when override_data_when_error is 1. 1 indicates to override the data to the client in case of an error only in the last request cycle. 0 indicates to override the data from the time the error indication arrives to delivery sub-block until end of packet. Note that the override may start a few cycles before or after the last data cycle that arrived from PGLUE.
42711 #define PSWRD2_REG_CPL_ERR_DETAILS_CLR 0x29d070UL //Access:W DataWidth:0x1 // Writing to this register clears cpl_err_details and cpl_err_details2 and enables logging new error details.
42713 #define PSWRD2_REG_PBF_IN_SEPARATE_VQ 0x29d078UL //Access:RW DataWidth:0x1 // 1' indicates that the PBF has a separate VQ and uses VQ4. '0' indicates it shares VQ9 with SDM clients. This field should be consistent with PBF_REGISTERS_PCI_VOQ_ID.PCI_VOQ_ID .
42714 #define PSWRD2_REG_PORT_IS_IDLE_0 0x29d07cUL //Access:R DataWidth:0x1 // Debug only: Indication if delivery ports are idle.
42715 #define PSWRD2_REG_PORT_IS_IDLE_1 0x29d080UL //Access:R DataWidth:0x1 // Debug only: Indication if delivery ports are idle.
42723 #define PSWRD2_REG_ALMOST_FULL_0 0x29d0e0UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42724 #define PSWRD2_REG_ALMOST_FULL_1 0x29d0e4UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42725 #define PSWRD2_REG_ALMOST_FULL_2 0x29d0e8UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42726 #define PSWRD2_REG_ALMOST_FULL_3 0x29d0ecUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42727 #define PSWRD2_REG_ALMOST_FULL_4 0x29d0f0UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42728 #define PSWRD2_REG_ALMOST_FULL_5 0x29d0f4UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42729 #define PSWRD2_REG_ALMOST_FULL_6 0x29d0f8UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42730 #define PSWRD2_REG_ALMOST_FULL_7 0x29d0fcUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42731 #define PSWRD2_REG_ALMOST_FULL_8 0x29d100UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42732 #define PSWRD2_REG_ALMOST_FULL_9 0x29d104UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42733 #define PSWRD2_REG_ALMOST_FULL_10 0x29d108UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42734 #define PSWRD2_REG_ALMOST_FULL_11 0x29d10cUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42735 #define PSWRD2_REG_ALMOST_FULL_12 0x29d110UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42736 #define PSWRD2_REG_ALMOST_FULL_13 0x29d114UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42737 #define PSWRD2_REG_ALMOST_FULL_14 0x29d118UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42738 #define PSWRD2_REG_ALMOST_FULL_15 0x29d11cUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).
42754 #define PSWRD2_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42756 #define PSWRD2_REG_INT_STS_SR_FIFO_ERROR (0x1<<1) // An error in the SR free list FIFO.
42758 #define PSWRD2_REG_INT_STS_BLK_FIFO_ERROR (0x1<<2) // An error in the blocks free list FIFO.
42760 #define PSWRD2_REG_INT_STS_PUSH_ERROR (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
42762 #define PSWRD2_REG_INT_STS_PUSH_PBF_ERROR (0x1<<4) // An error in the PBF FIFO push interface.
42765 #define PSWRD2_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.ADDRESS_ERROR .
42767 #define PSWRD2_REG_INT_MASK_SR_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.SR_FIFO_ERROR .
42769 #define PSWRD2_REG_INT_MASK_BLK_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.BLK_FIFO_ERROR .
42771 #define PSWRD2_REG_INT_MASK_PUSH_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.PUSH_ERROR .
42773 #define PSWRD2_REG_INT_MASK_PUSH_PBF_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.PUSH_PBF_ERROR .
42776 #define PSWRD2_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42778 #define PSWRD2_REG_INT_STS_WR_SR_FIFO_ERROR (0x1<<1) // An error in the SR free list FIFO.
42780 #define PSWRD2_REG_INT_STS_WR_BLK_FIFO_ERROR (0x1<<2) // An error in the blocks free list FIFO.
42782 #define PSWRD2_REG_INT_STS_WR_PUSH_ERROR (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
42784 #define PSWRD2_REG_INT_STS_WR_PUSH_PBF_ERROR (0x1<<4) // An error in the PBF FIFO push interface.
42787 #define PSWRD2_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42789 #define PSWRD2_REG_INT_STS_CLR_SR_FIFO_ERROR (0x1<<1) // An error in the SR free list FIFO.
42791 #define PSWRD2_REG_INT_STS_CLR_BLK_FIFO_ERROR (0x1<<2) // An error in the blocks free list FIFO.
42793 #define PSWRD2_REG_INT_STS_CLR_PUSH_ERROR (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
42795 #define PSWRD2_REG_INT_STS_CLR_PUSH_PBF_ERROR (0x1<<4) // An error in the PBF FIFO push interface.
42797 #define PSWRD2_REG_PRTY_MASK 0x29d194UL //Access:RW DataWidth:0x1 // Multi Field Register.
42798 #define PSWRD2_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS.DATAPATH_REGISTERS .
42801 #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
42803 #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT .
42805 #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM019_I_ECC_RF_INT .
42807 #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT .
42809 #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
42811 #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
42813 #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT .
42815 #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT .
42817 #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
42819 #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
42821 #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
42823 #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
42825 #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
42827 #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
42829 #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
42831 #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
42833 #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
42835 #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
42837 #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
42839 #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
42841 #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
42843 #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
42845 #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
42847 #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
42849 #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
42851 #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
42853 #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
42855 #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
42857 #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
42859 #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
42861 #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
42864 #define PSWRD2_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
42866 #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
42868 #define PSWRD2_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
42878 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
42880 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
42882 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42884 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42886 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42888 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42890 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN (0x1<<6) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42892 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN (0x1<<7) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42894 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42896 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN (0x1<<9) // Enable ECC for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap
42899 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
42901 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
42903 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42905 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42907 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42909 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42911 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY (0x1<<6) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42913 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY (0x1<<7) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42915 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42917 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY (0x1<<9) // Set parity only for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap
42920 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
42922 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw
42924 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42926 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42928 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42930 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42932 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42934 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42936 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap
42938 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap
42950 #define PSWRD2_REG_DISABLE_INPUTS 0x29d460UL //Access:RW DataWidth:0x1 // When '1'; inputs to the PSWRD block are ignored.
42953 #define PSWRD2_REG_ATC_GLOBAL_ENABLE 0x29d46cUL //Access:RW DataWidth:0x1 // Global ATC enable bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated. The value of this register must be the same as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
42954 #define PSWRD2_REG_CONTINUE_SERVING_PBF 0x29d470UL //Access:RW DataWidth:0x1 // This register defines the delivery port behavior when finishing delivering a request to the PBF and the data for the next request is already in the Tetris buffer. 0 - The delivery port continues delivering the next PBF request only if the second delivery port is idle. This is the behavior in E1 E1H and E2. 1 - The delivery port always continues delivering the next PBF request. This is more efficient since about 11 arbitration cycles are not wasted.
42986 #define PSWHST2_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42988 #define PSWHST2_REG_INT_STS_HST_HEADER_FIFO_ERR (0x1<<1) // An error in the header clock sync FIFO.
42990 #define PSWHST2_REG_INT_STS_HST_DATA_FIFO_ERR (0x1<<2) // An error in the data clock sync FIFO.
42992 #define PSWHST2_REG_INT_STS_HST_CPL_FIFO_ERR (0x1<<3) // An error in the completion clock sync FIFO.
42994 #define PSWHST2_REG_INT_STS_HST_IREQ_FIFO_ERR (0x1<<4) // An error in the ireq clock sync FIFO.
42997 #define PSWHST2_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.ADDRESS_ERROR .
42999 #define PSWHST2_REG_INT_MASK_HST_HEADER_FIFO_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_HEADER_FIFO_ERR .
43001 #define PSWHST2_REG_INT_MASK_HST_DATA_FIFO_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_DATA_FIFO_ERR .
43003 #define PSWHST2_REG_INT_MASK_HST_CPL_FIFO_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_CPL_FIFO_ERR .
43005 #define PSWHST2_REG_INT_MASK_HST_IREQ_FIFO_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_IREQ_FIFO_ERR .
43008 #define PSWHST2_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43010 #define PSWHST2_REG_INT_STS_WR_HST_HEADER_FIFO_ERR (0x1<<1) // An error in the header clock sync FIFO.
43012 #define PSWHST2_REG_INT_STS_WR_HST_DATA_FIFO_ERR (0x1<<2) // An error in the data clock sync FIFO.
43014 #define PSWHST2_REG_INT_STS_WR_HST_CPL_FIFO_ERR (0x1<<3) // An error in the completion clock sync FIFO.
43016 #define PSWHST2_REG_INT_STS_WR_HST_IREQ_FIFO_ERR (0x1<<4) // An error in the ireq clock sync FIFO.
43019 #define PSWHST2_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43021 #define PSWHST2_REG_INT_STS_CLR_HST_HEADER_FIFO_ERR (0x1<<1) // An error in the header clock sync FIFO.
43023 #define PSWHST2_REG_INT_STS_CLR_HST_DATA_FIFO_ERR (0x1<<2) // An error in the data clock sync FIFO.
43025 #define PSWHST2_REG_INT_STS_CLR_HST_CPL_FIFO_ERR (0x1<<3) // An error in the completion clock sync FIFO.
43027 #define PSWHST2_REG_INT_STS_CLR_HST_IREQ_FIFO_ERR (0x1<<4) // An error in the ireq clock sync FIFO.
43029 #define PSWHST2_REG_PRTY_MASK 0x29e194UL //Access:RW DataWidth:0x1 // Multi Field Register.
43030 #define PSWHST2_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST2_REG_PRTY_STS.DATAPATH_REGISTERS .
43032 #define PSWHST_REG_ZONE_PERM_TABLE_INIT 0x2a0000UL //Access:RW DataWidth:0x1 // Start the Init sequence for the zone permission table.
43033 #define PSWHST_REG_ZONE_PERM_TABLE_INIT_DONE 0x2a0004UL //Access:RC DataWidth:0x1 // Done indication for the permission table's init sequence. Driver should check the value of this register is 1 some time after it wrote 1 to zone_perm_table_init.
43034 #define PSWHST_REG_DISCARD_INTERNAL_WRITES 0x2a0040UL //Access:RW DataWidth:0x1 // When 1; new internal writes arriving to the block are discarded. Should be used for close the gates.
43035 #define PSWHST_REG_DISCARD_DOORBELLS 0x2a0044UL //Access:RW DataWidth:0x1 // When 1; doorbells are discarded and not passed to doorbell queue block. Should be used for close the gates.
43036 #define PSWHST_REG_DISCARD_P2M 0x2a0048UL //Access:RW DataWidth:0x1 // When 1; p2m are discarded and not passed to p2m queue block. Should be used for close the gates.
43038 #define PSWHST_REG_DISCARD_DOORBELLS_STATUS 0x2a0050UL //Access:R DataWidth:0x1 // Debug only: '1' means this PSWHST is discarding doorbells. This bit should update accoring to 'hst_discard_doorbells' register when the state machine is idle.
43039 #define PSWHST_REG_DISCARD_P2M_STATUS 0x2a0054UL //Access:R DataWidth:0x1 // Debug only: '1' means this PSWHST is discarding p2m. This bit should update accoring to 'hst_discard_p2m' register when the state machine is idle.
43042 #define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is logged.
43046 #define PSWHST_REG_INCORRECT_ACCESS_VALID 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1).
43048 #define PSWHST_REG_PER_VIOLATION_VALID 0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation data is logged. The valid bit is reset when the relevant interrupt register is read.
43055 #define PSWHST_REG_SOURCE_CREDIT_VIOL_VALID 0x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit violation is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1).
43061 #define PSWHST_REG_IS_IN_DRAIN_MODE 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain mode.
43062 #define PSWHST_REG_EXIT_DRAIN_MODE 0x2a00b0UL //Access:W DataWidth:0x1 // Writing 1 to this register indicates PSWHST to exit drain mode.
43064 #define PSWHST_REG_TIMEOUT_VALID 0x2a00b8UL //Access:R DataWidth:0x1 // 1 - An hst timeout data is logged. The valid bit is reset when exiting drain mode (writing to hst_exit_drain_mode).
43068 #define PSWHST_REG_HOST_STRICT_PRIORITY 0x2a00c8UL //Access:RW DataWidth:0x1 // When 1; host requests have strict priority on internal write requests; as in A0. When 0; arbiter alternately chooses host requests and internal write requests.
43093 #define PSWHST_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43095 #define PSWHST_REG_INT_STS_HST_SRC_FIFO1_ERR (0x1<<1) // An error in write source FIFO 1.
43097 #define PSWHST_REG_INT_STS_HST_SRC_FIFO2_ERR (0x1<<2) // An error in write source FIFO 2.
43099 #define PSWHST_REG_INT_STS_HST_SRC_FIFO3_ERR (0x1<<3) // An error in write source FIFO 3.
43101 #define PSWHST_REG_INT_STS_HST_SRC_FIFO4_ERR (0x1<<4) // An error in write source FIFO 4.
43103 #define PSWHST_REG_INT_STS_HST_SRC_FIFO5_ERR (0x1<<5) // An error in write source FIFO 5.
43105 #define PSWHST_REG_INT_STS_HST_HDR_SYNC_FIFO_ERR (0x1<<6) // An error in header clock sync FIFO.
43107 #define PSWHST_REG_INT_STS_HST_DATA_SYNC_FIFO_ERR (0x1<<7) // An error in data clock sync FIFO.
43109 #define PSWHST_REG_INT_STS_HST_CPL_SYNC_FIFO_ERR (0x1<<8) // An error in completion clock sync FIFO.
43111 #define PSWHST_REG_INT_STS_HST_VF_DISABLED_ACCESS (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
43113 #define PSWHST_REG_INT_STS_HST_PERMISSION_VIOLATION (0x1<<10) // Indicates Zone permission violation. The relevant data is stored in hst_per_violation_data.
43115 #define PSWHST_REG_INT_STS_HST_INCORRECT_ACCESS (0x1<<11) // Indicates there was an access to any of the clients with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
43117 #define PSWHST_REG_INT_STS_HST_SRC_FIFO6_ERR (0x1<<12) // An error in write source FIFO 6.
43119 #define PSWHST_REG_INT_STS_HST_SRC_FIFO7_ERR (0x1<<13) // An error in write source FIFO 7.
43121 #define PSWHST_REG_INT_STS_HST_SRC_FIFO8_ERR (0x1<<14) // An error in write source FIFO 8.
43123 #define PSWHST_REG_INT_STS_HST_SRC_FIFO9_ERR (0x1<<15) // An error in write source FIFO 9 (PBF).
43125 #define PSWHST_REG_INT_STS_HST_SOURCE_CREDIT_VIOLATION (0x1<<16) // Indicates an internal write source credit violation. The relevant data is stored in hst_source_credit_viol_data.
43127 #define PSWHST_REG_INT_STS_HST_TIMEOUT (0x1<<17) // Indicates hst_timeout occurred.
43130 #define PSWHST_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.ADDRESS_ERROR .
43132 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO1_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO1_ERR .
43134 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO2_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO2_ERR .
43136 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO3_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO3_ERR .
43138 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO4_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO4_ERR .
43140 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO5_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO5_ERR .
43142 #define PSWHST_REG_INT_MASK_HST_HDR_SYNC_FIFO_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_HDR_SYNC_FIFO_ERR .
43144 #define PSWHST_REG_INT_MASK_HST_DATA_SYNC_FIFO_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_DATA_SYNC_FIFO_ERR .
43146 #define PSWHST_REG_INT_MASK_HST_CPL_SYNC_FIFO_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_CPL_SYNC_FIFO_ERR .
43148 #define PSWHST_REG_INT_MASK_HST_VF_DISABLED_ACCESS (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_VF_DISABLED_ACCESS .
43150 #define PSWHST_REG_INT_MASK_HST_PERMISSION_VIOLATION (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_PERMISSION_VIOLATION .
43152 #define PSWHST_REG_INT_MASK_HST_INCORRECT_ACCESS (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_INCORRECT_ACCESS .
43154 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO6_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO6_ERR .
43156 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO7_ERR (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO7_ERR .
43158 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO8_ERR (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO8_ERR .
43160 #define PSWHST_REG_INT_MASK_HST_SRC_FIFO9_ERR (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO9_ERR .
43162 #define PSWHST_REG_INT_MASK_HST_SOURCE_CREDIT_VIOLATION (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SOURCE_CREDIT_VIOLATION .
43164 #define PSWHST_REG_INT_MASK_HST_TIMEOUT (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_TIMEOUT .
43167 #define PSWHST_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43169 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO1_ERR (0x1<<1) // An error in write source FIFO 1.
43171 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO2_ERR (0x1<<2) // An error in write source FIFO 2.
43173 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO3_ERR (0x1<<3) // An error in write source FIFO 3.
43175 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO4_ERR (0x1<<4) // An error in write source FIFO 4.
43177 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO5_ERR (0x1<<5) // An error in write source FIFO 5.
43179 #define PSWHST_REG_INT_STS_WR_HST_HDR_SYNC_FIFO_ERR (0x1<<6) // An error in header clock sync FIFO.
43181 #define PSWHST_REG_INT_STS_WR_HST_DATA_SYNC_FIFO_ERR (0x1<<7) // An error in data clock sync FIFO.
43183 #define PSWHST_REG_INT_STS_WR_HST_CPL_SYNC_FIFO_ERR (0x1<<8) // An error in completion clock sync FIFO.
43185 #define PSWHST_REG_INT_STS_WR_HST_VF_DISABLED_ACCESS (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
43187 #define PSWHST_REG_INT_STS_WR_HST_PERMISSION_VIOLATION (0x1<<10) // Indicates Zone permission violation. The relevant data is stored in hst_per_violation_data.
43189 #define PSWHST_REG_INT_STS_WR_HST_INCORRECT_ACCESS (0x1<<11) // Indicates there was an access to any of the clients with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
43191 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO6_ERR (0x1<<12) // An error in write source FIFO 6.
43193 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO7_ERR (0x1<<13) // An error in write source FIFO 7.
43195 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO8_ERR (0x1<<14) // An error in write source FIFO 8.
43197 #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO9_ERR (0x1<<15) // An error in write source FIFO 9 (PBF).
43199 #define PSWHST_REG_INT_STS_WR_HST_SOURCE_CREDIT_VIOLATION (0x1<<16) // Indicates an internal write source credit violation. The relevant data is stored in hst_source_credit_viol_data.
43201 #define PSWHST_REG_INT_STS_WR_HST_TIMEOUT (0x1<<17) // Indicates hst_timeout occurred.
43204 #define PSWHST_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43206 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO1_ERR (0x1<<1) // An error in write source FIFO 1.
43208 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO2_ERR (0x1<<2) // An error in write source FIFO 2.
43210 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO3_ERR (0x1<<3) // An error in write source FIFO 3.
43212 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO4_ERR (0x1<<4) // An error in write source FIFO 4.
43214 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO5_ERR (0x1<<5) // An error in write source FIFO 5.
43216 #define PSWHST_REG_INT_STS_CLR_HST_HDR_SYNC_FIFO_ERR (0x1<<6) // An error in header clock sync FIFO.
43218 #define PSWHST_REG_INT_STS_CLR_HST_DATA_SYNC_FIFO_ERR (0x1<<7) // An error in data clock sync FIFO.
43220 #define PSWHST_REG_INT_STS_CLR_HST_CPL_SYNC_FIFO_ERR (0x1<<8) // An error in completion clock sync FIFO.
43222 #define PSWHST_REG_INT_STS_CLR_HST_VF_DISABLED_ACCESS (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
43224 #define PSWHST_REG_INT_STS_CLR_HST_PERMISSION_VIOLATION (0x1<<10) // Indicates Zone permission violation. The relevant data is stored in hst_per_violation_data.
43226 #define PSWHST_REG_INT_STS_CLR_HST_INCORRECT_ACCESS (0x1<<11) // Indicates there was an access to any of the clients with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
43228 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO6_ERR (0x1<<12) // An error in write source FIFO 6.
43230 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO7_ERR (0x1<<13) // An error in write source FIFO 7.
43232 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO8_ERR (0x1<<14) // An error in write source FIFO 8.
43234 #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO9_ERR (0x1<<15) // An error in write source FIFO 9 (PBF).
43236 #define PSWHST_REG_INT_STS_CLR_HST_SOURCE_CREDIT_VIOLATION (0x1<<16) // Indicates an internal write source credit violation. The relevant data is stored in hst_source_credit_viol_data.
43238 #define PSWHST_REG_INT_STS_CLR_HST_TIMEOUT (0x1<<17) // Indicates hst_timeout occurred.
43240 #define PSWHST_REG_PRTY_MASK 0x2a0194UL //Access:RW DataWidth:0x1 // Multi Field Register.
43241 #define PSWHST_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS.DATAPATH_REGISTERS .
43244 #define PSWHST_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
43246 #define PSWHST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
43248 #define PSWHST_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
43250 #define PSWHST_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
43252 #define PSWHST_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
43254 #define PSWHST_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
43256 #define PSWHST_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
43258 #define PSWHST_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
43260 #define PSWHST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
43262 #define PSWHST_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
43264 #define PSWHST_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
43266 #define PSWHST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
43268 #define PSWHST_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
43270 #define PSWHST_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
43272 #define PSWHST_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
43274 #define PSWHST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
43276 #define PSWHST_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
43283 #define PGLUE_B_REG_START_INIT_INB_INT_MEM 0x2a8000UL //Access:W DataWidth:0x1 // Writing 1 to this register signals the PGLUE block to start initializing inbound interrupt memories for PF zone B. Memories are initialized such that all interrupts are disabled: start_address = 1; end_address = 0.
43285 #define PGLUE_B_REG_START_INIT_PTT_GTT 0x2a8008UL //Access:W DataWidth:0x1 // Writing 1 to this register signals the PGLUE block to start initializing PTT and GTT. Offsets should map to reserved space, pretend should map to the same PF. This register should be initialized by MCP.
43286 #define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL //Access:R DataWidth:0x1 // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.
43287 #define PGLUE_B_REG_START_INIT_ZONE_A 0x2a8010UL //Access:W DataWidth:0x1 // Writing 1 to this register signals the PGLUE block to start calculating the start address of each SDM zone A in VF BAR according to the sdm_queue_zone_size configurations.
43290 #define PGLUE_B_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43292 #define PGLUE_B_REG_INT_STS_INCORRECT_RCV_BEHAVIOR (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
43294 #define PGLUE_B_REG_INT_STS_WAS_ERROR_ATTN (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
43296 #define PGLUE_B_REG_INT_STS_VF_LENGTH_VIOLATION_ATTN (0x1<<3) // Indicates a VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
43298 #define PGLUE_B_REG_INT_STS_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
43300 #define PGLUE_B_REG_INT_STS_TCPL_ERROR_ATTN (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
43302 #define PGLUE_B_REG_INT_STS_TCPL_IN_TWO_RCBS_ATTN (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
43304 #define PGLUE_B_REG_INT_STS_CSSNOOP_FIFO_OVERFLOW (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
43306 #define PGLUE_B_REG_INT_STS_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
43308 #define PGLUE_B_REG_INT_STS_PCIE_RX_L0S_TIMEOUT (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly. If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
43310 #define PGLUE_B_REG_INT_STS_MASTER_ZLR_ATTN (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
43312 #define PGLUE_B_REG_INT_STS_ADMIN_WINDOW_VIOLATION_ATTN (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
43314 #define PGLUE_B_REG_INT_STS_OUT_OF_RANGE_FUNCTION_IN_PRETEND (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
43316 #define PGLUE_B_REG_INT_STS_ILLEGAL_ADDRESS (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
43318 #define PGLUE_B_REG_INT_STS_PGL_CPL_ERR (0x1<<14) // Completion error received from core.
43320 #define PGLUE_B_REG_INT_STS_PGL_TXW_OF (0x1<<15) // Overflow of tx write queue.
43322 #define PGLUE_B_REG_INT_STS_PGL_CPL_AFT (0x1<<16) // Overflow of cpl queue.
43324 #define PGLUE_B_REG_INT_STS_PGL_CPL_OF (0x1<<17) // Overflow error on completion or target write.
43326 #define PGLUE_B_REG_INT_STS_PGL_CPL_ECRC (0x1<<18) // Ecrc error on completion or target write.
43328 #define PGLUE_B_REG_INT_STS_PGL_PCIE_ATTN (0x1<<19) // Pcie core raised an attention.
43330 #define PGLUE_B_REG_INT_STS_PGL_READ_BLOCKED (0x1<<20) // Read was blocked due to master_en.
43332 #define PGLUE_B_REG_INT_STS_PGL_WRITE_BLOCKED (0x1<<21) // Write was blocked due to master_en.
43334 #define PGLUE_B_REG_INT_STS_VF_ILT_ERR (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
43336 #define PGLUE_B_REG_INT_STS_RXOBFFEXCEPTION_ATTN (0x1<<23) // Indicate rxobffexception_attn is asseted
43339 #define PGLUE_B_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ADDRESS_ERROR .
43341 #define PGLUE_B_REG_INT_MASK_INCORRECT_RCV_BEHAVIOR (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.INCORRECT_RCV_BEHAVIOR .
43343 #define PGLUE_B_REG_INT_MASK_WAS_ERROR_ATTN (0x1<<2) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.WAS_ERROR_ATTN .
43345 #define PGLUE_B_REG_INT_MASK_VF_LENGTH_VIOLATION_ATTN (0x1<<3) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_LENGTH_VIOLATION_ATTN .
43347 #define PGLUE_B_REG_INT_MASK_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_GRC_SPACE_VIOLATION_ATTN .
43349 #define PGLUE_B_REG_INT_MASK_TCPL_ERROR_ATTN (0x1<<5) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_ERROR_ATTN .
43351 #define PGLUE_B_REG_INT_MASK_TCPL_IN_TWO_RCBS_ATTN (0x1<<6) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_IN_TWO_RCBS_ATTN .
43353 #define PGLUE_B_REG_INT_MASK_CSSNOOP_FIFO_OVERFLOW (0x1<<7) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.CSSNOOP_FIFO_OVERFLOW .
43355 #define PGLUE_B_REG_INT_MASK_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<8) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_TRANSLATION_SIZE_DIFFERENT .
43357 #define PGLUE_B_REG_INT_MASK_PCIE_RX_L0S_TIMEOUT (0x1<<9) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PCIE_RX_L0S_TIMEOUT .
43359 #define PGLUE_B_REG_INT_MASK_MASTER_ZLR_ATTN (0x1<<10) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.MASTER_ZLR_ATTN .
43361 #define PGLUE_B_REG_INT_MASK_ADMIN_WINDOW_VIOLATION_ATTN (0x1<<11) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ADMIN_WINDOW_VIOLATION_ATTN .
43363 #define PGLUE_B_REG_INT_MASK_OUT_OF_RANGE_FUNCTION_IN_PRETEND (0x1<<12) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.OUT_OF_RANGE_FUNCTION_IN_PRETEND .
43365 #define PGLUE_B_REG_INT_MASK_ILLEGAL_ADDRESS (0x1<<13) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ILLEGAL_ADDRESS .
43367 #define PGLUE_B_REG_INT_MASK_PGL_CPL_ERR (0x1<<14) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_ERR .
43369 #define PGLUE_B_REG_INT_MASK_PGL_TXW_OF (0x1<<15) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_TXW_OF .
43371 #define PGLUE_B_REG_INT_MASK_PGL_CPL_AFT (0x1<<16) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_AFT .
43373 #define PGLUE_B_REG_INT_MASK_PGL_CPL_OF (0x1<<17) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_OF .
43375 #define PGLUE_B_REG_INT_MASK_PGL_CPL_ECRC (0x1<<18) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_ECRC .
43377 #define PGLUE_B_REG_INT_MASK_PGL_PCIE_ATTN (0x1<<19) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_PCIE_ATTN .
43379 #define PGLUE_B_REG_INT_MASK_PGL_READ_BLOCKED (0x1<<20) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_READ_BLOCKED .
43381 #define PGLUE_B_REG_INT_MASK_PGL_WRITE_BLOCKED (0x1<<21) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_WRITE_BLOCKED .
43383 #define PGLUE_B_REG_INT_MASK_VF_ILT_ERR (0x1<<22) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_ILT_ERR .
43385 #define PGLUE_B_REG_INT_MASK_RXOBFFEXCEPTION_ATTN (0x1<<23) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.RXOBFFEXCEPTION_ATTN .
43388 #define PGLUE_B_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43390 #define PGLUE_B_REG_INT_STS_WR_INCORRECT_RCV_BEHAVIOR (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
43392 #define PGLUE_B_REG_INT_STS_WR_WAS_ERROR_ATTN (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
43394 #define PGLUE_B_REG_INT_STS_WR_VF_LENGTH_VIOLATION_ATTN (0x1<<3) // Indicates a VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
43396 #define PGLUE_B_REG_INT_STS_WR_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
43398 #define PGLUE_B_REG_INT_STS_WR_TCPL_ERROR_ATTN (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
43400 #define PGLUE_B_REG_INT_STS_WR_TCPL_IN_TWO_RCBS_ATTN (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
43402 #define PGLUE_B_REG_INT_STS_WR_CSSNOOP_FIFO_OVERFLOW (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
43404 #define PGLUE_B_REG_INT_STS_WR_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
43406 #define PGLUE_B_REG_INT_STS_WR_PCIE_RX_L0S_TIMEOUT (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly. If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
43408 #define PGLUE_B_REG_INT_STS_WR_MASTER_ZLR_ATTN (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
43410 #define PGLUE_B_REG_INT_STS_WR_ADMIN_WINDOW_VIOLATION_ATTN (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
43412 #define PGLUE_B_REG_INT_STS_WR_OUT_OF_RANGE_FUNCTION_IN_PRETEND (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
43414 #define PGLUE_B_REG_INT_STS_WR_ILLEGAL_ADDRESS (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
43416 #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ERR (0x1<<14) // Completion error received from core.
43418 #define PGLUE_B_REG_INT_STS_WR_PGL_TXW_OF (0x1<<15) // Overflow of tx write queue.
43420 #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_AFT (0x1<<16) // Overflow of cpl queue.
43422 #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_OF (0x1<<17) // Overflow error on completion or target write.
43424 #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ECRC (0x1<<18) // Ecrc error on completion or target write.
43426 #define PGLUE_B_REG_INT_STS_WR_PGL_PCIE_ATTN (0x1<<19) // Pcie core raised an attention.
43428 #define PGLUE_B_REG_INT_STS_WR_PGL_READ_BLOCKED (0x1<<20) // Read was blocked due to master_en.
43430 #define PGLUE_B_REG_INT_STS_WR_PGL_WRITE_BLOCKED (0x1<<21) // Write was blocked due to master_en.
43432 #define PGLUE_B_REG_INT_STS_WR_VF_ILT_ERR (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
43434 #define PGLUE_B_REG_INT_STS_WR_RXOBFFEXCEPTION_ATTN (0x1<<23) // Indicate rxobffexception_attn is asseted
43437 #define PGLUE_B_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
43439 #define PGLUE_B_REG_INT_STS_CLR_INCORRECT_RCV_BEHAVIOR (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
43441 #define PGLUE_B_REG_INT_STS_CLR_WAS_ERROR_ATTN (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
43443 #define PGLUE_B_REG_INT_STS_CLR_VF_LENGTH_VIOLATION_ATTN (0x1<<3) // Indicates a VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
43445 #define PGLUE_B_REG_INT_STS_CLR_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
43447 #define PGLUE_B_REG_INT_STS_CLR_TCPL_ERROR_ATTN (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
43449 #define PGLUE_B_REG_INT_STS_CLR_TCPL_IN_TWO_RCBS_ATTN (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
43451 #define PGLUE_B_REG_INT_STS_CLR_CSSNOOP_FIFO_OVERFLOW (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
43453 #define PGLUE_B_REG_INT_STS_CLR_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
43455 #define PGLUE_B_REG_INT_STS_CLR_PCIE_RX_L0S_TIMEOUT (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly. If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
43457 #define PGLUE_B_REG_INT_STS_CLR_MASTER_ZLR_ATTN (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
43459 #define PGLUE_B_REG_INT_STS_CLR_ADMIN_WINDOW_VIOLATION_ATTN (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
43461 #define PGLUE_B_REG_INT_STS_CLR_OUT_OF_RANGE_FUNCTION_IN_PRETEND (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
43463 #define PGLUE_B_REG_INT_STS_CLR_ILLEGAL_ADDRESS (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
43465 #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ERR (0x1<<14) // Completion error received from core.
43467 #define PGLUE_B_REG_INT_STS_CLR_PGL_TXW_OF (0x1<<15) // Overflow of tx write queue.
43469 #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_AFT (0x1<<16) // Overflow of cpl queue.
43471 #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_OF (0x1<<17) // Overflow error on completion or target write.
43473 #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ECRC (0x1<<18) // Ecrc error on completion or target write.
43475 #define PGLUE_B_REG_INT_STS_CLR_PGL_PCIE_ATTN (0x1<<19) // Pcie core raised an attention.
43477 #define PGLUE_B_REG_INT_STS_CLR_PGL_READ_BLOCKED (0x1<<20) // Read was blocked due to master_en.
43479 #define PGLUE_B_REG_INT_STS_CLR_PGL_WRITE_BLOCKED (0x1<<21) // Write was blocked due to master_en.
43481 #define PGLUE_B_REG_INT_STS_CLR_VF_ILT_ERR (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
43483 #define PGLUE_B_REG_INT_STS_CLR_RXOBFFEXCEPTION_ATTN (0x1<<23) // Indicate rxobffexception_attn is asseted
43485 #define PGLUE_B_REG_PRTY_MASK 0x2a8194UL //Access:RW DataWidth:0x1 // Multi Field Register.
43486 #define PGLUE_B_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS.DATAPATH_REGISTERS .
43489 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
43491 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
43493 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
43495 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
43497 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
43499 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
43501 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
43503 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
43505 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
43507 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
43509 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
43511 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
43513 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
43515 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
43517 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
43519 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
43521 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
43523 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
43525 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
43527 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
43529 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
43531 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
43533 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
43535 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
43537 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
43539 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0 (0x1<<13) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
43541 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1 (0x1<<14) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
43543 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2 (0x1<<15) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_2 .
43545 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3 (0x1<<16) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_3 .
43547 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4 (0x1<<17) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_4 .
43549 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5 (0x1<<18) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_5 .
43551 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_6 (0x1<<19) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_6 .
43553 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_7 (0x1<<20) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_7 .
43555 #define PGLUE_B_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
43558 #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_6 (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY_6 .
43560 #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_7 (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY_7 .
43562 #define PGLUE_B_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
43578 #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E0 (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - Debug bus is output to RBCN_e0.
43580 #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E1 (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - Debug bus is output to RBCN_e1.
43583 #define PGLUE_B_REG_PGL_DEBUG_PGL_TXR_RELAX (0x1<<0) // Debug only.
43585 #define PGLUE_B_REG_PGL_DEBUG_PGL_TXW_RELAX (0x1<<1) // Debug only.
43587 #define PGLUE_B_REG_PGL_DEBUG_PGL_DISABLE (0x1<<2) // Debug only.
43595 #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_PARITY_MODE (0x1<<8) // This bit forces a parity error in the replay buffer.
43597 #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_TXARB_SP (0x1<<9) // This bit give strict priority to read over write on the PGL read-write arbiter.
43613 #define PGLUE_B_REG_PCIE_DBGSYN_ENABLE 0x2a84b4UL //Access:RW DataWidth:0x1 // Debug only: When 1, PCIe dbgsyn clock synchronization FIFO is enabled and frame, valid, data are output from it to the debug block. When 0, PCIe dbgsyn clock synchronization FIFO is disabled and pcie_top_wrapper should output 0 in frame, valid and data outputs.
43615 #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_HIGHER_BW_WAW (0x1<<0) // Debug only. Used to disable an E2 optimization of having less dead cycles between adjacent write request (write after write) from PGLUE to PCIe core. When disable_two_pending_wr_requests is 0; this bit must be 0 as well.
43617 #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_REQUESTS (0x1<<1) // Debug only. Used to disable an E2 optimization of sending two pending requests from PGLUE to PCIe core. The two pending requests are of different types (master write; master read; target completion).
43619 #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_WR_REQUESTS (0x1<<2) // Debug only. Used to disable an E2 optimization of sending two pending write requests from PGLUE to PCIe core. When this bit is 0; disable_higher_bw_waw must be 0 as well.
43621 #define PGLUE_B_REG_MEMCTRL_WR_RD_N 0x2a84bcUL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
43625 #define PGLUE_B_REG_PCIE_CHECKSUM_ERROR 0x2a84ccUL //Access:R DataWidth:0x1 // Indicates there was an error in PCIe checksum in data from PCIe core.
43626 #define PGLUE_B_REG_REMOVE_PCIE_CHECKSUM 0x2a84d0UL //Access:RW DataWidth:0x1 // Debug only: 0 - PCIe checksum is generated towards PCIe core. 1 - PCIe checksum is not generated towards PCIe core. This is a chicken bit in case that the extra sample added for checksum calculation needs to be bypassed.
43628 #define PGLUE_B_REG_PSEUDO_VF_MASTER_ENABLE 0x2a84d8UL //Access:RW DataWidth:0x1 // Enable for pseudo VF master mode.
43629 #define PGLUE_B_REG_PSEUDO_VF_TARGET_ENABLE 0x2a84dcUL //Access:RW DataWidth:0x1 // Enable for pseudo VF target mode.
43637 #define PGLUE_B_REG_PGL_CONTROL0_PGL_DISABLE_INPUTS (0x1<<7) // Debug only: disable inputs to pgl.
43680 #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_FLR_REQUEST (0x1<<0) // Debug only: When 1 flr request is not generated by PGLUE.
43682 #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_SRIOV_DISABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disbaled request is not generated by PGLUE.
43716 #define PGLUE_B_REG_DISABLE_ATS_EN_CLEARING 0x2aa0ecUL //Access:RW DataWidth:0x1 // Debug only: PGLUE automatically clears ATC enable for a function if a TCPL arrived for that function with Unsupported Request error. Setting this register to 1 disables this automatic clearing.
43747 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x2aa168UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and target transactions. E4: split240.
43748 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x2aa16cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transactions. E4: split16.
43749 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x2aa170UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write transactions. E4: split16.
43750 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x2aa174UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read transactions. E4: split16.
43815 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
43816 #define PGLUE_B_REG_MSDM_ZONE_A_SIZE_PF 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
43817 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
43818 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
43819 #define PGLUE_B_REG_YSDM_ZONE_A_SIZE_PF 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
43820 #define PGLUE_B_REG_PSDM_ZONE_A_SIZE_PF 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.
43858 #define PGLUE_B_REG_IDO_ENABLE_MASTER_RW2 0x2aa3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit towards PGLUE should be set for Translation Requests.
43859 #define PGLUE_B_REG_IDO_ENABLE_TARGET_CPL 0x2aa3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit towards PGLUE should be set for Target Completions.
43860 #define PGLUE_B_REG_IGU_BYPASS_ON_ERR 0x2aa3ccUL //Access:RW DataWidth:0x1 // 1 - Do not discard IGU master transactions for PF when the corresponding was_error bit is set.
43861 #define PGLUE_B_REG_ALLOW_MSIX_ACCESS_IN_BAR0 0x2aa3d0UL //Access:RW DataWidth:0x1 // 0 - Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value is configured; BAR2 size for PFs and VFs should be configured to 8KB to allow ONLY MSIX table and PBA access. 1 - All IGU space in BAR 0 is accessible; including the first 8KB. When this value is configured; BAR2 size for PFs can be configured to 64KB and for VFs to 16KB to allow all IGU space to be accessed in BAR2 as well.
43866 #define PGLUE_B_REG_DISABLE_TCPL_TRANSLATION_SIZE_CHECK 0x2aa3ecUL //Access:RW DataWidth:0x1 // Debug only: 0 - Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation Size field smaller than the Function programmed STU value; clear the ATS_en shadow bit and send UR to the ATC. 1 - Disable the fix for CQ45220.
43883 #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_DISABLE (0x1<<8) // This field disables the outstadnging tags limit mechanism.
43901 #define PGLUE_B_REG_PF_TRUSTED 0x2aa540UL //Access:RW DataWidth:0x1 // Each bit in this read-only register reflects the value of the corresponding 'PF trusted' config bit on the external configuration space (on PCI address 0x7C bit0). It is used for physical device assignment flow. 0 - PF is untranted. 1 - PF is trusted.
43905 #define PGLUE_B_REG_DISABLE_TPH_NONALIGNED 0x2aa550UL //Access:RW DataWidth:0x1 // Relevant for read request with tph_valid = '1' and with either address not DW aligned or length not a multiple of DWs. 0 - PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when sending the response to the client (already done in E3). 1 - PGLUE should handle the request as it as if it arrived with TPH_Valid = '0'.
43909 #define PGLUE_B_REG_DISABLE_EXTERNAL_BAR0 0x2aa560UL //Access:RW DataWidth:0x1 // 0 - Work with external BAR0 mechanism as defined in E4 spec. 1 - Disable external BAR0 mechanism. Access will be directly to the internal BAR, except accesses to the Admin Window which will still be executed.
43916 #define PGLUE_B_REG_FID_CHANNEL_ENABLE 0x2aa57cUL //Access:RW DataWidth:0x1 // FID channel enable configuration per-VF. Controls Target read/write access to specific locations in ZoneB of each SDM window in the VF BAR. E4: split240.
43921 #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_BME (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
43923 #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_FID_ENABLE (0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
43925 #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_WAS_ERROR (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
43927 #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_BME (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
43929 #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_FID_ENABLE (0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
43931 #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_WAS_ERROR (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
43946 #define PGLUE_B_REG_MASK_BLOCK_DISCARD_ATTN_PF 0x2aa594UL //Access:RW DataWidth:0x1 // When this bit is set and attntion setting configuration is 2 any block or discard event for that function will not generate an attention. This bit will allow SW to extend the period in which attention is masked beyond the FLR_in_progress period. E4: split16.
43947 #define PGLUE_B_REG_MASK_BLOCK_DISCARD_ATTN_VF 0x2aa598UL //Access:RW DataWidth:0x1 // When this bit is set and attntion setting configuration is 2 any block or discard event for that function will not generate an attention. This bit will allow SW to extend the period in which attention is masked beyond the FLR_in_progress period. E4: split240.
43953 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG 0x2aae04UL //Access:RW DataWidth:0x1 // A value of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH master write packets. This can be used for debug purposes.
43954 #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_EN 0x2aae08UL //Access:RW DataWidth:0x1 // This field is an enable bit for 'detection of out-of-range requests' debug feature. It should be initialized to '0' in systems with IOMMU enabled.
43968 #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL //Access:RW DataWidth:0x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and align them to cache line according to the sub-request configuration.
43983 #define PGLUE_B_REG_MCTP_ATTN_CLR 0x2aae6cUL //Access:W DataWidth:0x1 // Indication to clear MCTP attention that was genertaed due to bus number change detected by PCIe IP. MCP writes 1 to this register in order to clear the level attention.
43992 #define PGLUE_B_REG_MPS_ATTN 0x2aae90UL //Access:R DataWidth:0x1 // MPS attention dirty bit. Set by PXP. Reset by MCP writing 1 to the corresponding bit in mps_attn_clr.
43993 #define PGLUE_B_REG_MPS_ATTN_CLR 0x2aae94UL //Access:W DataWidth:0x1 // MPS attention dirty bit clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in mps_attn register.
43999 #define PGLUE_B_REG_STICKY_MASTER_ERROR_EN 0x2aaeacUL //Access:RW DataWidth:0x1 // Value of 1 indicates that was_error should be set when BME or fid_enabled bits are cleared for master request.
44000 #define PGLUE_B_REG_CFG_NO_L1_ON_INT 0x2aaeb0UL //Access:RW DataWidth:0x1 // Chicken bit to disable app_xfer_pending.
44008 #define PGLUE_B_REG_POISON_DISCARD_MCMPL 0x2aaed0UL //Access:RW DataWidth:0x1 // Discard when poisoned for MCTP packet
44009 #define PGLUE_B_REG_BUS_CHECK_ENABLE 0x2aaed4UL //Access:RW DataWidth:0x1 // PBUS bus_check_enable Its for MCTP
44010 #define PGLUE_B_REG_DEVICE_CHECK_ENABLE 0x2aaed8UL //Access:RW DataWidth:0x1 // PBUS device check enable Its for MCTP packet
44011 #define PGLUE_B_REG_MCTP_TD_NOT_DROP 0x2aaedcUL //Access:RW DataWidth:0x1 // enable drop packet when TD is 1
44013 #define PGLUE_B_REG_TXR_B2B_DISABLE 0x2aaee4UL //Access:RW DataWidth:0x1 // Disable master read back 2 back transition IT's checken bit for perfomance improvement If this register is set then b2b transfer will be disable like BB
44016 #define PGLUE_B_REG_TXW_B2B_DISABLE 0x2aaef0UL //Access:RW DataWidth:0x1 // Disable master write back 2 back transition
44018 #define PGLUE_B_REG_FLR_INVALIDATE_DISABLE 0x2aaef8UL //Access:RW DataWidth:0x1 // Disable FLR Invalidate process
44019 #define PGLUE_B_REG_INVALIDATE_TAGS_EN 0x2aaefcUL //Access:RW DataWidth:0x1 // Enable invalidate tag
44022 #define PGLUE_B_REG_DISABLE_POWER_STATE_CHECK 0x2aaf08UL //Access:RW DataWidth:0x1 // Power state check disable register If its 0 Then we will do power state check
44025 #define PGLUE_B_REG_CHECK_TC_ON_ERR 0x2aaf5cUL //Access:RW DataWidth:0x1 // check tc on error Its config register if check tc on error = 0 Then we will not check TC If check tc on error =1. we need check if TC = x000
44039 #define PGLUE_B_REG_MCTP_VENDERID_CHK_DISABLE 0x2aaf94UL //Access:RW DataWidth:0x1 // Disable vendorid check in MCTP
44047 #define PGLUE_B_REG_DISCARD_HEADER_UNKNOWN 0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header type 1 - Discard target request with unknown header type
44048 #define PGLUE_B_REG_COMPARE_CPL_FUNCTION 0x2aafb8UL //Access:RW DataWidth:0x1 // 0 - Don't compare the function received in the completion to the original MRD function. 1 - Compare the function received in the completion to the original MRD function. Discard the completion if the comparison fails.
44049 #define PGLUE_B_REG_DISABLE_B2B 0x2aafbcUL //Access:RW DataWidth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_rx. 1 - Disable b2b pop from sync fifos in pgl_pci_core_rx (chicken bit).
44050 #define PGLUE_B_REG_DISCARD_MASTER_REQUEST_IN_FLR 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 - Discard master request during FLR
44056 #define TM_REG_MEMORY_SELF_INIT_START_CONTEXT_MEM_SELF_INIT_START (0x1<<0) // Reset the context memory. When set, the context memory self init starts.
44058 #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_CONN_MEM_SELF_INIT_START (0x1<<1) // Reset the config conn memory. When set, the config conn memory self init starts.
44060 #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_TASK_MEM_SELF_INIT_START (0x1<<2) // Reset the config task memory. When set, the config task memory self init starts.
44062 #define TM_REG_MEMORY_SELF_INIT_START_PRE_SCAN_MEM_SELF_INIT_START (0x1<<3) // Reset the pre scan memory. When set, the pre scan memory self init starts.
44064 #define TM_REG_CONTEXT_MEM_SELF_INIT_DONE 0x2c0004UL //Access:R DataWidth:0x1 // When set, the self init for the context memory is done. TBD - need to change to read, all the bits.
44065 #define TM_REG_CONFIG_CONN_MEM_SELF_INIT_DONE 0x2c0008UL //Access:R DataWidth:0x1 // When set, the self init for the config conn memory is done.
44066 #define TM_REG_CONFIG_TASK_MEM_SELF_INIT_DONE 0x2c000cUL //Access:R DataWidth:0x1 // When set, the self init for the config task memory is done.
44067 #define TM_REG_PRE_SCAN_MEM_SELF_INIT_DONE 0x2c0010UL //Access:R DataWidth:0x1 // When set, the self init for the pre scan memory is done.
44068 #define TM_REG_PXP_READ_DATA_FIFO_INIT 0x2c0014UL //Access:RW DataWidth:0x1 // When set init the PXP READ DATA FIFO.
44069 #define TM_REG_PXP_READ_CTRL_FIFO_INIT 0x2c0018UL //Access:RW DataWidth:0x1 // When set init the PXP READ CTRL FIFO.
44070 #define TM_REG_CFC_LOAD_COMMAND_FIFO_INIT 0x2c001cUL //Access:RW DataWidth:0x1 // When set init the CFC LOAD COMMAND FIFO.
44071 #define TM_REG_CFC_LOAD_ECHO_FIFO_INIT 0x2c0020UL //Access:RW DataWidth:0x1 // When set init the CFC LOAD ECHO FIFO.
44072 #define TM_REG_CLIENT_OUT_FIFO_INIT 0x2c0024UL //Access:RW DataWidth:0x1 // When set init the CLIENT OUT FIFO.
44073 #define TM_REG_CLIENT_IN_PBF_FIFO_INIT 0x2c0028UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN PBF FIFO.
44074 #define TM_REG_CLIENT_IN_XCM_FIFO_INIT 0x2c002cUL //Access:RW DataWidth:0x1 // When set init the CLIENT IN XCM FIFO.
44075 #define TM_REG_CLIENT_IN_TCM_FIFO_INIT 0x2c0030UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN TCM FIFO.
44076 #define TM_REG_CLIENT_IN_UCM_FIFO_INIT 0x2c0034UL //Access:RW DataWidth:0x1 // When set init the CLIENT IN UCM FIFO.
44077 #define TM_REG_EXPIRATION_CMD_FIFO_INIT 0x2c0038UL //Access:RW DataWidth:0x1 // When set init the EXPIRATION COMMAND FIFO.
44078 #define TM_REG_AC_COMMAND_FIFO_INIT 0x2c003cUL //Access:RW DataWidth:0x1 // When set init the AC COMMAND FIFO.
44079 #define TM_REG_PXP_INTERFACE_ENABLE 0x2c0060UL //Access:RW DataWidth:0x1 // Enable pxp request, wr and rd interfaces.
44080 #define TM_REG_CFC_INTERFACE_ENABLE 0x2c0064UL //Access:RW DataWidth:0x1 // Enable cfc load request and load response interfaces.
44081 #define TM_REG_CLIENT_OUT_INTERFACE_ENABLE 0x2c0068UL //Access:RW DataWidth:0x1 // Enable client out interfaces (XCM, UCM, TCM).
44082 #define TM_REG_CLIENT_IN_INTERFACE_ENABLE 0x2c006cUL //Access:RW DataWidth:0x1 // Enable client in interfaces (XCM, UCM, TCM, PBF).
44089 #define TM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44091 #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_OV (0x1<<1) // PXP READ DATA FIFO Overflow.
44093 #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_UN (0x1<<2) // PXP READ DATA FIFO Underrun.
44095 #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_OV (0x1<<3) // PXP READ CTRL FIFO Overflow.
44097 #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_UN (0x1<<4) // PXP READ CTRL FIFO Underrun.
44099 #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_OV (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
44101 #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_UN (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
44103 #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_OV (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
44105 #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_UN (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
44107 #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_OV (0x1<<9) // CLIENT OUT FIFO Overflow.
44109 #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_UN (0x1<<10) // CLIENT OUT FIFO Underrun.
44111 #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_OV (0x1<<11) // AC COMMAND FIFO Overflow.
44113 #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_UN (0x1<<12) // AC COMMAND FIFO Underrun.
44115 #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_OV (0x1<<13) // CLIENT IN PBF FIFO Overflow.
44117 #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_UN (0x1<<14) // CLIENT IN PBF FIFO Underrun.
44119 #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_OV (0x1<<15) // CLIENT IN UCM FIFO Overflow.
44121 #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_UN (0x1<<16) // CLIENT IN UCM FIFO Underun.
44123 #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_OV (0x1<<17) // CLIENT IN TCM FIFO Overflow.
44125 #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_UN (0x1<<18) // CLIENT IN TCM FIFO Underrun.
44127 #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_OV (0x1<<19) // CLIENT IN XCM FIFO Overflow.
44129 #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_UN (0x1<<20) // CLIENT IN XCM FIFO Underrun.
44131 #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_OV (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
44133 #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_UN (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
44135 #define TM_REG_INT_STS_0_STOP_ALL_LC_INVALID (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
44137 #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_0 (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
44139 #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_1 (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
44141 #define TM_REG_INT_STS_0_INIT_COMMAND_LC_VALID (0x1<<26) // INIT command and the logical client valid bit is asserted.
44143 #define TM_REG_INT_STS_0_STOP_ALL_EXP_LC_VALID (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
44145 #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_0 (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
44147 #define TM_REG_INT_STS_0_RESERVED_COMMAND (0x1<<29) // RESERVED command.
44149 #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_1 (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
44151 #define TM_REG_INT_STS_0_CLOAD_RES_LOADERR_CONN (0x1<<31) // Connections Load response with Load Error.
44154 #define TM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.ADDRESS_ERROR .
44156 #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_OV (0x1<<1) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_DATA_FIFO_OV .
44158 #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_UN (0x1<<2) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_DATA_FIFO_UN .
44160 #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_OV (0x1<<3) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_CTRL_FIFO_OV .
44162 #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_UN (0x1<<4) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_CTRL_FIFO_UN .
44164 #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_OV (0x1<<5) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_COMMAND_FIFO_OV .
44166 #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_UN (0x1<<6) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_COMMAND_FIFO_UN .
44168 #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_OV (0x1<<7) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_ECHO_FIFO_OV .
44170 #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_UN (0x1<<8) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_ECHO_FIFO_UN .
44172 #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_OV (0x1<<9) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_OUT_FIFO_OV .
44174 #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_UN (0x1<<10) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_OUT_FIFO_UN .
44176 #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_OV (0x1<<11) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.AC_COMMAND_FIFO_OV .
44178 #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_UN (0x1<<12) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.AC_COMMAND_FIFO_UN .
44180 #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_OV (0x1<<13) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_PBF_FIFO_OV .
44182 #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_UN (0x1<<14) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_PBF_FIFO_UN .
44184 #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_OV (0x1<<15) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_UCM_FIFO_OV .
44186 #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_UN (0x1<<16) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_UCM_FIFO_UN .
44188 #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_OV (0x1<<17) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_TCM_FIFO_OV .
44190 #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_UN (0x1<<18) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_TCM_FIFO_UN .
44192 #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_OV (0x1<<19) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_XCM_FIFO_OV .
44194 #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_UN (0x1<<20) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_XCM_FIFO_UN .
44196 #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_OV (0x1<<21) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.EXPIRATION_CMD_FIFO_OV .
44198 #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_UN (0x1<<22) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.EXPIRATION_CMD_FIFO_UN .
44200 #define TM_REG_INT_MASK_0_STOP_ALL_LC_INVALID (0x1<<23) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.STOP_ALL_LC_INVALID .
44202 #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_0 (0x1<<24) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_LC_INVALID_0 .
44204 #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_1 (0x1<<25) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_LC_INVALID_1 .
44206 #define TM_REG_INT_MASK_0_INIT_COMMAND_LC_VALID (0x1<<26) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.INIT_COMMAND_LC_VALID .
44208 #define TM_REG_INT_MASK_0_STOP_ALL_EXP_LC_VALID (0x1<<27) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.STOP_ALL_EXP_LC_VALID .
44210 #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_0 (0x1<<28) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_CID_INVALID_0 .
44212 #define TM_REG_INT_MASK_0_RESERVED_COMMAND (0x1<<29) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.RESERVED_COMMAND .
44214 #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_1 (0x1<<30) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_CID_INVALID_1 .
44216 #define TM_REG_INT_MASK_0_CLOAD_RES_LOADERR_CONN (0x1<<31) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLOAD_RES_LOADERR_CONN .
44219 #define TM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44221 #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_OV (0x1<<1) // PXP READ DATA FIFO Overflow.
44223 #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_UN (0x1<<2) // PXP READ DATA FIFO Underrun.
44225 #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_OV (0x1<<3) // PXP READ CTRL FIFO Overflow.
44227 #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_UN (0x1<<4) // PXP READ CTRL FIFO Underrun.
44229 #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_OV (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
44231 #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_UN (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
44233 #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_OV (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
44235 #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_UN (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
44237 #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_OV (0x1<<9) // CLIENT OUT FIFO Overflow.
44239 #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_UN (0x1<<10) // CLIENT OUT FIFO Underrun.
44241 #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_OV (0x1<<11) // AC COMMAND FIFO Overflow.
44243 #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_UN (0x1<<12) // AC COMMAND FIFO Underrun.
44245 #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_OV (0x1<<13) // CLIENT IN PBF FIFO Overflow.
44247 #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_UN (0x1<<14) // CLIENT IN PBF FIFO Underrun.
44249 #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_OV (0x1<<15) // CLIENT IN UCM FIFO Overflow.
44251 #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_UN (0x1<<16) // CLIENT IN UCM FIFO Underun.
44253 #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_OV (0x1<<17) // CLIENT IN TCM FIFO Overflow.
44255 #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_UN (0x1<<18) // CLIENT IN TCM FIFO Underrun.
44257 #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_OV (0x1<<19) // CLIENT IN XCM FIFO Overflow.
44259 #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_UN (0x1<<20) // CLIENT IN XCM FIFO Underrun.
44261 #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_OV (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
44263 #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_UN (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
44265 #define TM_REG_INT_STS_WR_0_STOP_ALL_LC_INVALID (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
44267 #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_0 (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
44269 #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_1 (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
44271 #define TM_REG_INT_STS_WR_0_INIT_COMMAND_LC_VALID (0x1<<26) // INIT command and the logical client valid bit is asserted.
44273 #define TM_REG_INT_STS_WR_0_STOP_ALL_EXP_LC_VALID (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
44275 #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_0 (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
44277 #define TM_REG_INT_STS_WR_0_RESERVED_COMMAND (0x1<<29) // RESERVED command.
44279 #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_1 (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
44281 #define TM_REG_INT_STS_WR_0_CLOAD_RES_LOADERR_CONN (0x1<<31) // Connections Load response with Load Error.
44284 #define TM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44286 #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_OV (0x1<<1) // PXP READ DATA FIFO Overflow.
44288 #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_UN (0x1<<2) // PXP READ DATA FIFO Underrun.
44290 #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_OV (0x1<<3) // PXP READ CTRL FIFO Overflow.
44292 #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_UN (0x1<<4) // PXP READ CTRL FIFO Underrun.
44294 #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_OV (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
44296 #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_UN (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
44298 #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_OV (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
44300 #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_UN (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
44302 #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_OV (0x1<<9) // CLIENT OUT FIFO Overflow.
44304 #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_UN (0x1<<10) // CLIENT OUT FIFO Underrun.
44306 #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_OV (0x1<<11) // AC COMMAND FIFO Overflow.
44308 #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_UN (0x1<<12) // AC COMMAND FIFO Underrun.
44310 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_OV (0x1<<13) // CLIENT IN PBF FIFO Overflow.
44312 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_UN (0x1<<14) // CLIENT IN PBF FIFO Underrun.
44314 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_OV (0x1<<15) // CLIENT IN UCM FIFO Overflow.
44316 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_UN (0x1<<16) // CLIENT IN UCM FIFO Underun.
44318 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_OV (0x1<<17) // CLIENT IN TCM FIFO Overflow.
44320 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_UN (0x1<<18) // CLIENT IN TCM FIFO Underrun.
44322 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_OV (0x1<<19) // CLIENT IN XCM FIFO Overflow.
44324 #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_UN (0x1<<20) // CLIENT IN XCM FIFO Underrun.
44326 #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_OV (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
44328 #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_UN (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
44330 #define TM_REG_INT_STS_CLR_0_STOP_ALL_LC_INVALID (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
44332 #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_0 (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
44334 #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_1 (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
44336 #define TM_REG_INT_STS_CLR_0_INIT_COMMAND_LC_VALID (0x1<<26) // INIT command and the logical client valid bit is asserted.
44338 #define TM_REG_INT_STS_CLR_0_STOP_ALL_EXP_LC_VALID (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
44340 #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_0 (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
44342 #define TM_REG_INT_STS_CLR_0_RESERVED_COMMAND (0x1<<29) // RESERVED command.
44344 #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_1 (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
44346 #define TM_REG_INT_STS_CLR_0_CLOAD_RES_LOADERR_CONN (0x1<<31) // Connections Load response with Load Error.
44349 #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_CONN (0x1<<0) // Connections Load response with Load Cancel Error.
44351 #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_CONN (0x1<<1) // Connections Load response with Validation Error.
44353 #define TM_REG_INT_STS_1_CONTEXT_RD_LAST (0x1<<2) // Context Read with Last indication de-asserted.
44355 #define TM_REG_INT_STS_1_CONTEXT_WR_LAST (0x1<<3) // Context Write with Last indication de-asserted.
44357 #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_BVALID (0x1<<4) // PXP Read Data EOP with BVALID != 0.
44359 #define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
44361 #define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
44363 #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_ERROR (0x1<<7) // PXP Read Data EOP with ERROR.
44365 #define TM_REG_INT_STS_1_CLOAD_RES_LOADERR_TASK (0x1<<8) // Tasks Load response with Load Error
44367 #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_TASK (0x1<<9) // Tasks Load response with Load Cancel Error.
44369 #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_TASK (0x1<<10) // Tasks Load response with Validation Error.
44372 #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_CONN (0x1<<0) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADCANCEL_CONN .
44374 #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_CONN (0x1<<1) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_VALIDERR_CONN .
44376 #define TM_REG_INT_MASK_1_CONTEXT_RD_LAST (0x1<<2) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CONTEXT_RD_LAST .
44378 #define TM_REG_INT_MASK_1_CONTEXT_WR_LAST (0x1<<3) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CONTEXT_WR_LAST .
44380 #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_BVALID (0x1<<4) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PXP_RD_DATA_EOP_BVALID .
44382 #define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1<<5) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PEND_CONN_SCAN .
44384 #define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1<<6) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PEND_TASK_SCAN .
44386 #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PXP_RD_DATA_EOP_ERROR .
44388 #define TM_REG_INT_MASK_1_CLOAD_RES_LOADERR_TASK (0x1<<8) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADERR_TASK .
44390 #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_TASK (0x1<<9) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADCANCEL_TASK .
44392 #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_TASK (0x1<<10) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_VALIDERR_TASK .
44395 #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_CONN (0x1<<0) // Connections Load response with Load Cancel Error.
44397 #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_CONN (0x1<<1) // Connections Load response with Validation Error.
44399 #define TM_REG_INT_STS_WR_1_CONTEXT_RD_LAST (0x1<<2) // Context Read with Last indication de-asserted.
44401 #define TM_REG_INT_STS_WR_1_CONTEXT_WR_LAST (0x1<<3) // Context Write with Last indication de-asserted.
44403 #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_BVALID (0x1<<4) // PXP Read Data EOP with BVALID != 0.
44405 #define TM_REG_INT_STS_WR_1_PEND_CONN_SCAN (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
44407 #define TM_REG_INT_STS_WR_1_PEND_TASK_SCAN (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
44409 #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_ERROR (0x1<<7) // PXP Read Data EOP with ERROR.
44411 #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADERR_TASK (0x1<<8) // Tasks Load response with Load Error
44413 #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_TASK (0x1<<9) // Tasks Load response with Load Cancel Error.
44415 #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_TASK (0x1<<10) // Tasks Load response with Validation Error.
44418 #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_CONN (0x1<<0) // Connections Load response with Load Cancel Error.
44420 #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_CONN (0x1<<1) // Connections Load response with Validation Error.
44422 #define TM_REG_INT_STS_CLR_1_CONTEXT_RD_LAST (0x1<<2) // Context Read with Last indication de-asserted.
44424 #define TM_REG_INT_STS_CLR_1_CONTEXT_WR_LAST (0x1<<3) // Context Write with Last indication de-asserted.
44426 #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_BVALID (0x1<<4) // PXP Read Data EOP with BVALID != 0.
44428 #define TM_REG_INT_STS_CLR_1_PEND_CONN_SCAN (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
44430 #define TM_REG_INT_STS_CLR_1_PEND_TASK_SCAN (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
44432 #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_ERROR (0x1<<7) // PXP Read Data EOP with ERROR.
44434 #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADERR_TASK (0x1<<8) // Tasks Load response with Load Error
44436 #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_TASK (0x1<<9) // Tasks Load response with Load Cancel Error.
44438 #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_TASK (0x1<<10) // Tasks Load response with Validation Error.
44441 #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM012_I_ECC_0_RF_INT .
44443 #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM012_I_ECC_1_RF_INT .
44445 #define TM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
44447 #define TM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
44449 #define TM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
44451 #define TM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
44453 #define TM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
44455 #define TM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
44457 #define TM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
44459 #define TM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
44461 #define TM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
44463 #define TM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
44465 #define TM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
44467 #define TM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
44469 #define TM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
44471 #define TM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
44473 #define TM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
44476 #define TM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
44478 #define TM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
44480 #define TM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance tm.TM_PRE_SCAN_1024_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_1024_mem
44483 #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
44485 #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
44487 #define TM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance tm.TM_PRE_SCAN_1024_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_1024_mem
44490 #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance tm.i_tm_context_mem.i_ecc_0 in module tm_context_mem
44492 #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance tm.i_tm_context_mem.i_ecc_1 in module tm_context_mem
44494 #define TM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance tm.TM_PRE_SCAN_1024_ROWS_IF.i_tm_pre_scan_mem.i_ecc in module tm_pre_scan_1024_mem
44508 #define TM_REG_VF_ENABLE_CONN 0x2c0438UL //Access:RW DataWidth:0x1 // Enable the VF functions for the connections. This configuration is applicable only to scan operation. Was: en_linear0_timer.
44509 #define TM_REG_PF_ENABLE_CONN 0x2c043cUL //Access:RW DataWidth:0x1 // Enable the PF functions for the connections. This configuration is applicable only to scan opeartion.
44510 #define TM_REG_VF_ENABLE_TASK 0x2c0440UL //Access:RW DataWidth:0x1 // Enable the VF functions for the tasks. This configuration is applicable only to scan operation. Was: en_linear1_timer.
44513 #define TM_REG_TICK_TIMER_ENABLE 0x2c044cUL //Access:RW DataWidth:0x1 // When set, enable the tick_timer.
44515 #define TM_REG_CONNECTIONS_SCAN_TIMER_ENABLE 0x2c0454UL //Access:RW DataWidth:0x1 // When set, enable the connections scan timer.
44517 #define TM_REG_TASKS_SCAN_TIMER_ENABLE 0x2c045cUL //Access:RW DataWidth:0x1 // When set, enable the tasks scan timer.
44521 #define TM_REG_PCI_TPH_VALID 0x2c046cUL //Access:RW DataWidth:0x1 // Pci TPH valid.
44524 #define TM_REG_PCI_REQUEST_DONE_TYPE 0x2c0478UL //Access:RW DataWidth:0x1 // Pci request done type.
44525 #define TM_REG_PCI_USE_PARENT_PF 0x2c047cUL //Access:RW DataWidth:0x1 // Pci use parent PF.
44531 #define TM_REG_PRE_SCAN_MEM_BYPASS 0x2c0494UL //Access:RW DataWidth:0x1 // When set, the pre scan memory is bypassed. This configuration is applicable only if PreScanRange register is set to 0. TBD = name of the other register.
44557 #define TM_REG_PF_SCAN_ACTIVE_CONN 0x2c04fcUL //Access:R DataWidth:0x1 // Indicates if the PF connection is active, ie if it is during the scan process. When =1, the PF connection is active. When =0, the PF connection is not active.
44559 #define TM_REG_VF_SCAN_ACTIVE_CONN 0x2c0504UL //Access:R DataWidth:0x1 // Indicates if the VF connection is active, ie if it is during the scan process. When =1, the VF connection is active. When =0, the VF connection is not active.
44560 #define TM_REG_VF_SCAN_ACTIVE_TASK 0x2c0508UL //Access:R DataWidth:0x1 // Indicates if the VF task is active, ie if it is during the scan process. When =1, the VF task is active. When =0, the VF task is not active.
44561 #define TM_REG_DURING_SCAN_CONN 0x2c050cUL //Access:R DataWidth:0x1 // Indicates if the block is during the connections scan process. When =1, the block is during the connections scan process. When =0, the block is not during the connections scan process.
44562 #define TM_REG_DURING_SCAN_TASK 0x2c0510UL //Access:R DataWidth:0x1 // Indicates if the block is during the tasks scan process. When =1, the block is during the tasks scan process. When =0, the block is not during the tasks scan process.
44563 #define TM_REG_DURING_SCAN 0x2c0514UL //Access:R DataWidth:0x1 // Indicates if the block is during the tasks or connections scan process. When =1, the block is during the tasks or connections scan process. When =0, the block is not during the tasks or connections scan process.
44598 #define TM_REG_PXP_READ_DATA_FIFO_FULL 0x2c070cUL //Access:R DataWidth:0x1 // When set indicates that the PXP READ DATA FIFO is full.
44600 #define TM_REG_PXP_READ_CTRL_FIFO_FULL 0x2c0714UL //Access:R DataWidth:0x1 // When set indicates that the PXP READ CTRL FIFO is full.
44612 #define TM_REG_DEBUG_0_FID_EN 0x2c0744UL //Access:RW DataWidth:0x1 // If enabled, if the error took place, only a command with error for the fid in the register debug_0_fid_mask is kept in the debug_0 registers.
44614 #define TM_REG_DEBUG_0_SOURCE_EN 0x2c074cUL //Access:RW DataWidth:0x1 // If enabled, if the error took place, only a command with error from the source in the register debug_0_source_mask is kept in the debug_0 registers.
44616 #define TM_REG_DEBUG_0_ERROR_VALID 0x2c0754UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
44619 #define TM_REG_DEBUG_0_DONT_DEC_AC 0x2c0760UL //Access:R DataWidth:0x1 // The Dont Dec AC field for the errored command.
44623 #define TM_REG_DEBUG_0_LEADER_TYPE 0x2c0770UL //Access:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
44627 #define TM_REG_DEBUG_1_ERROR_VALID 0x2c0780UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
44630 #define TM_REG_DEBUG_2_ERROR_VALID 0x2c078cUL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
44632 #define TM_REG_DEBUG_3_ERROR_VALID 0x2c0794UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
44635 #define TM_REG_DEBUG_4_ERROR_VALID 0x2c07a0UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
44655 #define TCFC_REG_INIT_REG_AC_INIT (0x1<<0) // When set activity counter ram will be initialized to zeros. when this operation is completed CFC_REGISTERS_AC_INITDONE.AC_INIT_DONE will be set.
44659 #define TCFC_REG_INIT_REG_LL_INIT (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the empty link list. when this operation completes CFC_REGISTERS_LL_INITDONE.LL_INIT_DONE will be set.
44661 #define TCFC_REG_INIT_REG_CAM_INIT (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGISTERS_CAM_INITDONE.CAM_INIT_DONE will be set.
44663 #define TCFC_REG_INIT_REG_TIDRAM_INIT (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be idle or the request will be ignored. When this operation completes CFC_REGISTERS_TIDRAM_INITDONE.TIDRAM_INIT_DONE will be set.
44665 #define TCFC_REG_LL_INIT_DONE 0x2d0004UL //Access:R DataWidth:0x1 // Indication the initializing the link list by the hardware was done.
44666 #define TCFC_REG_AC_INIT_DONE 0x2d0008UL //Access:R DataWidth:0x1 // Indication the initializing the activity counter by the hardware was done.
44667 #define TCFC_REG_CAM_INIT_DONE 0x2d000cUL //Access:R DataWidth:0x1 // Indication that initializing the cams by the hardware was done.
44668 #define TCFC_REG_TIDRAM_INIT_DONE 0x2d0010UL //Access:R DataWidth:0x1 // Indication that initializing the TID Lock RAM by the hardware was done.
44670 #define TCFC_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44672 #define TCFC_REG_INT_STS_0_EXE_ERROR (0x1<<1) // Interrupt indicating that an execution error has occurred.
44675 #define TCFC_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TCFC_REG_INT_STS_0.ADDRESS_ERROR .
44677 #define TCFC_REG_INT_MASK_0_EXE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: TCFC_REG_INT_STS_0.EXE_ERROR .
44680 #define TCFC_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44682 #define TCFC_REG_INT_STS_WR_0_EXE_ERROR (0x1<<1) // Interrupt indicating that an execution error has occurred.
44685 #define TCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44687 #define TCFC_REG_INT_STS_CLR_0_EXE_ERROR (0x1<<1) // Interrupt indicating that an execution error has occurred.
44690 #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
44692 #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
44720 #define TCFC_REG_ERROR_DATA1 0x2d0558UL //Access:R DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Note that the Error ID starts counting at 0x1 so that there will always be a bit set in the ID. This means it is always 1 greater than the bit in the error_vector register which caused the error. See the CFC EAS document for more details.
44725 #define TCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB (0x1<<0) // When set CFC arbiter1 will work in strict priority.
44727 #define TCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB (0x1<<1) // When set load context arbiter will work in strict priority.
44729 #define TCFC_REG_ARBITERS_REG_SP_LC_INP_ARB (0x1<<2) // When set CFC arbiter2 will work in strict priority.
44731 #define TCFC_REG_ARBITERS_REG_SP_MISC_ARB (0x1<<3) // When set CFC arbiter3 will work in strict priority.
44733 #define TCFC_REG_ARBITERS_REG_SP_AC_DEC (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
44735 #define TCFC_REG_ARBITERS_REG_SP_AC_INC (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
44740 #define TCFC_REG_DEBUG0_DISABLE_INPUTS (0x1<<0) // This bit disables the inputs on the CFC.
44742 #define TCFC_REG_DEBUG0_DISABLE_OUTPUTS (0x1<<1) // This bit disables the outputs of the CFC.
44757 #define TCFC_REG_DEBUG1_WRITE_AC (0x1<<4) // Debug only.
44759 #define TCFC_REG_DEBUG1_MY_VAL_AC (0x1<<5) // Debug only.
44763 #define TCFC_REG_DEBUG1_TYPE_FROM_REQ (0x1<<8) // Debug only.
44765 #define TCFC_REG_DEBUG1_CHECK_DEL_STATE (0x1<<9) // Debug only.
44767 #define TCFC_REG_DEBUG1_SW_RESET (0x1<<10) // Debug only.
44769 #define TCFC_REG_DEBUG1_EN_ON_INT_CLR (0x1<<11) // Debug only.
44771 #define TCFC_REG_DEBUG1_UPD_CANCEL_DIS (0x1<<12) // Debug only.
44777 #define TCFC_REG_ROBUSTWB_PF 0x2d05d8UL //Access:RW DataWidth:0x1 // Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state.
44778 #define TCFC_REG_SREQ_FULL_STICKY 0x2d05dcUL //Access:RW DataWidth:0x1 // The Interface to Searcher Request Queue has reached the maximum value (4).
44779 #define TCFC_REG_PRSRESP_FULL_STICKY 0x2d05e0UL //Access:RW DataWidth:0x1 // The Interface to Parser Response Queue has reached the maximum value (6).
44781 #define TCFC_REG_PRTY_MASK_CCAM_PAR_ERR (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.CCAM_PAR_ERR .
44783 #define TCFC_REG_PRTY_MASK_SCAM_PAR_ERR (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.SCAM_PAR_ERR .
44785 #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR (0x1<<2) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_LSB_PAR_ERR .
44787 #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR (0x1<<3) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_MSB_PAR_ERR .
44789 #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR (0x1<<4) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_LSB_PAR_ERR .
44791 #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR (0x1<<5) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_MSB_PAR_ERR .
44804 #define TCFC_REG_WEAK_ENABLE_PF 0x2d0700UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.
44805 #define TCFC_REG_WEAK_ENABLE_VF 0x2d0704UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load request for VF and set an execution error. Set processes load requests normally.
44806 #define TCFC_REG_STRONG_ENABLE_PF 0x2d0708UL //Access:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf).
44807 #define TCFC_REG_STRONG_ENABLE_VF 0x2d070cUL //Access:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for VF. The VFID that caused the execution error will be stored (exec_error_pf).
44812 #define TCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit will prevent the CFC from setting an Attention or hanging when the AC Counter underflows, as long as the Invalidate Minicache for that LC Client is currently asserted.
44814 #define TCFC_REG_PF_MINICACHE_ENABLE 0x2d0718UL //Access:RW DataWidth:0x1 // Enables MiniCache in Load Clients.
44818 #define TCFC_REG_CONTROL0_STRING_CAM_DISABLE (0x1<<9) // When set to 1 the search string caching mechanism is disabled.
44820 #define TCFC_REG_CONTROL0_CID_CAM_DISABLE (0x1<<10) // When set to 1 the cid cam is disabled.
44822 #define TCFC_REG_CONTROL0_NLOE (0x1<<11) // New Load On Error. if this bit is set and there is a load request region that is in error state then a new load request for that region will be submitted; otherwise an immediate response will be sent to the client with error.
44824 #define TCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN (0x1<<12) // When set to 1 the string cam hit parity scrubbing feature is enabled.
44826 #define TCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN (0x1<<13) // When set to 1 the string cam miss parity scrubbing feature is enabled.
44828 #define TCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN (0x1<<14) // When set to 1 the cid cam hit parity scrubbing feature is enabled.
44830 #define TCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN (0x1<<15) // When set to 1 the cid cam miss parity scrubbing feature is enabled.
44866 #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #0.
44868 #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
44875 #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #1.
44877 #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
44884 #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #2.
44886 #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
44894 #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING (0x1<<0) // When set, the String CAM will be used to cache results from the Searcher that did not match an entry in the external tables.
44896 #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING (0x1<<1) // When set, the String CAM will be used to cache results from the Searcher that Matched on an L2 Filter.
44899 #define TCFC_REG_CCAM_SEARCH 0x2d0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_CID_CAM.CID_CAM interface. the write can be to any address).
44910 #define TCFC_REG_SCAM_SEARCH 0x2d0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_STRING_CAM.STRING_CAM interface. the write can be to any address).
44912 #define TCFC_REG_INCLUDE_TID_IN_HASH 0x2d0a40UL //Access:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by XORing TID[32:16] and TID[15:0] to the hash result. In this case, TID mask bit should be zero.
44913 #define TCFC_REG_INCLUDE_VLAN_IN_HASH 0x2d0a44UL //Access:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation by XORing VLAN [11:0] to the hash result. In this case, promiscuous VLAN bit should be zero.
44914 #define TCFC_REG_CID_CAM_BIST_EN 0x2d0b00UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
44918 #define TCFC_REG_STRING_CAM_BIST_EN 0x2d0b10UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
44945 #define CCFC_REG_INIT_REG_AC_INIT (0x1<<0) // When set activity counter ram will be initialized to zeros. when this operation is completed CFC_REGISTERS_AC_INITDONE.AC_INIT_DONE will be set.
44949 #define CCFC_REG_INIT_REG_LL_INIT (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the empty link list. when this operation completes CFC_REGISTERS_LL_INITDONE.LL_INIT_DONE will be set.
44951 #define CCFC_REG_INIT_REG_CAM_INIT (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGISTERS_CAM_INITDONE.CAM_INIT_DONE will be set.
44953 #define CCFC_REG_INIT_REG_TIDRAM_INIT (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be idle or the request will be ignored. When this operation completes CFC_REGISTERS_TIDRAM_INITDONE.TIDRAM_INIT_DONE will be set.
44955 #define CCFC_REG_LL_INIT_DONE 0x2e0004UL //Access:R DataWidth:0x1 // Indication the initializing the link list by the hardware was done.
44956 #define CCFC_REG_AC_INIT_DONE 0x2e0008UL //Access:R DataWidth:0x1 // Indication the initializing the activity counter by the hardware was done.
44957 #define CCFC_REG_CAM_INIT_DONE 0x2e000cUL //Access:R DataWidth:0x1 // Indication that initializing the cams by the hardware was done.
44958 #define CCFC_REG_TIDRAM_INIT_DONE 0x2e0010UL //Access:R DataWidth:0x1 // This bit does not exist for CCFC and will always read '1'.
44960 #define CCFC_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44962 #define CCFC_REG_INT_STS_0_EXE_ERROR (0x1<<1) // Interrupt indicating that an execution error has occurred.
44965 #define CCFC_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: CCFC_REG_INT_STS_0.ADDRESS_ERROR .
44967 #define CCFC_REG_INT_MASK_0_EXE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: CCFC_REG_INT_STS_0.EXE_ERROR .
44970 #define CCFC_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44972 #define CCFC_REG_INT_STS_WR_0_EXE_ERROR (0x1<<1) // Interrupt indicating that an execution error has occurred.
44975 #define CCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
44977 #define CCFC_REG_INT_STS_CLR_0_EXE_ERROR (0x1<<1) // Interrupt indicating that an execution error has occurred.
44980 #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
44982 #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
44984 #define CCFC_REG_MEM_ECC_ENABLE_0 0x2e0210UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
44985 #define CCFC_REG_MEM_ECC_PARITY_ONLY_0 0x2e0214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
44986 #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0 0x2e0218UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram
45013 #define CCFC_REG_ERROR_DATA1 0x2e0558UL //Access:R DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Note that the Error ID starts counting at 0x1 so that there will always be a bit set in the ID. This means it is always 1 greater than the bit in the error_vector register which caused the error. See the CFC EAS document for more details.
45018 #define CCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB (0x1<<0) // When set CFC arbiter1 will work in strict priority.
45020 #define CCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB (0x1<<1) // When set load context arbiter will work in strict priority.
45022 #define CCFC_REG_ARBITERS_REG_SP_LC_INP_ARB (0x1<<2) // When set CFC arbiter2 will work in strict priority.
45024 #define CCFC_REG_ARBITERS_REG_SP_MISC_ARB (0x1<<3) // When set CFC arbiter3 will work in strict priority.
45026 #define CCFC_REG_ARBITERS_REG_SP_AC_DEC (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
45028 #define CCFC_REG_ARBITERS_REG_SP_AC_INC (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
45033 #define CCFC_REG_DEBUG0_DISABLE_INPUTS (0x1<<0) // This bit disables the inputs on the CFC.
45035 #define CCFC_REG_DEBUG0_DISABLE_OUTPUTS (0x1<<1) // This bit disables the outputs of the CFC.
45050 #define CCFC_REG_DEBUG1_WRITE_AC (0x1<<4) // Debug only.
45052 #define CCFC_REG_DEBUG1_MY_VAL_AC (0x1<<5) // Debug only.
45056 #define CCFC_REG_DEBUG1_TYPE_FROM_REQ (0x1<<8) // Debug only.
45058 #define CCFC_REG_DEBUG1_CHECK_DEL_STATE (0x1<<9) // Debug only.
45060 #define CCFC_REG_DEBUG1_SW_RESET (0x1<<10) // Debug only.
45062 #define CCFC_REG_DEBUG1_EN_ON_INT_CLR (0x1<<11) // Debug only.
45064 #define CCFC_REG_DEBUG1_UPD_CANCEL_DIS (0x1<<12) // Debug only.
45070 #define CCFC_REG_ROBUSTWB_PF 0x2e05d8UL //Access:RW DataWidth:0x1 // Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state.
45071 #define CCFC_REG_SREQ_FULL_STICKY 0x2e05dcUL //Access:RW DataWidth:0x1 // The Interface to Searcher Request Queue has reached the maximum value (4).
45072 #define CCFC_REG_PRSRESP_FULL_STICKY 0x2e05e0UL //Access:RW DataWidth:0x1 // The Interface to Parser Response Queue has reached the maximum value (6).
45074 #define CCFC_REG_PRTY_MASK_CCAM_PAR_ERR (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.CCAM_PAR_ERR .
45076 #define CCFC_REG_PRTY_MASK_SCAM_PAR_ERR (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.SCAM_PAR_ERR .
45078 #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR (0x1<<2) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_LSB_PAR_ERR .
45080 #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR (0x1<<3) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_MSB_PAR_ERR .
45082 #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR (0x1<<4) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_LSB_PAR_ERR .
45084 #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR (0x1<<5) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_MSB_PAR_ERR .
45097 #define CCFC_REG_WEAK_ENABLE_PF 0x2e0700UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.
45098 #define CCFC_REG_WEAK_ENABLE_VF 0x2e0704UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load request for VF and set an execution error. Set processes load requests normally.
45099 #define CCFC_REG_STRONG_ENABLE_PF 0x2e0708UL //Access:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf).
45100 #define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL //Access:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for VF. The VFID that caused the execution error will be stored (exec_error_pf).
45105 #define CCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit will prevent the CFC from setting an Attention or hanging when the AC Counter underflows, as long as the Invalidate Minicache for that LC Client is currently asserted.
45107 #define CCFC_REG_PF_MINICACHE_ENABLE 0x2e0718UL //Access:RW DataWidth:0x1 // Enables MiniCache in Load Clients.
45111 #define CCFC_REG_CONTROL0_STRING_CAM_DISABLE (0x1<<9) // When set to 1 the search string caching mechanism is disabled.
45113 #define CCFC_REG_CONTROL0_CID_CAM_DISABLE (0x1<<10) // When set to 1 the cid cam is disabled.
45115 #define CCFC_REG_CONTROL0_NLOE (0x1<<11) // New Load On Error. if this bit is set and there is a load request region that is in error state then a new load request for that region will be submitted; otherwise an immediate response will be sent to the client with error.
45117 #define CCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN (0x1<<12) // When set to 1 the string cam hit parity scrubbing feature is enabled.
45119 #define CCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN (0x1<<13) // When set to 1 the string cam miss parity scrubbing feature is enabled.
45121 #define CCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN (0x1<<14) // When set to 1 the cid cam hit parity scrubbing feature is enabled.
45123 #define CCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN (0x1<<15) // When set to 1 the cid cam miss parity scrubbing feature is enabled.
45159 #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #0.
45161 #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
45168 #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #1.
45170 #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
45177 #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #2.
45179 #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
45187 #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING (0x1<<0) // When set, the String CAM will be used to cache results from the Searcher that did not match an entry in the external tables.
45189 #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING (0x1<<1) // When set, the String CAM will be used to cache results from the Searcher that Matched on an L2 Filter.
45192 #define CCFC_REG_CCAM_SEARCH 0x2e0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_CID_CAM.CID_CAM interface. the write can be to any address).
45203 #define CCFC_REG_SCAM_SEARCH 0x2e0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_STRING_CAM.STRING_CAM interface. the write can be to any address).
45205 #define CCFC_REG_INCLUDE_TID_IN_HASH 0x2e0a40UL //Access:RW DataWidth:0x1 // Added in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by XORing TID[32:16] and TID[15:0] to the hash result. In this case, TID mask bit should be zero.
45206 #define CCFC_REG_INCLUDE_VLAN_IN_HASH 0x2e0a44UL //Access:RW DataWidth:0x1 // Added in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation by XORing VLAN [11:0] to the hash result. In this case, promiscuous VLAN bit should be zero.
45207 #define CCFC_REG_CID_CAM_BIST_EN 0x2e0b00UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
45211 #define CCFC_REG_STRING_CAM_BIST_EN 0x2e0b10UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
45238 #define QM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
45240 #define QM_REG_INT_STS_OVF_ERR_TX (0x1<<1) // Over flow occurs on the TX Queue.
45242 #define QM_REG_INT_STS_OVF_ERR_OTHER (0x1<<2) // Over flow occurs on the Other Queue.
45244 #define QM_REG_INT_STS_PF_USG_CNT_ERR (0x1<<3) // Overflow of pf usage counter.
45246 #define QM_REG_INT_STS_VF_USG_CNT_ERR (0x1<<4) // Overflow of vf usage counter.
45248 #define QM_REG_INT_STS_VOQ_CRD_INC_ERR (0x1<<5) // Increment overflow on VOQ counter.
45250 #define QM_REG_INT_STS_VOQ_CRD_DEC_ERR (0x1<<6) // Decrement underflow on VOQ counter.
45252 #define QM_REG_INT_STS_BYTE_CRD_INC_ERR (0x1<<7) // Increment overflow on byte credit counter.
45254 #define QM_REG_INT_STS_BYTE_CRD_DEC_ERR (0x1<<8) // Decrement underflow on byte credit counter.
45256 #define QM_REG_INT_STS_ERR_INCDEC_RLGLBLCRD (0x1<<9) // Increment or Decrement error for the RL Global counters.
45258 #define QM_REG_INT_STS_ERR_INCDEC_RLPFCRD (0x1<<10) // Increment or Decrement error for the RL PF counters.
45260 #define QM_REG_INT_STS_ERR_INCDEC_WFQPFCRD (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
45262 #define QM_REG_INT_STS_ERR_INCDEC_WFQVPCRD (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
45264 #define QM_REG_INT_STS_ERR_INCDEC_VOQLINECRD (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
45266 #define QM_REG_INT_STS_ERR_INCDEC_VOQBYTECRD (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
45268 #define QM_REG_INT_STS_FIFOS_ERROR (0x1<<15) // Overflow or underflow error in one of FIFOs.
45270 #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR (0x1<<16) // EXP PF controller pop FIFO error.
45272 #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR (0x1<<17) // EXP PF controller push FIFO error.
45274 #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR (0x1<<18) // REQ controller pop FIFO error.
45276 #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR (0x1<<19) // REQ controller push FIFO error.
45278 #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR (0x1<<20) // RES controller pop FIFO error.
45280 #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR (0x1<<21) // RES controller push FIFO error.
45283 #define QM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ADDRESS_ERROR .
45285 #define QM_REG_INT_MASK_OVF_ERR_TX (0x1<<1) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.OVF_ERR_TX .
45287 #define QM_REG_INT_MASK_OVF_ERR_OTHER (0x1<<2) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.OVF_ERR_OTHER .
45289 #define QM_REG_INT_MASK_PF_USG_CNT_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.PF_USG_CNT_ERR .
45291 #define QM_REG_INT_MASK_VF_USG_CNT_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VF_USG_CNT_ERR .
45293 #define QM_REG_INT_MASK_VOQ_CRD_INC_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VOQ_CRD_INC_ERR .
45295 #define QM_REG_INT_MASK_VOQ_CRD_DEC_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VOQ_CRD_DEC_ERR .
45297 #define QM_REG_INT_MASK_BYTE_CRD_INC_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.BYTE_CRD_INC_ERR .
45299 #define QM_REG_INT_MASK_BYTE_CRD_DEC_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.BYTE_CRD_DEC_ERR .
45301 #define QM_REG_INT_MASK_ERR_INCDEC_RLGLBLCRD (0x1<<9) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_RLGLBLCRD .
45303 #define QM_REG_INT_MASK_ERR_INCDEC_RLPFCRD (0x1<<10) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_RLPFCRD .
45305 #define QM_REG_INT_MASK_ERR_INCDEC_WFQPFCRD (0x1<<11) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_WFQPFCRD .
45307 #define QM_REG_INT_MASK_ERR_INCDEC_WFQVPCRD (0x1<<12) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_WFQVPCRD .
45309 #define QM_REG_INT_MASK_ERR_INCDEC_VOQLINECRD (0x1<<13) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_VOQLINECRD .
45311 #define QM_REG_INT_MASK_ERR_INCDEC_VOQBYTECRD (0x1<<14) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_VOQBYTECRD .
45313 #define QM_REG_INT_MASK_FIFOS_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.FIFOS_ERROR .
45315 #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR .
45317 #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR .
45319 #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR .
45321 #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR .
45323 #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_RES_CONTROLER_POP_ERROR .
45325 #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR .
45328 #define QM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
45330 #define QM_REG_INT_STS_WR_OVF_ERR_TX (0x1<<1) // Over flow occurs on the TX Queue.
45332 #define QM_REG_INT_STS_WR_OVF_ERR_OTHER (0x1<<2) // Over flow occurs on the Other Queue.
45334 #define QM_REG_INT_STS_WR_PF_USG_CNT_ERR (0x1<<3) // Overflow of pf usage counter.
45336 #define QM_REG_INT_STS_WR_VF_USG_CNT_ERR (0x1<<4) // Overflow of vf usage counter.
45338 #define QM_REG_INT_STS_WR_VOQ_CRD_INC_ERR (0x1<<5) // Increment overflow on VOQ counter.
45340 #define QM_REG_INT_STS_WR_VOQ_CRD_DEC_ERR (0x1<<6) // Decrement underflow on VOQ counter.
45342 #define QM_REG_INT_STS_WR_BYTE_CRD_INC_ERR (0x1<<7) // Increment overflow on byte credit counter.
45344 #define QM_REG_INT_STS_WR_BYTE_CRD_DEC_ERR (0x1<<8) // Decrement underflow on byte credit counter.
45346 #define QM_REG_INT_STS_WR_ERR_INCDEC_RLGLBLCRD (0x1<<9) // Increment or Decrement error for the RL Global counters.
45348 #define QM_REG_INT_STS_WR_ERR_INCDEC_RLPFCRD (0x1<<10) // Increment or Decrement error for the RL PF counters.
45350 #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQPFCRD (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
45352 #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQVPCRD (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
45354 #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQLINECRD (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
45356 #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQBYTECRD (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
45358 #define QM_REG_INT_STS_WR_FIFOS_ERROR (0x1<<15) // Overflow or underflow error in one of FIFOs.
45360 #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR (0x1<<16) // EXP PF controller pop FIFO error.
45362 #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR (0x1<<17) // EXP PF controller push FIFO error.
45364 #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR (0x1<<18) // REQ controller pop FIFO error.
45366 #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR (0x1<<19) // REQ controller push FIFO error.
45368 #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR (0x1<<20) // RES controller pop FIFO error.
45370 #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR (0x1<<21) // RES controller push FIFO error.
45373 #define QM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
45375 #define QM_REG_INT_STS_CLR_OVF_ERR_TX (0x1<<1) // Over flow occurs on the TX Queue.
45377 #define QM_REG_INT_STS_CLR_OVF_ERR_OTHER (0x1<<2) // Over flow occurs on the Other Queue.
45379 #define QM_REG_INT_STS_CLR_PF_USG_CNT_ERR (0x1<<3) // Overflow of pf usage counter.
45381 #define QM_REG_INT_STS_CLR_VF_USG_CNT_ERR (0x1<<4) // Overflow of vf usage counter.
45383 #define QM_REG_INT_STS_CLR_VOQ_CRD_INC_ERR (0x1<<5) // Increment overflow on VOQ counter.
45385 #define QM_REG_INT_STS_CLR_VOQ_CRD_DEC_ERR (0x1<<6) // Decrement underflow on VOQ counter.
45387 #define QM_REG_INT_STS_CLR_BYTE_CRD_INC_ERR (0x1<<7) // Increment overflow on byte credit counter.
45389 #define QM_REG_INT_STS_CLR_BYTE_CRD_DEC_ERR (0x1<<8) // Decrement underflow on byte credit counter.
45391 #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLGLBLCRD (0x1<<9) // Increment or Decrement error for the RL Global counters.
45393 #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLPFCRD (0x1<<10) // Increment or Decrement error for the RL PF counters.
45395 #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQPFCRD (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
45397 #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQVPCRD (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
45399 #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQLINECRD (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
45401 #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQBYTECRD (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
45403 #define QM_REG_INT_STS_CLR_FIFOS_ERROR (0x1<<15) // Overflow or underflow error in one of FIFOs.
45405 #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR (0x1<<16) // EXP PF controller pop FIFO error.
45407 #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR (0x1<<17) // EXP PF controller push FIFO error.
45409 #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR (0x1<<18) // REQ controller pop FIFO error.
45411 #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR (0x1<<19) // REQ controller push FIFO error.
45413 #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR (0x1<<20) // RES controller pop FIFO error.
45415 #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR (0x1<<21) // RES controller push FIFO error.
45418 #define QM_REG_PRTY_MASK_XCM_WRC_FIFO (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.XCM_WRC_FIFO .
45420 #define QM_REG_PRTY_MASK_UCM_WRC_FIFO (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.UCM_WRC_FIFO .
45422 #define QM_REG_PRTY_MASK_TCM_WRC_FIFO (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.TCM_WRC_FIFO .
45424 #define QM_REG_PRTY_MASK_CCM_WRC_FIFO (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.CCM_WRC_FIFO .
45426 #define QM_REG_PRTY_MASK_BIGRAMHIGH (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMHIGH .
45428 #define QM_REG_PRTY_MASK_BIGRAMLOW (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMLOW .
45430 #define QM_REG_PRTY_MASK_BASE_ADDRESS (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BASE_ADDRESS .
45432 #define QM_REG_PRTY_MASK_WRBUFF (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.WRBUFF .
45434 #define QM_REG_PRTY_MASK_BIGRAMHIGH_EXT_A (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMHIGH_EXT_A .
45436 #define QM_REG_PRTY_MASK_BIGRAMLOW_EXT_A (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMLOW_EXT_A .
45438 #define QM_REG_PRTY_MASK_BASE_ADDRESS_EXT_A (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BASE_ADDRESS_EXT_A .
45441 #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
45443 #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
45445 #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
45447 #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
45449 #define QM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
45451 #define QM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
45453 #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
45455 #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
45457 #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
45459 #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
45461 #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
45463 #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
45465 #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
45467 #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
45469 #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
45471 #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
45473 #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
45475 #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
45477 #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
45479 #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
45481 #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
45483 #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
45485 #define QM_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
45487 #define QM_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
45489 #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
45491 #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
45493 #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
45495 #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
45497 #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
45499 #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
45501 #define QM_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
45504 #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
45506 #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
45508 #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
45510 #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
45512 #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
45514 #define QM_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
45516 #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
45518 #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY .
45520 #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
45522 #define QM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
45524 #define QM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
45526 #define QM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
45528 #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
45530 #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
45532 #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
45534 #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
45536 #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
45538 #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
45540 #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
45542 #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
45544 #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
45546 #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
45548 #define QM_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
45550 #define QM_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
45552 #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
45554 #define QM_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
45556 #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
45558 #define QM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
45560 #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_0 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_0 .
45562 #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_1 (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_1 .
45564 #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_2 .
45567 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_3 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_3 .
45569 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_4 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_4 .
45571 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_5 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_5 .
45573 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_6 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_6 .
45575 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_7 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_7 .
45577 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_8 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_8 .
45579 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_9 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_9 .
45581 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_10 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_10 .
45583 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_11 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_11 .
45585 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_12 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_12 .
45587 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_13 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_13 .
45589 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_14 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_14 .
45591 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_15 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_15 .
45593 #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
45595 #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM001_I_MEM_PRTY .
45597 #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
45599 #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM002_I_MEM_PRTY .
45601 #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
45603 #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
45606 #define QM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_TX_448PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram_tx_448pqtx
45608 #define QM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_TX_448PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram_tx_448pqtx
45610 #define QM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<2) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_64PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram_other_64pqother
45612 #define QM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<3) // Enable ECC for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_64PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram_other_64pqother
45614 #define QM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance qm.QM_MEM_PTR_TBL_TX_PQ_448PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tbl_tx_pq_448pqtx
45617 #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_TX_448PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram_tx_448pqtx
45619 #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_TX_448PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram_tx_448pqtx
45621 #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<2) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_64PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram_other_64pqother
45623 #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<3) // Set parity only for memory ecc instance qm.QM_MEM_BIGRAM_OTHER_64PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram_other_64pqother
45625 #define QM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance qm.QM_MEM_PTR_TBL_TX_PQ_448PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tbl_tx_pq_448pqtx
45628 #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_TX_448PQTX_IF.i_qm_mem_bigram_tx.i_ecc_0 in module qm_mem_bigram_tx_448pqtx
45630 #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_TX_448PQTX_IF.i_qm_mem_bigram_tx.i_ecc_1 in module qm_mem_bigram_tx_448pqtx
45632 #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_OTHER_64PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_0 in module qm_mem_bigram_other_64pqother
45634 #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_BIGRAM_OTHER_64PQOTHER_IF.i_qm_mem_bigram_other.i_ecc_1 in module qm_mem_bigram_other_64pqother
45636 #define QM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance qm.QM_MEM_PTR_TBL_TX_PQ_448PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_ecc in module qm_mem_ptr_tbl_tx_pq_448pqtx
45730 #define QM_REG_BIGRAMTXCMD 0x2f1010UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards of the TX bigRam. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamTxAddr; (b) writing the data BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data BigRamTxData (for rd cmd only).
45734 #define QM_REG_BIGRAMOTHERCMD 0x2f1030UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards of the Other bigRam. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamOtherAddr; (b) writing the data BigRamOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data BigRamOtherData (for rd cmd only).
45920 #define QM_REG_PCIREQPADTOCACHELINE 0x2f1534UL //Access:RW DataWidth:0x1 // pad to cache line field as part of PXP write request
45922 #define QM_REG_OVFERRORTX 0x2f153cUL //Access:RC DataWidth:0x1 // A flag to indicate that overflow error occurred in one of the queues.
45924 #define QM_REG_OVFERROROTHER 0x2f1544UL //Access:RC DataWidth:0x1 // A flag to indicate that overflow error occurred in one of the queues.
45954 #define QM_REG_QMBYPENABLE 0x2f1948UL //Access:RW DataWidth:0x1 // Allows the QM to work in qm bypass mode. i.e. sending the bypass indication when conditions are met and open the XCM bypass request interface from the XCM.
45955 #define QM_REG_OPRTNSTCCRDENABLE 0x2f194cUL //Access:RW DataWidth:0x1 // Allows the QM to answer and handle opportunistic bypass requests (i.e. which PQ credit info?) from the Xstorm. otherwise return null on the GPI interface.
45962 #define QM_REG_WRROTHERPQGRP_0 0x2f1968UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45963 #define QM_REG_WRROTHERPQGRP_1 0x2f196cUL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45964 #define QM_REG_WRROTHERPQGRP_2 0x2f1970UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45965 #define QM_REG_WRROTHERPQGRP_3 0x2f1974UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45966 #define QM_REG_WRROTHERPQGRP_4 0x2f1978UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45967 #define QM_REG_WRROTHERPQGRP_5 0x2f197cUL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45968 #define QM_REG_WRROTHERPQGRP_6 0x2f1980UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45969 #define QM_REG_WRROTHERPQGRP_7 0x2f1984UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45970 #define QM_REG_WRROTHERPQGRP_8 0x2f1988UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45971 #define QM_REG_WRROTHERPQGRP_9 0x2f198cUL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45972 #define QM_REG_WRROTHERPQGRP_10 0x2f1990UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45973 #define QM_REG_WRROTHERPQGRP_11 0x2f1994UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45974 #define QM_REG_WRROTHERPQGRP_12 0x2f1998UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45975 #define QM_REG_WRROTHERPQGRP_13 0x2f199cUL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45976 #define QM_REG_WRROTHERPQGRP_14 0x2f19a0UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
45977 #define QM_REG_WRROTHERPQGRP_15 0x2f19a4UL //Access:RW DataWidth:0x20 // The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.
46007 #define QM_REG_VOQBYTECRDENABLE 0x2f1e00UL //Access:RW DataWidth:0x1 // Enables the VOQ byte credit logic.
46011 #define QM_REG_SDMCMDREADY 0x2f1e10UL //Access:R DataWidth:0x1 // SDM command Ready. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.
46012 #define QM_REG_SDMCMDGO 0x2f1e14UL //Access:RW DataWidth:0x1 // SDM command Ready. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: wr value=1.
46019 #define QM_REG_PQSTSOTHER 0x2f2800UL //Access:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Should be read only access.
46021 #define QM_REG_SOFT_RESET 0x2f2c00UL //Access:RW DataWidth:0x1 // Initialization bit command.
46102 #define QM_REG_ARB_TX_EN 0x2f2e64UL //Access:RW DataWidth:0x1 // Enabling the TX PQ arbiter.
46103 #define QM_REG_ARB_OTHER_EN 0x2f2e68UL //Access:RW DataWidth:0x1 // Enabling the Other PQ arbiter.
46116 #define QM_REG_TXPQMAP_MASKACCESS 0x2f2e9cUL //Access:RW DataWidth:0x1 // Selects between the Mem Array (0) and the Mask Array (1) when accessing the TxPqMap CAM.
46117 #define QM_REG_PCI_RD_ERR 0x2f2ea0UL //Access:RW DataWidth:0x1 // PCI rd error indication. The QM sets this reg upon PXP rdata with error. The driver can clear this bit (through RBC) based on the functional flows (e.g. FLR). It is also possible to set this bit by the RBC but this is used for debug.
46118 #define QM_REG_PF_EN 0x2f2ea4UL //Access:RW DataWidth:0x1 // PF enable vector. Bit per PF. If set the PF is enabled.
46119 #define QM_REG_VF_EN 0x2f2ea8UL //Access:RW DataWidth:0x1 // VF enable vector. Bit per VF. If set the VF is enabled.
46145 #define QM_REG_RLGLBLENABLE 0x2f4c00UL //Access:RW DataWidth:0x1 // Enabling the global VP/QCN RL mechanism.
46147 #define QM_REG_RLGLBLCRD_FORCE_STS_UPDATE 0x2f4c08UL //Access:RW DataWidth:0x1 // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd did not change from XON->XOFF or XOFF->XON NOTE: this is valid only for rf_qm_ind_rlglblcrd* command (i.e. access the global RL through the RBC)
46160 #define QM_REG_RLPFENABLE 0x2f4e00UL //Access:RW DataWidth:0x1 // Enabling the PF RL mechanism.
46172 #define QM_REG_WFQPFENABLE 0x2f5c00UL //Access:RW DataWidth:0x1 // Enabling the PF WFQ mechanism.
46177 #define QM_REG_WFQVPENABLE 0x2f5c14UL //Access:RW DataWidth:0x1 // Enabling the VP WFQ mechanism.
46178 #define QM_REG_WFQVPCRD_FORCE_STS_UPDATE 0x2f5c18UL //Access:RW DataWidth:0x1 // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd did not change from XON->XOFF or XOFF->XON NOTE: this is valid only for rf_qm_ind_wfqvpcrd* command (i.e. access the global RL through the RBC)
46200 #define QM_REG_TX_ARB_GO_MODE 0x2f5d30UL //Access:RW DataWidth:0x1 // Represent the TX arbiter GO working mode. Whenever TX arbitration has completed (i.e. chose the PQ and completed updating all the relevant counters and state bits), new TX arbitration will start. When the new TX arbitration cannot start as no PQ can be chosen, the arbiter enters idle state. Moving to non-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new TX arbitration whenever one of the state bits (VOQ blocked, PF WFQ blocked, VP WFQ blocked, PF RL blocked, VP/QCN RL blocked, Q active, Q paused) changes its state (either XON or XOFF). 1 - start new TX arbitration whenever Tx_Arb_Go_Cycle_Period of cycles has passed from since the last time TX arbitration has started.
46202 #define QM_REG_PQ_ACTIVE_ENABLE 0x2f5d38UL //Access:RW DataWidth:0x1 // Enable the active state mechanism logic.
46219 #define QM_REG_MEM_INIT_GO 0x2f5d7cUL //Access:RW DataWidth:0x1 // Init go command. Upon Wr value of 1, the enabled mems (Mem_Init_Mask_0/1) will be initialized with value of Mem_Init_Value_0/1. NOTES: (a) Go command can be sent only when the mem init unit is ready (Mem_Init_Ready=1). the user is responsible to verify that prior to sending go command. (b) Go command can be sent only in init mode (i.e. no functional traffic is allowed). (c) Upon Go command and until the init is done (Mem_Init_Ready), RBC access to the mems that are being initialized (Mem_Init_Mask_0/1) is not allowed.
46220 #define QM_REG_MEM_INIT_READY 0x2f5d80UL //Access:R DataWidth:0x1 // When set indicates that the mem init unit is ready to accept mem init command (Mem_Init_Go)
46227 #define QM_REG_CAM_BIST_EN 0x2f5d9cUL //Access:RW DataWidth:0x1 // Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.
46253 #define RDIF_REG_RESET_MEMORIES 0x300000UL //Access:W DataWidth:0x1 // Write one to this register will write zero to all L1 entries. When the command is complete zero will be indicated in this register.
46254 #define RDIF_REG_STOP_ON_ERROR 0x300040UL //Access:RW DataWidth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
46255 #define RDIF_REG_BYPASS_MODE_EN 0x300044UL //Access:RW DataWidth:0x1 // If set allow bypass the pipline on pass through commands and in an empty system.
46258 #define RDIF_REG_DIRTY_L1 0x300054UL //Access:R DataWidth:0x1 // Indicates that there is a pending L1 WB. Set only if this is the case for at least min_eob2wf_l1_rd_del cycles.
46259 #define RDIF_REG_DEBUG_BUFER_0_READ_EN 0x300058UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.
46261 #define RDIF_REG_DEBUG_BUFER_1_READ_EN 0x300068UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.
46263 #define RDIF_REG_DEBUG_COMMAND_FIFO_EMPTY 0x300070UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
46264 #define RDIF_REG_DEBUG_ORDER_FIFO_EMPTY 0x300074UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
46265 #define RDIF_REG_DEBUG_RDATA_FIFO_EMPTY 0x300078UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
46285 #define RDIF_REG_DEBUG_DIX_FIFO_EMPTY 0x3000c8UL //Access:R DataWidth:0x1 // Debug: one bit for each protocol ID. 1 = fifo is empty.
46286 #define RDIF_REG_DEBUG_UCM_CREDIT 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is credit.
46287 #define RDIF_REG_DEBUG_UCM_MSG_PENDING 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message is pending (no credit) or waiting for done.
46289 #define RDIF_REG_DEBUG_PIPELINE_IDLE 0x3000d8UL //Access:R DataWidth:0x1 // DEBUG: if set there is no valid data in the pipeline.
46292 #define RDIF_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46294 #define RDIF_REG_INT_STS_FATAL_DIX_ERR (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
46296 #define RDIF_REG_INT_STS_FATAL_CONFIG_ERR (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
46298 #define RDIF_REG_INT_STS_CMD_FIFO_ERR (0x1<<3) // Write to full FIFO or read from empty FIFO.
46300 #define RDIF_REG_INT_STS_ORDER_FIFO_ERR (0x1<<4) // Write to full FIFO or read from empty FIFO.
46302 #define RDIF_REG_INT_STS_RDATA_FIFO_ERR (0x1<<5) // Write to full FIFO or read from empty FIFO.
46304 #define RDIF_REG_INT_STS_DIF_STOP_ERR (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
46306 #define RDIF_REG_INT_STS_PARTIAL_DIF_W_EOB (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
46308 #define RDIF_REG_INT_STS_L1_DIRTY_BIT (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
46311 #define RDIF_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.ADDRESS_ERROR .
46313 #define RDIF_REG_INT_MASK_FATAL_DIX_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.FATAL_DIX_ERR .
46315 #define RDIF_REG_INT_MASK_FATAL_CONFIG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.FATAL_CONFIG_ERR .
46317 #define RDIF_REG_INT_MASK_CMD_FIFO_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.CMD_FIFO_ERR .
46319 #define RDIF_REG_INT_MASK_ORDER_FIFO_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.ORDER_FIFO_ERR .
46321 #define RDIF_REG_INT_MASK_RDATA_FIFO_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.RDATA_FIFO_ERR .
46323 #define RDIF_REG_INT_MASK_DIF_STOP_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.DIF_STOP_ERR .
46325 #define RDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB (0x1<<7) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.PARTIAL_DIF_W_EOB .
46327 #define RDIF_REG_INT_MASK_L1_DIRTY_BIT (0x1<<8) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.L1_DIRTY_BIT .
46330 #define RDIF_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46332 #define RDIF_REG_INT_STS_WR_FATAL_DIX_ERR (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
46334 #define RDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
46336 #define RDIF_REG_INT_STS_WR_CMD_FIFO_ERR (0x1<<3) // Write to full FIFO or read from empty FIFO.
46338 #define RDIF_REG_INT_STS_WR_ORDER_FIFO_ERR (0x1<<4) // Write to full FIFO or read from empty FIFO.
46340 #define RDIF_REG_INT_STS_WR_RDATA_FIFO_ERR (0x1<<5) // Write to full FIFO or read from empty FIFO.
46342 #define RDIF_REG_INT_STS_WR_DIF_STOP_ERR (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
46344 #define RDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
46346 #define RDIF_REG_INT_STS_WR_L1_DIRTY_BIT (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
46349 #define RDIF_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46351 #define RDIF_REG_INT_STS_CLR_FATAL_DIX_ERR (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
46353 #define RDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
46355 #define RDIF_REG_INT_STS_CLR_CMD_FIFO_ERR (0x1<<3) // Write to full FIFO or read from empty FIFO.
46357 #define RDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR (0x1<<4) // Write to full FIFO or read from empty FIFO.
46359 #define RDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR (0x1<<5) // Write to full FIFO or read from empty FIFO.
46361 #define RDIF_REG_INT_STS_CLR_DIF_STOP_ERR (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
46363 #define RDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
46365 #define RDIF_REG_INT_STS_CLR_L1_DIRTY_BIT (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
46368 #define RDIF_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<1) // This bit masks, when set, the Parity bit: RDIF_REG_PRTY_STS.DATAPATH_REGISTERS .
46383 #define TDIF_REG_RESET_MEMORIES 0x310000UL //Access:W DataWidth:0x1 // Write one to this register will write zero to all L1 entries. When the command is complete zero will be indicated in this register.
46384 #define TDIF_REG_STOP_ON_ERROR 0x310040UL //Access:RW DataWidth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
46385 #define TDIF_REG_EOB_AND_PARTIAL_DIF_ERR_MASK 0x310044UL //Access:RW DataWidth:0x1 // mask bit for the following case: host interface = DIF end of burst arrived with end of interval and only partial DIF data arrived. If clear and this event occuer a fatal error will cause the DIF block to stop.
46386 #define TDIF_REG_BYPASS_MODE_EN 0x310048UL //Access:RW DataWidth:0x1 // If set allow bypass the pipline on pass through commands and in an empty system.
46389 #define TDIF_REG_DIRTY_L1 0x310054UL //Access:R DataWidth:0x1 // Indicates that there is a pending L1 WB. Set only if this is the case for at least min_eob2wf_l1_rd_del cycles.
46390 #define TDIF_REG_DEBUG_BUFER_0_READ_EN 0x310058UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.
46392 #define TDIF_REG_DEBUG_BUFER_1_READ_EN 0x310068UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.
46394 #define TDIF_REG_DEBUG_COMMAND_FIFO_EMPTY 0x310070UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
46395 #define TDIF_REG_DEBUG_ORDER_FIFO_EMPTY 0x310074UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
46396 #define TDIF_REG_DEBUG_RDATA_FIFO_EMPTY 0x310078UL //Access:R DataWidth:0x1 // Debug: 1 = fifo is empty.
46417 #define TDIF_REG_DEBUG_UCM_CREDIT 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is credit.
46418 #define TDIF_REG_DEBUG_UCM_MSG_PENDING 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message is pending (no credit) or waiting for done.
46421 #define TDIF_REG_DEBUG_PIPELINE_IDLE 0x3100dcUL //Access:R DataWidth:0x1 // DEBUG: if set there is no valid data in the pipeline.
46431 #define TDIF_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46433 #define TDIF_REG_INT_STS_FATAL_DIX_ERR (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
46435 #define TDIF_REG_INT_STS_FATAL_CONFIG_ERR (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
46437 #define TDIF_REG_INT_STS_CMD_FIFO_ERR (0x1<<3) // Write to full FIFO or read from empty FIFO.
46439 #define TDIF_REG_INT_STS_ORDER_FIFO_ERR (0x1<<4) // Write to full FIFO or read from empty FIFO.
46441 #define TDIF_REG_INT_STS_RDATA_FIFO_ERR (0x1<<5) // Write to full FIFO or read from empty FIFO.
46443 #define TDIF_REG_INT_STS_DIF_STOP_ERR (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
46445 #define TDIF_REG_INT_STS_PARTIAL_DIF_W_EOB (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
46447 #define TDIF_REG_INT_STS_L1_DIRTY_BIT (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
46450 #define TDIF_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.ADDRESS_ERROR .
46452 #define TDIF_REG_INT_MASK_FATAL_DIX_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.FATAL_DIX_ERR .
46454 #define TDIF_REG_INT_MASK_FATAL_CONFIG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.FATAL_CONFIG_ERR .
46456 #define TDIF_REG_INT_MASK_CMD_FIFO_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.CMD_FIFO_ERR .
46458 #define TDIF_REG_INT_MASK_ORDER_FIFO_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.ORDER_FIFO_ERR .
46460 #define TDIF_REG_INT_MASK_RDATA_FIFO_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.RDATA_FIFO_ERR .
46462 #define TDIF_REG_INT_MASK_DIF_STOP_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.DIF_STOP_ERR .
46464 #define TDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB (0x1<<7) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.PARTIAL_DIF_W_EOB .
46466 #define TDIF_REG_INT_MASK_L1_DIRTY_BIT (0x1<<8) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.L1_DIRTY_BIT .
46469 #define TDIF_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46471 #define TDIF_REG_INT_STS_WR_FATAL_DIX_ERR (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
46473 #define TDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
46475 #define TDIF_REG_INT_STS_WR_CMD_FIFO_ERR (0x1<<3) // Write to full FIFO or read from empty FIFO.
46477 #define TDIF_REG_INT_STS_WR_ORDER_FIFO_ERR (0x1<<4) // Write to full FIFO or read from empty FIFO.
46479 #define TDIF_REG_INT_STS_WR_RDATA_FIFO_ERR (0x1<<5) // Write to full FIFO or read from empty FIFO.
46481 #define TDIF_REG_INT_STS_WR_DIF_STOP_ERR (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
46483 #define TDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
46485 #define TDIF_REG_INT_STS_WR_L1_DIRTY_BIT (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
46488 #define TDIF_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46490 #define TDIF_REG_INT_STS_CLR_FATAL_DIX_ERR (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
46492 #define TDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
46494 #define TDIF_REG_INT_STS_CLR_CMD_FIFO_ERR (0x1<<3) // Write to full FIFO or read from empty FIFO.
46496 #define TDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR (0x1<<4) // Write to full FIFO or read from empty FIFO.
46498 #define TDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR (0x1<<5) // Write to full FIFO or read from empty FIFO.
46500 #define TDIF_REG_INT_STS_CLR_DIF_STOP_ERR (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
46502 #define TDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
46504 #define TDIF_REG_INT_STS_CLR_L1_DIRTY_BIT (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
46507 #define TDIF_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<1) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS.DATAPATH_REGISTERS .
46510 #define TDIF_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
46512 #define TDIF_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
46514 #define TDIF_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
46516 #define TDIF_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
46518 #define TDIF_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
46520 #define TDIF_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
46522 #define TDIF_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
46524 #define TDIF_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
46526 #define TDIF_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
46528 #define TDIF_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
46530 #define TDIF_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
46533 #define TDIF_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_sector0_mem
46535 #define TDIF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_sector4_mem
46537 #define TDIF_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_sector5_mem
46539 #define TDIF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_sector6_mem
46542 #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_sector0_mem
46544 #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_sector4_mem
46546 #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_sector5_mem
46548 #define TDIF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_sector6_mem
46551 #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector0_mem.i_ecc in module tdif_l1_sector0_mem
46553 #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector4_mem.i_ecc in module tdif_l1_sector4_mem
46555 #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector5_mem.i_ecc in module tdif_l1_sector5_mem
46557 #define TDIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance tdif.i_tdif_l1_sector6_mem.i_ecc in module tdif_l1_sector6_mem
46575 #define BRB_REG_START_EN 0x34000cUL //Access:RW DataWidth:0x1 // This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.
46577 #define BRB_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46579 #define BRB_REG_INT_STS_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
46581 #define BRB_REG_INT_STS_0_RC_PKT0_1ST_ERROR (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
46583 #define BRB_REG_INT_STS_0_RC_PKT0_LEN_ERROR (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
46585 #define BRB_REG_INT_STS_0_RC_PKT0_MIDDLE_ERROR (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
46587 #define BRB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
46589 #define BRB_REG_INT_STS_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
46591 #define BRB_REG_INT_STS_0_RC_PKT1_1ST_ERROR (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
46593 #define BRB_REG_INT_STS_0_RC_PKT1_LEN_ERROR (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
46595 #define BRB_REG_INT_STS_0_RC_PKT1_MIDDLE_ERROR (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
46597 #define BRB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
46599 #define BRB_REG_INT_STS_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
46601 #define BRB_REG_INT_STS_0_RC_PKT2_1ST_ERROR (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
46603 #define BRB_REG_INT_STS_0_RC_PKT2_LEN_ERROR (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
46605 #define BRB_REG_INT_STS_0_RC_PKT2_MIDDLE_ERROR (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
46607 #define BRB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
46609 #define BRB_REG_INT_STS_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
46611 #define BRB_REG_INT_STS_0_RC_PKT3_1ST_ERROR (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
46613 #define BRB_REG_INT_STS_0_RC_PKT3_LEN_ERROR (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
46615 #define BRB_REG_INT_STS_0_RC_PKT3_MIDDLE_ERROR (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
46617 #define BRB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
46619 #define BRB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
46621 #define BRB_REG_INT_STS_0_UNCOMPLIENT_LOSSLESS_ERROR (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
46623 #define BRB_REG_INT_STS_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
46625 #define BRB_REG_INT_STS_0_WC1_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
46627 #define BRB_REG_INT_STS_0_WC2_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
46629 #define BRB_REG_INT_STS_0_WC3_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
46631 #define BRB_REG_INT_STS_0_LL_ARB_PREFETCH_SOP_ERROR (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
46633 #define BRB_REG_INT_STS_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
46635 #define BRB_REG_INT_STS_0_PACKET_COUNTER_ERROR (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
46637 #define BRB_REG_INT_STS_0_BYTE_COUNTER_ERROR (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
46639 #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
46642 #define BRB_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.ADDRESS_ERROR .
46644 #define BRB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
46646 #define BRB_REG_INT_MASK_0_RC_PKT0_1ST_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_1ST_ERROR .
46648 #define BRB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_LEN_ERROR .
46650 #define BRB_REG_INT_MASK_0_RC_PKT0_MIDDLE_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_MIDDLE_ERROR .
46652 #define BRB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
46654 #define BRB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
46656 #define BRB_REG_INT_MASK_0_RC_PKT1_1ST_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_1ST_ERROR .
46658 #define BRB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_LEN_ERROR .
46660 #define BRB_REG_INT_MASK_0_RC_PKT1_MIDDLE_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_MIDDLE_ERROR .
46662 #define BRB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
46664 #define BRB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
46666 #define BRB_REG_INT_MASK_0_RC_PKT2_1ST_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_1ST_ERROR .
46668 #define BRB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_LEN_ERROR .
46670 #define BRB_REG_INT_MASK_0_RC_PKT2_MIDDLE_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_MIDDLE_ERROR .
46672 #define BRB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
46674 #define BRB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
46676 #define BRB_REG_INT_MASK_0_RC_PKT3_1ST_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_1ST_ERROR .
46678 #define BRB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_LEN_ERROR .
46680 #define BRB_REG_INT_MASK_0_RC_PKT3_MIDDLE_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_MIDDLE_ERROR .
46682 #define BRB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
46684 #define BRB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
46686 #define BRB_REG_INT_MASK_0_UNCOMPLIENT_LOSSLESS_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.UNCOMPLIENT_LOSSLESS_ERROR .
46688 #define BRB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
46690 #define BRB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC1_PROTOCOL_ERROR .
46692 #define BRB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC2_PROTOCOL_ERROR .
46694 #define BRB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC3_PROTOCOL_ERROR .
46696 #define BRB_REG_INT_MASK_0_LL_ARB_PREFETCH_SOP_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.LL_ARB_PREFETCH_SOP_ERROR .
46698 #define BRB_REG_INT_MASK_0_LL_BLK_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.LL_BLK_ERROR .
46700 #define BRB_REG_INT_MASK_0_PACKET_COUNTER_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.PACKET_COUNTER_ERROR .
46702 #define BRB_REG_INT_MASK_0_BYTE_COUNTER_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.BYTE_COUNTER_ERROR .
46704 #define BRB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.MAC0_FC_CNT_ERROR .
46707 #define BRB_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46709 #define BRB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
46711 #define BRB_REG_INT_STS_WR_0_RC_PKT0_1ST_ERROR (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
46713 #define BRB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
46715 #define BRB_REG_INT_STS_WR_0_RC_PKT0_MIDDLE_ERROR (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
46717 #define BRB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
46719 #define BRB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
46721 #define BRB_REG_INT_STS_WR_0_RC_PKT1_1ST_ERROR (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
46723 #define BRB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
46725 #define BRB_REG_INT_STS_WR_0_RC_PKT1_MIDDLE_ERROR (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
46727 #define BRB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
46729 #define BRB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
46731 #define BRB_REG_INT_STS_WR_0_RC_PKT2_1ST_ERROR (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
46733 #define BRB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
46735 #define BRB_REG_INT_STS_WR_0_RC_PKT2_MIDDLE_ERROR (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
46737 #define BRB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
46739 #define BRB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
46741 #define BRB_REG_INT_STS_WR_0_RC_PKT3_1ST_ERROR (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
46743 #define BRB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
46745 #define BRB_REG_INT_STS_WR_0_RC_PKT3_MIDDLE_ERROR (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
46747 #define BRB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
46749 #define BRB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
46751 #define BRB_REG_INT_STS_WR_0_UNCOMPLIENT_LOSSLESS_ERROR (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
46753 #define BRB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
46755 #define BRB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
46757 #define BRB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
46759 #define BRB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
46761 #define BRB_REG_INT_STS_WR_0_LL_ARB_PREFETCH_SOP_ERROR (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
46763 #define BRB_REG_INT_STS_WR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
46765 #define BRB_REG_INT_STS_WR_0_PACKET_COUNTER_ERROR (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
46767 #define BRB_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
46769 #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
46772 #define BRB_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
46774 #define BRB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
46776 #define BRB_REG_INT_STS_CLR_0_RC_PKT0_1ST_ERROR (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
46778 #define BRB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
46780 #define BRB_REG_INT_STS_CLR_0_RC_PKT0_MIDDLE_ERROR (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
46782 #define BRB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
46784 #define BRB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
46786 #define BRB_REG_INT_STS_CLR_0_RC_PKT1_1ST_ERROR (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
46788 #define BRB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
46790 #define BRB_REG_INT_STS_CLR_0_RC_PKT1_MIDDLE_ERROR (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
46792 #define BRB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
46794 #define BRB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
46796 #define BRB_REG_INT_STS_CLR_0_RC_PKT2_1ST_ERROR (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
46798 #define BRB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
46800 #define BRB_REG_INT_STS_CLR_0_RC_PKT2_MIDDLE_ERROR (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
46802 #define BRB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
46804 #define BRB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
46806 #define BRB_REG_INT_STS_CLR_0_RC_PKT3_1ST_ERROR (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
46808 #define BRB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
46810 #define BRB_REG_INT_STS_CLR_0_RC_PKT3_MIDDLE_ERROR (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
46812 #define BRB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
46814 #define BRB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
46816 #define BRB_REG_INT_STS_CLR_0_UNCOMPLIENT_LOSSLESS_ERROR (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
46818 #define BRB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
46820 #define BRB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
46822 #define BRB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
46824 #define BRB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
46826 #define BRB_REG_INT_STS_CLR_0_LL_ARB_PREFETCH_SOP_ERROR (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
46828 #define BRB_REG_INT_STS_CLR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
46830 #define BRB_REG_INT_STS_CLR_0_PACKET_COUNTER_ERROR (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
46832 #define BRB_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
46834 #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
46837 #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
46839 #define BRB_REG_INT_STS_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
46841 #define BRB_REG_INT_STS_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
46843 #define BRB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
46845 #define BRB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR (0x1<<6) // EOP FIFO error in write client 0.
46847 #define BRB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
46849 #define BRB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
46851 #define BRB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
46853 #define BRB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
46855 #define BRB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
46857 #define BRB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
46859 #define BRB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
46861 #define BRB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
46863 #define BRB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
46865 #define BRB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
46867 #define BRB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
46869 #define BRB_REG_INT_STS_1_WC1_INP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46871 #define BRB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46873 #define BRB_REG_INT_STS_1_WC1_EOP_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46875 #define BRB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46877 #define BRB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46879 #define BRB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46881 #define BRB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46883 #define BRB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46885 #define BRB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
46887 #define BRB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46889 #define BRB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46891 #define BRB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
46893 #define BRB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
46895 #define BRB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
46898 #define BRB_REG_INT_MASK_1_MAC1_FC_CNT_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.MAC1_FC_CNT_ERROR .
46900 #define BRB_REG_INT_MASK_1_LL_ARB_CALC_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
46902 #define BRB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
46904 #define BRB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
46906 #define BRB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_EOP_FIFO_ERROR .
46908 #define BRB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
46910 #define BRB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
46912 #define BRB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
46914 #define BRB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
46916 #define BRB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
46918 #define BRB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
46920 #define BRB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_COS_CNT_FIFO_ERROR .
46922 #define BRB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
46924 #define BRB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
46926 #define BRB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
46928 #define BRB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
46930 #define BRB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_INP_FIFO_ERROR .
46932 #define BRB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_SOP_FIFO_ERROR .
46934 #define BRB_REG_INT_MASK_1_WC1_EOP_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_EOP_FIFO_ERROR .
46936 #define BRB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_QUEUE_FIFO_ERROR .
46938 #define BRB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_FREE_POINT_FIFO_ERROR .
46940 #define BRB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_NEXT_POINT_FIFO_ERROR .
46942 #define BRB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_STRT_FIFO_ERROR .
46944 #define BRB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_SECOND_DSCR_FIFO_ERROR .
46946 #define BRB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_PKT_AVAIL_FIFO_ERROR .
46948 #define BRB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_COS_CNT_FIFO_ERROR .
46950 #define BRB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_NOTIFY_FIFO_ERROR .
46952 #define BRB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_LL_REQ_FIFO_ERROR .
46954 #define BRB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_LL_PA_CNT_ERROR .
46956 #define BRB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_BB_PA_CNT_ERROR .
46959 #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
46961 #define BRB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
46963 #define BRB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
46965 #define BRB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
46967 #define BRB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR (0x1<<6) // EOP FIFO error in write client 0.
46969 #define BRB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
46971 #define BRB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
46973 #define BRB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
46975 #define BRB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
46977 #define BRB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
46979 #define BRB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
46981 #define BRB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
46983 #define BRB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
46985 #define BRB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
46987 #define BRB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
46989 #define BRB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
46991 #define BRB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46993 #define BRB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46995 #define BRB_REG_INT_STS_WR_1_WC1_EOP_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46997 #define BRB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
46999 #define BRB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47001 #define BRB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47003 #define BRB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47005 #define BRB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47007 #define BRB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
47009 #define BRB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47011 #define BRB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47013 #define BRB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
47015 #define BRB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
47017 #define BRB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
47020 #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
47022 #define BRB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
47024 #define BRB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
47026 #define BRB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
47028 #define BRB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR (0x1<<6) // EOP FIFO error in write client 0.
47030 #define BRB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
47032 #define BRB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
47034 #define BRB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
47036 #define BRB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
47038 #define BRB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
47040 #define BRB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
47042 #define BRB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
47044 #define BRB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
47046 #define BRB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
47048 #define BRB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
47050 #define BRB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
47052 #define BRB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47054 #define BRB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47056 #define BRB_REG_INT_STS_CLR_1_WC1_EOP_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47058 #define BRB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47060 #define BRB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47062 #define BRB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47064 #define BRB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47066 #define BRB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47068 #define BRB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
47070 #define BRB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47072 #define BRB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
47074 #define BRB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
47076 #define BRB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
47078 #define BRB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
47081 #define BRB_REG_INT_STS_2_WC2_INP_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47083 #define BRB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47085 #define BRB_REG_INT_STS_2_WC2_EOP_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47087 #define BRB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47089 #define BRB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47091 #define BRB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47093 #define BRB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47095 #define BRB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47097 #define BRB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
47099 #define BRB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47101 #define BRB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47103 #define BRB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
47105 #define BRB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
47107 #define BRB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
47109 #define BRB_REG_INT_STS_2_WC3_INP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47111 #define BRB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47113 #define BRB_REG_INT_STS_2_WC3_EOP_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47115 #define BRB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47117 #define BRB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47119 #define BRB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47121 #define BRB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47123 #define BRB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47125 #define BRB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
47127 #define BRB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47129 #define BRB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47131 #define BRB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
47133 #define BRB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
47135 #define BRB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
47138 #define BRB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_INP_FIFO_ERROR .
47140 #define BRB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_SOP_FIFO_ERROR .
47142 #define BRB_REG_INT_MASK_2_WC2_EOP_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_EOP_FIFO_ERROR .
47144 #define BRB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_QUEUE_FIFO_ERROR .
47146 #define BRB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_FREE_POINT_FIFO_ERROR .
47148 #define BRB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_NEXT_POINT_FIFO_ERROR .
47150 #define BRB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_STRT_FIFO_ERROR .
47152 #define BRB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_SECOND_DSCR_FIFO_ERROR .
47154 #define BRB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_PKT_AVAIL_FIFO_ERROR .
47156 #define BRB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_COS_CNT_FIFO_ERROR .
47158 #define BRB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_NOTIFY_FIFO_ERROR .
47160 #define BRB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_LL_REQ_FIFO_ERROR .
47162 #define BRB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_LL_PA_CNT_ERROR .
47164 #define BRB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_BB_PA_CNT_ERROR .
47166 #define BRB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_INP_FIFO_ERROR .
47168 #define BRB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_SOP_FIFO_ERROR .
47170 #define BRB_REG_INT_MASK_2_WC3_EOP_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_EOP_FIFO_ERROR .
47172 #define BRB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_QUEUE_FIFO_ERROR .
47174 #define BRB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_FREE_POINT_FIFO_ERROR .
47176 #define BRB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_NEXT_POINT_FIFO_ERROR .
47178 #define BRB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_STRT_FIFO_ERROR .
47180 #define BRB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_SECOND_DSCR_FIFO_ERROR .
47182 #define BRB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_PKT_AVAIL_FIFO_ERROR .
47184 #define BRB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_COS_CNT_FIFO_ERROR .
47186 #define BRB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_NOTIFY_FIFO_ERROR .
47188 #define BRB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_LL_REQ_FIFO_ERROR .
47190 #define BRB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_LL_PA_CNT_ERROR .
47192 #define BRB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_BB_PA_CNT_ERROR .
47195 #define BRB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47197 #define BRB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47199 #define BRB_REG_INT_STS_WR_2_WC2_EOP_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47201 #define BRB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47203 #define BRB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47205 #define BRB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47207 #define BRB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47209 #define BRB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47211 #define BRB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
47213 #define BRB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47215 #define BRB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47217 #define BRB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
47219 #define BRB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
47221 #define BRB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
47223 #define BRB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47225 #define BRB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47227 #define BRB_REG_INT_STS_WR_2_WC3_EOP_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47229 #define BRB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47231 #define BRB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47233 #define BRB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47235 #define BRB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47237 #define BRB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47239 #define BRB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
47241 #define BRB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47243 #define BRB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47245 #define BRB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
47247 #define BRB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
47249 #define BRB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
47252 #define BRB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47254 #define BRB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47256 #define BRB_REG_INT_STS_CLR_2_WC2_EOP_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47258 #define BRB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47260 #define BRB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47262 #define BRB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47264 #define BRB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47266 #define BRB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47268 #define BRB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
47270 #define BRB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47272 #define BRB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
47274 #define BRB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
47276 #define BRB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
47278 #define BRB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
47280 #define BRB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47282 #define BRB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47284 #define BRB_REG_INT_STS_CLR_2_WC3_EOP_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47286 #define BRB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47288 #define BRB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47290 #define BRB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47292 #define BRB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47294 #define BRB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47296 #define BRB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
47298 #define BRB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47300 #define BRB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
47302 #define BRB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
47304 #define BRB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
47306 #define BRB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
47309 #define BRB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47311 #define BRB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47313 #define BRB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47315 #define BRB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47317 #define BRB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47319 #define BRB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47321 #define BRB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47323 #define BRB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47325 #define BRB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47327 #define BRB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47329 #define BRB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47331 #define BRB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47333 #define BRB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47335 #define BRB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47337 #define BRB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47339 #define BRB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47341 #define BRB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47343 #define BRB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47345 #define BRB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47347 #define BRB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47349 #define BRB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47351 #define BRB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47353 #define BRB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47355 #define BRB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47357 #define BRB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47359 #define BRB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47361 #define BRB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47363 #define BRB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47365 #define BRB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47367 #define BRB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47369 #define BRB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47372 #define BRB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
47374 #define BRB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
47376 #define BRB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
47378 #define BRB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
47380 #define BRB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
47382 #define BRB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
47384 #define BRB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
47386 #define BRB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
47388 #define BRB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
47390 #define BRB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
47392 #define BRB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
47394 #define BRB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
47396 #define BRB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
47398 #define BRB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
47400 #define BRB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
47402 #define BRB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
47404 #define BRB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
47406 #define BRB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
47408 #define BRB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
47410 #define BRB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
47412 #define BRB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
47414 #define BRB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
47416 #define BRB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
47418 #define BRB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
47420 #define BRB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
47422 #define BRB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
47424 #define BRB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
47426 #define BRB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
47428 #define BRB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
47430 #define BRB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
47432 #define BRB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
47435 #define BRB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47437 #define BRB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47439 #define BRB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47441 #define BRB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47443 #define BRB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47445 #define BRB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47447 #define BRB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47449 #define BRB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47451 #define BRB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47453 #define BRB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47455 #define BRB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47457 #define BRB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47459 #define BRB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47461 #define BRB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47463 #define BRB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47465 #define BRB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47467 #define BRB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47469 #define BRB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47471 #define BRB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47473 #define BRB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47475 #define BRB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47477 #define BRB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47479 #define BRB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47481 #define BRB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47483 #define BRB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47485 #define BRB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47487 #define BRB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47489 #define BRB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47491 #define BRB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47493 #define BRB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47495 #define BRB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47498 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47500 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47502 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47504 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47506 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47508 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47510 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47512 #define BRB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
47514 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47516 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47518 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47520 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47522 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47524 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47526 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47528 #define BRB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
47530 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47532 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47534 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47536 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47538 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47540 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47542 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47544 #define BRB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
47546 #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47548 #define BRB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47550 #define BRB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47552 #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47554 #define BRB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47556 #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47558 #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47561 #define BRB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47563 #define BRB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
47565 #define BRB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
47567 #define BRB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
47569 #define BRB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
47571 #define BRB_REG_INT_STS_4_RC0_EOP_ERROR (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
47573 #define BRB_REG_INT_STS_4_RC1_EOP_ERROR (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
47575 #define BRB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
47577 #define BRB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
47579 #define BRB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client PRM release fifo error
47581 #define BRB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client MSDM release fifo error
47583 #define BRB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client TSDM release fifo error
47585 #define BRB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client parser release fifo error
47587 #define BRB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client parser release fifo error
47589 #define BRB_REG_INT_STS_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
47591 #define BRB_REG_INT_STS_4_RC_PKT4_1ST_ERROR (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
47593 #define BRB_REG_INT_STS_4_RC_PKT4_LEN_ERROR (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
47595 #define BRB_REG_INT_STS_4_RC_PKT4_MIDDLE_ERROR (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
47597 #define BRB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
47599 #define BRB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47601 #define BRB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47603 #define BRB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47605 #define BRB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47607 #define BRB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47609 #define BRB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47611 #define BRB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47613 #define BRB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47616 #define BRB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
47618 #define BRB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_STRT_FIFO_ERROR .
47620 #define BRB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_REQ_FIFO_ERROR .
47622 #define BRB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_DSCR_FIFO_ERROR .
47624 #define BRB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
47626 #define BRB_REG_INT_MASK_4_RC0_EOP_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC0_EOP_ERROR .
47628 #define BRB_REG_INT_MASK_4_RC1_EOP_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC1_EOP_ERROR .
47630 #define BRB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
47632 #define BRB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
47634 #define BRB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
47636 #define BRB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
47638 #define BRB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
47640 #define BRB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
47642 #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
47644 #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
47646 #define BRB_REG_INT_MASK_4_RC_PKT4_1ST_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_1ST_ERROR .
47648 #define BRB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_LEN_ERROR .
47650 #define BRB_REG_INT_MASK_4_RC_PKT4_MIDDLE_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_MIDDLE_ERROR .
47652 #define BRB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
47654 #define BRB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
47656 #define BRB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
47658 #define BRB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
47660 #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
47662 #define BRB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
47664 #define BRB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
47666 #define BRB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
47668 #define BRB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
47671 #define BRB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47673 #define BRB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
47675 #define BRB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
47677 #define BRB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
47679 #define BRB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
47681 #define BRB_REG_INT_STS_WR_4_RC0_EOP_ERROR (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
47683 #define BRB_REG_INT_STS_WR_4_RC1_EOP_ERROR (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
47685 #define BRB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
47687 #define BRB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
47689 #define BRB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client PRM release fifo error
47691 #define BRB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client MSDM release fifo error
47693 #define BRB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client TSDM release fifo error
47695 #define BRB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client parser release fifo error
47697 #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client parser release fifo error
47699 #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
47701 #define BRB_REG_INT_STS_WR_4_RC_PKT4_1ST_ERROR (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
47703 #define BRB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
47705 #define BRB_REG_INT_STS_WR_4_RC_PKT4_MIDDLE_ERROR (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
47707 #define BRB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
47709 #define BRB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47711 #define BRB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47713 #define BRB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47715 #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47717 #define BRB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47719 #define BRB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47721 #define BRB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47723 #define BRB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47726 #define BRB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47728 #define BRB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
47730 #define BRB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
47732 #define BRB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
47734 #define BRB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
47736 #define BRB_REG_INT_STS_CLR_4_RC0_EOP_ERROR (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
47738 #define BRB_REG_INT_STS_CLR_4_RC1_EOP_ERROR (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
47740 #define BRB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
47742 #define BRB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
47744 #define BRB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client PRM release fifo error
47746 #define BRB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client MSDM release fifo error
47748 #define BRB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client TSDM release fifo error
47750 #define BRB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client parser release fifo error
47752 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client parser release fifo error
47754 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
47756 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_1ST_ERROR (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
47758 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
47760 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_MIDDLE_ERROR (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
47762 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
47764 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47766 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47768 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47770 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47772 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47774 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47776 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47778 #define BRB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
47780 #define BRB_REG_INT_STS_5 0x340138UL //Access:R DataWidth:0x1 // Multi Field Register.
47781 #define BRB_REG_INT_STS_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
47783 #define BRB_REG_INT_MASK_5 0x34013cUL //Access:RW DataWidth:0x1 // Multi Field Register.
47784 #define BRB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
47786 #define BRB_REG_INT_STS_WR_5 0x340140UL //Access:WR DataWidth:0x1 // Multi Field Register.
47787 #define BRB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
47789 #define BRB_REG_INT_STS_CLR_5 0x340144UL //Access:RC DataWidth:0x1 // Multi Field Register.
47790 #define BRB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
47793 #define BRB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
47795 #define BRB_REG_INT_STS_6_WC4_PROTOCOL_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
47797 #define BRB_REG_INT_STS_6_WC5_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
47799 #define BRB_REG_INT_STS_6_WC6_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
47801 #define BRB_REG_INT_STS_6_WC7_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
47803 #define BRB_REG_INT_STS_6_WC4_INP_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
47805 #define BRB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
47807 #define BRB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
47810 #define BRB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
47812 #define BRB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_PROTOCOL_ERROR .
47814 #define BRB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC5_PROTOCOL_ERROR .
47816 #define BRB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC6_PROTOCOL_ERROR .
47818 #define BRB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC7_PROTOCOL_ERROR .
47820 #define BRB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_INP_FIFO_ERROR .
47822 #define BRB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_SOP_FIFO_ERROR .
47824 #define BRB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_QUEUE_FIFO_ERROR .
47827 #define BRB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
47829 #define BRB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
47831 #define BRB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
47833 #define BRB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
47835 #define BRB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
47837 #define BRB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
47839 #define BRB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
47841 #define BRB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
47844 #define BRB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
47846 #define BRB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
47848 #define BRB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
47850 #define BRB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
47852 #define BRB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
47854 #define BRB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
47856 #define BRB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
47858 #define BRB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
47861 #define BRB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
47863 #define BRB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
47865 #define BRB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
47867 #define BRB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
47869 #define BRB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
47871 #define BRB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
47873 #define BRB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
47875 #define BRB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
47877 #define BRB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
47879 #define BRB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
47881 #define BRB_REG_INT_STS_7_WC5_INP_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
47883 #define BRB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
47885 #define BRB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
47887 #define BRB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
47889 #define BRB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
47891 #define BRB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
47893 #define BRB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
47895 #define BRB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
47897 #define BRB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
47899 #define BRB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // Notify FIFO error in write client 5
47901 #define BRB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
47903 #define BRB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
47905 #define BRB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
47907 #define BRB_REG_INT_STS_7_WC6_INP_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
47909 #define BRB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
47911 #define BRB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
47913 #define BRB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
47915 #define BRB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
47917 #define BRB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
47919 #define BRB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
47921 #define BRB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
47923 #define BRB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
47926 #define BRB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_FREE_POINT_FIFO_ERROR .
47928 #define BRB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_NEXT_POINT_FIFO_ERROR .
47930 #define BRB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_STRT_FIFO_ERROR .
47932 #define BRB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_SECOND_DSCR_FIFO_ERROR .
47934 #define BRB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_PKT_AVAIL_FIFO_ERROR .
47936 #define BRB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_COS_CNT_FIFO_ERROR .
47938 #define BRB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_NOTIFY_FIFO_ERROR .
47940 #define BRB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_LL_REQ_FIFO_ERROR .
47942 #define BRB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_LL_PA_CNT_ERROR .
47944 #define BRB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_BB_PA_CNT_ERROR .
47946 #define BRB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_INP_FIFO_ERROR .
47948 #define BRB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_SOP_FIFO_ERROR .
47950 #define BRB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_QUEUE_FIFO_ERROR .
47952 #define BRB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_FREE_POINT_FIFO_ERROR .
47954 #define BRB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_NEXT_POINT_FIFO_ERROR .
47956 #define BRB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_STRT_FIFO_ERROR .
47958 #define BRB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_SECOND_DSCR_FIFO_ERROR .
47960 #define BRB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_PKT_AVAIL_FIFO_ERROR .
47962 #define BRB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_COS_CNT_FIFO_ERROR .
47964 #define BRB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_NOTIFY_FIFO_ERROR .
47966 #define BRB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_LL_REQ_FIFO_ERROR .
47968 #define BRB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_LL_PA_CNT_ERROR .
47970 #define BRB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_BB_PA_CNT_ERROR .
47972 #define BRB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_INP_FIFO_ERROR .
47974 #define BRB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_SOP_FIFO_ERROR .
47976 #define BRB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_QUEUE_FIFO_ERROR .
47978 #define BRB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_FREE_POINT_FIFO_ERROR .
47980 #define BRB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_NEXT_POINT_FIFO_ERROR .
47982 #define BRB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_STRT_FIFO_ERROR .
47984 #define BRB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_SECOND_DSCR_FIFO_ERROR .
47986 #define BRB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_PKT_AVAIL_FIFO_ERROR .
47988 #define BRB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_COS_CNT_FIFO_ERROR .
47991 #define BRB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
47993 #define BRB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
47995 #define BRB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
47997 #define BRB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
47999 #define BRB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
48001 #define BRB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
48003 #define BRB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
48005 #define BRB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
48007 #define BRB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
48009 #define BRB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
48011 #define BRB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
48013 #define BRB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
48015 #define BRB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
48017 #define BRB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
48019 #define BRB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
48021 #define BRB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
48023 #define BRB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
48025 #define BRB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
48027 #define BRB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
48029 #define BRB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // Notify FIFO error in write client 5
48031 #define BRB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
48033 #define BRB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
48035 #define BRB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
48037 #define BRB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
48039 #define BRB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
48041 #define BRB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
48043 #define BRB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
48045 #define BRB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
48047 #define BRB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
48049 #define BRB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
48051 #define BRB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
48053 #define BRB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
48056 #define BRB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
48058 #define BRB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
48060 #define BRB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
48062 #define BRB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
48064 #define BRB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
48066 #define BRB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
48068 #define BRB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
48070 #define BRB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
48072 #define BRB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
48074 #define BRB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
48076 #define BRB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
48078 #define BRB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
48080 #define BRB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
48082 #define BRB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
48084 #define BRB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
48086 #define BRB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
48088 #define BRB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
48090 #define BRB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
48092 #define BRB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
48094 #define BRB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // Notify FIFO error in write client 5
48096 #define BRB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
48098 #define BRB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
48100 #define BRB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
48102 #define BRB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
48104 #define BRB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
48106 #define BRB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
48108 #define BRB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
48110 #define BRB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
48112 #define BRB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
48114 #define BRB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
48116 #define BRB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
48118 #define BRB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
48121 #define BRB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
48123 #define BRB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
48125 #define BRB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
48127 #define BRB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
48129 #define BRB_REG_INT_STS_8_WC7_INP_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
48131 #define BRB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
48133 #define BRB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
48135 #define BRB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
48137 #define BRB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
48139 #define BRB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
48141 #define BRB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
48143 #define BRB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
48145 #define BRB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
48147 #define BRB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
48149 #define BRB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
48151 #define BRB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
48153 #define BRB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
48156 #define BRB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
48158 #define BRB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_LL_REQ_FIFO_ERROR .
48160 #define BRB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_LL_PA_CNT_ERROR .
48162 #define BRB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_BB_PA_CNT_ERROR .
48164 #define BRB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_INP_FIFO_ERROR .
48166 #define BRB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_SOP_FIFO_ERROR .
48168 #define BRB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_QUEUE_FIFO_ERROR .
48170 #define BRB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_FREE_POINT_FIFO_ERROR .
48172 #define BRB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_NEXT_POINT_FIFO_ERROR .
48174 #define BRB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_STRT_FIFO_ERROR .
48176 #define BRB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_SECOND_DSCR_FIFO_ERROR .
48178 #define BRB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_PKT_AVAIL_FIFO_ERROR .
48180 #define BRB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_COS_CNT_FIFO_ERROR .
48182 #define BRB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_NOTIFY_FIFO_ERROR .
48184 #define BRB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_LL_REQ_FIFO_ERROR .
48186 #define BRB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_LL_PA_CNT_ERROR .
48188 #define BRB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_BB_PA_CNT_ERROR .
48191 #define BRB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
48193 #define BRB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
48195 #define BRB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
48197 #define BRB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
48199 #define BRB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
48201 #define BRB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
48203 #define BRB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
48205 #define BRB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
48207 #define BRB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
48209 #define BRB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
48211 #define BRB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
48213 #define BRB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
48215 #define BRB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
48217 #define BRB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
48219 #define BRB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
48221 #define BRB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
48223 #define BRB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
48226 #define BRB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
48228 #define BRB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
48230 #define BRB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
48232 #define BRB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
48234 #define BRB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
48236 #define BRB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
48238 #define BRB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
48240 #define BRB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
48242 #define BRB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
48244 #define BRB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
48246 #define BRB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
48248 #define BRB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
48250 #define BRB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
48252 #define BRB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
48254 #define BRB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
48256 #define BRB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
48258 #define BRB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
48260 #define BRB_REG_INT_STS_9 0x34019cUL //Access:R DataWidth:0x1 // Multi Field Register.
48261 #define BRB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
48263 #define BRB_REG_INT_MASK_9 0x3401a0UL //Access:RW DataWidth:0x1 // Multi Field Register.
48264 #define BRB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
48266 #define BRB_REG_INT_STS_WR_9 0x3401a4UL //Access:WR DataWidth:0x1 // Multi Field Register.
48267 #define BRB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
48269 #define BRB_REG_INT_STS_CLR_9 0x3401a8UL //Access:RC DataWidth:0x1 // Multi Field Register.
48270 #define BRB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
48273 #define BRB_REG_INT_STS_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<1) // SOP input SYNC FIFO error (for BRB)
48275 #define BRB_REG_INT_STS_10_RC0_INP_SYNC_FIFO_PUSH_ERROR (0x1<<2) // Packet RC input SYNC FIFO error
48277 #define BRB_REG_INT_STS_10_RC1_INP_SYNC_FIFO_PUSH_ERROR (0x1<<3) // Packet RC input SYNC FIFO error
48279 #define BRB_REG_INT_STS_10_RC2_INP_SYNC_FIFO_PUSH_ERROR (0x1<<4) // Packet RC input SYNC FIFO error
48281 #define BRB_REG_INT_STS_10_RC3_INP_SYNC_FIFO_PUSH_ERROR (0x1<<5) // Packet RC input SYNC FIFO error
48283 #define BRB_REG_INT_STS_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // Packet RC output SYNC FIFO error
48285 #define BRB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // Packet RC output SYNC FIFO error
48287 #define BRB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // Packet RC output SYNC FIFO error
48289 #define BRB_REG_INT_STS_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<15) // Packet RC output SYNC FIFO error
48291 #define BRB_REG_INT_STS_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<16) // Packet RC output SYNC FIFO error
48293 #define BRB_REG_INT_STS_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<22) // EOP RC input SYNC FIFO error
48295 #define BRB_REG_INT_STS_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<23) // EOP RC input SYNC FIFO error
48297 #define BRB_REG_INT_STS_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<24) // EOP RC input SYNC FIFO error
48299 #define BRB_REG_INT_STS_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<25) // EOP RC input SYNC FIFO error
48301 #define BRB_REG_INT_STS_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<26) // EOP RC output SYNC FIFO error
48303 #define BRB_REG_INT_STS_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<27) // EOP RC output SYNC FIFO error
48305 #define BRB_REG_INT_STS_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<28) // EOP RC output SYNC FIFO error
48307 #define BRB_REG_INT_STS_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<29) // EOP RC output SYNC FIFO error
48310 #define BRB_REG_INT_MASK_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC_SOP_INP_SYNC_FIFO_PUSH_ERROR .
48312 #define BRB_REG_INT_MASK_10_RC0_INP_SYNC_FIFO_PUSH_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_INP_SYNC_FIFO_PUSH_ERROR .
48314 #define BRB_REG_INT_MASK_10_RC1_INP_SYNC_FIFO_PUSH_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_INP_SYNC_FIFO_PUSH_ERROR .
48316 #define BRB_REG_INT_MASK_10_RC2_INP_SYNC_FIFO_PUSH_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_INP_SYNC_FIFO_PUSH_ERROR .
48318 #define BRB_REG_INT_MASK_10_RC3_INP_SYNC_FIFO_PUSH_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_INP_SYNC_FIFO_PUSH_ERROR .
48320 #define BRB_REG_INT_MASK_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_OUT_SYNC_FIFO_PUSH_ERROR .
48322 #define BRB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_OUT_SYNC_FIFO_PUSH_ERROR .
48324 #define BRB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_OUT_SYNC_FIFO_PUSH_ERROR .
48326 #define BRB_REG_INT_MASK_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_OUT_SYNC_FIFO_PUSH_ERROR .
48328 #define BRB_REG_INT_MASK_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC4_OUT_SYNC_FIFO_PUSH_ERROR .
48330 #define BRB_REG_INT_MASK_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR .
48332 #define BRB_REG_INT_MASK_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR .
48334 #define BRB_REG_INT_MASK_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR .
48336 #define BRB_REG_INT_MASK_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR .
48338 #define BRB_REG_INT_MASK_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
48340 #define BRB_REG_INT_MASK_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
48342 #define BRB_REG_INT_MASK_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
48344 #define BRB_REG_INT_MASK_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
48347 #define BRB_REG_INT_STS_WR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<1) // SOP input SYNC FIFO error (for BRB)
48349 #define BRB_REG_INT_STS_WR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR (0x1<<2) // Packet RC input SYNC FIFO error
48351 #define BRB_REG_INT_STS_WR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR (0x1<<3) // Packet RC input SYNC FIFO error
48353 #define BRB_REG_INT_STS_WR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR (0x1<<4) // Packet RC input SYNC FIFO error
48355 #define BRB_REG_INT_STS_WR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR (0x1<<5) // Packet RC input SYNC FIFO error
48357 #define BRB_REG_INT_STS_WR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // Packet RC output SYNC FIFO error
48359 #define BRB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // Packet RC output SYNC FIFO error
48361 #define BRB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // Packet RC output SYNC FIFO error
48363 #define BRB_REG_INT_STS_WR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<15) // Packet RC output SYNC FIFO error
48365 #define BRB_REG_INT_STS_WR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<16) // Packet RC output SYNC FIFO error
48367 #define BRB_REG_INT_STS_WR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<22) // EOP RC input SYNC FIFO error
48369 #define BRB_REG_INT_STS_WR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<23) // EOP RC input SYNC FIFO error
48371 #define BRB_REG_INT_STS_WR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<24) // EOP RC input SYNC FIFO error
48373 #define BRB_REG_INT_STS_WR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<25) // EOP RC input SYNC FIFO error
48375 #define BRB_REG_INT_STS_WR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<26) // EOP RC output SYNC FIFO error
48377 #define BRB_REG_INT_STS_WR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<27) // EOP RC output SYNC FIFO error
48379 #define BRB_REG_INT_STS_WR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<28) // EOP RC output SYNC FIFO error
48381 #define BRB_REG_INT_STS_WR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<29) // EOP RC output SYNC FIFO error
48384 #define BRB_REG_INT_STS_CLR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<1) // SOP input SYNC FIFO error (for BRB)
48386 #define BRB_REG_INT_STS_CLR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR (0x1<<2) // Packet RC input SYNC FIFO error
48388 #define BRB_REG_INT_STS_CLR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR (0x1<<3) // Packet RC input SYNC FIFO error
48390 #define BRB_REG_INT_STS_CLR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR (0x1<<4) // Packet RC input SYNC FIFO error
48392 #define BRB_REG_INT_STS_CLR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR (0x1<<5) // Packet RC input SYNC FIFO error
48394 #define BRB_REG_INT_STS_CLR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // Packet RC output SYNC FIFO error
48396 #define BRB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // Packet RC output SYNC FIFO error
48398 #define BRB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // Packet RC output SYNC FIFO error
48400 #define BRB_REG_INT_STS_CLR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<15) // Packet RC output SYNC FIFO error
48402 #define BRB_REG_INT_STS_CLR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<16) // Packet RC output SYNC FIFO error
48404 #define BRB_REG_INT_STS_CLR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<22) // EOP RC input SYNC FIFO error
48406 #define BRB_REG_INT_STS_CLR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<23) // EOP RC input SYNC FIFO error
48408 #define BRB_REG_INT_STS_CLR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<24) // EOP RC input SYNC FIFO error
48410 #define BRB_REG_INT_STS_CLR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<25) // EOP RC input SYNC FIFO error
48412 #define BRB_REG_INT_STS_CLR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<26) // EOP RC output SYNC FIFO error
48414 #define BRB_REG_INT_STS_CLR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<27) // EOP RC output SYNC FIFO error
48416 #define BRB_REG_INT_STS_CLR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<28) // EOP RC output SYNC FIFO error
48418 #define BRB_REG_INT_STS_CLR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<29) // EOP RC output SYNC FIFO error
48421 #define BRB_REG_INT_STS_11_RC2_EOP_ERROR (0x1<<10) // Read EOP client 2 request FIFO error
48423 #define BRB_REG_INT_STS_11_RC3_EOP_ERROR (0x1<<11) // Read EOP client 2 request FIFO error
48425 #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2
48427 #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3
48429 #define BRB_REG_INT_STS_11_WC4_EOP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
48431 #define BRB_REG_INT_STS_11_WC5_EOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
48433 #define BRB_REG_INT_STS_11_WC6_EOP_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
48435 #define BRB_REG_INT_STS_11_WC7_EOP_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
48438 #define BRB_REG_INT_MASK_11_RC2_EOP_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.RC2_EOP_ERROR .
48440 #define BRB_REG_INT_MASK_11_RC3_EOP_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.RC3_EOP_ERROR .
48442 #define BRB_REG_INT_MASK_11_MAC2_FC_CNT_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.MAC2_FC_CNT_ERROR .
48444 #define BRB_REG_INT_MASK_11_MAC3_FC_CNT_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.MAC3_FC_CNT_ERROR .
48446 #define BRB_REG_INT_MASK_11_WC4_EOP_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC4_EOP_FIFO_ERROR .
48448 #define BRB_REG_INT_MASK_11_WC5_EOP_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC5_EOP_FIFO_ERROR .
48450 #define BRB_REG_INT_MASK_11_WC6_EOP_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC6_EOP_FIFO_ERROR .
48452 #define BRB_REG_INT_MASK_11_WC7_EOP_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC7_EOP_FIFO_ERROR .
48455 #define BRB_REG_INT_STS_WR_11_RC2_EOP_ERROR (0x1<<10) // Read EOP client 2 request FIFO error
48457 #define BRB_REG_INT_STS_WR_11_RC3_EOP_ERROR (0x1<<11) // Read EOP client 2 request FIFO error
48459 #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2
48461 #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3
48463 #define BRB_REG_INT_STS_WR_11_WC4_EOP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
48465 #define BRB_REG_INT_STS_WR_11_WC5_EOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
48467 #define BRB_REG_INT_STS_WR_11_WC6_EOP_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
48469 #define BRB_REG_INT_STS_WR_11_WC7_EOP_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
48472 #define BRB_REG_INT_STS_CLR_11_RC2_EOP_ERROR (0x1<<10) // Read EOP client 2 request FIFO error
48474 #define BRB_REG_INT_STS_CLR_11_RC3_EOP_ERROR (0x1<<11) // Read EOP client 2 request FIFO error
48476 #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2
48478 #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3
48480 #define BRB_REG_INT_STS_CLR_11_WC4_EOP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
48482 #define BRB_REG_INT_STS_CLR_11_WC5_EOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
48484 #define BRB_REG_INT_STS_CLR_11_WC6_EOP_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
48486 #define BRB_REG_INT_STS_CLR_11_WC7_EOP_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
48489 #define BRB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
48491 #define BRB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
48493 #define BRB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
48495 #define BRB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
48497 #define BRB_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.DATAPATH_REGISTERS .
48500 #define BRB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
48502 #define BRB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
48504 #define BRB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
48506 #define BRB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
48508 #define BRB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
48510 #define BRB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
48512 #define BRB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
48514 #define BRB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
48516 #define BRB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
48518 #define BRB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
48520 #define BRB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
48522 #define BRB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
48524 #define BRB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
48526 #define BRB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
48528 #define BRB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT (0x1<<14) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
48530 #define BRB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT (0x1<<15) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
48532 #define BRB_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY .
48534 #define BRB_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY .
48536 #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
48538 #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
48540 #define BRB_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
48542 #define BRB_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
48544 #define BRB_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
48546 #define BRB_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
48548 #define BRB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
48550 #define BRB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
48552 #define BRB_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
48554 #define BRB_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
48556 #define BRB_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
48558 #define BRB_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
48560 #define BRB_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY .
48562 #define BRB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
48564 #define BRB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
48566 #define BRB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
48568 #define BRB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
48570 #define BRB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM049_I_MEM_PRTY .
48572 #define BRB_REG_PRTY_MASK_H_0_MEM050_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM050_I_MEM_PRTY .
48574 #define BRB_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
48576 #define BRB_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY .
48578 #define BRB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
48580 #define BRB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
48582 #define BRB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
48584 #define BRB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
48586 #define BRB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
48589 #define BRB_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
48591 #define BRB_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
48593 #define BRB_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
48595 #define BRB_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
48597 #define BRB_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
48599 #define BRB_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
48601 #define BRB_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
48603 #define BRB_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
48605 #define BRB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
48607 #define BRB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
48609 #define BRB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
48611 #define BRB_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
48613 #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
48615 #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
48617 #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
48619 #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
48621 #define BRB_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
48623 #define BRB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
48625 #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
48627 #define BRB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
48629 #define BRB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
48631 #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
48633 #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
48635 #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
48637 #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
48639 #define BRB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
48641 #define BRB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
48643 #define BRB_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
48645 #define BRB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
48647 #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
48649 #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
48651 #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
48653 #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
48655 #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
48658 #define BRB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48660 #define BRB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48662 #define BRB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48664 #define BRB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48666 #define BRB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48668 #define BRB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48670 #define BRB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN (0x1<<6) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48672 #define BRB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN (0x1<<7) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48674 #define BRB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48676 #define BRB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN (0x1<<9) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48678 #define BRB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<10) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48680 #define BRB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<11) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48682 #define BRB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<12) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48684 #define BRB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<13) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48686 #define BRB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN (0x1<<14) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48688 #define BRB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN (0x1<<15) // Enable ECC for memory ecc instance brb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48692 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48694 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48696 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48698 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48700 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48702 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48704 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY (0x1<<6) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48706 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY (0x1<<7) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48708 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48710 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY (0x1<<9) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48712 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<10) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48714 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<11) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48716 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<12) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48718 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<13) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48720 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY (0x1<<14) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48722 #define BRB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY (0x1<<15) // Set parity only for memory ecc instance brb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48726 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48728 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48730 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48732 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48734 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48736 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48738 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48740 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48742 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48744 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48746 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<10) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48748 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<11) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48750 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<12) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48752 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<13) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48754 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT (0x1<<14) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48756 #define BRB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT (0x1<<15) // Record if a correctable error occurred on memory ecc instance brb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module brb_bb_bank_bigbear
48988 #define BRB_REG_LOSSLESS_INT_EN 0x340db4UL //Access:RW DataWidth:0x1 // If 1 then interrupt will be asserted when number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC will be asserted.::/PAUSE_EN/d in Existance.
49008 #define BRB_REG_BR_FIX_HIGH_PRI_COLLISION 0x340ddcUL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
49045 #define BRB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure.
49054 #define BRB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure.
49060 #define BRB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN (0x1<<23) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set. This bit should be set after init procedure.
49062 #define BRB_REG_OUT_IF_ENABLE_STOP_PARSING_OUT_IF_EN (0x1<<24) // There is bit for stop parsing interfaces. When bit is set then stop parsing interface is enabled. When bit is reset then stop parsing interface will never be set. This bit should be set after init procedure. ::/PAUSE_EN/d in Existance.
49064 #define BRB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN (0x1<<25) // There is bit for power management interfaces. When bit is set then power management interface is enabled. When bit is reset then power management interface will never be set. This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
49240 #define BRB_REG_MEMCTRL_WR_RD_N 0x341c00UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
49253 #define XYLD_REG_TCFC_LOAD_MINI_CACHE_EN 0x4c001cUL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
49254 #define XYLD_REG_CCFC_LOAD_MINI_CACHE_EN 0x4c0020UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
49295 #define XYLD_REG_LD_HDR_CLR 0x4c00c4UL //Access:W DataWidth:0x1 // Writing to this register clears hdr registers and enables logging new error details.
49300 #define XYLD_REG_SEG_MSG_LOG_CLR 0x4c00d8UL //Access:W DataWidth:0x1 // Writing to this register clears seg msg logging registers and enables logging new error details::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
49301 #define XYLD_REG_SEG_MSG_LOG_V 0x4c00dcUL //Access:R DataWidth:0x1 // Indicates that the data at the seg_msg logging registers is valid::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.
49307 #define XYLD_REG_LEN_ERR_LOG_CLR 0x4c00f4UL //Access:W DataWidth:0x1 // Writing to this register clears len err logging registers and enables logging new error details.
49308 #define XYLD_REG_LEN_ERR_LOG_V 0x4c00f8UL //Access:R DataWidth:0x1 // Indicates that the data at the len_err logging registers is valid.
49310 #define XYLD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49312 #define XYLD_REG_INT_STS_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49314 #define XYLD_REG_INT_STS_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49316 #define XYLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49318 #define XYLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49320 #define XYLD_REG_INT_STS_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49323 #define XYLD_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.ADDRESS_ERROR .
49325 #define XYLD_REG_INT_MASK_LD_HDR_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_HDR_ERR .
49327 #define XYLD_REG_INT_MASK_LD_SEG_MSG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_SEG_MSG_ERR .
49329 #define XYLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
49331 #define XYLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
49333 #define XYLD_REG_INT_MASK_LD_LONG_MESSAGE (0x1<<5) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_LONG_MESSAGE .
49336 #define XYLD_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49338 #define XYLD_REG_INT_STS_WR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49340 #define XYLD_REG_INT_STS_WR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49342 #define XYLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49344 #define XYLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49346 #define XYLD_REG_INT_STS_WR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49349 #define XYLD_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49351 #define XYLD_REG_INT_STS_CLR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49353 #define XYLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49355 #define XYLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49357 #define XYLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49359 #define XYLD_REG_INT_STS_CLR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49362 #define XYLD_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
49364 #define XYLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
49366 #define XYLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
49368 #define XYLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
49370 #define XYLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
49372 #define XYLD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
49374 #define XYLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
49376 #define XYLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
49378 #define XYLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
49381 #define XYLD_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_ram_1
49383 #define XYLD_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rsep_buf_ram
49386 #define XYLD_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_ram_1
49388 #define XYLD_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rsep_buf_ram
49391 #define XYLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance xyld.i_msgq_ram.i_ecc in module xyld_i_msgq_ram_1
49393 #define XYLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance xyld.i_pci_rsep_buf_ram.i_ecc in module xyld_i_pci_rsep_buf_ram
49401 #define XYLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN (0x1<<0) // Enables L2 message aggregation
49403 #define XYLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
49405 #define XYLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK (0x1<<2) // defines that only back-to-back aggregation is allowed
49567 #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0 (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
49569 #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1 (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
49571 #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2 (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
49573 #define XYLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3 (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
49629 #define YULD_REG_TCFC_LOAD_MINI_CACHE_EN 0x4c8014UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
49630 #define YULD_REG_CCFC_LOAD_MINI_CACHE_EN 0x4c8018UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
49666 #define YULD_REG_LD_HDR_CLR 0x4c80a8UL //Access:W DataWidth:0x1 // Writing to this register clears hdr registers and enables logging new error details.
49672 #define YULD_REG_LEN_ERR_LOG_CLR 0x4c80c0UL //Access:W DataWidth:0x1 // Writing to this register clears len err logging registers and enables logging new error details.
49673 #define YULD_REG_LEN_ERR_LOG_V 0x4c80c4UL //Access:R DataWidth:0x1 // Indicates that the data at the len_err logging registers is valid.
49675 #define YULD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49677 #define YULD_REG_INT_STS_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49679 #define YULD_REG_INT_STS_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49681 #define YULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49683 #define YULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49685 #define YULD_REG_INT_STS_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49688 #define YULD_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.ADDRESS_ERROR .
49690 #define YULD_REG_INT_MASK_LD_HDR_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_HDR_ERR .
49692 #define YULD_REG_INT_MASK_LD_SEG_MSG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_SEG_MSG_ERR .
49694 #define YULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
49696 #define YULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
49698 #define YULD_REG_INT_MASK_LD_LONG_MESSAGE (0x1<<5) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_LONG_MESSAGE .
49701 #define YULD_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49703 #define YULD_REG_INT_STS_WR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49705 #define YULD_REG_INT_STS_WR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49707 #define YULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49709 #define YULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49711 #define YULD_REG_INT_STS_WR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49714 #define YULD_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49716 #define YULD_REG_INT_STS_CLR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49718 #define YULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49720 #define YULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49722 #define YULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49724 #define YULD_REG_INT_STS_CLR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49727 #define YULD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
49729 #define YULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
49731 #define YULD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
49733 #define YULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
49735 #define YULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
49737 #define YULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
49762 #define TMLD_REG_TCFC_LOAD_MINI_CACHE_EN 0x4d0014UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
49763 #define TMLD_REG_CCFC_LOAD_MINI_CACHE_EN 0x4d0018UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
49768 #define TMLD_REG_BRB_SWAP_EN 0x4d002cUL //Access:RW DataWidth:0x1 // When set the data returning from the BRB is swapped. meaning that bytes 0-3 is swapped with bytes 4-7 in each 64b boundary
49804 #define TMLD_REG_LD_HDR_CLR 0x4d00bcUL //Access:W DataWidth:0x1 // Writing to this register clears hdr registers and enables logging new error details.
49810 #define TMLD_REG_LEN_ERR_LOG_CLR 0x4d00d4UL //Access:W DataWidth:0x1 // Writing to this register clears len err logging registers and enables logging new error details.
49811 #define TMLD_REG_LEN_ERR_LOG_V 0x4d00d8UL //Access:R DataWidth:0x1 // Indicates that the data at the len_err logging registers is valid.
49813 #define TMLD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49815 #define TMLD_REG_INT_STS_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49817 #define TMLD_REG_INT_STS_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49819 #define TMLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49821 #define TMLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49823 #define TMLD_REG_INT_STS_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49826 #define TMLD_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.ADDRESS_ERROR .
49828 #define TMLD_REG_INT_MASK_LD_HDR_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_HDR_ERR .
49830 #define TMLD_REG_INT_MASK_LD_SEG_MSG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_SEG_MSG_ERR .
49832 #define TMLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
49834 #define TMLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
49836 #define TMLD_REG_INT_MASK_LD_LONG_MESSAGE (0x1<<5) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_LONG_MESSAGE .
49839 #define TMLD_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49841 #define TMLD_REG_INT_STS_WR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49843 #define TMLD_REG_INT_STS_WR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49845 #define TMLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49847 #define TMLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49849 #define TMLD_REG_INT_STS_WR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49852 #define TMLD_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
49854 #define TMLD_REG_INT_STS_CLR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
49856 #define TMLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
49858 #define TMLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
49860 #define TMLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
49862 #define TMLD_REG_INT_STS_CLR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
49865 #define TMLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
49867 #define TMLD_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
49869 #define TMLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
49871 #define TMLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
49873 #define TMLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
49875 #define TMLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
49877 #define TMLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
49879 #define TMLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
49882 #define TMLD_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_ram_1
49884 #define TMLD_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_resp_buf_ram
49887 #define TMLD_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_ram_1
49889 #define TMLD_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_resp_buf_ram
49892 #define TMLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance tmld.i_msgq_ram.i_ecc in module tmld_i_msgq_ram_1
49894 #define TMLD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance tmld.i_brb_resp_buf_ram.i_ecc in module tmld_i_brb_resp_buf_ram
49902 #define TMLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN (0x1<<0) // Enables L2 message aggregation
49904 #define TMLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
49906 #define TMLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK (0x1<<2) // defines that only back-to-back aggregation is allowed
50068 #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0 (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
50070 #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1 (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
50072 #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2 (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
50074 #define TMLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3 (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
50138 #define MULD_REG_TCFC_LOAD_MINI_CACHE_EN 0x4e0034UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
50139 #define MULD_REG_CCFC_LOAD_MINI_CACHE_EN 0x4e0038UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
50181 #define MULD_REG_LD_HDR_CLR 0x4e00e0UL //Access:W DataWidth:0x1 // Writing to this register clears hdr registers and enables logging new error details.
50187 #define MULD_REG_LEN_ERR_LOG_CLR 0x4e00f8UL //Access:W DataWidth:0x1 // Writing to this register clears len err logging registers and enables logging new error details.
50188 #define MULD_REG_LEN_ERR_LOG_V 0x4e00fcUL //Access:R DataWidth:0x1 // Indicates that the data at the len_err logging registers is valid.
50190 #define MULD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
50192 #define MULD_REG_INT_STS_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
50194 #define MULD_REG_INT_STS_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
50196 #define MULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
50198 #define MULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
50200 #define MULD_REG_INT_STS_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
50203 #define MULD_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.ADDRESS_ERROR .
50205 #define MULD_REG_INT_MASK_LD_HDR_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_HDR_ERR .
50207 #define MULD_REG_INT_MASK_LD_SEG_MSG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_SEG_MSG_ERR .
50209 #define MULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
50211 #define MULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
50213 #define MULD_REG_INT_MASK_LD_LONG_MESSAGE (0x1<<5) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_LONG_MESSAGE .
50216 #define MULD_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
50218 #define MULD_REG_INT_STS_WR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
50220 #define MULD_REG_INT_STS_WR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
50222 #define MULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
50224 #define MULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
50226 #define MULD_REG_INT_STS_WR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
50229 #define MULD_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
50231 #define MULD_REG_INT_STS_CLR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
50233 #define MULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
50235 #define MULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
50237 #define MULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
50239 #define MULD_REG_INT_STS_CLR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
50242 #define MULD_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
50244 #define MULD_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
50246 #define MULD_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
50248 #define MULD_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
50250 #define MULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
50252 #define MULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
50254 #define MULD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
50256 #define MULD_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
50258 #define MULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
50260 #define MULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
50263 #define MULD_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_ram_1
50265 #define MULD_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_ram_1
50267 #define MULD_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db_ram_1
50269 #define MULD_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rsep_buf_ram_1
50272 #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_ram_1
50274 #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_ram_1
50276 #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db_ram_1
50278 #define MULD_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rsep_buf_ram_1
50281 #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance muld.i_msgq_ram.i_ecc in module muld_i_msgq_ram_1
50283 #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance muld.i_bd_db_ram.i_ecc in module muld_i_bd_db_ram_1
50285 #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance muld.i_sge_db_ram.i_ecc in module muld_i_sge_db_ram_1
50287 #define MULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance muld.i_pci_rsep_buf_ram.i_ecc in module muld_i_pci_rsep_buf_ram_1
50299 #define MULD_REG_L2MA_AGGR_CONFIG1_L2MA_EN (0x1<<0) // Enables L2 message aggregation
50301 #define MULD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation).
50303 #define MULD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK (0x1<<2) // defines that only back-to-back aggregation is allowed
50465 #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0 (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
50467 #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1 (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
50469 #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2 (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
50471 #define MULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3 (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
50528 #define NIG_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
50530 #define NIG_REG_INT_STS_0_DEBUG_FIFO_ERROR (0x1<<1) // FIFO error in debug traffic FIFO.
50532 #define NIG_REG_INT_STS_0_DORQ_FIFO_ERROR (0x1<<2) // FIFO error in DORQ FIFO.
50534 #define NIG_REG_INT_STS_0_DBG_SYNCFIFO_ERROR_WR (0x1<<3) // FIFO error in debug traffic sync FIFO.
50536 #define NIG_REG_INT_STS_0_DORQ_SYNCFIFO_ERROR_WR (0x1<<4) // FIFO error in DORQ sync FIFO.
50538 #define NIG_REG_INT_STS_0_STORM_SYNCFIFO_ERROR_WR (0x1<<5) // FIFO error in STORM sync FIFO.
50540 #define NIG_REG_INT_STS_0_DBGMUX_SYNCFIFO_ERROR_WR (0x1<<6) // FIFO error in DBGMUX sync FIFO.
50542 #define NIG_REG_INT_STS_0_MSDM_SYNCFIFO_ERROR_WR (0x1<<7) // FIFO error in MSDM sync FIFO.
50544 #define NIG_REG_INT_STS_0_TSDM_SYNCFIFO_ERROR_WR (0x1<<8) // FIFO error in TSDM sync FIFO.
50546 #define NIG_REG_INT_STS_0_USDM_SYNCFIFO_ERROR_WR (0x1<<9) // FIFO error in USDM sync FIFO.
50548 #define NIG_REG_INT_STS_0_XSDM_SYNCFIFO_ERROR_WR (0x1<<10) // FIFO error in XSDM sync FIFO.
50550 #define NIG_REG_INT_STS_0_YSDM_SYNCFIFO_ERROR_WR (0x1<<11) // FIFO error in YSDM sync FIFO.
50553 #define NIG_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.ADDRESS_ERROR .
50555 #define NIG_REG_INT_MASK_0_DEBUG_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DEBUG_FIFO_ERROR .
50557 #define NIG_REG_INT_MASK_0_DORQ_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DORQ_FIFO_ERROR .
50559 #define NIG_REG_INT_MASK_0_DBG_SYNCFIFO_ERROR_WR (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DBG_SYNCFIFO_ERROR_WR .
50561 #define NIG_REG_INT_MASK_0_DORQ_SYNCFIFO_ERROR_WR (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DORQ_SYNCFIFO_ERROR_WR .
50563 #define NIG_REG_INT_MASK_0_STORM_SYNCFIFO_ERROR_WR (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.STORM_SYNCFIFO_ERROR_WR .
50565 #define NIG_REG_INT_MASK_0_DBGMUX_SYNCFIFO_ERROR_WR (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DBGMUX_SYNCFIFO_ERROR_WR .
50567 #define NIG_REG_INT_MASK_0_MSDM_SYNCFIFO_ERROR_WR (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.MSDM_SYNCFIFO_ERROR_WR .
50569 #define NIG_REG_INT_MASK_0_TSDM_SYNCFIFO_ERROR_WR (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.TSDM_SYNCFIFO_ERROR_WR .
50571 #define NIG_REG_INT_MASK_0_USDM_SYNCFIFO_ERROR_WR (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.USDM_SYNCFIFO_ERROR_WR .
50573 #define NIG_REG_INT_MASK_0_XSDM_SYNCFIFO_ERROR_WR (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.XSDM_SYNCFIFO_ERROR_WR .
50575 #define NIG_REG_INT_MASK_0_YSDM_SYNCFIFO_ERROR_WR (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.YSDM_SYNCFIFO_ERROR_WR .
50578 #define NIG_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
50580 #define NIG_REG_INT_STS_WR_0_DEBUG_FIFO_ERROR (0x1<<1) // FIFO error in debug traffic FIFO.
50582 #define NIG_REG_INT_STS_WR_0_DORQ_FIFO_ERROR (0x1<<2) // FIFO error in DORQ FIFO.
50584 #define NIG_REG_INT_STS_WR_0_DBG_SYNCFIFO_ERROR_WR (0x1<<3) // FIFO error in debug traffic sync FIFO.
50586 #define NIG_REG_INT_STS_WR_0_DORQ_SYNCFIFO_ERROR_WR (0x1<<4) // FIFO error in DORQ sync FIFO.
50588 #define NIG_REG_INT_STS_WR_0_STORM_SYNCFIFO_ERROR_WR (0x1<<5) // FIFO error in STORM sync FIFO.
50590 #define NIG_REG_INT_STS_WR_0_DBGMUX_SYNCFIFO_ERROR_WR (0x1<<6) // FIFO error in DBGMUX sync FIFO.
50592 #define NIG_REG_INT_STS_WR_0_MSDM_SYNCFIFO_ERROR_WR (0x1<<7) // FIFO error in MSDM sync FIFO.
50594 #define NIG_REG_INT_STS_WR_0_TSDM_SYNCFIFO_ERROR_WR (0x1<<8) // FIFO error in TSDM sync FIFO.
50596 #define NIG_REG_INT_STS_WR_0_USDM_SYNCFIFO_ERROR_WR (0x1<<9) // FIFO error in USDM sync FIFO.
50598 #define NIG_REG_INT_STS_WR_0_XSDM_SYNCFIFO_ERROR_WR (0x1<<10) // FIFO error in XSDM sync FIFO.
50600 #define NIG_REG_INT_STS_WR_0_YSDM_SYNCFIFO_ERROR_WR (0x1<<11) // FIFO error in YSDM sync FIFO.
50603 #define NIG_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
50605 #define NIG_REG_INT_STS_CLR_0_DEBUG_FIFO_ERROR (0x1<<1) // FIFO error in debug traffic FIFO.
50607 #define NIG_REG_INT_STS_CLR_0_DORQ_FIFO_ERROR (0x1<<2) // FIFO error in DORQ FIFO.
50609 #define NIG_REG_INT_STS_CLR_0_DBG_SYNCFIFO_ERROR_WR (0x1<<3) // FIFO error in debug traffic sync FIFO.
50611 #define NIG_REG_INT_STS_CLR_0_DORQ_SYNCFIFO_ERROR_WR (0x1<<4) // FIFO error in DORQ sync FIFO.
50613 #define NIG_REG_INT_STS_CLR_0_STORM_SYNCFIFO_ERROR_WR (0x1<<5) // FIFO error in STORM sync FIFO.
50615 #define NIG_REG_INT_STS_CLR_0_DBGMUX_SYNCFIFO_ERROR_WR (0x1<<6) // FIFO error in DBGMUX sync FIFO.
50617 #define NIG_REG_INT_STS_CLR_0_MSDM_SYNCFIFO_ERROR_WR (0x1<<7) // FIFO error in MSDM sync FIFO.
50619 #define NIG_REG_INT_STS_CLR_0_TSDM_SYNCFIFO_ERROR_WR (0x1<<8) // FIFO error in TSDM sync FIFO.
50621 #define NIG_REG_INT_STS_CLR_0_USDM_SYNCFIFO_ERROR_WR (0x1<<9) // FIFO error in USDM sync FIFO.
50623 #define NIG_REG_INT_STS_CLR_0_XSDM_SYNCFIFO_ERROR_WR (0x1<<10) // FIFO error in XSDM sync FIFO.
50625 #define NIG_REG_INT_STS_CLR_0_YSDM_SYNCFIFO_ERROR_WR (0x1<<11) // FIFO error in YSDM sync FIFO.
50628 #define NIG_REG_INT_STS_1_TX_SOPQ0_ERROR (0x1<<0) // Error in the TX SOPQ.
50630 #define NIG_REG_INT_STS_1_TX_SOPQ1_ERROR (0x1<<1) // Error in the TX SOPQ.
50632 #define NIG_REG_INT_STS_1_TX_SOPQ2_ERROR (0x1<<2) // Error in the TX SOPQ.
50634 #define NIG_REG_INT_STS_1_TX_SOPQ3_ERROR (0x1<<3) // Error in the TX SOPQ.
50636 #define NIG_REG_INT_STS_1_TX_SOPQ4_ERROR (0x1<<4) // Error in the TX SOPQ.
50638 #define NIG_REG_INT_STS_1_TX_SOPQ5_ERROR (0x1<<5) // Error in the TX SOPQ.
50640 #define NIG_REG_INT_STS_1_TX_SOPQ6_ERROR (0x1<<6) // Error in the TX SOPQ.
50642 #define NIG_REG_INT_STS_1_TX_SOPQ7_ERROR (0x1<<7) // Error in the TX SOPQ.
50644 #define NIG_REG_INT_STS_1_TX_SOPQ8_ERROR (0x1<<8) // Error in the TX SOPQ.
50646 #define NIG_REG_INT_STS_1_TX_SOPQ9_ERROR (0x1<<9) // Error in the TX SOPQ.
50648 #define NIG_REG_INT_STS_1_TX_SOPQ10_ERROR (0x1<<10) // Error in the TX SOPQ.
50650 #define NIG_REG_INT_STS_1_TX_SOPQ11_ERROR (0x1<<11) // Error in the TX SOPQ.
50652 #define NIG_REG_INT_STS_1_TX_SOPQ12_ERROR (0x1<<12) // Error in the TX SOPQ.
50654 #define NIG_REG_INT_STS_1_TX_SOPQ13_ERROR (0x1<<13) // Error in the TX SOPQ.
50656 #define NIG_REG_INT_STS_1_TX_SOPQ14_ERROR (0x1<<14) // Error in the TX SOPQ.
50658 #define NIG_REG_INT_STS_1_TX_SOPQ15_ERROR (0x1<<15) // Error in the TX SOPQ.
50660 #define NIG_REG_INT_STS_1_LB_SOPQ0_ERROR (0x1<<16) // Error in the LB SOPQ.
50662 #define NIG_REG_INT_STS_1_LB_SOPQ1_ERROR (0x1<<17) // Error in the LB SOPQ.
50664 #define NIG_REG_INT_STS_1_LB_SOPQ2_ERROR (0x1<<18) // Error in the LB SOPQ.
50666 #define NIG_REG_INT_STS_1_LB_SOPQ3_ERROR (0x1<<19) // Error in the LB SOPQ.
50668 #define NIG_REG_INT_STS_1_LB_SOPQ4_ERROR (0x1<<20) // Error in the LB SOPQ.
50670 #define NIG_REG_INT_STS_1_LB_SOPQ5_ERROR (0x1<<21) // Error in the LB SOPQ.
50672 #define NIG_REG_INT_STS_1_LB_SOPQ6_ERROR (0x1<<22) // Error in the LB SOPQ.
50674 #define NIG_REG_INT_STS_1_LB_SOPQ7_ERROR (0x1<<23) // Error in the LB SOPQ.
50676 #define NIG_REG_INT_STS_1_LB_SOPQ8_ERROR (0x1<<24) // Error in the LB SOPQ.
50678 #define NIG_REG_INT_STS_1_LB_SOPQ9_ERROR (0x1<<25) // Error in the LB SOPQ.
50680 #define NIG_REG_INT_STS_1_LB_SOPQ10_ERROR (0x1<<26) // Error in the LB SOPQ.
50682 #define NIG_REG_INT_STS_1_LB_SOPQ11_ERROR (0x1<<27) // Error in the LB SOPQ.
50684 #define NIG_REG_INT_STS_1_LB_SOPQ12_ERROR (0x1<<28) // Error in the LB SOPQ.
50686 #define NIG_REG_INT_STS_1_LB_SOPQ13_ERROR (0x1<<29) // Error in the LB SOPQ.
50688 #define NIG_REG_INT_STS_1_LB_SOPQ14_ERROR (0x1<<30) // Error in the LB SOPQ.
50690 #define NIG_REG_INT_STS_1_LB_SOPQ15_ERROR (0x1<<31) // Error in the LB SOPQ.
50693 #define NIG_REG_INT_MASK_1_TX_SOPQ0_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ0_ERROR .
50695 #define NIG_REG_INT_MASK_1_TX_SOPQ1_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ1_ERROR .
50697 #define NIG_REG_INT_MASK_1_TX_SOPQ2_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ2_ERROR .
50699 #define NIG_REG_INT_MASK_1_TX_SOPQ3_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ3_ERROR .
50701 #define NIG_REG_INT_MASK_1_TX_SOPQ4_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ4_ERROR .
50703 #define NIG_REG_INT_MASK_1_TX_SOPQ5_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ5_ERROR .
50705 #define NIG_REG_INT_MASK_1_TX_SOPQ6_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ6_ERROR .
50707 #define NIG_REG_INT_MASK_1_TX_SOPQ7_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ7_ERROR .
50709 #define NIG_REG_INT_MASK_1_TX_SOPQ8_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ8_ERROR .
50711 #define NIG_REG_INT_MASK_1_TX_SOPQ9_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ9_ERROR .
50713 #define NIG_REG_INT_MASK_1_TX_SOPQ10_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ10_ERROR .
50715 #define NIG_REG_INT_MASK_1_TX_SOPQ11_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ11_ERROR .
50717 #define NIG_REG_INT_MASK_1_TX_SOPQ12_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ12_ERROR .
50719 #define NIG_REG_INT_MASK_1_TX_SOPQ13_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ13_ERROR .
50721 #define NIG_REG_INT_MASK_1_TX_SOPQ14_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ14_ERROR .
50723 #define NIG_REG_INT_MASK_1_TX_SOPQ15_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ15_ERROR .
50725 #define NIG_REG_INT_MASK_1_LB_SOPQ0_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ0_ERROR .
50727 #define NIG_REG_INT_MASK_1_LB_SOPQ1_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ1_ERROR .
50729 #define NIG_REG_INT_MASK_1_LB_SOPQ2_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ2_ERROR .
50731 #define NIG_REG_INT_MASK_1_LB_SOPQ3_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ3_ERROR .
50733 #define NIG_REG_INT_MASK_1_LB_SOPQ4_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ4_ERROR .
50735 #define NIG_REG_INT_MASK_1_LB_SOPQ5_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ5_ERROR .
50737 #define NIG_REG_INT_MASK_1_LB_SOPQ6_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ6_ERROR .
50739 #define NIG_REG_INT_MASK_1_LB_SOPQ7_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ7_ERROR .
50741 #define NIG_REG_INT_MASK_1_LB_SOPQ8_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ8_ERROR .
50743 #define NIG_REG_INT_MASK_1_LB_SOPQ9_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ9_ERROR .
50745 #define NIG_REG_INT_MASK_1_LB_SOPQ10_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ10_ERROR .
50747 #define NIG_REG_INT_MASK_1_LB_SOPQ11_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ11_ERROR .
50749 #define NIG_REG_INT_MASK_1_LB_SOPQ12_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ12_ERROR .
50751 #define NIG_REG_INT_MASK_1_LB_SOPQ13_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ13_ERROR .
50753 #define NIG_REG_INT_MASK_1_LB_SOPQ14_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ14_ERROR .
50755 #define NIG_REG_INT_MASK_1_LB_SOPQ15_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ15_ERROR .
50758 #define NIG_REG_INT_STS_WR_1_TX_SOPQ0_ERROR (0x1<<0) // Error in the TX SOPQ.
50760 #define NIG_REG_INT_STS_WR_1_TX_SOPQ1_ERROR (0x1<<1) // Error in the TX SOPQ.
50762 #define NIG_REG_INT_STS_WR_1_TX_SOPQ2_ERROR (0x1<<2) // Error in the TX SOPQ.
50764 #define NIG_REG_INT_STS_WR_1_TX_SOPQ3_ERROR (0x1<<3) // Error in the TX SOPQ.
50766 #define NIG_REG_INT_STS_WR_1_TX_SOPQ4_ERROR (0x1<<4) // Error in the TX SOPQ.
50768 #define NIG_REG_INT_STS_WR_1_TX_SOPQ5_ERROR (0x1<<5) // Error in the TX SOPQ.
50770 #define NIG_REG_INT_STS_WR_1_TX_SOPQ6_ERROR (0x1<<6) // Error in the TX SOPQ.
50772 #define NIG_REG_INT_STS_WR_1_TX_SOPQ7_ERROR (0x1<<7) // Error in the TX SOPQ.
50774 #define NIG_REG_INT_STS_WR_1_TX_SOPQ8_ERROR (0x1<<8) // Error in the TX SOPQ.
50776 #define NIG_REG_INT_STS_WR_1_TX_SOPQ9_ERROR (0x1<<9) // Error in the TX SOPQ.
50778 #define NIG_REG_INT_STS_WR_1_TX_SOPQ10_ERROR (0x1<<10) // Error in the TX SOPQ.
50780 #define NIG_REG_INT_STS_WR_1_TX_SOPQ11_ERROR (0x1<<11) // Error in the TX SOPQ.
50782 #define NIG_REG_INT_STS_WR_1_TX_SOPQ12_ERROR (0x1<<12) // Error in the TX SOPQ.
50784 #define NIG_REG_INT_STS_WR_1_TX_SOPQ13_ERROR (0x1<<13) // Error in the TX SOPQ.
50786 #define NIG_REG_INT_STS_WR_1_TX_SOPQ14_ERROR (0x1<<14) // Error in the TX SOPQ.
50788 #define NIG_REG_INT_STS_WR_1_TX_SOPQ15_ERROR (0x1<<15) // Error in the TX SOPQ.
50790 #define NIG_REG_INT_STS_WR_1_LB_SOPQ0_ERROR (0x1<<16) // Error in the LB SOPQ.
50792 #define NIG_REG_INT_STS_WR_1_LB_SOPQ1_ERROR (0x1<<17) // Error in the LB SOPQ.
50794 #define NIG_REG_INT_STS_WR_1_LB_SOPQ2_ERROR (0x1<<18) // Error in the LB SOPQ.
50796 #define NIG_REG_INT_STS_WR_1_LB_SOPQ3_ERROR (0x1<<19) // Error in the LB SOPQ.
50798 #define NIG_REG_INT_STS_WR_1_LB_SOPQ4_ERROR (0x1<<20) // Error in the LB SOPQ.
50800 #define NIG_REG_INT_STS_WR_1_LB_SOPQ5_ERROR (0x1<<21) // Error in the LB SOPQ.
50802 #define NIG_REG_INT_STS_WR_1_LB_SOPQ6_ERROR (0x1<<22) // Error in the LB SOPQ.
50804 #define NIG_REG_INT_STS_WR_1_LB_SOPQ7_ERROR (0x1<<23) // Error in the LB SOPQ.
50806 #define NIG_REG_INT_STS_WR_1_LB_SOPQ8_ERROR (0x1<<24) // Error in the LB SOPQ.
50808 #define NIG_REG_INT_STS_WR_1_LB_SOPQ9_ERROR (0x1<<25) // Error in the LB SOPQ.
50810 #define NIG_REG_INT_STS_WR_1_LB_SOPQ10_ERROR (0x1<<26) // Error in the LB SOPQ.
50812 #define NIG_REG_INT_STS_WR_1_LB_SOPQ11_ERROR (0x1<<27) // Error in the LB SOPQ.
50814 #define NIG_REG_INT_STS_WR_1_LB_SOPQ12_ERROR (0x1<<28) // Error in the LB SOPQ.
50816 #define NIG_REG_INT_STS_WR_1_LB_SOPQ13_ERROR (0x1<<29) // Error in the LB SOPQ.
50818 #define NIG_REG_INT_STS_WR_1_LB_SOPQ14_ERROR (0x1<<30) // Error in the LB SOPQ.
50820 #define NIG_REG_INT_STS_WR_1_LB_SOPQ15_ERROR (0x1<<31) // Error in the LB SOPQ.
50823 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ0_ERROR (0x1<<0) // Error in the TX SOPQ.
50825 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ1_ERROR (0x1<<1) // Error in the TX SOPQ.
50827 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ2_ERROR (0x1<<2) // Error in the TX SOPQ.
50829 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ3_ERROR (0x1<<3) // Error in the TX SOPQ.
50831 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ4_ERROR (0x1<<4) // Error in the TX SOPQ.
50833 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ5_ERROR (0x1<<5) // Error in the TX SOPQ.
50835 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ6_ERROR (0x1<<6) // Error in the TX SOPQ.
50837 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ7_ERROR (0x1<<7) // Error in the TX SOPQ.
50839 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ8_ERROR (0x1<<8) // Error in the TX SOPQ.
50841 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ9_ERROR (0x1<<9) // Error in the TX SOPQ.
50843 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ10_ERROR (0x1<<10) // Error in the TX SOPQ.
50845 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ11_ERROR (0x1<<11) // Error in the TX SOPQ.
50847 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ12_ERROR (0x1<<12) // Error in the TX SOPQ.
50849 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ13_ERROR (0x1<<13) // Error in the TX SOPQ.
50851 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ14_ERROR (0x1<<14) // Error in the TX SOPQ.
50853 #define NIG_REG_INT_STS_CLR_1_TX_SOPQ15_ERROR (0x1<<15) // Error in the TX SOPQ.
50855 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ0_ERROR (0x1<<16) // Error in the LB SOPQ.
50857 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ1_ERROR (0x1<<17) // Error in the LB SOPQ.
50859 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ2_ERROR (0x1<<18) // Error in the LB SOPQ.
50861 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ3_ERROR (0x1<<19) // Error in the LB SOPQ.
50863 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ4_ERROR (0x1<<20) // Error in the LB SOPQ.
50865 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ5_ERROR (0x1<<21) // Error in the LB SOPQ.
50867 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ6_ERROR (0x1<<22) // Error in the LB SOPQ.
50869 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ7_ERROR (0x1<<23) // Error in the LB SOPQ.
50871 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ8_ERROR (0x1<<24) // Error in the LB SOPQ.
50873 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ9_ERROR (0x1<<25) // Error in the LB SOPQ.
50875 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ10_ERROR (0x1<<26) // Error in the LB SOPQ.
50877 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ11_ERROR (0x1<<27) // Error in the LB SOPQ.
50879 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ12_ERROR (0x1<<28) // Error in the LB SOPQ.
50881 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ13_ERROR (0x1<<29) // Error in the LB SOPQ.
50883 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ14_ERROR (0x1<<30) // Error in the LB SOPQ.
50885 #define NIG_REG_INT_STS_CLR_1_LB_SOPQ15_ERROR (0x1<<31) // Error in the LB SOPQ.
50888 #define NIG_REG_INT_STS_2_P0_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
50890 #define NIG_REG_INT_STS_2_P0_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
50892 #define NIG_REG_INT_STS_2_P0_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
50894 #define NIG_REG_INT_STS_2_P0_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
50896 #define NIG_REG_INT_STS_2_P0_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
50898 #define NIG_REG_INT_STS_2_P0_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
50900 #define NIG_REG_INT_STS_2_P0_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
50902 #define NIG_REG_INT_STS_2_P0_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
50904 #define NIG_REG_INT_STS_2_P0_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
50906 #define NIG_REG_INT_STS_2_P0_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
50908 #define NIG_REG_INT_STS_2_P0_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
50910 #define NIG_REG_INT_STS_2_P0_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
50912 #define NIG_REG_INT_STS_2_P0_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
50914 #define NIG_REG_INT_STS_2_P0_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
50916 #define NIG_REG_INT_STS_2_P0_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
50918 #define NIG_REG_INT_STS_2_P0_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
50920 #define NIG_REG_INT_STS_2_P0_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
50922 #define NIG_REG_INT_STS_2_P0_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
50924 #define NIG_REG_INT_STS_2_P0_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
50926 #define NIG_REG_INT_STS_2_P0_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
50929 #define NIG_REG_INT_MASK_2_P0_PURELB_SOPQ_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_PURELB_SOPQ_ERROR .
50931 #define NIG_REG_INT_MASK_2_P0_RX_MACFIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_MACFIFO_ERROR .
50933 #define NIG_REG_INT_MASK_2_P0_TX_MACFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_MACFIFO_ERROR .
50935 #define NIG_REG_INT_MASK_2_P0_TX_BMB_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_BMB_FIFO_ERROR .
50937 #define NIG_REG_INT_MASK_2_P0_LB_BMB_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_BMB_FIFO_ERROR .
50939 #define NIG_REG_INT_MASK_2_P0_TX_BTB_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_BTB_FIFO_ERROR .
50941 #define NIG_REG_INT_MASK_2_P0_LB_BTB_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_BTB_FIFO_ERROR .
50943 #define NIG_REG_INT_MASK_2_P0_RX_LLH_DFIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_DFIFO_ERROR .
50945 #define NIG_REG_INT_MASK_2_P0_TX_LLH_DFIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_DFIFO_ERROR .
50947 #define NIG_REG_INT_MASK_2_P0_LB_LLH_DFIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_DFIFO_ERROR .
50949 #define NIG_REG_INT_MASK_2_P0_RX_LLH_HFIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_HFIFO_ERROR .
50951 #define NIG_REG_INT_MASK_2_P0_TX_LLH_HFIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_HFIFO_ERROR .
50953 #define NIG_REG_INT_MASK_2_P0_LB_LLH_HFIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_HFIFO_ERROR .
50955 #define NIG_REG_INT_MASK_2_P0_RX_LLH_RFIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_RFIFO_ERROR .
50957 #define NIG_REG_INT_MASK_2_P0_TX_LLH_RFIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_RFIFO_ERROR .
50959 #define NIG_REG_INT_MASK_2_P0_LB_LLH_RFIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_RFIFO_ERROR .
50961 #define NIG_REG_INT_MASK_2_P0_STORM_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_STORM_FIFO_ERROR .
50963 #define NIG_REG_INT_MASK_2_P0_STORM_DSCR_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_STORM_DSCR_FIFO_ERROR .
50965 #define NIG_REG_INT_MASK_2_P0_TX_GNT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_GNT_FIFO_ERROR .
50967 #define NIG_REG_INT_MASK_2_P0_LB_GNT_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_GNT_FIFO_ERROR .
50970 #define NIG_REG_INT_STS_WR_2_P0_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
50972 #define NIG_REG_INT_STS_WR_2_P0_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
50974 #define NIG_REG_INT_STS_WR_2_P0_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
50976 #define NIG_REG_INT_STS_WR_2_P0_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
50978 #define NIG_REG_INT_STS_WR_2_P0_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
50980 #define NIG_REG_INT_STS_WR_2_P0_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
50982 #define NIG_REG_INT_STS_WR_2_P0_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
50984 #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
50986 #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
50988 #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
50990 #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
50992 #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
50994 #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
50996 #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
50998 #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51000 #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51002 #define NIG_REG_INT_STS_WR_2_P0_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51004 #define NIG_REG_INT_STS_WR_2_P0_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51006 #define NIG_REG_INT_STS_WR_2_P0_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51008 #define NIG_REG_INT_STS_WR_2_P0_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51011 #define NIG_REG_INT_STS_CLR_2_P0_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51013 #define NIG_REG_INT_STS_CLR_2_P0_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51015 #define NIG_REG_INT_STS_CLR_2_P0_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51017 #define NIG_REG_INT_STS_CLR_2_P0_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51019 #define NIG_REG_INT_STS_CLR_2_P0_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51021 #define NIG_REG_INT_STS_CLR_2_P0_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51023 #define NIG_REG_INT_STS_CLR_2_P0_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51025 #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51027 #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51029 #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51031 #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51033 #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51035 #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51037 #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51039 #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51041 #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51043 #define NIG_REG_INT_STS_CLR_2_P0_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51045 #define NIG_REG_INT_STS_CLR_2_P0_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51047 #define NIG_REG_INT_STS_CLR_2_P0_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51049 #define NIG_REG_INT_STS_CLR_2_P0_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51052 #define NIG_REG_INT_STS_3_P0_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51054 #define NIG_REG_INT_STS_3_P0_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51056 #define NIG_REG_INT_STS_3_P0_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51058 #define NIG_REG_INT_STS_3_P0_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51060 #define NIG_REG_INT_STS_3_P0_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51062 #define NIG_REG_INT_STS_3_P0_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51064 #define NIG_REG_INT_STS_3_P0_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51066 #define NIG_REG_INT_STS_3_P0_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51068 #define NIG_REG_INT_STS_3_P0_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51070 #define NIG_REG_INT_STS_3_P0_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51072 #define NIG_REG_INT_STS_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51074 #define NIG_REG_INT_STS_3_P0_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51076 #define NIG_REG_INT_STS_3_P0_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51078 #define NIG_REG_INT_STS_3_P0_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51080 #define NIG_REG_INT_STS_3_P0_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51082 #define NIG_REG_INT_STS_3_P0_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51084 #define NIG_REG_INT_STS_3_P0_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51086 #define NIG_REG_INT_STS_3_P0_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51089 #define NIG_REG_INT_MASK_3_P0_TX_PAUSE_TOO_LONG_INT (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TX_PAUSE_TOO_LONG_INT .
51091 #define NIG_REG_INT_MASK_3_P0_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC0_PAUSE_TOO_LONG_INT .
51093 #define NIG_REG_INT_MASK_3_P0_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC1_PAUSE_TOO_LONG_INT .
51095 #define NIG_REG_INT_MASK_3_P0_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC2_PAUSE_TOO_LONG_INT .
51097 #define NIG_REG_INT_MASK_3_P0_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC3_PAUSE_TOO_LONG_INT .
51099 #define NIG_REG_INT_MASK_3_P0_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC4_PAUSE_TOO_LONG_INT .
51101 #define NIG_REG_INT_MASK_3_P0_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC5_PAUSE_TOO_LONG_INT .
51103 #define NIG_REG_INT_MASK_3_P0_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC6_PAUSE_TOO_LONG_INT .
51105 #define NIG_REG_INT_MASK_3_P0_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC7_PAUSE_TOO_LONG_INT .
51107 #define NIG_REG_INT_MASK_3_P0_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC0_PAUSE_TOO_LONG_INT .
51109 #define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC1_PAUSE_TOO_LONG_INT .
51111 #define NIG_REG_INT_MASK_3_P0_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC2_PAUSE_TOO_LONG_INT .
51113 #define NIG_REG_INT_MASK_3_P0_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC3_PAUSE_TOO_LONG_INT .
51115 #define NIG_REG_INT_MASK_3_P0_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC4_PAUSE_TOO_LONG_INT .
51117 #define NIG_REG_INT_MASK_3_P0_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC5_PAUSE_TOO_LONG_INT .
51119 #define NIG_REG_INT_MASK_3_P0_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC6_PAUSE_TOO_LONG_INT .
51121 #define NIG_REG_INT_MASK_3_P0_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC7_PAUSE_TOO_LONG_INT .
51123 #define NIG_REG_INT_MASK_3_P0_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC8_PAUSE_TOO_LONG_INT .
51126 #define NIG_REG_INT_STS_WR_3_P0_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51128 #define NIG_REG_INT_STS_WR_3_P0_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51130 #define NIG_REG_INT_STS_WR_3_P0_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51132 #define NIG_REG_INT_STS_WR_3_P0_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51134 #define NIG_REG_INT_STS_WR_3_P0_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51136 #define NIG_REG_INT_STS_WR_3_P0_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51138 #define NIG_REG_INT_STS_WR_3_P0_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51140 #define NIG_REG_INT_STS_WR_3_P0_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51142 #define NIG_REG_INT_STS_WR_3_P0_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51144 #define NIG_REG_INT_STS_WR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51146 #define NIG_REG_INT_STS_WR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51148 #define NIG_REG_INT_STS_WR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51150 #define NIG_REG_INT_STS_WR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51152 #define NIG_REG_INT_STS_WR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51154 #define NIG_REG_INT_STS_WR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51156 #define NIG_REG_INT_STS_WR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51158 #define NIG_REG_INT_STS_WR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51160 #define NIG_REG_INT_STS_WR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51163 #define NIG_REG_INT_STS_CLR_3_P0_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51165 #define NIG_REG_INT_STS_CLR_3_P0_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51167 #define NIG_REG_INT_STS_CLR_3_P0_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51169 #define NIG_REG_INT_STS_CLR_3_P0_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51171 #define NIG_REG_INT_STS_CLR_3_P0_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51173 #define NIG_REG_INT_STS_CLR_3_P0_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51175 #define NIG_REG_INT_STS_CLR_3_P0_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51177 #define NIG_REG_INT_STS_CLR_3_P0_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51179 #define NIG_REG_INT_STS_CLR_3_P0_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51181 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51183 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51185 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51187 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51189 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51191 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51193 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51195 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51197 #define NIG_REG_INT_STS_CLR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51200 #define NIG_REG_INT_STS_4_P1_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51202 #define NIG_REG_INT_STS_4_P1_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51204 #define NIG_REG_INT_STS_4_P1_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51206 #define NIG_REG_INT_STS_4_P1_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51208 #define NIG_REG_INT_STS_4_P1_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51210 #define NIG_REG_INT_STS_4_P1_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51212 #define NIG_REG_INT_STS_4_P1_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51214 #define NIG_REG_INT_STS_4_P1_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51216 #define NIG_REG_INT_STS_4_P1_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51218 #define NIG_REG_INT_STS_4_P1_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51220 #define NIG_REG_INT_STS_4_P1_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51222 #define NIG_REG_INT_STS_4_P1_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51224 #define NIG_REG_INT_STS_4_P1_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51226 #define NIG_REG_INT_STS_4_P1_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51228 #define NIG_REG_INT_STS_4_P1_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51230 #define NIG_REG_INT_STS_4_P1_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51232 #define NIG_REG_INT_STS_4_P1_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51234 #define NIG_REG_INT_STS_4_P1_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51236 #define NIG_REG_INT_STS_4_P1_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51238 #define NIG_REG_INT_STS_4_P1_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51241 #define NIG_REG_INT_MASK_4_P1_PURELB_SOPQ_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_PURELB_SOPQ_ERROR .
51243 #define NIG_REG_INT_MASK_4_P1_RX_MACFIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_MACFIFO_ERROR .
51245 #define NIG_REG_INT_MASK_4_P1_TX_MACFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_MACFIFO_ERROR .
51247 #define NIG_REG_INT_MASK_4_P1_TX_BMB_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_BMB_FIFO_ERROR .
51249 #define NIG_REG_INT_MASK_4_P1_LB_BMB_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_BMB_FIFO_ERROR .
51251 #define NIG_REG_INT_MASK_4_P1_TX_BTB_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_BTB_FIFO_ERROR .
51253 #define NIG_REG_INT_MASK_4_P1_LB_BTB_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_BTB_FIFO_ERROR .
51255 #define NIG_REG_INT_MASK_4_P1_RX_LLH_DFIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_DFIFO_ERROR .
51257 #define NIG_REG_INT_MASK_4_P1_TX_LLH_DFIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_DFIFO_ERROR .
51259 #define NIG_REG_INT_MASK_4_P1_LB_LLH_DFIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_DFIFO_ERROR .
51261 #define NIG_REG_INT_MASK_4_P1_RX_LLH_HFIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_HFIFO_ERROR .
51263 #define NIG_REG_INT_MASK_4_P1_TX_LLH_HFIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_HFIFO_ERROR .
51265 #define NIG_REG_INT_MASK_4_P1_LB_LLH_HFIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_HFIFO_ERROR .
51267 #define NIG_REG_INT_MASK_4_P1_RX_LLH_RFIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_RFIFO_ERROR .
51269 #define NIG_REG_INT_MASK_4_P1_TX_LLH_RFIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_RFIFO_ERROR .
51271 #define NIG_REG_INT_MASK_4_P1_LB_LLH_RFIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_RFIFO_ERROR .
51273 #define NIG_REG_INT_MASK_4_P1_STORM_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_STORM_FIFO_ERROR .
51275 #define NIG_REG_INT_MASK_4_P1_STORM_DSCR_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_STORM_DSCR_FIFO_ERROR .
51277 #define NIG_REG_INT_MASK_4_P1_TX_GNT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_GNT_FIFO_ERROR .
51279 #define NIG_REG_INT_MASK_4_P1_LB_GNT_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_GNT_FIFO_ERROR .
51282 #define NIG_REG_INT_STS_WR_4_P1_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51284 #define NIG_REG_INT_STS_WR_4_P1_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51286 #define NIG_REG_INT_STS_WR_4_P1_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51288 #define NIG_REG_INT_STS_WR_4_P1_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51290 #define NIG_REG_INT_STS_WR_4_P1_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51292 #define NIG_REG_INT_STS_WR_4_P1_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51294 #define NIG_REG_INT_STS_WR_4_P1_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51296 #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51298 #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51300 #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51302 #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51304 #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51306 #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51308 #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51310 #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51312 #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51314 #define NIG_REG_INT_STS_WR_4_P1_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51316 #define NIG_REG_INT_STS_WR_4_P1_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51318 #define NIG_REG_INT_STS_WR_4_P1_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51320 #define NIG_REG_INT_STS_WR_4_P1_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51323 #define NIG_REG_INT_STS_CLR_4_P1_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51325 #define NIG_REG_INT_STS_CLR_4_P1_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51327 #define NIG_REG_INT_STS_CLR_4_P1_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51329 #define NIG_REG_INT_STS_CLR_4_P1_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51331 #define NIG_REG_INT_STS_CLR_4_P1_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51333 #define NIG_REG_INT_STS_CLR_4_P1_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51335 #define NIG_REG_INT_STS_CLR_4_P1_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51337 #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51339 #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51341 #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51343 #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51345 #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51347 #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51349 #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51351 #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51353 #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51355 #define NIG_REG_INT_STS_CLR_4_P1_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51357 #define NIG_REG_INT_STS_CLR_4_P1_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51359 #define NIG_REG_INT_STS_CLR_4_P1_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51361 #define NIG_REG_INT_STS_CLR_4_P1_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51364 #define NIG_REG_INT_STS_5_P1_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51366 #define NIG_REG_INT_STS_5_P1_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51368 #define NIG_REG_INT_STS_5_P1_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51370 #define NIG_REG_INT_STS_5_P1_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51372 #define NIG_REG_INT_STS_5_P1_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51374 #define NIG_REG_INT_STS_5_P1_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51376 #define NIG_REG_INT_STS_5_P1_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51378 #define NIG_REG_INT_STS_5_P1_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51380 #define NIG_REG_INT_STS_5_P1_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51382 #define NIG_REG_INT_STS_5_P1_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51384 #define NIG_REG_INT_STS_5_P1_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51386 #define NIG_REG_INT_STS_5_P1_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51388 #define NIG_REG_INT_STS_5_P1_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51390 #define NIG_REG_INT_STS_5_P1_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51392 #define NIG_REG_INT_STS_5_P1_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51394 #define NIG_REG_INT_STS_5_P1_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51396 #define NIG_REG_INT_STS_5_P1_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51398 #define NIG_REG_INT_STS_5_P1_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51401 #define NIG_REG_INT_MASK_5_P1_TX_PAUSE_TOO_LONG_INT (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TX_PAUSE_TOO_LONG_INT .
51403 #define NIG_REG_INT_MASK_5_P1_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC0_PAUSE_TOO_LONG_INT .
51405 #define NIG_REG_INT_MASK_5_P1_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC1_PAUSE_TOO_LONG_INT .
51407 #define NIG_REG_INT_MASK_5_P1_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC2_PAUSE_TOO_LONG_INT .
51409 #define NIG_REG_INT_MASK_5_P1_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC3_PAUSE_TOO_LONG_INT .
51411 #define NIG_REG_INT_MASK_5_P1_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC4_PAUSE_TOO_LONG_INT .
51413 #define NIG_REG_INT_MASK_5_P1_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC5_PAUSE_TOO_LONG_INT .
51415 #define NIG_REG_INT_MASK_5_P1_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC6_PAUSE_TOO_LONG_INT .
51417 #define NIG_REG_INT_MASK_5_P1_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC7_PAUSE_TOO_LONG_INT .
51419 #define NIG_REG_INT_MASK_5_P1_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC0_PAUSE_TOO_LONG_INT .
51421 #define NIG_REG_INT_MASK_5_P1_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC1_PAUSE_TOO_LONG_INT .
51423 #define NIG_REG_INT_MASK_5_P1_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC2_PAUSE_TOO_LONG_INT .
51425 #define NIG_REG_INT_MASK_5_P1_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC3_PAUSE_TOO_LONG_INT .
51427 #define NIG_REG_INT_MASK_5_P1_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC4_PAUSE_TOO_LONG_INT .
51429 #define NIG_REG_INT_MASK_5_P1_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC5_PAUSE_TOO_LONG_INT .
51431 #define NIG_REG_INT_MASK_5_P1_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC6_PAUSE_TOO_LONG_INT .
51433 #define NIG_REG_INT_MASK_5_P1_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC7_PAUSE_TOO_LONG_INT .
51435 #define NIG_REG_INT_MASK_5_P1_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC8_PAUSE_TOO_LONG_INT .
51438 #define NIG_REG_INT_STS_WR_5_P1_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51440 #define NIG_REG_INT_STS_WR_5_P1_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51442 #define NIG_REG_INT_STS_WR_5_P1_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51444 #define NIG_REG_INT_STS_WR_5_P1_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51446 #define NIG_REG_INT_STS_WR_5_P1_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51448 #define NIG_REG_INT_STS_WR_5_P1_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51450 #define NIG_REG_INT_STS_WR_5_P1_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51452 #define NIG_REG_INT_STS_WR_5_P1_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51454 #define NIG_REG_INT_STS_WR_5_P1_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51456 #define NIG_REG_INT_STS_WR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51458 #define NIG_REG_INT_STS_WR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51460 #define NIG_REG_INT_STS_WR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51462 #define NIG_REG_INT_STS_WR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51464 #define NIG_REG_INT_STS_WR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51466 #define NIG_REG_INT_STS_WR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51468 #define NIG_REG_INT_STS_WR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51470 #define NIG_REG_INT_STS_WR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51472 #define NIG_REG_INT_STS_WR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51475 #define NIG_REG_INT_STS_CLR_5_P1_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51477 #define NIG_REG_INT_STS_CLR_5_P1_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51479 #define NIG_REG_INT_STS_CLR_5_P1_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51481 #define NIG_REG_INT_STS_CLR_5_P1_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51483 #define NIG_REG_INT_STS_CLR_5_P1_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51485 #define NIG_REG_INT_STS_CLR_5_P1_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51487 #define NIG_REG_INT_STS_CLR_5_P1_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51489 #define NIG_REG_INT_STS_CLR_5_P1_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51491 #define NIG_REG_INT_STS_CLR_5_P1_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51493 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51495 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51497 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51499 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51501 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51503 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51505 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51507 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51509 #define NIG_REG_INT_STS_CLR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51512 #define NIG_REG_INT_STS_6_P2_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51514 #define NIG_REG_INT_STS_6_P2_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51516 #define NIG_REG_INT_STS_6_P2_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51518 #define NIG_REG_INT_STS_6_P2_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51520 #define NIG_REG_INT_STS_6_P2_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51522 #define NIG_REG_INT_STS_6_P2_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51524 #define NIG_REG_INT_STS_6_P2_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51526 #define NIG_REG_INT_STS_6_P2_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51528 #define NIG_REG_INT_STS_6_P2_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51530 #define NIG_REG_INT_STS_6_P2_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51532 #define NIG_REG_INT_STS_6_P2_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51534 #define NIG_REG_INT_STS_6_P2_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51536 #define NIG_REG_INT_STS_6_P2_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51538 #define NIG_REG_INT_STS_6_P2_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51540 #define NIG_REG_INT_STS_6_P2_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51542 #define NIG_REG_INT_STS_6_P2_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51544 #define NIG_REG_INT_STS_6_P2_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51546 #define NIG_REG_INT_STS_6_P2_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51548 #define NIG_REG_INT_STS_6_P2_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51550 #define NIG_REG_INT_STS_6_P2_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51553 #define NIG_REG_INT_MASK_6_P2_PURELB_SOPQ_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_PURELB_SOPQ_ERROR .
51555 #define NIG_REG_INT_MASK_6_P2_RX_MACFIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_MACFIFO_ERROR .
51557 #define NIG_REG_INT_MASK_6_P2_TX_MACFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_MACFIFO_ERROR .
51559 #define NIG_REG_INT_MASK_6_P2_TX_BMB_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_BMB_FIFO_ERROR .
51561 #define NIG_REG_INT_MASK_6_P2_LB_BMB_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_BMB_FIFO_ERROR .
51563 #define NIG_REG_INT_MASK_6_P2_TX_BTB_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_BTB_FIFO_ERROR .
51565 #define NIG_REG_INT_MASK_6_P2_LB_BTB_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_BTB_FIFO_ERROR .
51567 #define NIG_REG_INT_MASK_6_P2_RX_LLH_DFIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_DFIFO_ERROR .
51569 #define NIG_REG_INT_MASK_6_P2_TX_LLH_DFIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_DFIFO_ERROR .
51571 #define NIG_REG_INT_MASK_6_P2_LB_LLH_DFIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_DFIFO_ERROR .
51573 #define NIG_REG_INT_MASK_6_P2_RX_LLH_HFIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_HFIFO_ERROR .
51575 #define NIG_REG_INT_MASK_6_P2_TX_LLH_HFIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_HFIFO_ERROR .
51577 #define NIG_REG_INT_MASK_6_P2_LB_LLH_HFIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_HFIFO_ERROR .
51579 #define NIG_REG_INT_MASK_6_P2_RX_LLH_RFIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_RFIFO_ERROR .
51581 #define NIG_REG_INT_MASK_6_P2_TX_LLH_RFIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_RFIFO_ERROR .
51583 #define NIG_REG_INT_MASK_6_P2_LB_LLH_RFIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_RFIFO_ERROR .
51585 #define NIG_REG_INT_MASK_6_P2_STORM_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_STORM_FIFO_ERROR .
51587 #define NIG_REG_INT_MASK_6_P2_STORM_DSCR_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_STORM_DSCR_FIFO_ERROR .
51589 #define NIG_REG_INT_MASK_6_P2_TX_GNT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_GNT_FIFO_ERROR .
51591 #define NIG_REG_INT_MASK_6_P2_LB_GNT_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_GNT_FIFO_ERROR .
51594 #define NIG_REG_INT_STS_WR_6_P2_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51596 #define NIG_REG_INT_STS_WR_6_P2_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51598 #define NIG_REG_INT_STS_WR_6_P2_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51600 #define NIG_REG_INT_STS_WR_6_P2_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51602 #define NIG_REG_INT_STS_WR_6_P2_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51604 #define NIG_REG_INT_STS_WR_6_P2_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51606 #define NIG_REG_INT_STS_WR_6_P2_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51608 #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51610 #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51612 #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51614 #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51616 #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51618 #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51620 #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51622 #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51624 #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51626 #define NIG_REG_INT_STS_WR_6_P2_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51628 #define NIG_REG_INT_STS_WR_6_P2_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51630 #define NIG_REG_INT_STS_WR_6_P2_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51632 #define NIG_REG_INT_STS_WR_6_P2_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51635 #define NIG_REG_INT_STS_CLR_6_P2_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51637 #define NIG_REG_INT_STS_CLR_6_P2_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51639 #define NIG_REG_INT_STS_CLR_6_P2_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51641 #define NIG_REG_INT_STS_CLR_6_P2_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51643 #define NIG_REG_INT_STS_CLR_6_P2_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51645 #define NIG_REG_INT_STS_CLR_6_P2_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51647 #define NIG_REG_INT_STS_CLR_6_P2_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51649 #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51651 #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51653 #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51655 #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51657 #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51659 #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51661 #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51663 #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51665 #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51667 #define NIG_REG_INT_STS_CLR_6_P2_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51669 #define NIG_REG_INT_STS_CLR_6_P2_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51671 #define NIG_REG_INT_STS_CLR_6_P2_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51673 #define NIG_REG_INT_STS_CLR_6_P2_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51676 #define NIG_REG_INT_STS_7_P2_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51678 #define NIG_REG_INT_STS_7_P2_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51680 #define NIG_REG_INT_STS_7_P2_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51682 #define NIG_REG_INT_STS_7_P2_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51684 #define NIG_REG_INT_STS_7_P2_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51686 #define NIG_REG_INT_STS_7_P2_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51688 #define NIG_REG_INT_STS_7_P2_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51690 #define NIG_REG_INT_STS_7_P2_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51692 #define NIG_REG_INT_STS_7_P2_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51694 #define NIG_REG_INT_STS_7_P2_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51696 #define NIG_REG_INT_STS_7_P2_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51698 #define NIG_REG_INT_STS_7_P2_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51700 #define NIG_REG_INT_STS_7_P2_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51702 #define NIG_REG_INT_STS_7_P2_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51704 #define NIG_REG_INT_STS_7_P2_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51706 #define NIG_REG_INT_STS_7_P2_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51708 #define NIG_REG_INT_STS_7_P2_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51710 #define NIG_REG_INT_STS_7_P2_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51713 #define NIG_REG_INT_MASK_7_P2_TX_PAUSE_TOO_LONG_INT (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TX_PAUSE_TOO_LONG_INT .
51715 #define NIG_REG_INT_MASK_7_P2_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC0_PAUSE_TOO_LONG_INT .
51717 #define NIG_REG_INT_MASK_7_P2_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC1_PAUSE_TOO_LONG_INT .
51719 #define NIG_REG_INT_MASK_7_P2_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC2_PAUSE_TOO_LONG_INT .
51721 #define NIG_REG_INT_MASK_7_P2_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC3_PAUSE_TOO_LONG_INT .
51723 #define NIG_REG_INT_MASK_7_P2_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC4_PAUSE_TOO_LONG_INT .
51725 #define NIG_REG_INT_MASK_7_P2_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC5_PAUSE_TOO_LONG_INT .
51727 #define NIG_REG_INT_MASK_7_P2_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC6_PAUSE_TOO_LONG_INT .
51729 #define NIG_REG_INT_MASK_7_P2_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC7_PAUSE_TOO_LONG_INT .
51731 #define NIG_REG_INT_MASK_7_P2_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC0_PAUSE_TOO_LONG_INT .
51733 #define NIG_REG_INT_MASK_7_P2_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC1_PAUSE_TOO_LONG_INT .
51735 #define NIG_REG_INT_MASK_7_P2_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC2_PAUSE_TOO_LONG_INT .
51737 #define NIG_REG_INT_MASK_7_P2_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC3_PAUSE_TOO_LONG_INT .
51739 #define NIG_REG_INT_MASK_7_P2_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC4_PAUSE_TOO_LONG_INT .
51741 #define NIG_REG_INT_MASK_7_P2_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC5_PAUSE_TOO_LONG_INT .
51743 #define NIG_REG_INT_MASK_7_P2_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC6_PAUSE_TOO_LONG_INT .
51745 #define NIG_REG_INT_MASK_7_P2_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC7_PAUSE_TOO_LONG_INT .
51747 #define NIG_REG_INT_MASK_7_P2_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC8_PAUSE_TOO_LONG_INT .
51750 #define NIG_REG_INT_STS_WR_7_P2_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51752 #define NIG_REG_INT_STS_WR_7_P2_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51754 #define NIG_REG_INT_STS_WR_7_P2_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51756 #define NIG_REG_INT_STS_WR_7_P2_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51758 #define NIG_REG_INT_STS_WR_7_P2_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51760 #define NIG_REG_INT_STS_WR_7_P2_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51762 #define NIG_REG_INT_STS_WR_7_P2_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51764 #define NIG_REG_INT_STS_WR_7_P2_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51766 #define NIG_REG_INT_STS_WR_7_P2_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51768 #define NIG_REG_INT_STS_WR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51770 #define NIG_REG_INT_STS_WR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51772 #define NIG_REG_INT_STS_WR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51774 #define NIG_REG_INT_STS_WR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51776 #define NIG_REG_INT_STS_WR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51778 #define NIG_REG_INT_STS_WR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51780 #define NIG_REG_INT_STS_WR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51782 #define NIG_REG_INT_STS_WR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51784 #define NIG_REG_INT_STS_WR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51787 #define NIG_REG_INT_STS_CLR_7_P2_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51789 #define NIG_REG_INT_STS_CLR_7_P2_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51791 #define NIG_REG_INT_STS_CLR_7_P2_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51793 #define NIG_REG_INT_STS_CLR_7_P2_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51795 #define NIG_REG_INT_STS_CLR_7_P2_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51797 #define NIG_REG_INT_STS_CLR_7_P2_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
51799 #define NIG_REG_INT_STS_CLR_7_P2_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
51801 #define NIG_REG_INT_STS_CLR_7_P2_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
51803 #define NIG_REG_INT_STS_CLR_7_P2_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
51805 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
51807 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
51809 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
51811 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
51813 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
51815 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
51817 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
51819 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
51821 #define NIG_REG_INT_STS_CLR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
51824 #define NIG_REG_INT_STS_8_P3_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51826 #define NIG_REG_INT_STS_8_P3_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51828 #define NIG_REG_INT_STS_8_P3_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51830 #define NIG_REG_INT_STS_8_P3_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51832 #define NIG_REG_INT_STS_8_P3_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51834 #define NIG_REG_INT_STS_8_P3_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51836 #define NIG_REG_INT_STS_8_P3_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51838 #define NIG_REG_INT_STS_8_P3_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51840 #define NIG_REG_INT_STS_8_P3_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51842 #define NIG_REG_INT_STS_8_P3_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51844 #define NIG_REG_INT_STS_8_P3_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51846 #define NIG_REG_INT_STS_8_P3_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51848 #define NIG_REG_INT_STS_8_P3_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51850 #define NIG_REG_INT_STS_8_P3_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51852 #define NIG_REG_INT_STS_8_P3_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51854 #define NIG_REG_INT_STS_8_P3_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51856 #define NIG_REG_INT_STS_8_P3_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51858 #define NIG_REG_INT_STS_8_P3_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51860 #define NIG_REG_INT_STS_8_P3_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51862 #define NIG_REG_INT_STS_8_P3_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51865 #define NIG_REG_INT_MASK_8_P3_PURELB_SOPQ_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_PURELB_SOPQ_ERROR .
51867 #define NIG_REG_INT_MASK_8_P3_RX_MACFIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_MACFIFO_ERROR .
51869 #define NIG_REG_INT_MASK_8_P3_TX_MACFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_MACFIFO_ERROR .
51871 #define NIG_REG_INT_MASK_8_P3_TX_BMB_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_BMB_FIFO_ERROR .
51873 #define NIG_REG_INT_MASK_8_P3_LB_BMB_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_BMB_FIFO_ERROR .
51875 #define NIG_REG_INT_MASK_8_P3_TX_BTB_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_BTB_FIFO_ERROR .
51877 #define NIG_REG_INT_MASK_8_P3_LB_BTB_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_BTB_FIFO_ERROR .
51879 #define NIG_REG_INT_MASK_8_P3_RX_LLH_DFIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_DFIFO_ERROR .
51881 #define NIG_REG_INT_MASK_8_P3_TX_LLH_DFIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_DFIFO_ERROR .
51883 #define NIG_REG_INT_MASK_8_P3_LB_LLH_DFIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_DFIFO_ERROR .
51885 #define NIG_REG_INT_MASK_8_P3_RX_LLH_HFIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_HFIFO_ERROR .
51887 #define NIG_REG_INT_MASK_8_P3_TX_LLH_HFIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_HFIFO_ERROR .
51889 #define NIG_REG_INT_MASK_8_P3_LB_LLH_HFIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_HFIFO_ERROR .
51891 #define NIG_REG_INT_MASK_8_P3_RX_LLH_RFIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_RFIFO_ERROR .
51893 #define NIG_REG_INT_MASK_8_P3_TX_LLH_RFIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_RFIFO_ERROR .
51895 #define NIG_REG_INT_MASK_8_P3_LB_LLH_RFIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_RFIFO_ERROR .
51897 #define NIG_REG_INT_MASK_8_P3_STORM_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_STORM_FIFO_ERROR .
51899 #define NIG_REG_INT_MASK_8_P3_STORM_DSCR_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_STORM_DSCR_FIFO_ERROR .
51901 #define NIG_REG_INT_MASK_8_P3_TX_GNT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_GNT_FIFO_ERROR .
51903 #define NIG_REG_INT_MASK_8_P3_LB_GNT_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_GNT_FIFO_ERROR .
51906 #define NIG_REG_INT_STS_WR_8_P3_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51908 #define NIG_REG_INT_STS_WR_8_P3_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51910 #define NIG_REG_INT_STS_WR_8_P3_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51912 #define NIG_REG_INT_STS_WR_8_P3_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51914 #define NIG_REG_INT_STS_WR_8_P3_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51916 #define NIG_REG_INT_STS_WR_8_P3_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51918 #define NIG_REG_INT_STS_WR_8_P3_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51920 #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51922 #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51924 #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51926 #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51928 #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51930 #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51932 #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51934 #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51936 #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51938 #define NIG_REG_INT_STS_WR_8_P3_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51940 #define NIG_REG_INT_STS_WR_8_P3_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51942 #define NIG_REG_INT_STS_WR_8_P3_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51944 #define NIG_REG_INT_STS_WR_8_P3_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51947 #define NIG_REG_INT_STS_CLR_8_P3_PURELB_SOPQ_ERROR (0x1<<0) // Error in the pure-loopback SOPQ.
51949 #define NIG_REG_INT_STS_CLR_8_P3_RX_MACFIFO_ERROR (0x1<<1) // Error in RX MAC FIFO.
51951 #define NIG_REG_INT_STS_CLR_8_P3_TX_MACFIFO_ERROR (0x1<<2) // Error in TX MAC FIFO.
51953 #define NIG_REG_INT_STS_CLR_8_P3_TX_BMB_FIFO_ERROR (0x1<<3) // FIFO error in TX BMB FIFO.
51955 #define NIG_REG_INT_STS_CLR_8_P3_LB_BMB_FIFO_ERROR (0x1<<4) // FIFO error in LB BMB FIFO.
51957 #define NIG_REG_INT_STS_CLR_8_P3_TX_BTB_FIFO_ERROR (0x1<<5) // Error in BTB FIFO for TX path.
51959 #define NIG_REG_INT_STS_CLR_8_P3_LB_BTB_FIFO_ERROR (0x1<<6) // Error in BTB FIFO for LB path.
51961 #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_DFIFO_ERROR (0x1<<7) // Error in LLH Data FIFO.
51963 #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_DFIFO_ERROR (0x1<<8) // Error in LLH Data FIFO.
51965 #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_DFIFO_ERROR (0x1<<9) // Error in LLH Data FIFO.
51967 #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_HFIFO_ERROR (0x1<<10) // Error in LLH Header FIFO.
51969 #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_HFIFO_ERROR (0x1<<11) // Error in LLH Header FIFO.
51971 #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_HFIFO_ERROR (0x1<<12) // Error in LLH Header FIFO.
51973 #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_RFIFO_ERROR (0x1<<13) // Error in LLH Result FIFO.
51975 #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_RFIFO_ERROR (0x1<<14) // Error in LLH Result FIFO.
51977 #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_RFIFO_ERROR (0x1<<15) // Error in LLH Result FIFO.
51979 #define NIG_REG_INT_STS_CLR_8_P3_STORM_FIFO_ERROR (0x1<<16) // FIFO error in STORM message FIFO.
51981 #define NIG_REG_INT_STS_CLR_8_P3_STORM_DSCR_FIFO_ERROR (0x1<<17) // FIFO error in STORM descriptor FIFO.
51983 #define NIG_REG_INT_STS_CLR_8_P3_TX_GNT_FIFO_ERROR (0x1<<18) // Error in grant FIFO.
51985 #define NIG_REG_INT_STS_CLR_8_P3_LB_GNT_FIFO_ERROR (0x1<<19) // Error in grant FIFO.
51988 #define NIG_REG_INT_STS_9_P3_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
51990 #define NIG_REG_INT_STS_9_P3_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
51992 #define NIG_REG_INT_STS_9_P3_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
51994 #define NIG_REG_INT_STS_9_P3_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
51996 #define NIG_REG_INT_STS_9_P3_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
51998 #define NIG_REG_INT_STS_9_P3_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
52000 #define NIG_REG_INT_STS_9_P3_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
52002 #define NIG_REG_INT_STS_9_P3_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
52004 #define NIG_REG_INT_STS_9_P3_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
52006 #define NIG_REG_INT_STS_9_P3_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
52008 #define NIG_REG_INT_STS_9_P3_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
52010 #define NIG_REG_INT_STS_9_P3_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
52012 #define NIG_REG_INT_STS_9_P3_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
52014 #define NIG_REG_INT_STS_9_P3_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
52016 #define NIG_REG_INT_STS_9_P3_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
52018 #define NIG_REG_INT_STS_9_P3_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
52020 #define NIG_REG_INT_STS_9_P3_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
52022 #define NIG_REG_INT_STS_9_P3_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
52025 #define NIG_REG_INT_MASK_9_P3_TX_PAUSE_TOO_LONG_INT (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TX_PAUSE_TOO_LONG_INT .
52027 #define NIG_REG_INT_MASK_9_P3_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC0_PAUSE_TOO_LONG_INT .
52029 #define NIG_REG_INT_MASK_9_P3_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC1_PAUSE_TOO_LONG_INT .
52031 #define NIG_REG_INT_MASK_9_P3_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC2_PAUSE_TOO_LONG_INT .
52033 #define NIG_REG_INT_MASK_9_P3_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC3_PAUSE_TOO_LONG_INT .
52035 #define NIG_REG_INT_MASK_9_P3_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC4_PAUSE_TOO_LONG_INT .
52037 #define NIG_REG_INT_MASK_9_P3_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC5_PAUSE_TOO_LONG_INT .
52039 #define NIG_REG_INT_MASK_9_P3_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC6_PAUSE_TOO_LONG_INT .
52041 #define NIG_REG_INT_MASK_9_P3_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC7_PAUSE_TOO_LONG_INT .
52043 #define NIG_REG_INT_MASK_9_P3_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC0_PAUSE_TOO_LONG_INT .
52045 #define NIG_REG_INT_MASK_9_P3_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC1_PAUSE_TOO_LONG_INT .
52047 #define NIG_REG_INT_MASK_9_P3_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC2_PAUSE_TOO_LONG_INT .
52049 #define NIG_REG_INT_MASK_9_P3_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC3_PAUSE_TOO_LONG_INT .
52051 #define NIG_REG_INT_MASK_9_P3_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC4_PAUSE_TOO_LONG_INT .
52053 #define NIG_REG_INT_MASK_9_P3_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC5_PAUSE_TOO_LONG_INT .
52055 #define NIG_REG_INT_MASK_9_P3_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC6_PAUSE_TOO_LONG_INT .
52057 #define NIG_REG_INT_MASK_9_P3_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC7_PAUSE_TOO_LONG_INT .
52059 #define NIG_REG_INT_MASK_9_P3_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC8_PAUSE_TOO_LONG_INT .
52062 #define NIG_REG_INT_STS_WR_9_P3_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
52064 #define NIG_REG_INT_STS_WR_9_P3_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
52066 #define NIG_REG_INT_STS_WR_9_P3_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
52068 #define NIG_REG_INT_STS_WR_9_P3_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
52070 #define NIG_REG_INT_STS_WR_9_P3_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
52072 #define NIG_REG_INT_STS_WR_9_P3_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
52074 #define NIG_REG_INT_STS_WR_9_P3_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
52076 #define NIG_REG_INT_STS_WR_9_P3_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
52078 #define NIG_REG_INT_STS_WR_9_P3_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
52080 #define NIG_REG_INT_STS_WR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
52082 #define NIG_REG_INT_STS_WR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
52084 #define NIG_REG_INT_STS_WR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
52086 #define NIG_REG_INT_STS_WR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
52088 #define NIG_REG_INT_STS_WR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
52090 #define NIG_REG_INT_STS_WR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
52092 #define NIG_REG_INT_STS_WR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
52094 #define NIG_REG_INT_STS_WR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
52096 #define NIG_REG_INT_STS_WR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
52099 #define NIG_REG_INT_STS_CLR_9_P3_TX_PAUSE_TOO_LONG_INT (0x1<<0) // Triggered by TX path being paused for the configured period of time.
52101 #define NIG_REG_INT_STS_CLR_9_P3_TC0_PAUSE_TOO_LONG_INT (0x1<<1) // Triggered by TC being paused for the configured period of time.
52103 #define NIG_REG_INT_STS_CLR_9_P3_TC1_PAUSE_TOO_LONG_INT (0x1<<2) // Triggered by TC being paused for the configured period of time.
52105 #define NIG_REG_INT_STS_CLR_9_P3_TC2_PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC being paused for the configured period of time.
52107 #define NIG_REG_INT_STS_CLR_9_P3_TC3_PAUSE_TOO_LONG_INT (0x1<<4) // Triggered by TC being paused for the configured period of time.
52109 #define NIG_REG_INT_STS_CLR_9_P3_TC4_PAUSE_TOO_LONG_INT (0x1<<5) // Triggered by TC being paused for the configured period of time.
52111 #define NIG_REG_INT_STS_CLR_9_P3_TC5_PAUSE_TOO_LONG_INT (0x1<<6) // Triggered by TC being paused for the configured period of time.
52113 #define NIG_REG_INT_STS_CLR_9_P3_TC6_PAUSE_TOO_LONG_INT (0x1<<7) // Triggered by TC being paused for the configured period of time.
52115 #define NIG_REG_INT_STS_CLR_9_P3_TC7_PAUSE_TOO_LONG_INT (0x1<<8) // Triggered by TC being paused for the configured period of time.
52117 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT (0x1<<9) // Triggered by TC being paused for the configured period of time.
52119 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT (0x1<<10) // Triggered by TC being paused for the configured period of time.
52121 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT (0x1<<11) // Triggered by TC being paused for the configured period of time.
52123 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT (0x1<<12) // Triggered by TC being paused for the configured period of time.
52125 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT (0x1<<13) // Triggered by TC being paused for the configured period of time.
52127 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT (0x1<<14) // Triggered by TC being paused for the configured period of time.
52129 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT (0x1<<15) // Triggered by TC being paused for the configured period of time.
52131 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT (0x1<<16) // Triggered by TC being paused for the configured period of time.
52133 #define NIG_REG_INT_STS_CLR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT (0x1<<17) // Triggered by TC being paused for the configured period of time.
52135 #define NIG_REG_PRTY_MASK 0x5000a4UL //Access:RW DataWidth:0x1 // Multi Field Register.
52136 #define NIG_REG_PRTY_MASK_DATAPATH_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS.DATAPATH_PARITY_ERROR .
52139 #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM107_I_MEM_PRTY .
52141 #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM103_I_MEM_PRTY .
52143 #define NIG_REG_PRTY_MASK_H_0_MEM104_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM104_I_MEM_PRTY .
52145 #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM105_I_MEM_PRTY .
52147 #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM106_I_MEM_PRTY .
52149 #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM072_I_MEM_PRTY .
52151 #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM071_I_MEM_PRTY .
52153 #define NIG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM074_I_MEM_PRTY .
52155 #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY .
52157 #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM076_I_MEM_PRTY .
52159 #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM075_I_MEM_PRTY .
52161 #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM078_I_MEM_PRTY .
52163 #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM077_I_MEM_PRTY .
52165 #define NIG_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
52167 #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
52169 #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
52171 #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
52173 #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY .
52175 #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM066_I_MEM_PRTY .
52177 #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM067_I_MEM_PRTY .
52179 #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM068_I_MEM_PRTY .
52181 #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY .
52183 #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY .
52185 #define NIG_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
52187 #define NIG_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
52189 #define NIG_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
52191 #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
52193 #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
52195 #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
52197 #define NIG_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
52199 #define NIG_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
52201 #define NIG_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
52203 #define NIG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY .
52205 #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM090_I_MEM_PRTY .
52207 #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY .
52209 #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM092_I_MEM_PRTY .
52211 #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM091_I_MEM_PRTY .
52213 #define NIG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM109_I_MEM_PRTY .
52215 #define NIG_REG_PRTY_MASK_H_0_MEM110_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM110_I_MEM_PRTY .
52217 #define NIG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
52219 #define NIG_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
52221 #define NIG_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
52223 #define NIG_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
52225 #define NIG_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
52227 #define NIG_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
52229 #define NIG_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
52231 #define NIG_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
52233 #define NIG_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
52235 #define NIG_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
52237 #define NIG_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
52239 #define NIG_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
52241 #define NIG_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
52243 #define NIG_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
52245 #define NIG_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
52247 #define NIG_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
52249 #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY .
52251 #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM081_I_MEM_PRTY .
52253 #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM082_I_MEM_PRTY .
52255 #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM083_I_MEM_PRTY .
52258 #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
52260 #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
52262 #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
52264 #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
52266 #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
52268 #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
52270 #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
52272 #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
52274 #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
52276 #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
52278 #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
52280 #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY .
52282 #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY .
52284 #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM041_I_MEM_PRTY .
52286 #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY .
52288 #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY .
52290 #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
52292 #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
52294 #define NIG_REG_PRTY_MASK_H_1_MEM091_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM091_I_MEM_PRTY .
52296 #define NIG_REG_PRTY_MASK_H_1_MEM092_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM092_I_MEM_PRTY .
52298 #define NIG_REG_PRTY_MASK_H_1_MEM093_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM093_I_MEM_PRTY .
52300 #define NIG_REG_PRTY_MASK_H_1_MEM094_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM094_I_MEM_PRTY .
52302 #define NIG_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
52304 #define NIG_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
52306 #define NIG_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
52308 #define NIG_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
52310 #define NIG_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
52312 #define NIG_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
52314 #define NIG_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
52316 #define NIG_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
52318 #define NIG_REG_PRTY_MASK_H_1_MEM095_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM095_I_MEM_PRTY .
52320 #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM084_I_MEM_PRTY .
52322 #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM085_I_MEM_PRTY .
52324 #define NIG_REG_PRTY_MASK_H_1_MEM086_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM086_I_MEM_PRTY .
52326 #define NIG_REG_PRTY_MASK_H_1_MEM087_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM087_I_MEM_PRTY .
52328 #define NIG_REG_PRTY_MASK_H_1_MEM088_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM088_I_MEM_PRTY .
52330 #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY .
52332 #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY .
52334 #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY .
52336 #define NIG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM077_I_MEM_PRTY .
52338 #define NIG_REG_PRTY_MASK_H_1_MEM078_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM078_I_MEM_PRTY .
52340 #define NIG_REG_PRTY_MASK_H_1_MEM079_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM079_I_MEM_PRTY .
52342 #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
52344 #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
52346 #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM065_I_MEM_PRTY .
52348 #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
52350 #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
52352 #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
52354 #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM069_I_MEM_PRTY .
52356 #define NIG_REG_PRTY_MASK_H_1_MEM070_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM070_I_MEM_PRTY .
52358 #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM071_I_MEM_PRTY .
52360 #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY .
52362 #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
52364 #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
52366 #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
52368 #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
52370 #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
52372 #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
52374 #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
52376 #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
52378 #define NIG_REG_PRTY_MASK_H_1_MEM099_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM099_I_MEM_PRTY .
52380 #define NIG_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM100_I_MEM_PRTY .
52383 #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM096_I_MEM_PRTY .
52385 #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM097_I_MEM_PRTY .
52387 #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM098_I_MEM_PRTY .
52389 #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY .
52391 #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM032_I_MEM_PRTY .
52393 #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM033_I_MEM_PRTY .
52395 #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_I_MEM_PRTY .
52397 #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM019_I_MEM_PRTY .
52399 #define NIG_REG_PRTY_MASK_H_2_MEM020_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM020_I_MEM_PRTY .
52401 #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM021_I_MEM_PRTY .
52403 #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM022_I_MEM_PRTY .
52405 #define NIG_REG_PRTY_MASK_H_2_MEM099_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM099_I_MEM_PRTY .
52407 #define NIG_REG_PRTY_MASK_H_2_MEM100_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM100_I_MEM_PRTY .
52409 #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM101_I_MEM_PRTY .
52411 #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM102_I_MEM_PRTY .
52413 #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM023_I_MEM_PRTY .
52415 #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM024_I_MEM_PRTY .
52417 #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY .
52419 #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY .
52421 #define NIG_REG_PRTY_MASK_H_2_MEM083_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM083_I_MEM_PRTY .
52423 #define NIG_REG_PRTY_MASK_H_2_MEM084_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM084_I_MEM_PRTY .
52425 #define NIG_REG_PRTY_MASK_H_2_MEM085_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM085_I_MEM_PRTY .
52427 #define NIG_REG_PRTY_MASK_H_2_MEM086_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM086_I_MEM_PRTY .
52429 #define NIG_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY .
52431 #define NIG_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM008_I_MEM_PRTY .
52433 #define NIG_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
52435 #define NIG_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
52437 #define NIG_REG_PRTY_MASK_H_2_MEM087_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM087_I_MEM_PRTY .
52439 #define NIG_REG_PRTY_MASK_H_2_MEM088_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM088_I_MEM_PRTY .
52441 #define NIG_REG_PRTY_MASK_H_2_MEM089_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM089_I_MEM_PRTY .
52443 #define NIG_REG_PRTY_MASK_H_2_MEM090_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM090_I_MEM_PRTY .
52445 #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM045_I_MEM_PRTY .
52447 #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM046_I_MEM_PRTY .
52449 #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM107_I_MEM_PRTY .
52451 #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM047_I_MEM_PRTY .
52453 #define NIG_REG_PRTY_MASK_H_2_MEM048_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM048_I_MEM_PRTY .
52455 #define NIG_REG_PRTY_MASK_H_2_MEM053_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM053_I_MEM_PRTY .
52457 #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
52459 #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
52461 #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM103_I_MEM_PRTY .
52463 #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY .
52465 #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM108_I_MEM_PRTY .
52467 #define NIG_REG_PRTY_MASK_H_2_MEM049_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM049_I_MEM_PRTY .
52469 #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM050_I_MEM_PRTY .
52471 #define NIG_REG_PRTY_MASK_H_2_MEM054_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM054_I_MEM_PRTY .
52473 #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM029_I_MEM_PRTY .
52475 #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM030_I_MEM_PRTY .
52477 #define NIG_REG_PRTY_MASK_H_2_MEM031_EXT_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_EXT_I_MEM_PRTY .
52479 #define NIG_REG_PRTY_MASK_H_2_MEM034_EXT_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_EXT_I_MEM_PRTY .
52481 #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM095_I_MEM_PRTY .
52484 #define NIG_REG_PRTY_MASK_H_3_MEM011_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM011_I_MEM_PRTY .
52486 #define NIG_REG_PRTY_MASK_H_3_MEM012_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM012_I_MEM_PRTY .
52488 #define NIG_REG_PRTY_MASK_H_3_MEM013_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM013_I_MEM_PRTY .
52490 #define NIG_REG_PRTY_MASK_H_3_MEM014_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM014_I_MEM_PRTY .
52492 #define NIG_REG_PRTY_MASK_H_3_MEM001_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM001_I_MEM_PRTY .
52494 #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY .
52496 #define NIG_REG_PRTY_MASK_H_3_MEM079_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM079_I_MEM_PRTY .
52498 #define NIG_REG_PRTY_MASK_H_3_MEM080_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM080_I_MEM_PRTY .
52500 #define NIG_REG_PRTY_MASK_H_3_MEM081_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM081_I_MEM_PRTY .
52502 #define NIG_REG_PRTY_MASK_H_3_MEM082_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM082_I_MEM_PRTY .
52504 #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY .
52506 #define NIG_REG_PRTY_MASK_H_3_MEM004_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM004_I_MEM_PRTY .
52508 #define NIG_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY .
52510 #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM006_I_MEM_PRTY .
52512 #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM023_I_MEM_PRTY .
52514 #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM024_I_MEM_PRTY .
52516 #define NIG_REG_PRTY_MASK_H_3_MEM017_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM017_I_MEM_PRTY .
52518 #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM018_I_MEM_PRTY .
52520 #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM093_I_MEM_PRTY .
52522 #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM094_I_MEM_PRTY .
52524 #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM019_I_MEM_PRTY .
52526 #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM020_I_MEM_PRTY .
52528 #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM040_I_MEM_PRTY .
52530 #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM036_I_MEM_PRTY .
52532 #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM039_I_MEM_PRTY .
52534 #define NIG_REG_PRTY_MASK_H_3_MEM041_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM041_I_MEM_PRTY .
52536 #define NIG_REG_PRTY_MASK_H_3_MEM042_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM042_I_MEM_PRTY .
52538 #define NIG_REG_PRTY_MASK_H_3_MEM043_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM043_I_MEM_PRTY .
52540 #define NIG_REG_PRTY_MASK_H_3_MEM044_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM044_I_MEM_PRTY .
52542 #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM038_I_MEM_PRTY .
52544 #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM037_I_MEM_PRTY .
52547 #define NIG_REG_CLOSE_GATE_DISABLE 0x500800UL //Access:RW DataWidth:0x1 // Close-gate function disable bit: 0 - egress drain mode is enabled when close-gate input from MISC to NIG is active; 1 - close-gate input is ignored. (The egress drain mode is for dropping all packets in the TX pipe without forwarding the packets to the TX MAC.).
52560 #define NIG_REG_MNG_TO_MCP 0x500834UL //Access:RW DataWidth:0x1 // Direct all management traffic to BMB toward MCP.
52561 #define NIG_REG_FWD_PKT_TO_STORM 0x500838UL //Access:RW DataWidth:0x1 // Select bit for choosing between XSTORM and YSTORM for forwarding RX packets. 0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.
52566 #define NIG_REG_CM_HDR_T_BIT (0x1<<8) // T-bit to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
52568 #define NIG_REG_CM_HDR_DSTSTORMFLG (0x1<<9) // DstStormFlg to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
52570 #define NIG_REG_CM_HDR_CONDOMAIN (0x1<<10) // ConnectionDomainExist to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
52572 #define NIG_REG_TX_LB_DROP_FWDERR 0x500844UL //Access:RW DataWidth:0x1 // Global configuration for selecting whether to drop the per-PF drop and per-VPORT drop packets or forward the packet to the destination with the error bit set. Set this bit to 1 to forward the packet to the destination with error (as if the error indication in the BTB SOP descriptor as set). This bit affects both the main TX traffic and LB traffic.
52573 #define NIG_REG_TX_LB_VPORT_DROP_0 0x500848UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52574 #define NIG_REG_TX_LB_VPORT_DROP_1 0x50084cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52575 #define NIG_REG_TX_LB_VPORT_DROP_2 0x500850UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52576 #define NIG_REG_TX_LB_VPORT_DROP_3 0x500854UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52577 #define NIG_REG_TX_LB_VPORT_DROP_4 0x500858UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52578 #define NIG_REG_TX_LB_VPORT_DROP_5 0x50085cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52579 #define NIG_REG_TX_LB_VPORT_DROP_6 0x500860UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52580 #define NIG_REG_TX_LB_VPORT_DROP_7 0x500864UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52581 #define NIG_REG_TX_LB_VPORT_DROP_8 0x500868UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52582 #define NIG_REG_TX_LB_VPORT_DROP_9 0x50086cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52583 #define NIG_REG_TX_LB_VPORT_DROP_10 0x500870UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52584 #define NIG_REG_TX_LB_VPORT_DROP_11 0x500874UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52585 #define NIG_REG_TX_LB_VPORT_DROP_12 0x500878UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52586 #define NIG_REG_TX_LB_VPORT_DROP_13 0x50087cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52587 #define NIG_REG_TX_LB_VPORT_DROP_14 0x500880UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52588 #define NIG_REG_TX_LB_VPORT_DROP_15 0x500884UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52589 #define NIG_REG_TX_LB_VPORT_DROP_16 0x500888UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52590 #define NIG_REG_TX_LB_VPORT_DROP_17 0x50088cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52591 #define NIG_REG_TX_LB_VPORT_DROP_18 0x500890UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52592 #define NIG_REG_TX_LB_VPORT_DROP_19 0x500894UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52593 #define NIG_REG_TX_LB_VPORT_DROP_20 0x500898UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52594 #define NIG_REG_TX_LB_VPORT_DROP_21 0x50089cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52595 #define NIG_REG_TX_LB_VPORT_DROP_22 0x5008a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52596 #define NIG_REG_TX_LB_VPORT_DROP_23 0x5008a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52597 #define NIG_REG_TX_LB_VPORT_DROP_24 0x5008a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52598 #define NIG_REG_TX_LB_VPORT_DROP_25 0x5008acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52599 #define NIG_REG_TX_LB_VPORT_DROP_26 0x5008b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52600 #define NIG_REG_TX_LB_VPORT_DROP_27 0x5008b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52601 #define NIG_REG_TX_LB_VPORT_DROP_28 0x5008b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52602 #define NIG_REG_TX_LB_VPORT_DROP_29 0x5008bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52603 #define NIG_REG_TX_LB_VPORT_DROP_30 0x5008c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52604 #define NIG_REG_TX_LB_VPORT_DROP_31 0x5008c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52605 #define NIG_REG_TX_LB_VPORT_DROP_32 0x5008c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52606 #define NIG_REG_TX_LB_VPORT_DROP_33 0x5008ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52607 #define NIG_REG_TX_LB_VPORT_DROP_34 0x5008d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52608 #define NIG_REG_TX_LB_VPORT_DROP_35 0x5008d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52609 #define NIG_REG_TX_LB_VPORT_DROP_36 0x5008d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52610 #define NIG_REG_TX_LB_VPORT_DROP_37 0x5008dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52611 #define NIG_REG_TX_LB_VPORT_DROP_38 0x5008e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52612 #define NIG_REG_TX_LB_VPORT_DROP_39 0x5008e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52613 #define NIG_REG_TX_LB_VPORT_DROP_40 0x5008e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52614 #define NIG_REG_TX_LB_VPORT_DROP_41 0x5008ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52615 #define NIG_REG_TX_LB_VPORT_DROP_42 0x5008f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52616 #define NIG_REG_TX_LB_VPORT_DROP_43 0x5008f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52617 #define NIG_REG_TX_LB_VPORT_DROP_44 0x5008f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52618 #define NIG_REG_TX_LB_VPORT_DROP_45 0x5008fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52619 #define NIG_REG_TX_LB_VPORT_DROP_46 0x500900UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52620 #define NIG_REG_TX_LB_VPORT_DROP_47 0x500904UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52621 #define NIG_REG_TX_LB_VPORT_DROP_48 0x500908UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52622 #define NIG_REG_TX_LB_VPORT_DROP_49 0x50090cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52623 #define NIG_REG_TX_LB_VPORT_DROP_50 0x500910UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52624 #define NIG_REG_TX_LB_VPORT_DROP_51 0x500914UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52625 #define NIG_REG_TX_LB_VPORT_DROP_52 0x500918UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52626 #define NIG_REG_TX_LB_VPORT_DROP_53 0x50091cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52627 #define NIG_REG_TX_LB_VPORT_DROP_54 0x500920UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52628 #define NIG_REG_TX_LB_VPORT_DROP_55 0x500924UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52629 #define NIG_REG_TX_LB_VPORT_DROP_56 0x500928UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52630 #define NIG_REG_TX_LB_VPORT_DROP_57 0x50092cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52631 #define NIG_REG_TX_LB_VPORT_DROP_58 0x500930UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52632 #define NIG_REG_TX_LB_VPORT_DROP_59 0x500934UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52633 #define NIG_REG_TX_LB_VPORT_DROP_60 0x500938UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52634 #define NIG_REG_TX_LB_VPORT_DROP_61 0x50093cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52635 #define NIG_REG_TX_LB_VPORT_DROP_62 0x500940UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52636 #define NIG_REG_TX_LB_VPORT_DROP_63 0x500944UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52637 #define NIG_REG_TX_LB_VPORT_DROP_64 0x500948UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52638 #define NIG_REG_TX_LB_VPORT_DROP_65 0x50094cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52639 #define NIG_REG_TX_LB_VPORT_DROP_66 0x500950UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52640 #define NIG_REG_TX_LB_VPORT_DROP_67 0x500954UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52641 #define NIG_REG_TX_LB_VPORT_DROP_68 0x500958UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52642 #define NIG_REG_TX_LB_VPORT_DROP_69 0x50095cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52643 #define NIG_REG_TX_LB_VPORT_DROP_70 0x500960UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52644 #define NIG_REG_TX_LB_VPORT_DROP_71 0x500964UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52645 #define NIG_REG_TX_LB_VPORT_DROP_72 0x500968UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52646 #define NIG_REG_TX_LB_VPORT_DROP_73 0x50096cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52647 #define NIG_REG_TX_LB_VPORT_DROP_74 0x500970UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52648 #define NIG_REG_TX_LB_VPORT_DROP_75 0x500974UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52649 #define NIG_REG_TX_LB_VPORT_DROP_76 0x500978UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52650 #define NIG_REG_TX_LB_VPORT_DROP_77 0x50097cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52651 #define NIG_REG_TX_LB_VPORT_DROP_78 0x500980UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52652 #define NIG_REG_TX_LB_VPORT_DROP_79 0x500984UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52653 #define NIG_REG_TX_LB_VPORT_DROP_80 0x500988UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52654 #define NIG_REG_TX_LB_VPORT_DROP_81 0x50098cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52655 #define NIG_REG_TX_LB_VPORT_DROP_82 0x500990UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52656 #define NIG_REG_TX_LB_VPORT_DROP_83 0x500994UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52657 #define NIG_REG_TX_LB_VPORT_DROP_84 0x500998UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52658 #define NIG_REG_TX_LB_VPORT_DROP_85 0x50099cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52659 #define NIG_REG_TX_LB_VPORT_DROP_86 0x5009a0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52660 #define NIG_REG_TX_LB_VPORT_DROP_87 0x5009a4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52661 #define NIG_REG_TX_LB_VPORT_DROP_88 0x5009a8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52662 #define NIG_REG_TX_LB_VPORT_DROP_89 0x5009acUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52663 #define NIG_REG_TX_LB_VPORT_DROP_90 0x5009b0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52664 #define NIG_REG_TX_LB_VPORT_DROP_91 0x5009b4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52665 #define NIG_REG_TX_LB_VPORT_DROP_92 0x5009b8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52666 #define NIG_REG_TX_LB_VPORT_DROP_93 0x5009bcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52667 #define NIG_REG_TX_LB_VPORT_DROP_94 0x5009c0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52668 #define NIG_REG_TX_LB_VPORT_DROP_95 0x5009c4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52669 #define NIG_REG_TX_LB_VPORT_DROP_96 0x5009c8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52670 #define NIG_REG_TX_LB_VPORT_DROP_97 0x5009ccUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52671 #define NIG_REG_TX_LB_VPORT_DROP_98 0x5009d0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52672 #define NIG_REG_TX_LB_VPORT_DROP_99 0x5009d4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52673 #define NIG_REG_TX_LB_VPORT_DROP_100 0x5009d8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52674 #define NIG_REG_TX_LB_VPORT_DROP_101 0x5009dcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52675 #define NIG_REG_TX_LB_VPORT_DROP_102 0x5009e0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52676 #define NIG_REG_TX_LB_VPORT_DROP_103 0x5009e4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52677 #define NIG_REG_TX_LB_VPORT_DROP_104 0x5009e8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52678 #define NIG_REG_TX_LB_VPORT_DROP_105 0x5009ecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52679 #define NIG_REG_TX_LB_VPORT_DROP_106 0x5009f0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52680 #define NIG_REG_TX_LB_VPORT_DROP_107 0x5009f4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52681 #define NIG_REG_TX_LB_VPORT_DROP_108 0x5009f8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52682 #define NIG_REG_TX_LB_VPORT_DROP_109 0x5009fcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52683 #define NIG_REG_TX_LB_VPORT_DROP_110 0x500a00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52684 #define NIG_REG_TX_LB_VPORT_DROP_111 0x500a04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52685 #define NIG_REG_TX_LB_VPORT_DROP_112 0x500a08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52686 #define NIG_REG_TX_LB_VPORT_DROP_113 0x500a0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52687 #define NIG_REG_TX_LB_VPORT_DROP_114 0x500a10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52688 #define NIG_REG_TX_LB_VPORT_DROP_115 0x500a14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52689 #define NIG_REG_TX_LB_VPORT_DROP_116 0x500a18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52690 #define NIG_REG_TX_LB_VPORT_DROP_117 0x500a1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52691 #define NIG_REG_TX_LB_VPORT_DROP_118 0x500a20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52692 #define NIG_REG_TX_LB_VPORT_DROP_119 0x500a24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52693 #define NIG_REG_TX_LB_VPORT_DROP_120 0x500a28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52694 #define NIG_REG_TX_LB_VPORT_DROP_121 0x500a2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52695 #define NIG_REG_TX_LB_VPORT_DROP_122 0x500a30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52696 #define NIG_REG_TX_LB_VPORT_DROP_123 0x500a34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52697 #define NIG_REG_TX_LB_VPORT_DROP_124 0x500a38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52698 #define NIG_REG_TX_LB_VPORT_DROP_125 0x500a3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52699 #define NIG_REG_TX_LB_VPORT_DROP_126 0x500a40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52700 #define NIG_REG_TX_LB_VPORT_DROP_127 0x500a44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52701 #define NIG_REG_TX_LB_VPORT_DROP_128 0x500a48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52702 #define NIG_REG_TX_LB_VPORT_DROP_129 0x500a4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52703 #define NIG_REG_TX_LB_VPORT_DROP_130 0x500a50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52704 #define NIG_REG_TX_LB_VPORT_DROP_131 0x500a54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52705 #define NIG_REG_TX_LB_VPORT_DROP_132 0x500a58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52706 #define NIG_REG_TX_LB_VPORT_DROP_133 0x500a5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52707 #define NIG_REG_TX_LB_VPORT_DROP_134 0x500a60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52708 #define NIG_REG_TX_LB_VPORT_DROP_135 0x500a64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52709 #define NIG_REG_TX_LB_VPORT_DROP_136 0x500a68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52710 #define NIG_REG_TX_LB_VPORT_DROP_137 0x500a6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52711 #define NIG_REG_TX_LB_VPORT_DROP_138 0x500a70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52712 #define NIG_REG_TX_LB_VPORT_DROP_139 0x500a74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52713 #define NIG_REG_TX_LB_VPORT_DROP_140 0x500a78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52714 #define NIG_REG_TX_LB_VPORT_DROP_141 0x500a7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52715 #define NIG_REG_TX_LB_VPORT_DROP_142 0x500a80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52716 #define NIG_REG_TX_LB_VPORT_DROP_143 0x500a84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52717 #define NIG_REG_TX_LB_VPORT_DROP_144 0x500a88UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52718 #define NIG_REG_TX_LB_VPORT_DROP_145 0x500a8cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52719 #define NIG_REG_TX_LB_VPORT_DROP_146 0x500a90UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52720 #define NIG_REG_TX_LB_VPORT_DROP_147 0x500a94UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52721 #define NIG_REG_TX_LB_VPORT_DROP_148 0x500a98UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52722 #define NIG_REG_TX_LB_VPORT_DROP_149 0x500a9cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52723 #define NIG_REG_TX_LB_VPORT_DROP_150 0x500aa0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52724 #define NIG_REG_TX_LB_VPORT_DROP_151 0x500aa4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52725 #define NIG_REG_TX_LB_VPORT_DROP_152 0x500aa8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52726 #define NIG_REG_TX_LB_VPORT_DROP_153 0x500aacUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52727 #define NIG_REG_TX_LB_VPORT_DROP_154 0x500ab0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52728 #define NIG_REG_TX_LB_VPORT_DROP_155 0x500ab4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52729 #define NIG_REG_TX_LB_VPORT_DROP_156 0x500ab8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52730 #define NIG_REG_TX_LB_VPORT_DROP_157 0x500abcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52731 #define NIG_REG_TX_LB_VPORT_DROP_158 0x500ac0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52732 #define NIG_REG_TX_LB_VPORT_DROP_159 0x500ac4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52733 #define NIG_REG_TX_LB_VPORT_DROP_160 0x500ac8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52734 #define NIG_REG_TX_LB_VPORT_DROP_161 0x500accUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52735 #define NIG_REG_TX_LB_VPORT_DROP_162 0x500ad0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52736 #define NIG_REG_TX_LB_VPORT_DROP_163 0x500ad4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52737 #define NIG_REG_TX_LB_VPORT_DROP_164 0x500ad8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52738 #define NIG_REG_TX_LB_VPORT_DROP_165 0x500adcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52739 #define NIG_REG_TX_LB_VPORT_DROP_166 0x500ae0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52740 #define NIG_REG_TX_LB_VPORT_DROP_167 0x500ae4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52741 #define NIG_REG_TX_LB_VPORT_DROP_168 0x500ae8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52742 #define NIG_REG_TX_LB_VPORT_DROP_169 0x500aecUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52743 #define NIG_REG_TX_LB_VPORT_DROP_170 0x500af0UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52744 #define NIG_REG_TX_LB_VPORT_DROP_171 0x500af4UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52745 #define NIG_REG_TX_LB_VPORT_DROP_172 0x500af8UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52746 #define NIG_REG_TX_LB_VPORT_DROP_173 0x500afcUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52747 #define NIG_REG_TX_LB_VPORT_DROP_174 0x500b00UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52748 #define NIG_REG_TX_LB_VPORT_DROP_175 0x500b04UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52749 #define NIG_REG_TX_LB_VPORT_DROP_176 0x500b08UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52750 #define NIG_REG_TX_LB_VPORT_DROP_177 0x500b0cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52751 #define NIG_REG_TX_LB_VPORT_DROP_178 0x500b10UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52752 #define NIG_REG_TX_LB_VPORT_DROP_179 0x500b14UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52753 #define NIG_REG_TX_LB_VPORT_DROP_180 0x500b18UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52754 #define NIG_REG_TX_LB_VPORT_DROP_181 0x500b1cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52755 #define NIG_REG_TX_LB_VPORT_DROP_182 0x500b20UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52756 #define NIG_REG_TX_LB_VPORT_DROP_183 0x500b24UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52757 #define NIG_REG_TX_LB_VPORT_DROP_184 0x500b28UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52758 #define NIG_REG_TX_LB_VPORT_DROP_185 0x500b2cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52759 #define NIG_REG_TX_LB_VPORT_DROP_186 0x500b30UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52760 #define NIG_REG_TX_LB_VPORT_DROP_187 0x500b34UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52761 #define NIG_REG_TX_LB_VPORT_DROP_188 0x500b38UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52762 #define NIG_REG_TX_LB_VPORT_DROP_189 0x500b3cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52763 #define NIG_REG_TX_LB_VPORT_DROP_190 0x500b40UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52764 #define NIG_REG_TX_LB_VPORT_DROP_191 0x500b44UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52765 #define NIG_REG_TX_LB_VPORT_DROP_192 0x500b48UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52766 #define NIG_REG_TX_LB_VPORT_DROP_193 0x500b4cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52767 #define NIG_REG_TX_LB_VPORT_DROP_194 0x500b50UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52768 #define NIG_REG_TX_LB_VPORT_DROP_195 0x500b54UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52769 #define NIG_REG_TX_LB_VPORT_DROP_196 0x500b58UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52770 #define NIG_REG_TX_LB_VPORT_DROP_197 0x500b5cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52771 #define NIG_REG_TX_LB_VPORT_DROP_198 0x500b60UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52772 #define NIG_REG_TX_LB_VPORT_DROP_199 0x500b64UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52773 #define NIG_REG_TX_LB_VPORT_DROP_200 0x500b68UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52774 #define NIG_REG_TX_LB_VPORT_DROP_201 0x500b6cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52775 #define NIG_REG_TX_LB_VPORT_DROP_202 0x500b70UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52776 #define NIG_REG_TX_LB_VPORT_DROP_203 0x500b74UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52777 #define NIG_REG_TX_LB_VPORT_DROP_204 0x500b78UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52778 #define NIG_REG_TX_LB_VPORT_DROP_205 0x500b7cUL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52779 #define NIG_REG_TX_LB_VPORT_DROP_206 0x500b80UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52780 #define NIG_REG_TX_LB_VPORT_DROP_207 0x500b84UL //Access:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52781 #define NIG_REG_TX_LB_PF_DROP_PERPF 0x500c00UL //Access:RW DataWidth:0x1 // Per-PF drop configuration to be used for main and LB traffic of all ports. Set the bit to 1 to enable the dropping of packets.
52788 #define NIG_REG_DORQ_IN_EN 0x500e00UL //Access:RW DataWidth:0x1 // Input enable for the DORQ interface.
52789 #define NIG_REG_DEBUG_IN_EN 0x500e04UL //Access:RW DataWidth:0x1 // Input enable for debug traffic.
52790 #define NIG_REG_STORM_OUT_EN 0x500e08UL //Access:RW DataWidth:0x1 // Output enable for the STORM interface. This configuration should be static during run-time.
52791 #define NIG_REG_PPP_OUT_EN 0x500e0cUL //Access:RW DataWidth:0x1 // Output enable of message to PXP IF.
52792 #define NIG_REG_MAC_IN_EN 0x500e10UL //Access:RW DataWidth:0x1 // Input enable for RX MAC interface.
52793 #define NIG_REG_MAC_OUT_EN 0x500e14UL //Access:RW DataWidth:0x1 // Output enable for TX MAC interface.
52794 #define NIG_REG_RX_BRB_OUT_EN 0x500e18UL //Access:RW DataWidth:0x1 // Output enble for RX path to BRB.
52795 #define NIG_REG_LB_BRB_OUT_EN 0x500e1cUL //Access:RW DataWidth:0x1 // Output enable for LB path to BRB.
52796 #define NIG_REG_FLOWCTRL_OUT_EN 0x500e20UL //Access:RW DataWidth:0x1 // Output enable for flow control interfaces to the MAC.
52798 #define NIG_REG_RX_MACFIFO_EMPTY 0x500e44UL //Access:R DataWidth:0x1 // RX FIFO for receiving data from MAC is empty.
52799 #define NIG_REG_RX_MACFIFO_FULL 0x500e48UL //Access:R DataWidth:0x1 // RX FIFO for receiving data from MAC is full.
52800 #define NIG_REG_TX_MACFIFO_ALM_FULL 0x500e4cUL //Access:R DataWidth:0x1 // TX FIFO for transmitting data to MAC is almost full.
52801 #define NIG_REG_TX_MACFIFO_EMPTY 0x500e50UL //Access:R DataWidth:0x1 // TX FIFO for transmitting data to MAC is empty.
52802 #define NIG_REG_TX_MACFIFO_FULL 0x500f00UL //Access:R DataWidth:0x1 // TX FIFO for transmitting data to MAC is full.
52805 #define NIG_REG_RX_PKT_HAS_FCS 0x501008UL //Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that the packet has the FCS field at the end of the packet.
52826 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. This enables the comparison of the GRE protocol type field to the configured *gre_eth_type.
52828 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encapsulation. This enables the comparison of the GRE protocol type field to the configured *ipv4_type and *ipv6_type.
52830 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1<<2) // Enable bit for VXLAN encapsulation. This enables the comparison of the UDP destination port number to the configured *vxlan_port.
52874 #define NIG_REG_LLH_IPV4_IPV6_0 0x501104UL //Access:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
52875 #define NIG_REG_LLH_IPV4_IPV6_1 0x501108UL //Access:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
52876 #define NIG_REG_LLH_IPV4_IPV6_2 0x50110cUL //Access:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
52884 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_BRCST (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
52886 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ALLMLCST (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
52888 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV4MLCST (0x1<<2) // Mask bit for forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to MCP.
52890 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV6_MLCST (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
52892 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UNCST (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
52894 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC0 (0x1<<5) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to MCP.
52896 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC1 (0x1<<6) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to MCP.
52898 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC2 (0x1<<7) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to MCP.
52900 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC3 (0x1<<8) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to MCP.
52902 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC4 (0x1<<9) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to MCP.
52904 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC5 (0x1<<10) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to MCP.
52906 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE0 (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
52908 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE1 (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
52910 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ARP (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and Bcast address to MCP.
52912 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP0 (0x1<<14) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
52914 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP1 (0x1<<15) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
52916 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP2 (0x1<<16) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
52918 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP0 (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
52920 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP1 (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
52922 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP2 (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
52924 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_DST (0x1<<20) // Mask bit for forwarding packets with NetBIOS TCP destination port 137/138/139 to MCP.
52926 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_SRC (0x1<<21) // Mask bit for forwarding packets with NetBIOS TCP source port 137/138 /139 to MCP.
52928 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP0 (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
52930 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP1 (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
52932 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP2 (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
52934 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_RMCP (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
52936 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_DST (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
52938 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_SRC (0x1<<27) // Mask bit for forwarding packets with NetBIOS UDP source port 137/138 /139 to MCP.
52940 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_DHCP (0x1<<28) // Mask bit for forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to MCP.
52942 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_NA (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
52944 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_RA (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
52946 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6 (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
52949 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ANY (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to MCP.
52951 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_NONE (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to MCP.
52953 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID0 (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to MCP.
52955 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID1 (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to MCP.
52957 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID2 (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to MCP.
52960 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_ANY (0x1<<0) // Mask bit for forwarding packets with outer tag present to MCP.
52962 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_NONE (0x1<<1) // Mask bit for forwarding packets with no outer tag to MCP.
52964 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG0 (0x1<<2) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id0 to MCP.
52966 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG1 (0x1<<3) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id1 to MCP.
52968 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_PF (0x1<<4) // Mask bit for forwarding packets with outer tag matching the outer tag of one of the enabled PFs to MCP.
52971 #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ARP (0x1<<0) // Mask bit for forwarding packets with Ethertype matching llh_arp_type to MCP.
52973 #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4 (0x1<<1) // Mask bit for forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to MCP.
52975 #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6 (0x1<<2) // Mask bit for forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to MCP.
52977 #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_ER (0x1<<3) // Mask bit for forwarding ICMPv4 packets with ICMP type 8 to MCP.
52979 #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_ER (0x1<<4) // Mask bit for forwarding ICMPv6 packets with ICMP type 128 to MCP.
52981 #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_NS (0x1<<5) // Mask bit for forwarding ICMPv6 packets with ICMP type 135 to MCP.
52983 #define NIG_REG_RX_LLH_SVOL_MCP_FWD_ALLPF 0x501138UL //Access:RW DataWidth:0x1 // Enable bit for forwarding packets from all PFs, including packets that failed PF classification, to MCP in multifunction mode.
52984 #define NIG_REG_RX_LLH_SVOL_MCP_FWD_PERPF 0x50113cUL //Access:RW DataWidth:0x1 // Enable bit for forwarding packets for each PF to MCP in multifunction mode. This is a per-PF split register.
52986 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_BRCST (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the host.
52988 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ALLMLCST (0x1<<1) // Mask bit for not forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the host.
52990 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV4MLCST (0x1<<2) // Mask bit for not forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to the host.
52992 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLCST (0x1<<3) // Mask bit for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the host.
52994 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UNCST (0x1<<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the host.
52996 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC0 (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to the host.
52998 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC1 (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to the host.
53000 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC2 (0x1<<7) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to the host.
53002 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC3 (0x1<<8) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to the host.
53004 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC4 (0x1<<9) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to the host.
53006 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC5 (0x1<<10) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to the host.
53008 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE0 (0x1<<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the host.
53010 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE1 (0x1<<12) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
53012 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ARP (0x1<<13) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the host.
53014 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP0 (0x1<<14) // Mask bit for not forwarding packets with the IP destination address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the host.
53016 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP1 (0x1<<15) // Mask bit for not forwarding packets with the IP destination address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the host.
53018 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP2 (0x1<<16) // Mask bit for not forwarding packets with the IP destination address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the host.
53020 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP0 (0x1<<17) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the host.
53022 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP1 (0x1<<18) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the host.
53024 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP2 (0x1<<19) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the host.
53026 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_DST (0x1<<20) // Mask bit for not forwarding packets with NetBIOS TCP destination port 137/138/139 to the host.
53028 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_SRC (0x1<<21) // Mask bit for not forwarding packets with NetBIOS TCP source port 137/138 /139 to the host.
53030 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP0 (0x1<<22) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the host.
53032 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP1 (0x1<<23) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the host.
53034 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP2 (0x1<<24) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the host.
53036 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_RMCP (0x1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the host.
53038 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_DST (0x1<<26) // Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the host.
53040 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_SRC (0x1<<27) // Mask bit for not forwarding packets with NetBIOS UDP source port 137/138 /139 to the host.
53042 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP (0x1<<28) // Mask bit for not forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to the host.
53044 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_NA (0x1<<29) // Mask bit for not forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the host.
53046 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_RA (0x1<<30) // Mask bit for not forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the host.
53048 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6 (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the host.
53051 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ANY (0x1<<0) // Mask bit for not forwarding packets with inner VLAN present to the host.
53053 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_NONE (0x1<<1) // Mask bit for not forwarding packets with no inner VLAN to the host.
53055 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID0 (0x1<<2) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the host.
53057 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID1 (0x1<<3) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the host.
53059 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID2 (0x1<<4) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the host.
53062 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_ANY (0x1<<0) // Mask bit for not forwarding packets with outer tag present to the host.
53064 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_NONE (0x1<<1) // Mask bit for not forwarding packets with no outer tag to the host.
53066 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG0 (0x1<<2) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id0 to the host.
53068 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG1 (0x1<<3) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id1 to the host.
53070 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_PF (0x1<<4) // Mask bit for not forwarding packets with outer tag matching the outer tag of one of the enabled PFs to the host.
53073 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ARP (0x1<<0) // Mask bit for not forwarding packets with Ethertype matching llh_arp_type to the host.
53075 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4 (0x1<<1) // Mask bit for not forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to the host.
53077 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6 (0x1<<2) // Mask bit for not forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to the host.
53079 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_ER (0x1<<3) // Mask bit for not forwarding ICMPv4 packets with ICMP type 8 to the host.
53081 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_ER (0x1<<4) // Mask bit for not forwarding ICMPv6 packets with ICMP type 128 to the host.
53083 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_NS (0x1<<5) // Mask bit for not forwarding ICMPv6 packets with ICMP type 135 to the host.
53085 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_ALLPF 0x501150UL //Access:RW DataWidth:0x1 // Enable bit for not forwarding packets from all PFs, including packets that failed PF classification, to the host in multifunction mode.
53086 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_PERPF 0x501154UL //Access:RW DataWidth:0x1 // Enable bit for not forwarding packets for the PF to the host in multifunction mode. This is a per-PF split register.
53108 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_EN (0x1<<0) // L2 filter rule enable. Set this bit to enable this rule.
53110 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_EN (0x1<<1) // L2 filter address matching enable.
53114 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_EN (0x1<<5) // L2 filter Ethertype matching enable.
53118 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53120 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53123 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_EN (0x1<<0) // See definition for *l2filt_mcp_rule0.
53125 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_EN (0x1<<1) // See definition for *l2filt_mcp_rule0.
53129 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_mcp_rule0.
53133 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53135 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53138 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_EN (0x1<<0) // See definition for *l2filt_mcp_rule0.
53140 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_EN (0x1<<1) // See definition for *l2filt_mcp_rule0.
53144 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_mcp_rule0.
53148 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53150 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53153 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_EN (0x1<<0) // See definition for *l2filt_mcp_rule0.
53155 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_EN (0x1<<1) // See definition for *l2filt_mcp_rule0.
53159 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_mcp_rule0.
53163 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53165 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53168 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_EN (0x1<<0) // See definition for *l2filt_mcp_rule0.
53170 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_EN (0x1<<1) // See definition for *l2filt_mcp_rule0.
53174 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_mcp_rule0.
53178 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53180 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53183 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_EN (0x1<<0) // See definition for *l2filt_mcp_rule0.
53185 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_EN (0x1<<1) // See definition for *l2filt_mcp_rule0.
53189 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_mcp_rule0.
53193 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53195 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53198 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_EN (0x1<<0) // See definition for *l2filt_mcp_rule0.
53200 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_EN (0x1<<1) // See definition for *l2filt_mcp_rule0.
53204 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_mcp_rule0.
53208 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53210 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53213 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_EN (0x1<<0) // See definition for *l2filt_mcp_rule0.
53215 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_EN (0x1<<1) // See definition for *l2filt_mcp_rule0.
53219 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_mcp_rule0.
53223 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53225 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53228 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_EN (0x1<<0) // L2 filter (for not forwarding to the host) rule enable. Set this bit to enable this rule.
53230 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_EN (0x1<<1) // L2 filter (for not forwarding to the host) address matching enable.
53234 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_EN (0x1<<5) // L2 filter (for not forwarding to the host) Ethertype matching enable.
53238 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53240 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53243 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_EN (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
53245 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_EN (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
53249 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
53253 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53255 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53258 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_EN (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
53260 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_EN (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
53264 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
53268 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53270 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53273 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_EN (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
53275 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_EN (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
53279 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
53283 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53285 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53288 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_EN (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
53290 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_EN (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
53294 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
53298 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53300 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53303 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_EN (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
53305 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_EN (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
53309 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
53313 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53315 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53318 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_EN (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
53320 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_EN (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
53324 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
53328 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53330 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53333 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_EN (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
53335 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_EN (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
53339 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_EN (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
53343 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_INNER_VLAN_EN (0x1<<9) // L2 filter inner VLAN matching enable.
53345 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_OUTER_TAG_EN (0x1<<10) // L2 filter outer tag matching enable.
53347 #define NIG_REG_BRB_GATE_DNTFWD_PORT 0x5011e8UL //Access:RW DataWidth:0x1 // Disable bit for forwarding packets to the host for this port. No packet is forwarded to BRB when this bit is set.
53348 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD 0x5011ecUL //Access:RW DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded to BRB when this bit is set.
53349 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_CLSFAILED 0x5011f0UL //Access:RW DataWidth:0x1 // Disable bit for forwarding packets that failed PF classification to the host. No packet with classification failed status is forwarded to BRB when this bit is set in multifunction mode.
53350 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF 0x5011f4UL //Access:RW DataWidth:0x1 // Per-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that have this bit set in multifunction mode. This is a per-PF split register.
53356 #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE0 (0x1<<0) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype0 to the STORM(s).
53358 #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE1 (0x1<<1) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype1 to the STORM(s).
53360 #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE2 (0x1<<2) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype2 to the STORM(s).
53362 #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE3 (0x1<<3) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype3 to the STORM(s).
53364 #define NIG_REG_RX_LLH_DFIFO_EMPTY 0x501308UL //Access:R DataWidth:0x1 // LLH Data FIFO empty.
53365 #define NIG_REG_RX_LLH_DFIFO_FULL 0x50130cUL //Access:R DataWidth:0x1 // LLH Data FIFO full.
53366 #define NIG_REG_RX_LLH_HFIFO_EMPTY 0x501310UL //Access:R DataWidth:0x1 // LLH header FIFO empty.
53367 #define NIG_REG_RX_LLH_HFIFO_FULL 0x501314UL //Access:R DataWidth:0x1 // LLH header FIFO full.
53368 #define NIG_REG_RX_LLH_RFIFO_EMPTY 0x501318UL //Access:R DataWidth:0x1 // LLH result FIFO empty.
53369 #define NIG_REG_RX_LLH_RFIFO_FULL 0x50131cUL //Access:R DataWidth:0x1 // LLH result FIFO full.
53372 #define NIG_REG_LB_PKT_HAS_FCS 0x501504UL //Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that the packet has the FCS field at the end of the packet.
53373 #define NIG_REG_LB_ZERO_PAD_EN 0x501508UL //Access:RW DataWidth:0x1 // Zero-padding enable for LB packets. Set this bit to enable the padding of short packets to 60B. When this bit is clear, LB packets with less than 60B are dropped and not forwarded to the BRB.
53375 #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN (0x1<<0) // Enable bit for the BRB interface rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 40Gbps.
53384 #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53389 #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_EN_1 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53394 #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_EN_2 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53399 #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_EN_3 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53404 #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_EN_4 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53409 #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_EN_5 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53414 #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_EN_6 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53419 #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_EN_7 (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. Default to enabled rate limiter for 20Gbps.
53462 #define NIG_REG_LB_ARB_PSEUDO_RR_EN 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mode.
53493 #define NIG_REG_LB_LLH_BRB_GATE_DNTFWD 0x50165cUL //Access:RW DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded to BRB when this bit is set.
53494 #define NIG_REG_LB_LLH_BRB_GATE_DNTFWD_CLSFAILED 0x501660UL //Access:RW DataWidth:0x1 // Disable bit for forwarding packets that failed PF classification to the host. No packet with classification failed status is forwarded to BRB when this bit is set in multifunction mode.
53495 #define NIG_REG_LB_LLH_BRB_GATE_DNTFWD_PERPF 0x501664UL //Access:RW DataWidth:0x1 // Per-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that have this bit set in multifunction mode. This is a per-PF split register.
53498 #define NIG_REG_LB_BTB_FIFO_EMPTY 0x50176cUL //Access:R DataWidth:0x1 // LB BTB FIFO empty status.
53499 #define NIG_REG_LB_BTB_FIFO_FULL 0x501770UL //Access:R DataWidth:0x1 // LB BTB FIFO full status.
53503 #define NIG_REG_LB_LLH_DFIFO_EMPTY 0x501780UL //Access:R DataWidth:0x1 // LLH Data FIFO empty.
53504 #define NIG_REG_LB_LLH_DFIFO_ALM_FULL 0x501784UL //Access:R DataWidth:0x1 // LLH Data FIFO almost full.
53505 #define NIG_REG_LB_LLH_DFIFO_FULL 0x501788UL //Access:R DataWidth:0x1 // LLH Data FIFO full.
53506 #define NIG_REG_LB_LLH_HFIFO_EMPTY 0x50178cUL //Access:R DataWidth:0x1 // LLH header FIFO empty.
53507 #define NIG_REG_LB_LLH_HFIFO_ALM_FULL 0x501790UL //Access:R DataWidth:0x1 // LLH header FIFO almost full.
53508 #define NIG_REG_LB_LLH_HFIFO_FULL 0x501794UL //Access:R DataWidth:0x1 // LLH header FIFO full.
53509 #define NIG_REG_LB_LLH_RFIFO_EMPTY 0x501798UL //Access:R DataWidth:0x1 // LLH result FIFO empty.
53510 #define NIG_REG_LB_LLH_RFIFO_ALM_FULL 0x50179cUL //Access:R DataWidth:0x1 // LLH result FIFO almost full.
53511 #define NIG_REG_LB_LLH_RFIFO_FULL 0x501800UL //Access:R DataWidth:0x1 // LLH result FIFO full.
53514 #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP packets to be forwarded to the host.
53515 #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP packets to be forwarded to MCP.
53516 #define NIG_REG_PTP_SW_TXTSEN 0x501910UL //Access:RW DataWidth:0x1 // Enable for SW-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indicated through PBF interface for host traffic or through the p*_tx_mng_timestamp_pkt bit for TX management packet. Note that the tx_ptp_en[0] bit has to be set to enable TimeSync on TX side for this mode to work. NIG will extract and capture the sequence ID if one of the version bits is enabled.
53535 #define NIG_REG_LLH_MULTI_FUNCTION_MODE 0x50195cUL //Access:RW DataWidth:0x1 // Multifunction mode enable. Set this bit to perform PF classification before sending the packet to the BRB and performing WOL detection. In single function mode, the PFID for port 0 is based on the translation table entry 0 of port 0, the PFID for port 1 is based on the translation table entry 1 of port 1, the PFID for port 2 is based on the translation table entry 2 of port 2, and the PFID for port 3 is based on the translation table entry 3 of port 3. If reset default values are used, then PFID is the same as port ID.
53554 #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function outer tag/inner VLAN enable for PF classification. There are 4 of this register per port per function.
53556 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL 0x5019c0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function select bit for choosing between the tunnel and encapsulated header from which to take the inner VLAN for comparison with that in llh_func_tag_value for PF classification; 0 selects the outer/tunnel header. There are 4 of this register per port per function.
53560 #define NIG_REG_LLH_FUNC_NO_TAG 0x5019e0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function no outer tag/inner VLAN configuration for PF classification. Set this bit to enable a match for the function when there is no outer tag/inner VLAN.
53563 #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function filter enable for PF classification. There are 16 of this register per port per function.
53565 #define NIG_REG_LLH_FUNC_FILTER_MODE 0x501ac0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used for MAC-addresss based classification or protocol-based classification. Set this bit to 1 to select protocol-based classification. There are 16 of this register per port per function.
53569 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL 0x501b40UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function select bit for choosing between the tunnel and encapsulated header from which to take the MAC address to be compared with that in llh_func_filter_value for PF classification; 0 selects the outer/tunnel header. There are 16 of this register per port per function.
53571 #define NIG_REG_LLH_ENG_CLS_TYPE 0x501b80UL //Access:RW DataWidth:0x1 // Engine classification type. 0 selects connection-based classification. 1 selects the PF-based classification. This register is used only in the single-port with dual engine mode.
53572 #define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL //Access:RW DataWidth:0x1 // TCP 4-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination port numbers and IP source and destination IP addresses) as the hash string. This register is used only in the single-port with dual engine mode.
53573 #define NIG_REG_LLH_ENG_CLS_UDP_4_TUPLE_SEARCH 0x501b88UL //Access:RW DataWidth:0x1 // UDP 4-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination port numbers and IP source and destination IP addresses) as the hash string. This register is used only in the single-port with dual engine mode.
53578 #define NIG_REG_LLH_ENG_CLS_ENG_ID_PERPF 0x501b9cUL //Access:RW DataWidth:0x1 // Per-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packets associated with the PF to be routed to engine 1. Otherwise, the packet is routed to engine 0. This register is used only in the single-port with dual engine mode.
53593 #define NIG_REG_LB_NO_DROP_EN 0x501bc0UL //Access:RW DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set, the no-drop-hdr-ind bit of the TC has the same effect as the lb_tc_en configuration above.
53594 #define NIG_REG_LB_NO_DROP_ON_FULL 0x501bc4UL //Access:RW DataWidth:0x1 // Enable the no-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB. Note that only the first lb_no_drop_hdr_size cycles of the packet are not dropped. If per-TC full condition exists after the lb_no_drop_hdr_size cycles, then a trunctation cycle of EOP+ERR is sent to the BRB.
53616 #define NIG_REG_TX_DRAIN_EN 0x501c1cUL //Access:RW DataWidth:0x1 // Drain mode enable. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.
53617 #define NIG_REG_TX_MCP_DRAIN_EN 0x501c20UL //Access:RW DataWidth:0x1 // Drain mode enable for TX MCP traffic. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion. Note that TX MCP traffic may also be drained if it is based on a TC and the corresponding TC is enabled to drain.
53629 #define NIG_REG_RX_FLOWCTRL_STATUS_CLEAR 0x501c50UL //Access:RW DataWidth:0x1 // Set this bit to clear the current flow control (PFC and LLFC) latched status.
53793 #define NIG_REG_TX_ZERO_PAD_EN 0x501f08UL //Access:RW DataWidth:0x1 // Zero-padding enable for TX packets. Set this bit to enable the padding of short packets to 60B.
53795 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1<<0) // Enable EDPM for the port.
53803 #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN (0x1<<0) // Enable bit for the global rate limiter to be used in pacing TX and LB traffic of the same port. Defaults to enabled rate limit of 48Gbps.
53811 #define NIG_REG_TX_ARB_EN 0x501f30UL //Access:RW DataWidth:0x1 // TX ETS arbitration enable.
53819 #define NIG_REG_TX_ARB_PSEUDO_RR_EN 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mode.
53820 #define NIG_REG_TX_ARB_DBG_CLIENT_DISABLE 0x501f54UL //Access:RW DataWidth:0x1 // Set this bit to disable debug traffic at the inputs to the ETS arbiter.
53858 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_BRCST (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
53860 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ALLMLCST (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
53862 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV4MLCST (0x1<<2) // Mask bit for forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to MCP.
53864 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV6_MLCST (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
53866 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UNCST (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
53868 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC0 (0x1<<5) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to MCP.
53870 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC1 (0x1<<6) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to MCP.
53872 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC2 (0x1<<7) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to MCP.
53874 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC3 (0x1<<8) // Mask bit for forwarding packets with the MAC destination address mtching *llh*_dest_mac_3 to MCP.
53876 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC4 (0x1<<9) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to MCP.
53878 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC5 (0x1<<10) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to MCP.
53880 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE0 (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
53882 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE1 (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
53884 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ARP (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to MCP.
53886 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP0 (0x1<<14) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
53888 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP1 (0x1<<15) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
53890 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP2 (0x1<<16) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
53892 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP0 (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
53894 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP1 (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
53896 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP2 (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
53898 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_DST (0x1<<20) // Mask bit for forwarding packets with NetBIOS TCP destination port 137/138/139 to MCP.
53900 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_SRC (0x1<<21) // Mask bit for forwarding packets with NetBIOS TCP source port 137/138 /139 to MCP.
53902 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP0 (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
53904 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP1 (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
53906 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP2 (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
53908 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_RMCP (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
53910 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_DST (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
53912 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_SRC (0x1<<27) // Mask bit for forwarding packets with NetBIOS UDP source port 137/138 /139 to MCP.
53914 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_DHCP (0x1<<28) // Mask bit for forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to MCP.
53916 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_NA (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
53918 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_RA (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
53920 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6 (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
53923 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ANY (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
53925 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_NONE (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
53927 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID0 (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
53929 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID1 (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
53931 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID2 (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
53934 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_BRCST (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the network.
53936 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ALLMLCST (0x1<<1) // Mask bit for not forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the network.
53938 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV4MLCST (0x1<<2) // Mask bit for not forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to the network.
53940 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLCST (0x1<<3) // Mask bit for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
53942 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UNCST (0x1<<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the network.
53944 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC0 (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to the network.
53946 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC1 (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to the network.
53948 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC2 (0x1<<7) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to the network.
53950 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC3 (0x1<<8) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to the network.
53952 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC4 (0x1<<9) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to the network.
53954 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC5 (0x1<<10) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to the network.
53956 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE0 (0x1<<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the network.
53958 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE1 (0x1<<12) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
53960 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ARP (0x1<<13) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the network.
53962 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP0 (0x1<<14) // Mask bit for not forwarding packets with the IP destination address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
53964 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP1 (0x1<<15) // Mask bit for not forwarding packets with the IP destination address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
53966 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP2 (0x1<<16) // Mask bit for not forwarding packets with the IP destination address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
53968 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP0 (0x1<<17) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
53970 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP1 (0x1<<18) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
53972 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP2 (0x1<<19) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
53974 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_DST (0x1<<20) // Mask bit for not forwarding packets with NetBIOS TCP destination port 137/138/139 to the network.
53976 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_SRC (0x1<<21) // Mask bit for not forwarding packets with NetBIOS TCP source port 137/138 /139 to the network.
53978 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP0 (0x1<<22) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
53980 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP1 (0x1<<23) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
53982 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP2 (0x1<<24) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
53984 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_RMCP (0x1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
53986 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_DST (0x1<<26) // Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
53988 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_SRC (0x1<<27) // Mask bit for not forwarding packets with NetBIOS UDP source port 137/138 /139 to the network.
53990 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP (0x1<<28) // Mask bit for not forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to the network.
53992 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_NA (0x1<<29) // Mask bit for not forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
53994 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_RA (0x1<<30) // Mask bit for not forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
53996 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6 (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the network.
53999 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_BRCST (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to the network.
54001 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ALLMLCST (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is a broadcast packet) packets to the network.
54003 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV4MLCST (0x1<<2) // Mask bit for forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to the network.
54005 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV6_MLCST (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
54007 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UNCST (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to the network.
54009 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC0 (0x1<<5) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to the network.
54011 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC1 (0x1<<6) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to the network.
54013 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC2 (0x1<<7) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to the network.
54015 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC3 (0x1<<8) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to the network.
54017 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC4 (0x1<<9) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to the network.
54019 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC5 (0x1<<10) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to the network.
54021 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE0 (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to the network.
54023 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE1 (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
54025 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ARP (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to the network.
54027 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP0 (0x1<<14) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
54029 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP1 (0x1<<15) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
54031 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP2 (0x1<<16) // Mask bit for forwarding packets with the IP destination address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
54033 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP0 (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
54035 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP1 (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
54037 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP2 (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
54039 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_DST (0x1<<20) // Mask bit for forwarding packets with NetBIOS TCP destination port 137/138/139 to the network.
54041 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_SRC (0x1<<21) // Mask bit for forwarding packets with NetBIOS TCP source port 137/138 /139 to the network.
54043 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP0 (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
54045 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP1 (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
54047 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP2 (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
54049 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_RMCP (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
54051 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_DST (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
54053 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_SRC (0x1<<27) // Mask bit for forwarding packets with NetBIOS UDP source port 137/138 /139 to the network.
54055 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_DHCP (0x1<<28) // Mask bit for forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to the network.
54057 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_NA (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
54059 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_RA (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
54061 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6 (0x1<<31) // Mask bit for forwarding ICMPv6 packets to the network.
54064 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ANY (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
54066 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_NONE (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
54068 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID0 (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
54070 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID1 (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
54072 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID2 (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
54074 #define NIG_REG_TX_BTB_FIFO_EMPTY 0x501ffcUL //Access:R DataWidth:0x1 // TX BTB FIFO empty status.
54075 #define NIG_REG_TX_BTB_FIFO_FULL 0x502000UL //Access:R DataWidth:0x1 // TX BTB FIFO full status.
54079 #define NIG_REG_TX_LLH_DFIFO_EMPTY 0x502010UL //Access:R DataWidth:0x1 // TX LLH Data FIFO is empty.
54080 #define NIG_REG_TX_LLH_DFIFO_ALM_FULL 0x502014UL //Access:R DataWidth:0x1 // TX LLH Data FIFO almost full.
54081 #define NIG_REG_TX_LLH_DFIFO_FULL 0x502018UL //Access:R DataWidth:0x1 // TX LLH Data FIFO is full.
54082 #define NIG_REG_TX_LLH_HFIFO_EMPTY 0x50201cUL //Access:R DataWidth:0x1 // TX LLH header FIFO is empty.
54083 #define NIG_REG_TX_LLH_HFIFO_ALM_FULL 0x502020UL //Access:R DataWidth:0x1 // TX LLH header FIFO almost full.
54084 #define NIG_REG_TX_LLH_HFIFO_FULL 0x502024UL //Access:R DataWidth:0x1 // TX LLH header FIFO is full.
54085 #define NIG_REG_TX_LLH_RFIFO_EMPTY 0x502028UL //Access:R DataWidth:0x1 // TX LLH result FIFO is empty.
54086 #define NIG_REG_TX_LLH_RFIFO_ALM_FULL 0x50202cUL //Access:R DataWidth:0x1 // TX LLH result FIFO almost full.
54087 #define NIG_REG_TX_LLH_RFIFO_FULL 0x502030UL //Access:R DataWidth:0x1 // TX LLH result FIFO is full.
54088 #define NIG_REG_TX_GNT_FIFO_EMPTY 0x502034UL //Access:R DataWidth:0x1 // TX GNT FIFO empty status.
54089 #define NIG_REG_TX_GNT_FIFO_FULL 0x502038UL //Access:R DataWidth:0x1 // TX GNT FIFO full status.
54113 #define NIG_REG_TX_MNG_TC_EN 0x502098UL //Access:RW DataWidth:0x1 // Enable the use of TC to control the flow of TX management traffic. Set this bit to 1 to enable the use of *mng_tc configuration to select the TC to use to pause/drain management traffic sent to the network.
54114 #define NIG_REG_TX_HOST_MNG_ENABLE 0x50209cUL //Access:RW DataWidth:0x1 // Host-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface toward MCP when the criteria for the MCP filters are met. All packets from PBF are forwarded to the network when this bit is cleared.
54115 #define NIG_REG_TX_MNG_TIMESTAMP_PKT 0x5020a0UL //Access:RW DataWidth:0x1 // Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.
54116 #define NIG_REG_BMB_PAUSE_NTWK_EN 0x5020a4UL //Access:RW DataWidth:0x1 // Enable the usage of BMB WC pause inputs to OR with others for pausing the network peer.
54119 #define NIG_REG_TX_BMB_FIFO_EMPTY 0x5020b0UL //Access:R DataWidth:0x1 // TX BMB FIFO empty status.
54120 #define NIG_REG_TX_BMB_FIFO_FULL 0x5020b4UL //Access:R DataWidth:0x1 // TX BMB FIFO full status.
54121 #define NIG_REG_LB_BMB_FIFO_EMPTY 0x5020b8UL //Access:R DataWidth:0x1 // LB BMB FIFO empty status.
54122 #define NIG_REG_LB_BMB_FIFO_FULL 0x5020bcUL //Access:R DataWidth:0x1 // LB BMB FIFO full status.
54124 #define NIG_REG_DORQ_FIFO_EMPTY 0x5020c4UL //Access:R DataWidth:0x1 // DORQ FIFO is empty..
54125 #define NIG_REG_DORQ_FIFO_FULL 0x5020c8UL //Access:R DataWidth:0x1 // DORQ FIFO is full.
54131 #define NIG_REG_DEBUG_FIFO_EMPTY 0x5020e0UL //Access:R DataWidth:0x1 // Debug traffic FIFO is empty..
54132 #define NIG_REG_DEBUG_FIFO_FULL 0x5020e4UL //Access:R DataWidth:0x1 // Debug traffic FIFO is full.
54177 #define NIG_REG_ACPI_PROP_HDR_RM 0x508004UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Proprietary header removal configuration for ACPI. Set this bit to 1 to enable the removal of the header. Clear the bit to keep the header in the packet.
54178 #define NIG_REG_MF_GLOBAL_EN 0x508008UL //Access:RW DataWidth:0x1 // Set this bit to enable ACPI pattern matching and TCP SYN matching in multi-function mode even when the per-function outer tag matching fails.
54179 #define NIG_REG_UPON_MGMT 0x50800cUL //Access:RW DataWidth:0x1 // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP. Clear this bit to disable ACPI and TCP SYN matching when the packet is forwarded to MCP.
54182 #define NIG_REG_ACPI_ENABLE 0x508100UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. When this bit is set ACPI packet recognition will be enabled. This bit must not be enabled until after all other ACPI registers were configured.
54212 #define NIG_REG_MPKT_ENABLE 0x508188UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. When this bit is set Magic Packet recognition will be enabled. This bit must not be enabled until after after all other Magic Packet registers are configured.
54215 #define NIG_REG_FORCE_WOL 0x508198UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high transition of this bit forces a wake event.
54218 #define NIG_REG_WAKE_BUFFER_CLEAR 0x5081c0UL //Access:RW DataWidth:0x1 // Clear the Wake Buffer and Status - a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details registers and allows the wake buffer to be overwritten, thereby re-enabling pattern detection.
54226 #define NIG_REG_TX_UP_TS_EN 0x508820UL //Access:RW DataWidth:0x1 // TX User protocol time stamp enable
54227 #define NIG_REG_RX_UP_TS_EN 0x508824UL //Access:RW DataWidth:0x1 // RX User protocol time stamp enable
54228 #define NIG_REG_TX_PTP_ONE_STP_EN 0x508828UL //Access:RW DataWidth:0x1 // Enable one step 1588 on TX
54229 #define NIG_REG_RX_PTP_ONE_STP_EN 0x50882cUL //Access:RW DataWidth:0x1 // Enable one step 1588 on RX
54238 #define NIG_REG_ADD_FREECNT_OFFSET 0x508850UL //Access:RW DataWidth:0x1 // This bit defines whether to add offset and jitter of the timestamp to the returned timestamp from the MAC This bit is shared by TX and RX paths.
54239 #define NIG_REG_UP_TS_INSERT_EN 0x508854UL //Access:RW DataWidth:0x1 // Enable for on wire timestamp insertion for user protocol packets
54243 #define NIG_REG_TXOSTS_SIGNEXT 0x508864UL //Access:RW DataWidth:0x1 // sign extension indication for the MAC.
54246 #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL //Access:RW DataWidth:0x1 // Output enable for TS passed to the Port Macro
54247 #define NIG_REG_TS_OUTPUT_ENABLE_HV 0x508874UL //Access:RW DataWidth:0x1 // Output enable for TS passed to the Port Macro
54248 #define NIG_REG_USER_ONE_STEP_32 0x508878UL //Access:RW DataWidth:0x1 // Global parameter which defines that 32 bits timestamp will be inserted to the packet instead of 48 bits
54267 #define NIG_REG_TSGEN_HW_PPS_EN 0x5088c8UL //Access:RW DataWidth:0x1 // In this mode, Start time, high period and low period are all configurable, and when asserting this bit the PPS starts to toggle accoring to HW machine
54268 #define NIG_REG_TSGEN_SW_PPS_EN 0x5088ccUL //Access:RW DataWidth:0x1 // In this mode, whenever the synchronized time reaches a configurable value, PPS signal is toggled
54271 #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL //Access:RW DataWidth:0x1 // This is a level indication to reset drift counter's value
54279 #define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL //Access:RW DataWidth:0x1 // This field enables the feature that maps DSCP to TC in case that there is no TC in one of the L2 tags
54284 #define NIG_REG_VXLAN_ZERO_UDP_IGNORE 0x508b00UL //Access:RW DataWidth:0x1 // This field defines whether to ignore zero UDP value for VXLAN
54285 #define NIG_REG_NGE_ZERO_UDP_IGNORE 0x508b04UL //Access:RW DataWidth:0x1 // This field defines whether to ignore zero UDP value for NGE
54286 #define NIG_REG_RROCE_ZERO_UDP_IGNORE 0x508b08UL //Access:RW DataWidth:0x1 // This field defines whether to ignore zero UDP value for RROCE
54289 #define NIG_REG_ACPI_PROP_HDR_REMOVE 0x508b14UL //Access:RW DataWidth:0x1 // This is a per-port register. Proprietary header removal configuration for ACPI. Set this bit to 1 to enable the removal of the header. Clear the bit to keep the header in the packet.
54290 #define NIG_REG_CHECK_ETH_CRC 0x508b18UL //Access:RW DataWidth:0x1 // This is a per-port register. When enabled, NIG will check Ethernet CRC in the packet and update error indication before transferring it to BRB/BMB/Storm
54291 #define NIG_REG_RM_ETH_CRC 0x508b1cUL //Access:RW DataWidth:0x1 // This is a per-port register. When enabled, NIG will remove Ethernet CRC from the packet before transferring it to BRB/BMB/Storm
54292 #define NIG_REG_ADD_ETH_CRC 0x508b20UL //Access:RW DataWidth:0x1 // This is a per-port register. When enabled, NIG will add Ethernet CRC to the packet
54293 #define NIG_REG_CORRUPT_ETH_CRC 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When enabled, NIG will corrupt ethernet CRC for packets which are received from BTB with error indication or are classified by the NIG as packets which should be transmitted with errors
54294 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enables NGE port matching during UDP header parsing when the encapsulated header is IP.
54295 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enables NGE port matching during UDP header parsing when the encapsulated header is Ethernet.
54296 #define NIG_REG_NGE_COMP_VER 0x508b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perform NGE version match to 2�b0
54303 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding IPV6 MLD (configurable MLD MsgType) packets to MCP.
54305 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding IPv6 Neighbor solicitation packets to MCP.
54307 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding IPv6 DHCP server packets to MCP.
54309 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding DCHPv4 client packets to MCP.
54311 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP V4 packets to MCP.
54313 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC6 (0x1<<5) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_6 to MCP.
54315 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC7 (0x1<<6) // Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_7 to MCP.
54318 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding unicast IPv6 MLD (Configurable MsgType) packets to MCP.
54320 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to MCP.
54322 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to MCP.
54324 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to MCP.
54326 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to MCP.
54329 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLD (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the host.
54331 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the host.
54333 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the host.
54335 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the host.
54337 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the host.
54339 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC6 (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_6 to the host.
54341 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC7 (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address matching *llh*_dest_mac_7 to the host.
54344 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLD (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the network.
54346 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the network.
54348 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the network.
54350 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the network.
54352 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the network.
54355 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding IPv6 MLD (Configurable MsgType) packets to the network.
54357 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to the network.
54359 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to the network.
54361 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to the network.
54363 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to the network.
54365 #define NIG_REG_DBGMUX_OVFLW_IND_EN 0x508b5cUL //Access:RW DataWidth:0x1 // This is a Global register. When this bit is enabled, instead of sending frame[0] from dbgmux, NIG will set an indication that some of the entries to the debug mux Were not written as the FIFO was full. This indication will be valid In the next entry which will be written to the FIFO.
54367 #define NIG_REG_LB_GNT_FIFO_EMPTY 0x508b64UL //Access:R DataWidth:0x1 // LB GNT FIFO empty status.
54368 #define NIG_REG_LB_GNT_FIFO_FULL 0x508b68UL //Access:R DataWidth:0x1 // LB GNT FIFO full status.
54372 #define NIG_REG_TX_PARITY_ERROR_CLOSE_EGRESS 0x508b78UL //Access:RW DataWidth:0x1 // When this bit is set and there is a parity error on the Tranmit data path, the data to the CNIG will be discarded.
54377 #define NIG_REG_TX_INHIBIT_BMB_ARB_EN 0x508b8cUL //Access:RW DataWidth:0x1 // This bit inhibits sending more than one outstanding packet request to the BMB until the last data of the current granted packet is received.
54378 #define NIG_REG_LB_INHIBIT_BMB_ARB_EN 0x508b90UL //Access:RW DataWidth:0x1 // This bit inhibits sending more than one outstanding packet request to the BMB until the last data of the current granted packet is received.
54379 #define NIG_REG_TX_TDM_0_ENABLE 0x509000UL //Access:RW DataWidth:0x1 // When this bit is configured to 1, NIG trasmits ports 0 and 1 data in TDM manner. If 0, then NIG transmits only port 0 data.
54380 #define NIG_REG_TX_TDM_1_ENABLE 0x509004UL //Access:RW DataWidth:0x1 // When this bit is configured to 1, NIG trasmits ports 2 and 2 data in TDM manner. If 0, then NIG transmits only port 2 data.
54387 #define NIG_REG_TSGEN_TSIO_IN_SEL_POL 0x509020UL //Access:RW DataWidth:0x1 // This register selects the polarity of TSIO signals. 1: active high. 0: active low
54395 #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL //Access:RW DataWidth:0x1 // This bit enables time stamp latching for one step PTP packets.
54396 #define NIG_REG_PTP_LATCH_SW_OSTS_PKT_TIME 0x509044UL //Access:RW DataWidth:0x1 // This bit enables time stamp latching for one step PTP packets with RECORD_TIME_STAMP bit from BTB/PBF on. This feature is enabled when ptp_sw_txtsen is 1.
54397 #define NIG_REG_PTP_UPDATE_SW_OSTS_PKT_TIME 0x509048UL //Access:RW DataWidth:0x1 // This bit enables correction field update for one step PTP packets with RECORD_TIME_STAMP bit from BTB/PBF on. This feature is enabled when ptp_sw_txtsen is 1.
54405 #define NIG_REG_MPA_MUL_PDU_CRC_CALC_EN 0x509068UL //Access:RW DataWidth:0x1 // This bit selects whether to use the MPA CRC calculation on one fully contained PDU (legacy mode - 0) or on multiple PDUs (1).
54408 #define BMB_REG_START_EN 0x54000cUL //Access:RW DataWidth:0x1 // This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.
54410 #define BMB_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
54412 #define BMB_REG_INT_STS_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
54414 #define BMB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
54416 #define BMB_REG_INT_STS_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
54418 #define BMB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
54420 #define BMB_REG_INT_STS_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
54422 #define BMB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
54424 #define BMB_REG_INT_STS_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
54426 #define BMB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
54428 #define BMB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
54430 #define BMB_REG_INT_STS_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
54432 #define BMB_REG_INT_STS_0_WC1_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
54434 #define BMB_REG_INT_STS_0_WC2_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
54436 #define BMB_REG_INT_STS_0_WC3_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
54438 #define BMB_REG_INT_STS_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
54440 #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
54443 #define BMB_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.ADDRESS_ERROR .
54445 #define BMB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
54447 #define BMB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
54449 #define BMB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
54451 #define BMB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
54453 #define BMB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
54455 #define BMB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
54457 #define BMB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
54459 #define BMB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
54461 #define BMB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
54463 #define BMB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
54465 #define BMB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC1_PROTOCOL_ERROR .
54467 #define BMB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC2_PROTOCOL_ERROR .
54469 #define BMB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC3_PROTOCOL_ERROR .
54471 #define BMB_REG_INT_MASK_0_LL_BLK_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.LL_BLK_ERROR .
54473 #define BMB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.MAC0_FC_CNT_ERROR .
54476 #define BMB_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
54478 #define BMB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
54480 #define BMB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
54482 #define BMB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
54484 #define BMB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
54486 #define BMB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
54488 #define BMB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
54490 #define BMB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
54492 #define BMB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
54494 #define BMB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
54496 #define BMB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
54498 #define BMB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
54500 #define BMB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
54502 #define BMB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
54504 #define BMB_REG_INT_STS_WR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
54506 #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
54509 #define BMB_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
54511 #define BMB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
54513 #define BMB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
54515 #define BMB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
54517 #define BMB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
54519 #define BMB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
54521 #define BMB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
54523 #define BMB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
54525 #define BMB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
54527 #define BMB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
54529 #define BMB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
54531 #define BMB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
54533 #define BMB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
54535 #define BMB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
54537 #define BMB_REG_INT_STS_CLR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
54539 #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
54542 #define BMB_REG_INT_STS_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
54544 #define BMB_REG_INT_STS_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
54546 #define BMB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
54548 #define BMB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR (0x1<<5) // LEN FIFO error in write client 0.
54550 #define BMB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
54552 #define BMB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
54554 #define BMB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
54556 #define BMB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
54558 #define BMB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
54560 #define BMB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
54562 #define BMB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
54564 #define BMB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
54566 #define BMB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
54568 #define BMB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
54570 #define BMB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
54572 #define BMB_REG_INT_STS_1_WC1_INP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54574 #define BMB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54576 #define BMB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54578 #define BMB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54580 #define BMB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54582 #define BMB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54584 #define BMB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54586 #define BMB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
54588 #define BMB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54590 #define BMB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54592 #define BMB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
54594 #define BMB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
54596 #define BMB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
54599 #define BMB_REG_INT_MASK_1_LL_ARB_CALC_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
54601 #define BMB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
54603 #define BMB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
54605 #define BMB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LEN_FIFO_ERROR .
54607 #define BMB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
54609 #define BMB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
54611 #define BMB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
54613 #define BMB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
54615 #define BMB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
54617 #define BMB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
54619 #define BMB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_COS_CNT_FIFO_ERROR .
54621 #define BMB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
54623 #define BMB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
54625 #define BMB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
54627 #define BMB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
54629 #define BMB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_INP_FIFO_ERROR .
54631 #define BMB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_SOP_FIFO_ERROR .
54633 #define BMB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_QUEUE_FIFO_ERROR .
54635 #define BMB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_FREE_POINT_FIFO_ERROR .
54637 #define BMB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_NEXT_POINT_FIFO_ERROR .
54639 #define BMB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_STRT_FIFO_ERROR .
54641 #define BMB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_SECOND_DSCR_FIFO_ERROR .
54643 #define BMB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_PKT_AVAIL_FIFO_ERROR .
54645 #define BMB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_COS_CNT_FIFO_ERROR .
54647 #define BMB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_NOTIFY_FIFO_ERROR .
54649 #define BMB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_LL_REQ_FIFO_ERROR .
54651 #define BMB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_LL_PA_CNT_ERROR .
54653 #define BMB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_BB_PA_CNT_ERROR .
54656 #define BMB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
54658 #define BMB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
54660 #define BMB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
54662 #define BMB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR (0x1<<5) // LEN FIFO error in write client 0.
54664 #define BMB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
54666 #define BMB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
54668 #define BMB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
54670 #define BMB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
54672 #define BMB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
54674 #define BMB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
54676 #define BMB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
54678 #define BMB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
54680 #define BMB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
54682 #define BMB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
54684 #define BMB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
54686 #define BMB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54688 #define BMB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54690 #define BMB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54692 #define BMB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54694 #define BMB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54696 #define BMB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54698 #define BMB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54700 #define BMB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
54702 #define BMB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54704 #define BMB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54706 #define BMB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
54708 #define BMB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
54710 #define BMB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
54713 #define BMB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
54715 #define BMB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
54717 #define BMB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
54719 #define BMB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR (0x1<<5) // LEN FIFO error in write client 0.
54721 #define BMB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
54723 #define BMB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
54725 #define BMB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
54727 #define BMB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
54729 #define BMB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
54731 #define BMB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
54733 #define BMB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
54735 #define BMB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
54737 #define BMB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
54739 #define BMB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
54741 #define BMB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
54743 #define BMB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54745 #define BMB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54747 #define BMB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54749 #define BMB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54751 #define BMB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54753 #define BMB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54755 #define BMB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54757 #define BMB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
54759 #define BMB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54761 #define BMB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
54763 #define BMB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
54765 #define BMB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
54767 #define BMB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
54770 #define BMB_REG_INT_STS_2_WC2_INP_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54772 #define BMB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54774 #define BMB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54776 #define BMB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54778 #define BMB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54780 #define BMB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54782 #define BMB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54784 #define BMB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
54786 #define BMB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54788 #define BMB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54790 #define BMB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
54792 #define BMB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
54794 #define BMB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
54796 #define BMB_REG_INT_STS_2_WC3_INP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54798 #define BMB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54800 #define BMB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54802 #define BMB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54804 #define BMB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54806 #define BMB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54808 #define BMB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54810 #define BMB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
54812 #define BMB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54814 #define BMB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54816 #define BMB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
54818 #define BMB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
54820 #define BMB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
54823 #define BMB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_INP_FIFO_ERROR .
54825 #define BMB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_SOP_FIFO_ERROR .
54827 #define BMB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_QUEUE_FIFO_ERROR .
54829 #define BMB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_FREE_POINT_FIFO_ERROR .
54831 #define BMB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_NEXT_POINT_FIFO_ERROR .
54833 #define BMB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_STRT_FIFO_ERROR .
54835 #define BMB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_SECOND_DSCR_FIFO_ERROR .
54837 #define BMB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_PKT_AVAIL_FIFO_ERROR .
54839 #define BMB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_COS_CNT_FIFO_ERROR .
54841 #define BMB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_NOTIFY_FIFO_ERROR .
54843 #define BMB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_LL_REQ_FIFO_ERROR .
54845 #define BMB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_LL_PA_CNT_ERROR .
54847 #define BMB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_BB_PA_CNT_ERROR .
54849 #define BMB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_INP_FIFO_ERROR .
54851 #define BMB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_SOP_FIFO_ERROR .
54853 #define BMB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_QUEUE_FIFO_ERROR .
54855 #define BMB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_FREE_POINT_FIFO_ERROR .
54857 #define BMB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_NEXT_POINT_FIFO_ERROR .
54859 #define BMB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_STRT_FIFO_ERROR .
54861 #define BMB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_SECOND_DSCR_FIFO_ERROR .
54863 #define BMB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_PKT_AVAIL_FIFO_ERROR .
54865 #define BMB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_COS_CNT_FIFO_ERROR .
54867 #define BMB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_NOTIFY_FIFO_ERROR .
54869 #define BMB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_LL_REQ_FIFO_ERROR .
54871 #define BMB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_LL_PA_CNT_ERROR .
54873 #define BMB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_BB_PA_CNT_ERROR .
54876 #define BMB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54878 #define BMB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54880 #define BMB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54882 #define BMB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54884 #define BMB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54886 #define BMB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54888 #define BMB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54890 #define BMB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
54892 #define BMB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54894 #define BMB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54896 #define BMB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
54898 #define BMB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
54900 #define BMB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
54902 #define BMB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54904 #define BMB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54906 #define BMB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54908 #define BMB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54910 #define BMB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54912 #define BMB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54914 #define BMB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54916 #define BMB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
54918 #define BMB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54920 #define BMB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54922 #define BMB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
54924 #define BMB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
54926 #define BMB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
54929 #define BMB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54931 #define BMB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54933 #define BMB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54935 #define BMB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54937 #define BMB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54939 #define BMB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54941 #define BMB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54943 #define BMB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
54945 #define BMB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54947 #define BMB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
54949 #define BMB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
54951 #define BMB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
54953 #define BMB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
54955 #define BMB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54957 #define BMB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54959 #define BMB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54961 #define BMB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54963 #define BMB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54965 #define BMB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54967 #define BMB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54969 #define BMB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
54971 #define BMB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54973 #define BMB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
54975 #define BMB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
54977 #define BMB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
54979 #define BMB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
54982 #define BMB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54984 #define BMB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54986 #define BMB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54988 #define BMB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54990 #define BMB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54992 #define BMB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54994 #define BMB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54996 #define BMB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
54998 #define BMB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55000 #define BMB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55002 #define BMB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55004 #define BMB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55006 #define BMB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55008 #define BMB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55010 #define BMB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55012 #define BMB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55014 #define BMB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55016 #define BMB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55018 #define BMB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55020 #define BMB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55022 #define BMB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55024 #define BMB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55026 #define BMB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55028 #define BMB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55030 #define BMB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55032 #define BMB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55034 #define BMB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55036 #define BMB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55038 #define BMB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55040 #define BMB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55042 #define BMB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55045 #define BMB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
55047 #define BMB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
55049 #define BMB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
55051 #define BMB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
55053 #define BMB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
55055 #define BMB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
55057 #define BMB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
55059 #define BMB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
55061 #define BMB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
55063 #define BMB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
55065 #define BMB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
55067 #define BMB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
55069 #define BMB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
55071 #define BMB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
55073 #define BMB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
55075 #define BMB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
55077 #define BMB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
55079 #define BMB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
55081 #define BMB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
55083 #define BMB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
55085 #define BMB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
55087 #define BMB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
55089 #define BMB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
55091 #define BMB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
55093 #define BMB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
55095 #define BMB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
55097 #define BMB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
55099 #define BMB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
55101 #define BMB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
55103 #define BMB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
55105 #define BMB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
55108 #define BMB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55110 #define BMB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55112 #define BMB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55114 #define BMB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55116 #define BMB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55118 #define BMB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55120 #define BMB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55122 #define BMB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55124 #define BMB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55126 #define BMB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55128 #define BMB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55130 #define BMB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55132 #define BMB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55134 #define BMB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55136 #define BMB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55138 #define BMB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55140 #define BMB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55142 #define BMB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55144 #define BMB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55146 #define BMB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55148 #define BMB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55150 #define BMB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55152 #define BMB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55154 #define BMB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55156 #define BMB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55158 #define BMB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55160 #define BMB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55162 #define BMB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55164 #define BMB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55166 #define BMB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55168 #define BMB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55171 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55173 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55175 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55177 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55179 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55181 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55183 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55185 #define BMB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
55187 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55189 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55191 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55193 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55195 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55197 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55199 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55201 #define BMB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
55203 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55205 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55207 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55209 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55211 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55213 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55215 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55217 #define BMB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
55219 #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55221 #define BMB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55223 #define BMB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55225 #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55227 #define BMB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55229 #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55231 #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55234 #define BMB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55236 #define BMB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
55238 #define BMB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
55240 #define BMB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
55242 #define BMB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
55244 #define BMB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
55246 #define BMB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
55248 #define BMB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client rc0 release fifo error
55250 #define BMB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client rc1 release fifo error
55252 #define BMB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client rc2 release fifo error
55254 #define BMB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client rc3 release fifo error
55256 #define BMB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client rc4 release fifo error
55258 #define BMB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // Read packet client rc4 release fifo error
55260 #define BMB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // Read packet client rc4 release fifo error
55262 #define BMB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // Read packet client rc4 release fifo error
55264 #define BMB_REG_INT_STS_4_RC_PKT8_RLS_FIFO_ERROR (0x1<<17) // Read packet client rc4 release fifo error
55266 #define BMB_REG_INT_STS_4_RC_PKT9_RLS_FIFO_ERROR (0x1<<18) // Read packet client rc4 release fifo error
55268 #define BMB_REG_INT_STS_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
55270 #define BMB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
55272 #define BMB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55274 #define BMB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55276 #define BMB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55278 #define BMB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55280 #define BMB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55282 #define BMB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55284 #define BMB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55286 #define BMB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55289 #define BMB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
55291 #define BMB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_STRT_FIFO_ERROR .
55293 #define BMB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_REQ_FIFO_ERROR .
55295 #define BMB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_DSCR_FIFO_ERROR .
55297 #define BMB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
55299 #define BMB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
55301 #define BMB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
55303 #define BMB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
55305 #define BMB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
55307 #define BMB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
55309 #define BMB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
55311 #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
55313 #define BMB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT5_RLS_FIFO_ERROR .
55315 #define BMB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT6_RLS_FIFO_ERROR .
55317 #define BMB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT7_RLS_FIFO_ERROR .
55319 #define BMB_REG_INT_MASK_4_RC_PKT8_RLS_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT8_RLS_FIFO_ERROR .
55321 #define BMB_REG_INT_MASK_4_RC_PKT9_RLS_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT9_RLS_FIFO_ERROR .
55323 #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
55325 #define BMB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
55327 #define BMB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
55329 #define BMB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
55331 #define BMB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
55333 #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
55335 #define BMB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
55337 #define BMB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
55339 #define BMB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
55341 #define BMB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
55344 #define BMB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55346 #define BMB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
55348 #define BMB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
55350 #define BMB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
55352 #define BMB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
55354 #define BMB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
55356 #define BMB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
55358 #define BMB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client rc0 release fifo error
55360 #define BMB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client rc1 release fifo error
55362 #define BMB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client rc2 release fifo error
55364 #define BMB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client rc3 release fifo error
55366 #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client rc4 release fifo error
55368 #define BMB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // Read packet client rc4 release fifo error
55370 #define BMB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // Read packet client rc4 release fifo error
55372 #define BMB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // Read packet client rc4 release fifo error
55374 #define BMB_REG_INT_STS_WR_4_RC_PKT8_RLS_FIFO_ERROR (0x1<<17) // Read packet client rc4 release fifo error
55376 #define BMB_REG_INT_STS_WR_4_RC_PKT9_RLS_FIFO_ERROR (0x1<<18) // Read packet client rc4 release fifo error
55378 #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
55380 #define BMB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
55382 #define BMB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55384 #define BMB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55386 #define BMB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55388 #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55390 #define BMB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55392 #define BMB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55394 #define BMB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55396 #define BMB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55399 #define BMB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55401 #define BMB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
55403 #define BMB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
55405 #define BMB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
55407 #define BMB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
55409 #define BMB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
55411 #define BMB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
55413 #define BMB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client rc0 release fifo error
55415 #define BMB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client rc1 release fifo error
55417 #define BMB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client rc2 release fifo error
55419 #define BMB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client rc3 release fifo error
55421 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client rc4 release fifo error
55423 #define BMB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // Read packet client rc4 release fifo error
55425 #define BMB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // Read packet client rc4 release fifo error
55427 #define BMB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // Read packet client rc4 release fifo error
55429 #define BMB_REG_INT_STS_CLR_4_RC_PKT8_RLS_FIFO_ERROR (0x1<<17) // Read packet client rc4 release fifo error
55431 #define BMB_REG_INT_STS_CLR_4_RC_PKT9_RLS_FIFO_ERROR (0x1<<18) // Read packet client rc4 release fifo error
55433 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
55435 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
55437 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55439 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55441 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55443 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55445 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55447 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55449 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55451 #define BMB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
55454 #define BMB_REG_INT_STS_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
55456 #define BMB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
55458 #define BMB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // Read packet client5 side info FIFO error
55460 #define BMB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // Read packet client5 request FIFO error
55462 #define BMB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // Read packet client5 block FIFO error
55464 #define BMB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // Read packet client5 releases left FIFO error
55466 #define BMB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet client5 start pointer FIFO error
55468 #define BMB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet client5 second pointer FIFO
55470 #define BMB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // Read packet client5 response FIFO error
55472 #define BMB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // Read packet client5 descriptor FIFO error
55474 #define BMB_REG_INT_STS_5_RC_PKT6_RLS_ERROR (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
55476 #define BMB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
55478 #define BMB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // Read packet client6 side info FIFO error
55480 #define BMB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // Read packet client6 request FIFO error
55482 #define BMB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // Read packet client6 block FIFO error
55484 #define BMB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // Read packet client6 releases left FIFO error
55486 #define BMB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // Read packet client6 start pointer FIFO error
55488 #define BMB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // Read packet client6 second pointer FIFO
55490 #define BMB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // Read packet client6 response FIFO error
55492 #define BMB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // Read packet client6 descriptor FIFO error
55494 #define BMB_REG_INT_STS_5_RC_PKT7_RLS_ERROR (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
55496 #define BMB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
55498 #define BMB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // Read packet client7 side info FIFO error
55500 #define BMB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // Read packet client7 request FIFO error
55502 #define BMB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // Read packet client7 block FIFO error
55504 #define BMB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client7 releases left FIFO error
55506 #define BMB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client7 start pointer FIFO error
55508 #define BMB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client7 second pointer FIFO
55510 #define BMB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // Read packet client7 response FIFO error
55513 #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
55515 #define BMB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_PROTOCOL_ERROR .
55517 #define BMB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_SIDE_FIFO_ERROR .
55519 #define BMB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_REQ_FIFO_ERROR .
55521 #define BMB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_BLK_FIFO_ERROR .
55523 #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RLS_LEFT_FIFO_ERROR .
55525 #define BMB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_STRT_PTR_FIFO_ERROR .
55527 #define BMB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_SECOND_PTR_FIFO_ERROR .
55529 #define BMB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RSP_FIFO_ERROR .
55531 #define BMB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_DSCR_FIFO_ERROR .
55533 #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RLS_ERROR .
55535 #define BMB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_PROTOCOL_ERROR .
55537 #define BMB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_SIDE_FIFO_ERROR .
55539 #define BMB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_REQ_FIFO_ERROR .
55541 #define BMB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_BLK_FIFO_ERROR .
55543 #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RLS_LEFT_FIFO_ERROR .
55545 #define BMB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_STRT_PTR_FIFO_ERROR .
55547 #define BMB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_SECOND_PTR_FIFO_ERROR .
55549 #define BMB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RSP_FIFO_ERROR .
55551 #define BMB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_DSCR_FIFO_ERROR .
55553 #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RLS_ERROR .
55555 #define BMB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_PROTOCOL_ERROR .
55557 #define BMB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_SIDE_FIFO_ERROR .
55559 #define BMB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_REQ_FIFO_ERROR .
55561 #define BMB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_BLK_FIFO_ERROR .
55563 #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RLS_LEFT_FIFO_ERROR .
55565 #define BMB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_STRT_PTR_FIFO_ERROR .
55567 #define BMB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_SECOND_PTR_FIFO_ERROR .
55569 #define BMB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RSP_FIFO_ERROR .
55572 #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
55574 #define BMB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
55576 #define BMB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // Read packet client5 side info FIFO error
55578 #define BMB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // Read packet client5 request FIFO error
55580 #define BMB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // Read packet client5 block FIFO error
55582 #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // Read packet client5 releases left FIFO error
55584 #define BMB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet client5 start pointer FIFO error
55586 #define BMB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet client5 second pointer FIFO
55588 #define BMB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // Read packet client5 response FIFO error
55590 #define BMB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // Read packet client5 descriptor FIFO error
55592 #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
55594 #define BMB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
55596 #define BMB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // Read packet client6 side info FIFO error
55598 #define BMB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // Read packet client6 request FIFO error
55600 #define BMB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // Read packet client6 block FIFO error
55602 #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // Read packet client6 releases left FIFO error
55604 #define BMB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // Read packet client6 start pointer FIFO error
55606 #define BMB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // Read packet client6 second pointer FIFO
55608 #define BMB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // Read packet client6 response FIFO error
55610 #define BMB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // Read packet client6 descriptor FIFO error
55612 #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
55614 #define BMB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
55616 #define BMB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // Read packet client7 side info FIFO error
55618 #define BMB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // Read packet client7 request FIFO error
55620 #define BMB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // Read packet client7 block FIFO error
55622 #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client7 releases left FIFO error
55624 #define BMB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client7 start pointer FIFO error
55626 #define BMB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client7 second pointer FIFO
55628 #define BMB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // Read packet client7 response FIFO error
55631 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
55633 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
55635 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // Read packet client5 side info FIFO error
55637 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // Read packet client5 request FIFO error
55639 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // Read packet client5 block FIFO error
55641 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // Read packet client5 releases left FIFO error
55643 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet client5 start pointer FIFO error
55645 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet client5 second pointer FIFO
55647 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // Read packet client5 response FIFO error
55649 #define BMB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // Read packet client5 descriptor FIFO error
55651 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
55653 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
55655 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // Read packet client6 side info FIFO error
55657 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // Read packet client6 request FIFO error
55659 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // Read packet client6 block FIFO error
55661 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // Read packet client6 releases left FIFO error
55663 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // Read packet client6 start pointer FIFO error
55665 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // Read packet client6 second pointer FIFO
55667 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // Read packet client6 response FIFO error
55669 #define BMB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // Read packet client6 descriptor FIFO error
55671 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
55673 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
55675 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // Read packet client7 side info FIFO error
55677 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // Read packet client7 request FIFO error
55679 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // Read packet client7 block FIFO error
55681 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client7 releases left FIFO error
55683 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client7 start pointer FIFO error
55685 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client7 second pointer FIFO
55687 #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // Read packet client7 response FIFO error
55690 #define BMB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
55692 #define BMB_REG_INT_STS_6_RC_PKT8_RLS_ERROR (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
55694 #define BMB_REG_INT_STS_6_RC_PKT8_PROTOCOL_ERROR (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
55696 #define BMB_REG_INT_STS_6_RC_PKT8_SIDE_FIFO_ERROR (0x1<<4) // Read packet client8 side info FIFO error
55698 #define BMB_REG_INT_STS_6_RC_PKT8_REQ_FIFO_ERROR (0x1<<5) // Read packet client8 request FIFO error
55700 #define BMB_REG_INT_STS_6_RC_PKT8_BLK_FIFO_ERROR (0x1<<6) // Read packet client8 block FIFO error
55702 #define BMB_REG_INT_STS_6_RC_PKT8_RLS_LEFT_FIFO_ERROR (0x1<<7) // Read packet client8 releases left FIFO error
55704 #define BMB_REG_INT_STS_6_RC_PKT8_STRT_PTR_FIFO_ERROR (0x1<<8) // Read packet client8 start pointer FIFO error
55706 #define BMB_REG_INT_STS_6_RC_PKT8_SECOND_PTR_FIFO_ERROR (0x1<<9) // Read packet client8 second pointer FIFO
55708 #define BMB_REG_INT_STS_6_RC_PKT8_RSP_FIFO_ERROR (0x1<<10) // Read packet client8 response FIFO error
55710 #define BMB_REG_INT_STS_6_RC_PKT8_DSCR_FIFO_ERROR (0x1<<11) // Read packet client8 descriptor FIFO error
55712 #define BMB_REG_INT_STS_6_RC_PKT9_RLS_ERROR (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
55714 #define BMB_REG_INT_STS_6_RC_PKT9_PROTOCOL_ERROR (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
55716 #define BMB_REG_INT_STS_6_RC_PKT9_SIDE_FIFO_ERROR (0x1<<15) // Read packet client9 side info FIFO error
55718 #define BMB_REG_INT_STS_6_RC_PKT9_REQ_FIFO_ERROR (0x1<<16) // Read packet client9 request FIFO error
55720 #define BMB_REG_INT_STS_6_RC_PKT9_BLK_FIFO_ERROR (0x1<<17) // Read packet client9 block FIFO error
55722 #define BMB_REG_INT_STS_6_RC_PKT9_RLS_LEFT_FIFO_ERROR (0x1<<18) // Read packet client9 releases left FIFO error
55724 #define BMB_REG_INT_STS_6_RC_PKT9_STRT_PTR_FIFO_ERROR (0x1<<19) // Read packet client9 start pointer FIFO error
55726 #define BMB_REG_INT_STS_6_RC_PKT9_SECOND_PTR_FIFO_ERROR (0x1<<20) // Read packet client9 second pointer FIFO
55728 #define BMB_REG_INT_STS_6_RC_PKT9_RSP_FIFO_ERROR (0x1<<21) // Read packet client9 response FIFO error
55730 #define BMB_REG_INT_STS_6_RC_PKT9_DSCR_FIFO_ERROR (0x1<<22) // Read packet client9 descriptor FIFO error
55732 #define BMB_REG_INT_STS_6_WC4_PROTOCOL_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
55734 #define BMB_REG_INT_STS_6_WC5_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
55736 #define BMB_REG_INT_STS_6_WC6_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
55738 #define BMB_REG_INT_STS_6_WC7_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
55740 #define BMB_REG_INT_STS_6_WC8_PROTOCOL_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
55742 #define BMB_REG_INT_STS_6_WC9_PROTOCOL_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
55744 #define BMB_REG_INT_STS_6_WC4_INP_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
55746 #define BMB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
55748 #define BMB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
55751 #define BMB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
55753 #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RLS_ERROR .
55755 #define BMB_REG_INT_MASK_6_RC_PKT8_PROTOCOL_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_PROTOCOL_ERROR .
55757 #define BMB_REG_INT_MASK_6_RC_PKT8_SIDE_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_SIDE_FIFO_ERROR .
55759 #define BMB_REG_INT_MASK_6_RC_PKT8_REQ_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_REQ_FIFO_ERROR .
55761 #define BMB_REG_INT_MASK_6_RC_PKT8_BLK_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_BLK_FIFO_ERROR .
55763 #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_LEFT_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RLS_LEFT_FIFO_ERROR .
55765 #define BMB_REG_INT_MASK_6_RC_PKT8_STRT_PTR_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_STRT_PTR_FIFO_ERROR .
55767 #define BMB_REG_INT_MASK_6_RC_PKT8_SECOND_PTR_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_SECOND_PTR_FIFO_ERROR .
55769 #define BMB_REG_INT_MASK_6_RC_PKT8_RSP_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RSP_FIFO_ERROR .
55771 #define BMB_REG_INT_MASK_6_RC_PKT8_DSCR_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_DSCR_FIFO_ERROR .
55773 #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RLS_ERROR .
55775 #define BMB_REG_INT_MASK_6_RC_PKT9_PROTOCOL_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_PROTOCOL_ERROR .
55777 #define BMB_REG_INT_MASK_6_RC_PKT9_SIDE_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_SIDE_FIFO_ERROR .
55779 #define BMB_REG_INT_MASK_6_RC_PKT9_REQ_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_REQ_FIFO_ERROR .
55781 #define BMB_REG_INT_MASK_6_RC_PKT9_BLK_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_BLK_FIFO_ERROR .
55783 #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_LEFT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RLS_LEFT_FIFO_ERROR .
55785 #define BMB_REG_INT_MASK_6_RC_PKT9_STRT_PTR_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_STRT_PTR_FIFO_ERROR .
55787 #define BMB_REG_INT_MASK_6_RC_PKT9_SECOND_PTR_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_SECOND_PTR_FIFO_ERROR .
55789 #define BMB_REG_INT_MASK_6_RC_PKT9_RSP_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RSP_FIFO_ERROR .
55791 #define BMB_REG_INT_MASK_6_RC_PKT9_DSCR_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_DSCR_FIFO_ERROR .
55793 #define BMB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_PROTOCOL_ERROR .
55795 #define BMB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC5_PROTOCOL_ERROR .
55797 #define BMB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC6_PROTOCOL_ERROR .
55799 #define BMB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC7_PROTOCOL_ERROR .
55801 #define BMB_REG_INT_MASK_6_WC8_PROTOCOL_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC8_PROTOCOL_ERROR .
55803 #define BMB_REG_INT_MASK_6_WC9_PROTOCOL_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC9_PROTOCOL_ERROR .
55805 #define BMB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_INP_FIFO_ERROR .
55807 #define BMB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_SOP_FIFO_ERROR .
55809 #define BMB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_QUEUE_FIFO_ERROR .
55812 #define BMB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
55814 #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_ERROR (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
55816 #define BMB_REG_INT_STS_WR_6_RC_PKT8_PROTOCOL_ERROR (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
55818 #define BMB_REG_INT_STS_WR_6_RC_PKT8_SIDE_FIFO_ERROR (0x1<<4) // Read packet client8 side info FIFO error
55820 #define BMB_REG_INT_STS_WR_6_RC_PKT8_REQ_FIFO_ERROR (0x1<<5) // Read packet client8 request FIFO error
55822 #define BMB_REG_INT_STS_WR_6_RC_PKT8_BLK_FIFO_ERROR (0x1<<6) // Read packet client8 block FIFO error
55824 #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR (0x1<<7) // Read packet client8 releases left FIFO error
55826 #define BMB_REG_INT_STS_WR_6_RC_PKT8_STRT_PTR_FIFO_ERROR (0x1<<8) // Read packet client8 start pointer FIFO error
55828 #define BMB_REG_INT_STS_WR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR (0x1<<9) // Read packet client8 second pointer FIFO
55830 #define BMB_REG_INT_STS_WR_6_RC_PKT8_RSP_FIFO_ERROR (0x1<<10) // Read packet client8 response FIFO error
55832 #define BMB_REG_INT_STS_WR_6_RC_PKT8_DSCR_FIFO_ERROR (0x1<<11) // Read packet client8 descriptor FIFO error
55834 #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_ERROR (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
55836 #define BMB_REG_INT_STS_WR_6_RC_PKT9_PROTOCOL_ERROR (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
55838 #define BMB_REG_INT_STS_WR_6_RC_PKT9_SIDE_FIFO_ERROR (0x1<<15) // Read packet client9 side info FIFO error
55840 #define BMB_REG_INT_STS_WR_6_RC_PKT9_REQ_FIFO_ERROR (0x1<<16) // Read packet client9 request FIFO error
55842 #define BMB_REG_INT_STS_WR_6_RC_PKT9_BLK_FIFO_ERROR (0x1<<17) // Read packet client9 block FIFO error
55844 #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR (0x1<<18) // Read packet client9 releases left FIFO error
55846 #define BMB_REG_INT_STS_WR_6_RC_PKT9_STRT_PTR_FIFO_ERROR (0x1<<19) // Read packet client9 start pointer FIFO error
55848 #define BMB_REG_INT_STS_WR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR (0x1<<20) // Read packet client9 second pointer FIFO
55850 #define BMB_REG_INT_STS_WR_6_RC_PKT9_RSP_FIFO_ERROR (0x1<<21) // Read packet client9 response FIFO error
55852 #define BMB_REG_INT_STS_WR_6_RC_PKT9_DSCR_FIFO_ERROR (0x1<<22) // Read packet client9 descriptor FIFO error
55854 #define BMB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
55856 #define BMB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
55858 #define BMB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
55860 #define BMB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
55862 #define BMB_REG_INT_STS_WR_6_WC8_PROTOCOL_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
55864 #define BMB_REG_INT_STS_WR_6_WC9_PROTOCOL_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
55866 #define BMB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
55868 #define BMB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
55870 #define BMB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
55873 #define BMB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
55875 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_ERROR (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
55877 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_PROTOCOL_ERROR (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
55879 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SIDE_FIFO_ERROR (0x1<<4) // Read packet client8 side info FIFO error
55881 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_REQ_FIFO_ERROR (0x1<<5) // Read packet client8 request FIFO error
55883 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_BLK_FIFO_ERROR (0x1<<6) // Read packet client8 block FIFO error
55885 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR (0x1<<7) // Read packet client8 releases left FIFO error
55887 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_STRT_PTR_FIFO_ERROR (0x1<<8) // Read packet client8 start pointer FIFO error
55889 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR (0x1<<9) // Read packet client8 second pointer FIFO
55891 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RSP_FIFO_ERROR (0x1<<10) // Read packet client8 response FIFO error
55893 #define BMB_REG_INT_STS_CLR_6_RC_PKT8_DSCR_FIFO_ERROR (0x1<<11) // Read packet client8 descriptor FIFO error
55895 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_ERROR (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
55897 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_PROTOCOL_ERROR (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
55899 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SIDE_FIFO_ERROR (0x1<<15) // Read packet client9 side info FIFO error
55901 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_REQ_FIFO_ERROR (0x1<<16) // Read packet client9 request FIFO error
55903 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_BLK_FIFO_ERROR (0x1<<17) // Read packet client9 block FIFO error
55905 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR (0x1<<18) // Read packet client9 releases left FIFO error
55907 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_STRT_PTR_FIFO_ERROR (0x1<<19) // Read packet client9 start pointer FIFO error
55909 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR (0x1<<20) // Read packet client9 second pointer FIFO
55911 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RSP_FIFO_ERROR (0x1<<21) // Read packet client9 response FIFO error
55913 #define BMB_REG_INT_STS_CLR_6_RC_PKT9_DSCR_FIFO_ERROR (0x1<<22) // Read packet client9 descriptor FIFO error
55915 #define BMB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
55917 #define BMB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
55919 #define BMB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
55921 #define BMB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
55923 #define BMB_REG_INT_STS_CLR_6_WC8_PROTOCOL_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
55925 #define BMB_REG_INT_STS_CLR_6_WC9_PROTOCOL_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
55927 #define BMB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
55929 #define BMB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
55931 #define BMB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
55934 #define BMB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
55936 #define BMB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
55938 #define BMB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
55940 #define BMB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
55942 #define BMB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
55944 #define BMB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
55946 #define BMB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
55948 #define BMB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
55950 #define BMB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
55952 #define BMB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
55954 #define BMB_REG_INT_STS_7_WC5_INP_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
55956 #define BMB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
55958 #define BMB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
55960 #define BMB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
55962 #define BMB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
55964 #define BMB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
55966 #define BMB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
55968 #define BMB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
55970 #define BMB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
55972 #define BMB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // Notify FIFO error in write client 5
55974 #define BMB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
55976 #define BMB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
55978 #define BMB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
55980 #define BMB_REG_INT_STS_7_WC6_INP_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
55982 #define BMB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
55984 #define BMB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
55986 #define BMB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
55988 #define BMB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
55990 #define BMB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
55992 #define BMB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
55994 #define BMB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
55996 #define BMB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
55999 #define BMB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_FREE_POINT_FIFO_ERROR .
56001 #define BMB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_NEXT_POINT_FIFO_ERROR .
56003 #define BMB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_STRT_FIFO_ERROR .
56005 #define BMB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_SECOND_DSCR_FIFO_ERROR .
56007 #define BMB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_PKT_AVAIL_FIFO_ERROR .
56009 #define BMB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_COS_CNT_FIFO_ERROR .
56011 #define BMB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_NOTIFY_FIFO_ERROR .
56013 #define BMB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_LL_REQ_FIFO_ERROR .
56015 #define BMB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_LL_PA_CNT_ERROR .
56017 #define BMB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_BB_PA_CNT_ERROR .
56019 #define BMB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_INP_FIFO_ERROR .
56021 #define BMB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_SOP_FIFO_ERROR .
56023 #define BMB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_QUEUE_FIFO_ERROR .
56025 #define BMB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_FREE_POINT_FIFO_ERROR .
56027 #define BMB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_NEXT_POINT_FIFO_ERROR .
56029 #define BMB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_STRT_FIFO_ERROR .
56031 #define BMB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_SECOND_DSCR_FIFO_ERROR .
56033 #define BMB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_PKT_AVAIL_FIFO_ERROR .
56035 #define BMB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_COS_CNT_FIFO_ERROR .
56037 #define BMB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_NOTIFY_FIFO_ERROR .
56039 #define BMB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_LL_REQ_FIFO_ERROR .
56041 #define BMB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_LL_PA_CNT_ERROR .
56043 #define BMB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_BB_PA_CNT_ERROR .
56045 #define BMB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_INP_FIFO_ERROR .
56047 #define BMB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_SOP_FIFO_ERROR .
56049 #define BMB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_QUEUE_FIFO_ERROR .
56051 #define BMB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_FREE_POINT_FIFO_ERROR .
56053 #define BMB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_NEXT_POINT_FIFO_ERROR .
56055 #define BMB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_STRT_FIFO_ERROR .
56057 #define BMB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_SECOND_DSCR_FIFO_ERROR .
56059 #define BMB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_PKT_AVAIL_FIFO_ERROR .
56061 #define BMB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_COS_CNT_FIFO_ERROR .
56064 #define BMB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
56066 #define BMB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
56068 #define BMB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
56070 #define BMB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
56072 #define BMB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
56074 #define BMB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
56076 #define BMB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
56078 #define BMB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
56080 #define BMB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
56082 #define BMB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
56084 #define BMB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
56086 #define BMB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
56088 #define BMB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
56090 #define BMB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
56092 #define BMB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
56094 #define BMB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
56096 #define BMB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
56098 #define BMB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
56100 #define BMB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
56102 #define BMB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // Notify FIFO error in write client 5
56104 #define BMB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
56106 #define BMB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
56108 #define BMB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
56110 #define BMB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
56112 #define BMB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
56114 #define BMB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
56116 #define BMB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
56118 #define BMB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
56120 #define BMB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
56122 #define BMB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
56124 #define BMB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
56126 #define BMB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
56129 #define BMB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
56131 #define BMB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
56133 #define BMB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
56135 #define BMB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
56137 #define BMB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
56139 #define BMB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
56141 #define BMB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
56143 #define BMB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
56145 #define BMB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
56147 #define BMB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
56149 #define BMB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
56151 #define BMB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
56153 #define BMB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
56155 #define BMB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
56157 #define BMB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
56159 #define BMB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
56161 #define BMB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
56163 #define BMB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
56165 #define BMB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
56167 #define BMB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR (0x1<<19) // Notify FIFO error in write client 5
56169 #define BMB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
56171 #define BMB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
56173 #define BMB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
56175 #define BMB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
56177 #define BMB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
56179 #define BMB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
56181 #define BMB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
56183 #define BMB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
56185 #define BMB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
56187 #define BMB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
56189 #define BMB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
56191 #define BMB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
56194 #define BMB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
56196 #define BMB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
56198 #define BMB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
56200 #define BMB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
56202 #define BMB_REG_INT_STS_8_WC7_INP_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
56204 #define BMB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
56206 #define BMB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
56208 #define BMB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
56210 #define BMB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
56212 #define BMB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
56214 #define BMB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
56216 #define BMB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
56218 #define BMB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
56220 #define BMB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
56222 #define BMB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
56224 #define BMB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
56226 #define BMB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
56228 #define BMB_REG_INT_STS_8_WC8_INP_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
56230 #define BMB_REG_INT_STS_8_WC8_SOP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
56232 #define BMB_REG_INT_STS_8_WC8_QUEUE_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
56234 #define BMB_REG_INT_STS_8_WC8_FREE_POINT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
56236 #define BMB_REG_INT_STS_8_WC8_NEXT_POINT_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
56238 #define BMB_REG_INT_STS_8_WC8_STRT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
56240 #define BMB_REG_INT_STS_8_WC8_SECOND_DSCR_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
56242 #define BMB_REG_INT_STS_8_WC8_PKT_AVAIL_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
56244 #define BMB_REG_INT_STS_8_WC8_COS_CNT_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
56246 #define BMB_REG_INT_STS_8_WC8_NOTIFY_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
56248 #define BMB_REG_INT_STS_8_WC8_LL_REQ_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
56250 #define BMB_REG_INT_STS_8_WC8_LL_PA_CNT_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
56252 #define BMB_REG_INT_STS_8_WC8_BB_PA_CNT_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
56254 #define BMB_REG_INT_STS_8_WC9_INP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
56256 #define BMB_REG_INT_STS_8_WC9_SOP_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
56259 #define BMB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
56261 #define BMB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_LL_REQ_FIFO_ERROR .
56263 #define BMB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_LL_PA_CNT_ERROR .
56265 #define BMB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_BB_PA_CNT_ERROR .
56267 #define BMB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_INP_FIFO_ERROR .
56269 #define BMB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_SOP_FIFO_ERROR .
56271 #define BMB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_QUEUE_FIFO_ERROR .
56273 #define BMB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_FREE_POINT_FIFO_ERROR .
56275 #define BMB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_NEXT_POINT_FIFO_ERROR .
56277 #define BMB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_STRT_FIFO_ERROR .
56279 #define BMB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_SECOND_DSCR_FIFO_ERROR .
56281 #define BMB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_PKT_AVAIL_FIFO_ERROR .
56283 #define BMB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_COS_CNT_FIFO_ERROR .
56285 #define BMB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_NOTIFY_FIFO_ERROR .
56287 #define BMB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_LL_REQ_FIFO_ERROR .
56289 #define BMB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_LL_PA_CNT_ERROR .
56291 #define BMB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_BB_PA_CNT_ERROR .
56293 #define BMB_REG_INT_MASK_8_WC8_INP_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_INP_FIFO_ERROR .
56295 #define BMB_REG_INT_MASK_8_WC8_SOP_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_SOP_FIFO_ERROR .
56297 #define BMB_REG_INT_MASK_8_WC8_QUEUE_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_QUEUE_FIFO_ERROR .
56299 #define BMB_REG_INT_MASK_8_WC8_FREE_POINT_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_FREE_POINT_FIFO_ERROR .
56301 #define BMB_REG_INT_MASK_8_WC8_NEXT_POINT_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_NEXT_POINT_FIFO_ERROR .
56303 #define BMB_REG_INT_MASK_8_WC8_STRT_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_STRT_FIFO_ERROR .
56305 #define BMB_REG_INT_MASK_8_WC8_SECOND_DSCR_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_SECOND_DSCR_FIFO_ERROR .
56307 #define BMB_REG_INT_MASK_8_WC8_PKT_AVAIL_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_PKT_AVAIL_FIFO_ERROR .
56309 #define BMB_REG_INT_MASK_8_WC8_COS_CNT_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_COS_CNT_FIFO_ERROR .
56311 #define BMB_REG_INT_MASK_8_WC8_NOTIFY_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_NOTIFY_FIFO_ERROR .
56313 #define BMB_REG_INT_MASK_8_WC8_LL_REQ_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_LL_REQ_FIFO_ERROR .
56315 #define BMB_REG_INT_MASK_8_WC8_LL_PA_CNT_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_LL_PA_CNT_ERROR .
56317 #define BMB_REG_INT_MASK_8_WC8_BB_PA_CNT_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_BB_PA_CNT_ERROR .
56319 #define BMB_REG_INT_MASK_8_WC9_INP_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC9_INP_FIFO_ERROR .
56321 #define BMB_REG_INT_MASK_8_WC9_SOP_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC9_SOP_FIFO_ERROR .
56324 #define BMB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
56326 #define BMB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
56328 #define BMB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
56330 #define BMB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
56332 #define BMB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
56334 #define BMB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
56336 #define BMB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
56338 #define BMB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
56340 #define BMB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
56342 #define BMB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
56344 #define BMB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
56346 #define BMB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
56348 #define BMB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
56350 #define BMB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
56352 #define BMB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
56354 #define BMB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
56356 #define BMB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
56358 #define BMB_REG_INT_STS_WR_8_WC8_INP_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
56360 #define BMB_REG_INT_STS_WR_8_WC8_SOP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
56362 #define BMB_REG_INT_STS_WR_8_WC8_QUEUE_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
56364 #define BMB_REG_INT_STS_WR_8_WC8_FREE_POINT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
56366 #define BMB_REG_INT_STS_WR_8_WC8_NEXT_POINT_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
56368 #define BMB_REG_INT_STS_WR_8_WC8_STRT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
56370 #define BMB_REG_INT_STS_WR_8_WC8_SECOND_DSCR_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
56372 #define BMB_REG_INT_STS_WR_8_WC8_PKT_AVAIL_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
56374 #define BMB_REG_INT_STS_WR_8_WC8_COS_CNT_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
56376 #define BMB_REG_INT_STS_WR_8_WC8_NOTIFY_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
56378 #define BMB_REG_INT_STS_WR_8_WC8_LL_REQ_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
56380 #define BMB_REG_INT_STS_WR_8_WC8_LL_PA_CNT_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
56382 #define BMB_REG_INT_STS_WR_8_WC8_BB_PA_CNT_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
56384 #define BMB_REG_INT_STS_WR_8_WC9_INP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
56386 #define BMB_REG_INT_STS_WR_8_WC9_SOP_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
56389 #define BMB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
56391 #define BMB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
56393 #define BMB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
56395 #define BMB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
56397 #define BMB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
56399 #define BMB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
56401 #define BMB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
56403 #define BMB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
56405 #define BMB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
56407 #define BMB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
56409 #define BMB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
56411 #define BMB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
56413 #define BMB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
56415 #define BMB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
56417 #define BMB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
56419 #define BMB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
56421 #define BMB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
56423 #define BMB_REG_INT_STS_CLR_8_WC8_INP_FIFO_ERROR (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
56425 #define BMB_REG_INT_STS_CLR_8_WC8_SOP_FIFO_ERROR (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
56427 #define BMB_REG_INT_STS_CLR_8_WC8_QUEUE_FIFO_ERROR (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
56429 #define BMB_REG_INT_STS_CLR_8_WC8_FREE_POINT_FIFO_ERROR (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
56431 #define BMB_REG_INT_STS_CLR_8_WC8_NEXT_POINT_FIFO_ERROR (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
56433 #define BMB_REG_INT_STS_CLR_8_WC8_STRT_FIFO_ERROR (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
56435 #define BMB_REG_INT_STS_CLR_8_WC8_SECOND_DSCR_FIFO_ERROR (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
56437 #define BMB_REG_INT_STS_CLR_8_WC8_PKT_AVAIL_FIFO_ERROR (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
56439 #define BMB_REG_INT_STS_CLR_8_WC8_COS_CNT_FIFO_ERROR (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
56441 #define BMB_REG_INT_STS_CLR_8_WC8_NOTIFY_FIFO_ERROR (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
56443 #define BMB_REG_INT_STS_CLR_8_WC8_LL_REQ_FIFO_ERROR (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
56445 #define BMB_REG_INT_STS_CLR_8_WC8_LL_PA_CNT_ERROR (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
56447 #define BMB_REG_INT_STS_CLR_8_WC8_BB_PA_CNT_ERROR (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
56449 #define BMB_REG_INT_STS_CLR_8_WC9_INP_FIFO_ERROR (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
56451 #define BMB_REG_INT_STS_CLR_8_WC9_SOP_FIFO_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
56454 #define BMB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
56456 #define BMB_REG_INT_STS_9_WC9_FREE_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
56458 #define BMB_REG_INT_STS_9_WC9_NEXT_POINT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
56460 #define BMB_REG_INT_STS_9_WC9_STRT_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
56462 #define BMB_REG_INT_STS_9_WC9_SECOND_DSCR_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
56464 #define BMB_REG_INT_STS_9_WC9_PKT_AVAIL_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
56466 #define BMB_REG_INT_STS_9_WC9_COS_CNT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
56468 #define BMB_REG_INT_STS_9_WC9_NOTIFY_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
56470 #define BMB_REG_INT_STS_9_WC9_LL_REQ_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
56472 #define BMB_REG_INT_STS_9_WC9_LL_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
56474 #define BMB_REG_INT_STS_9_WC9_BB_PA_CNT_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
56476 #define BMB_REG_INT_STS_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // SOP DSCR SYNC FIFO error for RC2
56478 #define BMB_REG_INT_STS_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // SOP output SYNC FIFO error for RC2
56480 #define BMB_REG_INT_STS_9_RC0_SOP_PEND_FIFO_ERROR (0x1<<13) // SOP pending FIFO error for RC0
56482 #define BMB_REG_INT_STS_9_RC1_SOP_PEND_FIFO_ERROR (0x1<<14) // SOP pending FIFO error for RC01
56484 #define BMB_REG_INT_STS_9_RC2_SOP_PEND_FIFO_ERROR (0x1<<15) // SOP pending FIFO error for RC2
56486 #define BMB_REG_INT_STS_9_RC3_SOP_PEND_FIFO_ERROR (0x1<<16) // SOP pending FIFO error for RC3
56488 #define BMB_REG_INT_STS_9_RC4_SOP_PEND_FIFO_ERROR (0x1<<17) // SOP pending FIFO error for RC4
56490 #define BMB_REG_INT_STS_9_RC5_SOP_PEND_FIFO_ERROR (0x1<<18) // SOP pending FIFO error for RC05
56492 #define BMB_REG_INT_STS_9_RC6_SOP_PEND_FIFO_ERROR (0x1<<19) // SOP pending FIFO error for RC6
56494 #define BMB_REG_INT_STS_9_RC7_SOP_PEND_FIFO_ERROR (0x1<<20) // SOP pending FIFO error for RC7
56496 #define BMB_REG_INT_STS_9_RC0_DSCR_PEND_FIFO_ERROR (0x1<<21) // SOP descriptor FIFO error for RC0
56498 #define BMB_REG_INT_STS_9_RC1_DSCR_PEND_FIFO_ERROR (0x1<<22) // SOP descriptor FIFO error for RC1
56500 #define BMB_REG_INT_STS_9_RC2_DSCR_PEND_FIFO_ERROR (0x1<<23) // SOP descriptor FIFO error for RC02
56502 #define BMB_REG_INT_STS_9_RC3_DSCR_PEND_FIFO_ERROR (0x1<<24) // SOP descriptor FIFO error for RC3
56504 #define BMB_REG_INT_STS_9_RC4_DSCR_PEND_FIFO_ERROR (0x1<<25) // SOP descriptor FIFO error for RC4
56506 #define BMB_REG_INT_STS_9_RC5_DSCR_PEND_FIFO_ERROR (0x1<<26) // SOP descriptor FIFO error for RC5
56508 #define BMB_REG_INT_STS_9_RC6_DSCR_PEND_FIFO_ERROR (0x1<<27) // SOP descriptor FIFO error for RC6
56510 #define BMB_REG_INT_STS_9_RC7_DSCR_PEND_FIFO_ERROR (0x1<<28) // SOP descriptor FIFO error for RC7
56512 #define BMB_REG_INT_STS_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // SOP input SYNC FIFO error for RC1
56514 #define BMB_REG_INT_STS_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // SOP input SYNC FIFO error for RC2
56516 #define BMB_REG_INT_STS_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // SOP output SYNC FIFO error for RC1
56518 #define BMB_REG_INT_STS_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
56520 #define BMB_REG_INT_STS_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // SOP output SYNC FIFO error for RC8
56522 #define BMB_REG_INT_STS_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // SOP input SYNC FIFO error for RC8
56524 #define BMB_REG_INT_STS_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // SOP input SYNC FIFO error for RC9
56526 #define BMB_REG_INT_STS_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // SOP output SYNC FIFO error for RC8
56529 #define BMB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
56531 #define BMB_REG_INT_MASK_9_WC9_FREE_POINT_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_FREE_POINT_FIFO_ERROR .
56533 #define BMB_REG_INT_MASK_9_WC9_NEXT_POINT_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NEXT_POINT_FIFO_ERROR .
56535 #define BMB_REG_INT_MASK_9_WC9_STRT_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_STRT_FIFO_ERROR .
56537 #define BMB_REG_INT_MASK_9_WC9_SECOND_DSCR_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_SECOND_DSCR_FIFO_ERROR .
56539 #define BMB_REG_INT_MASK_9_WC9_PKT_AVAIL_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_PKT_AVAIL_FIFO_ERROR .
56541 #define BMB_REG_INT_MASK_9_WC9_COS_CNT_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_COS_CNT_FIFO_ERROR .
56543 #define BMB_REG_INT_MASK_9_WC9_NOTIFY_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NOTIFY_FIFO_ERROR .
56545 #define BMB_REG_INT_MASK_9_WC9_LL_REQ_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_REQ_FIFO_ERROR .
56547 #define BMB_REG_INT_MASK_9_WC9_LL_PA_CNT_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_PA_CNT_ERROR .
56549 #define BMB_REG_INT_MASK_9_WC9_BB_PA_CNT_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_BB_PA_CNT_ERROR .
56551 #define BMB_REG_INT_MASK_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_RC_OUT_SYNC_FIFO_ERROR .
56553 #define BMB_REG_INT_MASK_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
56555 #define BMB_REG_INT_MASK_9_RC0_SOP_PEND_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_SOP_PEND_FIFO_ERROR .
56557 #define BMB_REG_INT_MASK_9_RC1_SOP_PEND_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_PEND_FIFO_ERROR .
56559 #define BMB_REG_INT_MASK_9_RC2_SOP_PEND_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_PEND_FIFO_ERROR .
56561 #define BMB_REG_INT_MASK_9_RC3_SOP_PEND_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_SOP_PEND_FIFO_ERROR .
56563 #define BMB_REG_INT_MASK_9_RC4_SOP_PEND_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_SOP_PEND_FIFO_ERROR .
56565 #define BMB_REG_INT_MASK_9_RC5_SOP_PEND_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_SOP_PEND_FIFO_ERROR .
56567 #define BMB_REG_INT_MASK_9_RC6_SOP_PEND_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_SOP_PEND_FIFO_ERROR .
56569 #define BMB_REG_INT_MASK_9_RC7_SOP_PEND_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_SOP_PEND_FIFO_ERROR .
56571 #define BMB_REG_INT_MASK_9_RC0_DSCR_PEND_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_DSCR_PEND_FIFO_ERROR .
56573 #define BMB_REG_INT_MASK_9_RC1_DSCR_PEND_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_DSCR_PEND_FIFO_ERROR .
56575 #define BMB_REG_INT_MASK_9_RC2_DSCR_PEND_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_DSCR_PEND_FIFO_ERROR .
56577 #define BMB_REG_INT_MASK_9_RC3_DSCR_PEND_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_DSCR_PEND_FIFO_ERROR .
56579 #define BMB_REG_INT_MASK_9_RC4_DSCR_PEND_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_DSCR_PEND_FIFO_ERROR .
56581 #define BMB_REG_INT_MASK_9_RC5_DSCR_PEND_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_DSCR_PEND_FIFO_ERROR .
56583 #define BMB_REG_INT_MASK_9_RC6_DSCR_PEND_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_DSCR_PEND_FIFO_ERROR .
56585 #define BMB_REG_INT_MASK_9_RC7_DSCR_PEND_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_DSCR_PEND_FIFO_ERROR .
56587 #define BMB_REG_INT_MASK_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR .
56589 #define BMB_REG_INT_MASK_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR .
56591 #define BMB_REG_INT_MASK_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
56593 #define BMB_REG_INT_MASK_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_RC_OUT_SYNC_FIFO_ERROR .
56595 #define BMB_REG_INT_MASK_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
56597 #define BMB_REG_INT_MASK_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR .
56599 #define BMB_REG_INT_MASK_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR .
56601 #define BMB_REG_INT_MASK_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
56604 #define BMB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
56606 #define BMB_REG_INT_STS_WR_9_WC9_FREE_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
56608 #define BMB_REG_INT_STS_WR_9_WC9_NEXT_POINT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
56610 #define BMB_REG_INT_STS_WR_9_WC9_STRT_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
56612 #define BMB_REG_INT_STS_WR_9_WC9_SECOND_DSCR_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
56614 #define BMB_REG_INT_STS_WR_9_WC9_PKT_AVAIL_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
56616 #define BMB_REG_INT_STS_WR_9_WC9_COS_CNT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
56618 #define BMB_REG_INT_STS_WR_9_WC9_NOTIFY_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
56620 #define BMB_REG_INT_STS_WR_9_WC9_LL_REQ_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
56622 #define BMB_REG_INT_STS_WR_9_WC9_LL_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
56624 #define BMB_REG_INT_STS_WR_9_WC9_BB_PA_CNT_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
56626 #define BMB_REG_INT_STS_WR_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // SOP DSCR SYNC FIFO error for RC2
56628 #define BMB_REG_INT_STS_WR_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // SOP output SYNC FIFO error for RC2
56630 #define BMB_REG_INT_STS_WR_9_RC0_SOP_PEND_FIFO_ERROR (0x1<<13) // SOP pending FIFO error for RC0
56632 #define BMB_REG_INT_STS_WR_9_RC1_SOP_PEND_FIFO_ERROR (0x1<<14) // SOP pending FIFO error for RC01
56634 #define BMB_REG_INT_STS_WR_9_RC2_SOP_PEND_FIFO_ERROR (0x1<<15) // SOP pending FIFO error for RC2
56636 #define BMB_REG_INT_STS_WR_9_RC3_SOP_PEND_FIFO_ERROR (0x1<<16) // SOP pending FIFO error for RC3
56638 #define BMB_REG_INT_STS_WR_9_RC4_SOP_PEND_FIFO_ERROR (0x1<<17) // SOP pending FIFO error for RC4
56640 #define BMB_REG_INT_STS_WR_9_RC5_SOP_PEND_FIFO_ERROR (0x1<<18) // SOP pending FIFO error for RC05
56642 #define BMB_REG_INT_STS_WR_9_RC6_SOP_PEND_FIFO_ERROR (0x1<<19) // SOP pending FIFO error for RC6
56644 #define BMB_REG_INT_STS_WR_9_RC7_SOP_PEND_FIFO_ERROR (0x1<<20) // SOP pending FIFO error for RC7
56646 #define BMB_REG_INT_STS_WR_9_RC0_DSCR_PEND_FIFO_ERROR (0x1<<21) // SOP descriptor FIFO error for RC0
56648 #define BMB_REG_INT_STS_WR_9_RC1_DSCR_PEND_FIFO_ERROR (0x1<<22) // SOP descriptor FIFO error for RC1
56650 #define BMB_REG_INT_STS_WR_9_RC2_DSCR_PEND_FIFO_ERROR (0x1<<23) // SOP descriptor FIFO error for RC02
56652 #define BMB_REG_INT_STS_WR_9_RC3_DSCR_PEND_FIFO_ERROR (0x1<<24) // SOP descriptor FIFO error for RC3
56654 #define BMB_REG_INT_STS_WR_9_RC4_DSCR_PEND_FIFO_ERROR (0x1<<25) // SOP descriptor FIFO error for RC4
56656 #define BMB_REG_INT_STS_WR_9_RC5_DSCR_PEND_FIFO_ERROR (0x1<<26) // SOP descriptor FIFO error for RC5
56658 #define BMB_REG_INT_STS_WR_9_RC6_DSCR_PEND_FIFO_ERROR (0x1<<27) // SOP descriptor FIFO error for RC6
56660 #define BMB_REG_INT_STS_WR_9_RC7_DSCR_PEND_FIFO_ERROR (0x1<<28) // SOP descriptor FIFO error for RC7
56662 #define BMB_REG_INT_STS_WR_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // SOP input SYNC FIFO error for RC1
56664 #define BMB_REG_INT_STS_WR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // SOP input SYNC FIFO error for RC2
56666 #define BMB_REG_INT_STS_WR_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // SOP output SYNC FIFO error for RC1
56668 #define BMB_REG_INT_STS_WR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
56670 #define BMB_REG_INT_STS_WR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // SOP output SYNC FIFO error for RC8
56672 #define BMB_REG_INT_STS_WR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // SOP input SYNC FIFO error for RC8
56674 #define BMB_REG_INT_STS_WR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // SOP input SYNC FIFO error for RC9
56676 #define BMB_REG_INT_STS_WR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // SOP output SYNC FIFO error for RC8
56679 #define BMB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
56681 #define BMB_REG_INT_STS_CLR_9_WC9_FREE_POINT_FIFO_ERROR (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
56683 #define BMB_REG_INT_STS_CLR_9_WC9_NEXT_POINT_FIFO_ERROR (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
56685 #define BMB_REG_INT_STS_CLR_9_WC9_STRT_FIFO_ERROR (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
56687 #define BMB_REG_INT_STS_CLR_9_WC9_SECOND_DSCR_FIFO_ERROR (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
56689 #define BMB_REG_INT_STS_CLR_9_WC9_PKT_AVAIL_FIFO_ERROR (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
56691 #define BMB_REG_INT_STS_CLR_9_WC9_COS_CNT_FIFO_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
56693 #define BMB_REG_INT_STS_CLR_9_WC9_NOTIFY_FIFO_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
56695 #define BMB_REG_INT_STS_CLR_9_WC9_LL_REQ_FIFO_ERROR (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
56697 #define BMB_REG_INT_STS_CLR_9_WC9_LL_PA_CNT_ERROR (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
56699 #define BMB_REG_INT_STS_CLR_9_WC9_BB_PA_CNT_ERROR (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
56701 #define BMB_REG_INT_STS_CLR_9_RC2_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // SOP DSCR SYNC FIFO error for RC2
56703 #define BMB_REG_INT_STS_CLR_9_RC2_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // SOP output SYNC FIFO error for RC2
56705 #define BMB_REG_INT_STS_CLR_9_RC0_SOP_PEND_FIFO_ERROR (0x1<<13) // SOP pending FIFO error for RC0
56707 #define BMB_REG_INT_STS_CLR_9_RC1_SOP_PEND_FIFO_ERROR (0x1<<14) // SOP pending FIFO error for RC01
56709 #define BMB_REG_INT_STS_CLR_9_RC2_SOP_PEND_FIFO_ERROR (0x1<<15) // SOP pending FIFO error for RC2
56711 #define BMB_REG_INT_STS_CLR_9_RC3_SOP_PEND_FIFO_ERROR (0x1<<16) // SOP pending FIFO error for RC3
56713 #define BMB_REG_INT_STS_CLR_9_RC4_SOP_PEND_FIFO_ERROR (0x1<<17) // SOP pending FIFO error for RC4
56715 #define BMB_REG_INT_STS_CLR_9_RC5_SOP_PEND_FIFO_ERROR (0x1<<18) // SOP pending FIFO error for RC05
56717 #define BMB_REG_INT_STS_CLR_9_RC6_SOP_PEND_FIFO_ERROR (0x1<<19) // SOP pending FIFO error for RC6
56719 #define BMB_REG_INT_STS_CLR_9_RC7_SOP_PEND_FIFO_ERROR (0x1<<20) // SOP pending FIFO error for RC7
56721 #define BMB_REG_INT_STS_CLR_9_RC0_DSCR_PEND_FIFO_ERROR (0x1<<21) // SOP descriptor FIFO error for RC0
56723 #define BMB_REG_INT_STS_CLR_9_RC1_DSCR_PEND_FIFO_ERROR (0x1<<22) // SOP descriptor FIFO error for RC1
56725 #define BMB_REG_INT_STS_CLR_9_RC2_DSCR_PEND_FIFO_ERROR (0x1<<23) // SOP descriptor FIFO error for RC02
56727 #define BMB_REG_INT_STS_CLR_9_RC3_DSCR_PEND_FIFO_ERROR (0x1<<24) // SOP descriptor FIFO error for RC3
56729 #define BMB_REG_INT_STS_CLR_9_RC4_DSCR_PEND_FIFO_ERROR (0x1<<25) // SOP descriptor FIFO error for RC4
56731 #define BMB_REG_INT_STS_CLR_9_RC5_DSCR_PEND_FIFO_ERROR (0x1<<26) // SOP descriptor FIFO error for RC5
56733 #define BMB_REG_INT_STS_CLR_9_RC6_DSCR_PEND_FIFO_ERROR (0x1<<27) // SOP descriptor FIFO error for RC6
56735 #define BMB_REG_INT_STS_CLR_9_RC7_DSCR_PEND_FIFO_ERROR (0x1<<28) // SOP descriptor FIFO error for RC7
56737 #define BMB_REG_INT_STS_CLR_9_RC1_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // SOP input SYNC FIFO error for RC1
56739 #define BMB_REG_INT_STS_CLR_9_RC2_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // SOP input SYNC FIFO error for RC2
56741 #define BMB_REG_INT_STS_CLR_9_RC1_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // SOP output SYNC FIFO error for RC1
56743 #define BMB_REG_INT_STS_CLR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
56745 #define BMB_REG_INT_STS_CLR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<12) // SOP output SYNC FIFO error for RC8
56747 #define BMB_REG_INT_STS_CLR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<29) // SOP input SYNC FIFO error for RC8
56749 #define BMB_REG_INT_STS_CLR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR (0x1<<30) // SOP input SYNC FIFO error for RC9
56751 #define BMB_REG_INT_STS_CLR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<31) // SOP output SYNC FIFO error for RC8
56754 #define BMB_REG_INT_STS_10_RC_GNT_PEND_FIFO_ERROR (0x1<<0) //
56756 #define BMB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // Packet RC output SYNC FIFO error
56758 #define BMB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // Packet RC output SYNC FIFO error
56760 #define BMB_REG_INT_STS_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<20) // Packet RC output SYNC FIFO error
56762 #define BMB_REG_INT_STS_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<21) // Packet RC output SYNC FIFO error
56765 #define BMB_REG_INT_MASK_10_RC_GNT_PEND_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC_GNT_PEND_FIFO_ERROR .
56767 #define BMB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC1_OUT_SYNC_FIFO_PUSH_ERROR .
56769 #define BMB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC2_OUT_SYNC_FIFO_PUSH_ERROR .
56771 #define BMB_REG_INT_MASK_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC8_OUT_SYNC_FIFO_PUSH_ERROR .
56773 #define BMB_REG_INT_MASK_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC9_OUT_SYNC_FIFO_PUSH_ERROR .
56776 #define BMB_REG_INT_STS_WR_10_RC_GNT_PEND_FIFO_ERROR (0x1<<0) //
56778 #define BMB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // Packet RC output SYNC FIFO error
56780 #define BMB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // Packet RC output SYNC FIFO error
56782 #define BMB_REG_INT_STS_WR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<20) // Packet RC output SYNC FIFO error
56784 #define BMB_REG_INT_STS_WR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<21) // Packet RC output SYNC FIFO error
56787 #define BMB_REG_INT_STS_CLR_10_RC_GNT_PEND_FIFO_ERROR (0x1<<0) //
56789 #define BMB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<13) // Packet RC output SYNC FIFO error
56791 #define BMB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<14) // Packet RC output SYNC FIFO error
56793 #define BMB_REG_INT_STS_CLR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<20) // Packet RC output SYNC FIFO error
56795 #define BMB_REG_INT_STS_CLR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR (0x1<<21) // Packet RC output SYNC FIFO error
56798 #define BMB_REG_INT_STS_11_WC8_SYNC_FIFO_PUSH_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
56800 #define BMB_REG_INT_STS_11_WC9_SYNC_FIFO_PUSH_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
56802 #define BMB_REG_INT_STS_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // SOP DSCR SYNC FIFO error for RC1
56804 #define BMB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // Read packet client7 descriptor FIFO error
56806 #define BMB_REG_INT_STS_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
56809 #define BMB_REG_INT_MASK_11_WC8_SYNC_FIFO_PUSH_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.WC8_SYNC_FIFO_PUSH_ERROR .
56811 #define BMB_REG_INT_MASK_11_WC9_SYNC_FIFO_PUSH_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.WC9_SYNC_FIFO_PUSH_ERROR .
56813 #define BMB_REG_INT_MASK_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC1_SOP_RC_OUT_SYNC_FIFO_ERROR .
56815 #define BMB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC_PKT7_DSCR_FIFO_ERROR .
56817 #define BMB_REG_INT_MASK_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC8_SOP_RC_OUT_SYNC_FIFO_ERROR .
56820 #define BMB_REG_INT_STS_WR_11_WC8_SYNC_FIFO_PUSH_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
56822 #define BMB_REG_INT_STS_WR_11_WC9_SYNC_FIFO_PUSH_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
56824 #define BMB_REG_INT_STS_WR_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // SOP DSCR SYNC FIFO error for RC1
56826 #define BMB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // Read packet client7 descriptor FIFO error
56828 #define BMB_REG_INT_STS_WR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
56831 #define BMB_REG_INT_STS_CLR_11_WC8_SYNC_FIFO_PUSH_ERROR (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
56833 #define BMB_REG_INT_STS_CLR_11_WC9_SYNC_FIFO_PUSH_ERROR (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
56835 #define BMB_REG_INT_STS_CLR_11_RC1_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // SOP DSCR SYNC FIFO error for RC1
56837 #define BMB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // Read packet client7 descriptor FIFO error
56839 #define BMB_REG_INT_STS_CLR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
56842 #define BMB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
56844 #define BMB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
56846 #define BMB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
56848 #define BMB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
56850 #define BMB_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.DATAPATH_REGISTERS .
56853 #define BMB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
56855 #define BMB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
56857 #define BMB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
56859 #define BMB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
56861 #define BMB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
56863 #define BMB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
56865 #define BMB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
56867 #define BMB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
56869 #define BMB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
56871 #define BMB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
56873 #define BMB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
56875 #define BMB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
56877 #define BMB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
56879 #define BMB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
56881 #define BMB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
56883 #define BMB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT (0x1<<15) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
56885 #define BMB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
56887 #define BMB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
56889 #define BMB_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
56891 #define BMB_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
56893 #define BMB_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
56895 #define BMB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
56897 #define BMB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
56899 #define BMB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
56901 #define BMB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
56903 #define BMB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
56905 #define BMB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
56907 #define BMB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
56909 #define BMB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
56911 #define BMB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
56913 #define BMB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM049_I_MEM_PRTY .
56916 #define BMB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
56918 #define BMB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
56920 #define BMB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
56922 #define BMB_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
56924 #define BMB_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
56926 #define BMB_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
56928 #define BMB_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
56930 #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
56932 #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
56934 #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
56936 #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
56938 #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
56940 #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
56942 #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
56944 #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
56963 #define BMB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
56965 #define BMB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
56967 #define BMB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
56969 #define BMB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
56971 #define BMB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
56973 #define BMB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
56975 #define BMB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN (0x1<<6) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
56977 #define BMB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN (0x1<<7) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
56979 #define BMB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
56981 #define BMB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN (0x1<<9) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
56983 #define BMB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<10) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
56985 #define BMB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<11) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
56987 #define BMB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<12) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
56989 #define BMB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<13) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
56991 #define BMB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN (0x1<<14) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
56993 #define BMB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN (0x1<<15) // Enable ECC for memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
56996 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
56998 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
57000 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
57002 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
57004 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
57006 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
57008 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY (0x1<<6) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
57010 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY (0x1<<7) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
57012 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
57014 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY (0x1<<9) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
57016 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<10) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
57018 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<11) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
57020 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<12) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
57022 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<13) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
57024 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY (0x1<<14) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
57026 #define BMB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY (0x1<<15) // Set parity only for memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
57029 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_ecc in module bmb_bb_bank
57031 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_ecc in module bmb_bb_bank
57033 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_ecc in module bmb_bb_bank
57035 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_ecc in module bmb_bb_bank
57037 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_ecc in module bmb_bb_bank
57039 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_ecc in module bmb_bb_bank
57041 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_ecc in module bmb_bb_bank
57043 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_ecc in module bmb_bb_bank
57045 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_ecc in module bmb_bb_bank
57047 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_ecc in module bmb_bb_bank
57049 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<10) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_ecc in module bmb_bb_bank
57051 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<11) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_ecc in module bmb_bb_bank
57053 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<12) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_ecc in module bmb_bb_bank
57055 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<13) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_ecc in module bmb_bb_bank
57057 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT (0x1<<14) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_ecc in module bmb_bb_bank
57059 #define BMB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT (0x1<<15) // Record if a correctable error occurred on memory ecc instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_ecc in module bmb_bb_bank
57135 #define BMB_REG_BR_FIX_HIGH_PRI_COLLISION 0x540954UL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
57170 #define BMB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure.
57177 #define BMB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure.
57181 #define BMB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN (0x1<<15) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set. This bit should be set after init procedure.
57183 #define BMB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN (0x1<<16) // There is bit for power management interfaces. When bit is set then power management interface is enabled. When bit is reset then power management interface will never be set. This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
57243 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_0 0x540c24UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57244 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_1 0x540c28UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57245 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_2 0x540c2cUL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57246 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_3 0x540c30UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57247 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_4 0x540c34UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57248 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_5 0x540c38UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57249 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_6 0x540c3cUL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57250 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_7 0x540c40UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP pending FIFO for each client
57251 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_0 0x540c44UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57252 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_1 0x540c48UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57253 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_2 0x540c4cUL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57254 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_3 0x540c50UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57255 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_4 0x540c54UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57256 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_5 0x540c58UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57257 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_6 0x540c5cUL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57258 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_7 0x540c60UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP pending FIFO for each client
57267 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_0 0x540c84UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57268 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_1 0x540c88UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57269 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_2 0x540c8cUL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57270 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_3 0x540c90UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57271 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_4 0x540c94UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57272 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_5 0x540c98UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57273 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_6 0x540c9cUL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57274 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_7 0x540ca0UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP DSCR pending FIFO for each client
57275 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_0 0x540ca4UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57276 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_1 0x540ca8UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57277 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_2 0x540cacUL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57278 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_3 0x540cb0UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57279 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_4 0x540cb4UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57280 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_5 0x540cb8UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57281 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_6 0x540cbcUL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57282 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_7 0x540cc0UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP DSCR pending FIFO for each client
57291 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_1 0x540ce4UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC INP FIFO for client 1
57292 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_8 0x540ce4UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC INP FIFO for client 8
57293 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_2 0x540ce8UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC INP FIFO for client 2
57294 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_9 0x540ce8UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC INP FIFO for client 9
57299 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_1 0x540cf4UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC out FIFO for client 1
57300 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_8 0x540cf4UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC out FIFO for client 8
57301 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_2 0x540cf8UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC out FIFO for client 2
57302 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_9 0x540cf8UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP SYNC out FIFO for client 9
57307 #define BMB_REG_RC_GNT_PEND_FIFO_EMPTY 0x540d04UL //Access:R DataWidth:0x1 // Debug register. This is empty status of SOP grant FIFO
57308 #define BMB_REG_RC_GNT_PEND_FIFO_FULL 0x540d08UL //Access:R DataWidth:0x1 // Debug register. This is full status of SOP grant FIFO
57359 #define PTU_REG_ATC_INIT_ARRAY 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid bits.
57360 #define PTU_REG_ATC_INIT_DONE 0x560004UL //Access:R DataWidth:0x1 // ATC initalization done.
57369 #define PTU_REG_RO_CFG 0x560060UL //Access:RW DataWidth:0x1 // Releaxed Ordering flag of the PXP read requests issued by the PTU.
57370 #define PTU_REG_NS_CFG 0x560064UL //Access:RW DataWidth:0x1 // No Snoop flag of the PXP read requests issued by the PTU.
57377 #define PTU_REG_INV_TID_V 0x560080UL //Access:RW DataWidth:0x1 // Bit per PF.Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation should take place. When invalidation operation is done, the corresponding bit in inv_tid_done is set
57378 #define PTU_REG_INV_TID_DONE 0x560084UL //Access:RW DataWidth:0x1 // Bit per PF. Indicates that the marked invalidation is done - when read it is also being reset.
57379 #define PTU_REG_INV_HALT_ON_ERR 0x560088UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the block halts in case it gets PTU requests to an address belongs to a range which is currently invalidated; if reset such requests will be sent towards the PXP with the PBLBase and discard flag (in case of PRM).
57380 #define PTU_REG_INV_HALT_ON_REUSE_CNT_ERR 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will halt in case reuse cnt error is found, other wise the erronous request will be sent on with error indication
57386 #define PTU_REG_USE_CRC_INDEX1 0x5600a4UL //Access:RW DataWidth:0x1 // CRC Index1 enable
57387 #define PTU_REG_USE_CRC_INDEX2 0x5600a8UL //Access:RW DataWidth:0x1 // CRC Index2 enable
57394 #define PTU_REG_ATC_REP_MODE 0x5600c4UL //Access:RW DataWidth:0x1 // Replacement mode for the ATC. If de-asserted then low priority request will replace a high priority entry only if there are no low priority entries at all. If set then a high priority with PLRU=0 will be replaced in higher priority than low priority entries with PLRU=1.
57399 #define PTU_REG_PTU_B0_DISABLE 0x5600d8UL //Access:RW DataWidth:0x1 // Disable B0 feature
57400 #define PTU_REG_ATC_OTB_OVERRUN_FIX_CHICKEN_BIT 0x5600dcUL //Access:RW DataWidth:0x1 // Chicken bit for the atc otb overrun fix.
57411 #define PTU_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57413 #define PTU_REG_INT_STS_ATC_TCPL_TO_NOT_PEND (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
57415 #define PTU_REG_INT_STS_ATC_GPA_MULTIPLE_HITS (0x1<<2) // Several hits in the GPA for the same lookup.
57417 #define PTU_REG_INT_STS_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
57419 #define PTU_REG_INT_STS_ATC_TCPL_ERROR (0x1<<4) // Indicates TCPL response with error code set.
57421 #define PTU_REG_INT_STS_ATC_INV_HALT (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
57423 #define PTU_REG_INT_STS_ATC_REUSE_TRANSPEND (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
57425 #define PTU_REG_INT_STS_ATC_IREQ_LESS_THAN_STU (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
57428 #define PTU_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ADDRESS_ERROR .
57430 #define PTU_REG_INT_MASK_ATC_TCPL_TO_NOT_PEND (0x1<<1) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_TCPL_TO_NOT_PEND .
57432 #define PTU_REG_INT_MASK_ATC_GPA_MULTIPLE_HITS (0x1<<2) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_GPA_MULTIPLE_HITS .
57434 #define PTU_REG_INT_MASK_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_RCPL_TO_EMPTY_CNT .
57436 #define PTU_REG_INT_MASK_ATC_TCPL_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_TCPL_ERROR .
57438 #define PTU_REG_INT_MASK_ATC_INV_HALT (0x1<<5) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_INV_HALT .
57440 #define PTU_REG_INT_MASK_ATC_REUSE_TRANSPEND (0x1<<6) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_REUSE_TRANSPEND .
57442 #define PTU_REG_INT_MASK_ATC_IREQ_LESS_THAN_STU (0x1<<7) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_IREQ_LESS_THAN_STU .
57445 #define PTU_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57447 #define PTU_REG_INT_STS_WR_ATC_TCPL_TO_NOT_PEND (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
57449 #define PTU_REG_INT_STS_WR_ATC_GPA_MULTIPLE_HITS (0x1<<2) // Several hits in the GPA for the same lookup.
57451 #define PTU_REG_INT_STS_WR_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
57453 #define PTU_REG_INT_STS_WR_ATC_TCPL_ERROR (0x1<<4) // Indicates TCPL response with error code set.
57455 #define PTU_REG_INT_STS_WR_ATC_INV_HALT (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
57457 #define PTU_REG_INT_STS_WR_ATC_REUSE_TRANSPEND (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
57459 #define PTU_REG_INT_STS_WR_ATC_IREQ_LESS_THAN_STU (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
57462 #define PTU_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57464 #define PTU_REG_INT_STS_CLR_ATC_TCPL_TO_NOT_PEND (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
57466 #define PTU_REG_INT_STS_CLR_ATC_GPA_MULTIPLE_HITS (0x1<<2) // Several hits in the GPA for the same lookup.
57468 #define PTU_REG_INT_STS_CLR_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
57470 #define PTU_REG_INT_STS_CLR_ATC_TCPL_ERROR (0x1<<4) // Indicates TCPL response with error code set.
57472 #define PTU_REG_INT_STS_CLR_ATC_INV_HALT (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
57474 #define PTU_REG_INT_STS_CLR_ATC_REUSE_TRANSPEND (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
57476 #define PTU_REG_INT_STS_CLR_ATC_IREQ_LESS_THAN_STU (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
57479 #define PTU_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
57481 #define PTU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
57483 #define PTU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
57485 #define PTU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
57487 #define PTU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
57489 #define PTU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
57491 #define PTU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
57493 #define PTU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
57495 #define PTU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
57497 #define PTU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
57499 #define PTU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
57501 #define PTU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
57503 #define PTU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
57505 #define PTU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
57507 #define PTU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
57509 #define PTU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
57511 #define PTU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
57513 #define PTU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
57515 #define PTU_REG_MEM_ECC_ENABLE_0 0x560210UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
57516 #define PTU_REG_MEM_ECC_PARITY_ONLY_0 0x560214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
57517 #define PTU_REG_MEM_ECC_ERROR_CORRECTED_0 0x560218UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance ptu.i_ram_spa.i_ecc in module ptu_spa_ram
57520 #define PTU_REG_ATC_1_WAY 0x560404UL //Access:RW DataWidth:0x1 // If set the ATC will use only one way per set.
57523 #define PTU_REG_ATC_WAIT_IF_MISS 0x560410UL //Access:RW DataWidth:0x1 // WaitIfMiss configuration bit.
57524 #define PTU_REG_ATC_WAIT_IF_PENDING 0x560414UL //Access:RW DataWidth:0x1 // WaitTransPending cofiguration bit.
57537 #define PTU_REG_ATC_DISABLE_BYPASS 0x560448UL //Access:RW DataWidth:0x1 // Disables the bypass on the GPA table.
57538 #define PTU_REG_ATC_ISSUE_4_CYCLES 0x56044cUL //Access:RW DataWidth:0x1 // Issue event once in four cycles (instead of 2).
57541 #define PTU_REG_ATC_PIGGYBACKED_TREQ_EN 0x560458UL //Access:RW DataWidth:0x1 // Piggybacked treq issue enabled.
57542 #define PTU_REG_ATC_WAIT_RESP 0x56045cUL //Access:RW DataWidth:0x1 // Allows the ATC to return Wait response.
57551 #define PTU_REG_ATC_CHECK_TAGS 0x560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the available NPH credits is checked before issuing TREQ.
57554 #define PTU_REG_ATC_DIS_MLKP 0x56048cUL //Access:RW DataWidth:0x1 // Disables the main lookup interface.
57555 #define PTU_REG_ATC_DIS_PLKP 0x560490UL //Access:RW DataWidth:0x1 // Disables the pre lookup interface.
57556 #define PTU_REG_ATC_DIS_IREQ 0x560494UL //Access:RW DataWidth:0x1 // Disables the invalidation request interface.
57557 #define PTU_REG_ATC_DIS_TCPL 0x560498UL //Access:RW DataWidth:0x1 // Disables the translation completion interface.
57558 #define PTU_REG_ATC_DIS_SPAD 0x56049cUL //Access:RW DataWidth:0x1 // Disables the spa done interface.
57559 #define PTU_REG_ATC_DIS_RCPL 0x5604a0UL //Access:RW DataWidth:0x1 // Disables the Read Completion interface.
57560 #define PTU_REG_ATC_DIS_LKPRES 0x5604a4UL //Access:RW DataWidth:0x1 // Disables the lookup response interface.
57561 #define PTU_REG_ATC_DIS_TREQ 0x5604a8UL //Access:RW DataWidth:0x1 // Disables the translation request interface.
57562 #define PTU_REG_ATC_DIS_ICPL 0x5604acUL //Access:RW DataWidth:0x1 // Disables the invalidation completion interface.
57564 #define PTU_REG_ATC_SCRUB_DIS 0x5604b4UL //Access:RW DataWidth:0x1 // Disable bit for the scrubbing event of the GPA table.
57572 #define PTU_REG_ATC_STAT_ACTIVE 0x5604d4UL //Access:RW DataWidth:0x1 // When this signal is set the statistics count is on.
57609 #define PTU_REG_ATC_GPA_HASH_EN 0x560568UL //Access:RW DataWidth:0x1 // Enable the use of a hash function for the GPA table; instead of the lsb bits of the address.
57610 #define PTU_REG_ATC_GPA_HASH_CRC 0x56056cUL //Access:RW DataWidth:0x1 // Relevant only if hash_en is set. selects the CRC as hash function for the GPA table; If reset use xor of the FID LS bits with the relevant bits out of the GPA as hash function.
57616 #define PTU_REG_ATC_TCPL_ERR_LOG_VALID 0x560584UL //Access:R DataWidth:0x1 // Indicates valid data at the tcpl error log registers.
57617 #define PTU_REG_ATC_ARRAY_ACCESS_ENABLE 0x560588UL //Access:RW DataWidth:0x1 // Allows GRC access to the GPA and SPA table.
57618 #define PTU_REG_ATC_DURING_FLI 0x56058cUL //Access:R DataWidth:0x1 // Indication that the ATC currently handles FLI.
57619 #define PTU_REG_ATC_DURING_INV 0x560590UL //Access:R DataWidth:0x1 // Indication that the ATC currently handles Any type of invalidation.
57635 #define PTU_REG_ATC_ALLOW_LOW_REP_HIGH 0x5605d0UL //Access:RW DataWidth:0x1 // When set low priority lookup can replace high priority entry; iff the set is full with high prio entries.
57636 #define PTU_REG_ATC_DIS_IREQ_EVENT 0x5605d4UL //Access:RW DataWidth:0x1 // When set Ireq event won't be selected by the ATC arbiter.
57637 #define PTU_REG_ATC_ECO_RESERVED 0x5605d8UL //Access:RW DataWidth:0x1 // For future ECOs implementation.
57667 #define PTU_REG_GP_INV_TID_V 0x560680UL //Access:RW DataWidth:0x1 // Bit per Storm. Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation should take place. When invalidation operation is done, the corresponding bit in inv_tid_done is set
57669 #define PTU_REG_GP_INV_TID_DONE 0x5606a0UL //Access:RW DataWidth:0x1 // Bit per Storm. Indicates that the marked invalidation is done - when read it is also being reset.
57671 #define PTU_REG_GP_INV_HALT_ON_ERR 0x5606c0UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the block halts in case it gets PTU requests to an address belongs to a range which is currently invalidated; if reset such requests will be sent towards the PXP with the PBLBase and discard flag (in case of PRM).
57698 #define CDU_REG_CONTROL0_ENABLE_PXP (0x1<<0) // Enables PXP Accesses.
57700 #define CDU_REG_CONTROL0_ENABLE_INPUTS (0x1<<1) // Enables CDU Inputs -- Must be set for normal operation.
57702 #define CDU_REG_CONTROL0_ENABLE_OUTPUTS (0x1<<2) // Enables CDU Outputs -- Must be set for normal operation.
57704 #define CDU_REG_CONTROL0_L1TT_SP (0x1<<3) // Sets the L1TT Arbiter to Strict Priority; This causes the WB Controller to always have priority over the LD Controller.
57706 #define CDU_REG_CONTROL0_MATT_SP (0x1<<4) // Sets the MATT Arbiter to Strict Priority; This causes the WB Controller to always have priority over the LD Controller.
57708 #define CDU_REG_CONTROL0_PXP_SP (0x1<<5) // Sets the PXP Arbiter to Strict Priority; This causes the WB Controller to always have priority over the LD Controller.
57710 #define CDU_REG_CONTROL0_MASK_PCIE_ERR (0x1<<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connected in E4 A0.
57713 #define CDU_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57715 #define CDU_REG_INT_STS_CCFC_LD_L1_NUM_ERROR (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
57717 #define CDU_REG_INT_STS_TCFC_LD_L1_NUM_ERROR (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
57719 #define CDU_REG_INT_STS_CCFC_WB_L1_NUM_ERROR (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
57721 #define CDU_REG_INT_STS_TCFC_WB_L1_NUM_ERROR (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
57723 #define CDU_REG_INT_STS_CCFC_CVLD_ERROR (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
57725 #define CDU_REG_INT_STS_TCFC_CVLD_ERROR (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
57727 #define CDU_REG_INT_STS_BVALID_ERROR (0x1<<7) // Byte valid Error on PXP Interface. All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
57730 #define CDU_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57732 #define CDU_REG_INT_STS_CLR_CCFC_LD_L1_NUM_ERROR (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
57734 #define CDU_REG_INT_STS_CLR_TCFC_LD_L1_NUM_ERROR (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
57736 #define CDU_REG_INT_STS_CLR_CCFC_WB_L1_NUM_ERROR (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
57738 #define CDU_REG_INT_STS_CLR_TCFC_WB_L1_NUM_ERROR (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
57740 #define CDU_REG_INT_STS_CLR_CCFC_CVLD_ERROR (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
57742 #define CDU_REG_INT_STS_CLR_TCFC_CVLD_ERROR (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
57744 #define CDU_REG_INT_STS_CLR_BVALID_ERROR (0x1<<7) // Byte valid Error on PXP Interface. All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
57747 #define CDU_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57749 #define CDU_REG_INT_STS_WR_CCFC_LD_L1_NUM_ERROR (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
57751 #define CDU_REG_INT_STS_WR_TCFC_LD_L1_NUM_ERROR (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
57753 #define CDU_REG_INT_STS_WR_CCFC_WB_L1_NUM_ERROR (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
57755 #define CDU_REG_INT_STS_WR_TCFC_WB_L1_NUM_ERROR (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
57757 #define CDU_REG_INT_STS_WR_CCFC_CVLD_ERROR (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
57759 #define CDU_REG_INT_STS_WR_TCFC_CVLD_ERROR (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
57761 #define CDU_REG_INT_STS_WR_BVALID_ERROR (0x1<<7) // Byte valid Error on PXP Interface. All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
57764 #define CDU_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.ADDRESS_ERROR .
57766 #define CDU_REG_INT_MASK_CCFC_LD_L1_NUM_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_LD_L1_NUM_ERROR .
57768 #define CDU_REG_INT_MASK_TCFC_LD_L1_NUM_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_LD_L1_NUM_ERROR .
57770 #define CDU_REG_INT_MASK_CCFC_WB_L1_NUM_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_WB_L1_NUM_ERROR .
57772 #define CDU_REG_INT_MASK_TCFC_WB_L1_NUM_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_WB_L1_NUM_ERROR .
57774 #define CDU_REG_INT_MASK_CCFC_CVLD_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_CVLD_ERROR .
57776 #define CDU_REG_INT_MASK_TCFC_CVLD_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_CVLD_ERROR .
57778 #define CDU_REG_INT_MASK_BVALID_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.BVALID_ERROR .
57781 #define CDU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
57783 #define CDU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
57785 #define CDU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
57787 #define CDU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
57789 #define CDU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
57837 #define CDU_REG_CCFC_PXP_CCFC_TPH_VALID (0x1<<16) // TPH Valid bit for CCFC PXP Requests.
57839 #define CDU_REG_CCFC_PXP_CCFC_RO_LD (0x1<<17) // Relaxed ordering bit for CCFC PXP rd_req.
57841 #define CDU_REG_CCFC_PXP_CCFC_RO_WB (0x1<<18) // Relaxed ordering bit for CCFC PXP wr_req.
57843 #define CDU_REG_CCFC_PXP_CCFC_NS_LD (0x1<<19) // No snoop bit for CCFC PXP rd_req.
57845 #define CDU_REG_CCFC_PXP_CCFC_NS_WB (0x1<<20) // No snoop bit for CCFC PXP wr_req.
57854 #define CDU_REG_TCFC_PXP_TCFC_TPH_VALID (0x1<<16) // TPH Valid bit for TCFC PXP Requests.
57856 #define CDU_REG_TCFC_PXP_TCFC_RO_LD (0x1<<17) // Relaxed ordering bit for TCFC working memory PXP rd_req.
57858 #define CDU_REG_TCFC_PXP_TCFC_FL_RO_LD (0x1<<18) // Relaxed ordering bit for TCFC init memory PXP rd_req.
57860 #define CDU_REG_TCFC_PXP_TCFC_RO_WB (0x1<<19) // Relaxed ordering bit for TCFC working memory PXP wr_req.
57862 #define CDU_REG_TCFC_PXP_TCFC_NS_LD (0x1<<20) // No snoop bit for TCFC working memory PXP rd_req.
57864 #define CDU_REG_TCFC_PXP_TCFC_FL_NS_LD (0x1<<21) // No snoop bit for TCFC init memory PXP rd_req.
57866 #define CDU_REG_TCFC_PXP_TCFC_NS_WB (0x1<<22) // No snoop bit for TCFC working memory PXP wr_req.
57871 #define CDU_REG_DEBUG_DISABLE_MERGE (0x1<<0) // Disables Merge Functionality.
57879 #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT_SET (0x1<<23) // Uses pxp_init_ldcredit to update PXP Read Credits.
57885 #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT_SET (0x1<<31) // Uses pxp_init_wbcredit to update PXP Write Credits.
57897 #define CDU_REG_MEMCTRL_WR_RD_N 0x58074cUL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
57952 #define WOL_REG_INT_STS_0 0x600040UL //Access:R DataWidth:0x1 // Multi Field Register.
57953 #define WOL_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
57955 #define WOL_REG_INT_MASK_0 0x600044UL //Access:RW DataWidth:0x1 // Multi Field Register.
57956 #define WOL_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: WOL_REG_INT_STS_0.ADDRESS_ERROR .
57958 #define WOL_REG_INT_STS_WR_0 0x600048UL //Access:WR DataWidth:0x1 // Multi Field Register.
57959 #define WOL_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
57961 #define WOL_REG_INT_STS_CLR_0 0x60004cUL //Access:RC DataWidth:0x1 // Multi Field Register.
57962 #define WOL_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
57974 #define WOL_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
57976 #define WOL_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
57978 #define WOL_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
57980 #define WOL_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
57982 #define WOL_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
57984 #define WOL_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
57986 #define WOL_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
57988 #define WOL_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
57990 #define WOL_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
57992 #define WOL_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
57994 #define WOL_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
57996 #define WOL_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
57998 #define WOL_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
58000 #define WOL_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
58002 #define WOL_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
58004 #define WOL_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
58006 #define WOL_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
58008 #define WOL_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
58010 #define WOL_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
58012 #define WOL_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
58014 #define WOL_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
58016 #define WOL_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
58018 #define WOL_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
58020 #define WOL_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
58024 #define WOL_REG_UPON_MGMT 0x608004UL //Access:RW DataWidth:0x1 // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP. Clear this bit to disable ACPI and TCP SYN matching when the packet is forwarded to MCP.
58027 #define WOL_REG_ACPI_ENABLE 0x608100UL //Access:RW DataWidth:0x1 // This is a per-port register. When this bit is set ACPI packet recognition will be enabled. This bit must not be enabled until after all other ACPI registers were configured.
58044 #define WOL_REG_MPKT_ENABLE 0x608144UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. When this bit is set Magic Packet recognition will be enabled. This bit must not be enabled until after after all other Magic Packet registers are configured.
58047 #define WOL_REG_FORCE_WOL 0x608150UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high transition of this bit forces a wake event.
58050 #define WOL_REG_WAKE_BUFFER_CLEAR 0x608180UL //Access:RW DataWidth:0x1 // Clear the Wake Buffer and Status - a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details registers and allows the wake buffer to be overwritten, thereby re-enabling pattern detection.
58066 #define WOL_REG_HDR_FIFO_EMPTY 0x6081c0UL //Access:R DataWidth:0x1 // WOL header FIFO empty status.
58067 #define WOL_REG_HDR_FIFO_FULL 0x6081c4UL //Access:R DataWidth:0x1 // WOL header FIFO full status.
58068 #define WOL_REG_HDR_FIFO_ERROR 0x6081c8UL //Access:R DataWidth:0x1 // WOL header FIFO error status.
58069 #define BMBN_REG_INT_STS_0 0x610040UL //Access:R DataWidth:0x1 // Multi Field Register.
58070 #define BMBN_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
58072 #define BMBN_REG_INT_MASK_0 0x610044UL //Access:RW DataWidth:0x1 // Multi Field Register.
58073 #define BMBN_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMBN_REG_INT_STS_0.ADDRESS_ERROR .
58075 #define BMBN_REG_INT_STS_WR_0 0x610048UL //Access:WR DataWidth:0x1 // Multi Field Register.
58076 #define BMBN_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
58078 #define BMBN_REG_INT_STS_CLR_0 0x61004cUL //Access:RC DataWidth:0x1 // Multi Field Register.
58079 #define BMBN_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the RF module.
58108 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_L_I (0x1<<2) //
58110 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_L_I (0x1<<3) //
58112 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_R_I (0x1<<4) //
58114 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_R_I (0x1<<5) //
58116 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_SEL_I (0x1<<6) //
58120 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_L_I (0x1<<9) //
58122 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_L_I (0x1<<10) //
58124 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_R_I (0x1<<11) //
58126 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_R_I (0x1<<12) //
58128 #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_SEL_I (0x1<<13) //
58133 #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_PD_I (0x1<<2) //
58135 #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_PD_I (0x1<<3) //
58137 #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_IDDQ_I (0x1<<4) //
58139 #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_IDDQ_I (0x1<<5) //
58141 #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_REFCLK_GATE_I (0x1<<6) //
58143 #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_REFCLK_GATE_I (0x1<<7) //
58146 #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PWR_RST_N (0x1<<0) //
58148 #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PHY_RST_N (0x1<<1) //
58153 #define PHY_PCIE_REG_PHY_RESET_CONTROL_CMU_RESETN_I (0x1<<8) // Firmware must set this bit to 1 after finished configuring PCIe Serdes AHB registers to bring Serdes CMU out of reset
58156 #define PHY_PCIE_REG_PHY_STATUS_PHY0_CMU_OK_O (0x1<<0) //
58158 #define PHY_PCIE_REG_PHY_STATUS_PHY1_CMU_OK_O (0x1<<1) //
58160 #define PHY_PCIE_REG_PHY_STATUS_PHY0_REFCLK_GATE_ACK_O (0x1<<2) //
58162 #define PHY_PCIE_REG_PHY_STATUS_PHY1_REFCLK_GATE_ACK_O (0x1<<3) //
58195 #define PHY_PCIE_REG_HW_INIT_CONFIG_FIRMWARE_EXIST (0x1<<0) // When set to 1, represents FW exists
58197 #define PHY_PCIE_REG_HW_INIT_CONFIG_CMU_RESET_OVR (0x1<<1) // When set to 0, HWInit controls cmu_reset
58199 #define PHY_PCIE_REG_HW_INIT_CONFIG_LN_RESET_OVR (0x1<<2) // When set to 0, HWInit controls ln_reset
58212 #define MS_REG_COMMON_CONTROL_POR_N_I (0x1<<0) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) write 1 to this bit to allow the SerDes to begin normal Operation.
58214 #define MS_REG_COMMON_CONTROL_CMU_RESETN_I (0x1<<1) // Active low. Can be asserted on CMU0 in multiple CMU PHYs to save power if TX clock is being supplied by CMU1 and there are active lanes.
58216 #define MS_REG_COMMON_CONTROL_CMU_PD_I (0x1<<2) // Powerdown control for CMU. Can be asserted when CMU is in reset mode for increased power savings. Cannot be asserted on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so has no affect in power on reset state.
58218 #define MS_REG_COMMON_CONTROL_CMU_IDDQ_I (0x1<<3) // Turn off CMU master bias only. Cannot be asserted if there are any active lanes.
58222 #define MS_REG_COMMON_CONTROL_CMU1_RESETN_I (0x1<<6) // Active low.
58224 #define MS_REG_COMMON_CONTROL_CMU1_PD_I (0x1<<7) // Powerdown control for CMU1.
58226 #define MS_REG_COMMON_CONTROL_CMU1_IDDQ_I (0x1<<8) // Turn off CMU master bias only. Cannot be asserted if there are any active lanes.
58230 #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_L_I (0x1<<11) // Forward reference clock control from refclk_l_o.
58232 #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_R_I (0x1<<12) // Forward reference clock control from refclk_r_o.
58237 #define MS_REG_LN1_CNTL_LN1_IDDQ (0x1<<3) // Lane IDDQ mode enable. Powers down entire PMA lane when asserted.
58243 #define MS_REG_LN1_CNTL_LN1_RSTN_I (0x1<<18) // Active low. lane reset signal.
58248 #define MS_REG_CMU_STATUS_CMU_OK_O (0x1<<0) // Indicates CMU PLL has locked to the reference clock and all output clocks are at the correct frequency.
58250 #define MS_REG_CMU_STATUS_CMU1_OK_O (0x1<<1) // Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency.
58260 #define MS_REG_CLOCK_SELECT_CMU_REFCLK_SEL_I (0x1<<3) // Assert to provide CMU0 with the reference clock selected by CMU1.
58264 #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_SEL_I (0x1<<6) // Assert to provide CMU1 with the reference clock selected by CMU0.
58266 #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_L_I (0x1<<7) // Output enables for bidirectional CML refclk buffers.
58268 #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_R_I (0x1<<8) // Output enables for bidirectional CML refclk buffers.
58271 #define MS_REG_INT_STS 0x6a0180UL //Access:R DataWidth:0x1 // Multi Field Register.
58272 #define MS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58274 #define MS_REG_INT_MASK 0x6a0184UL //Access:RW DataWidth:0x1 // Multi Field Register.
58275 #define MS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MS_REG_INT_STS.ADDRESS_ERROR .
58277 #define MS_REG_INT_STS_WR 0x6a0188UL //Access:WR DataWidth:0x1 // Multi Field Register.
58278 #define MS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58280 #define MS_REG_INT_STS_CLR 0x6a018cUL //Access:RC DataWidth:0x1 // Multi Field Register.
58281 #define MS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58297 #define MS_REG_DBG_FW_TRIGGER_ENABLE 0x6a0250UL //Access:RW DataWidth:0x1 // Debug only: FW trigger is set.
58303 #define AVS_WRAP_REG_AVS_CONTROL_HRESET (0x1<<0) // Asynchronous reset, active high When asserted, it resets all the controller logic, except configuration register. It is internally synchronized with cmn_refclk.
58312 #define AVS_WRAP_REG_AVS_INDICATION_CORE_PWROK (0x1<<0) // This signal is set when the voltage is stable at its target value, typically after a change of selection (either mode or set) When either modesel and setsel changes, the output goes down. Once power reaches the target voltage, it is asserted.
58321 #define AVS_WRAP_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58323 #define AVS_WRAP_REG_INT_STS_AVS_IRQ (0x1<<2) // This interrupt is asserted following the assertion of the AVS block interrupt
58326 #define AVS_WRAP_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: AVS_WRAP_REG_INT_STS.ADDRESS_ERROR .
58328 #define AVS_WRAP_REG_INT_MASK_AVS_IRQ (0x1<<2) // This bit masks, when set, the Interrupt bit: AVS_WRAP_REG_INT_STS.AVS_IRQ .
58331 #define AVS_WRAP_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58333 #define AVS_WRAP_REG_INT_STS_WR_AVS_IRQ (0x1<<2) // This interrupt is asserted following the assertion of the AVS block interrupt
58336 #define AVS_WRAP_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58338 #define AVS_WRAP_REG_INT_STS_CLR_AVS_IRQ (0x1<<2) // This interrupt is asserted following the assertion of the AVS block interrupt
58341 #define AVS_WRAP_REG_PRTY_MASK_FUSE_STAT_CORRUPTED (0x1<<0) // This bit masks, when set, the Parity bit: AVS_WRAP_REG_PRTY_STS.FUSE_STAT_CORRUPTED .
58343 #define AVS_WRAP_REG_PRTY_MASK_MEANSMEM_PERR (0x1<<1) // This bit masks, when set, the Parity bit: AVS_WRAP_REG_PRTY_STS.MEANSMEM_PERR .
58345 #define AVS_WRAP_REG_PRTY_MASK_BINMEM_PERR (0x1<<2) // This bit masks, when set, the Parity bit: AVS_WRAP_REG_PRTY_STS.BINMEM_PERR .
58357 #define LED_REG_CONTROL_OVERRIDE_TRAFFIC (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC And LED_CONTROL_BLINK_TRAFFIC
58359 #define LED_REG_CONTROL_TRAFFIC (0x1<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
58361 #define LED_REG_CONTROL_BLINK_TRAFFIC (0x1<<8) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
58363 #define LED_REG_CONTROL_BLINK_RATE_ENA (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field defined below. If this bit is cleared: Number of main clock cycles the led is ON will be 2^32. Number of main clock cycles the led is ON will be 2^32.
58365 #define LED_REG_CONTROL_ALTERNATING (0x1<<13) // This bit is set to enable the alternating between activity and speed LEDs of the same port The alternating feature is used only with MAC1 and MAC2 modes.
58388 #define LED_REG_INT_STS_0 0x6b8180UL //Access:R DataWidth:0x1 // Multi Field Register.
58389 #define LED_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58391 #define LED_REG_INT_MASK_0 0x6b8184UL //Access:RW DataWidth:0x1 // Multi Field Register.
58392 #define LED_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: LED_REG_INT_STS_0.ADDRESS_ERROR .
58394 #define LED_REG_INT_STS_WR_0 0x6b8188UL //Access:WR DataWidth:0x1 // Multi Field Register.
58395 #define LED_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58397 #define LED_REG_INT_STS_CLR_0 0x6b818cUL //Access:RC DataWidth:0x1 // Multi Field Register.
58398 #define LED_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58401 #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I (0x3<<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the left side 0x2 - Same as 0x0 0x3 - Select inter-macro refrence clock from the right side
58403 #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the right side 0x3 - Same as 0x2
58405 #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the left side 0x3 - Same as 0x2
58409 #define NWS_REG_COMMON_CONTROL_CPU_RESET (0x1<<10) // Controls cpu_reset_i reset signal into the SerDes.
58411 #define NWS_REG_COMMON_CONTROL_POR_N (0x1<<11) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) while the SerDes program and data rams are being written, and the serdes is being configured. This holds the SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the SerDes to begin normal Operation.
58413 #define NWS_REG_COMMON_CONTROL_CM0_RST_N (0x1<<12) // Controls cm0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation.
58415 #define NWS_REG_COMMON_CONTROL_CM1_RST_N (0x1<<13) // Controls cm1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation.
58417 #define NWS_REG_COMMON_CONTROL_LN0_RST_N (0x1<<14) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to begin normal Operation on ln0.
58419 #define NWS_REG_COMMON_CONTROL_LN1_RST_N (0x1<<15) // Controls ln1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to begin normal Operation on ln1.
58421 #define NWS_REG_COMMON_CONTROL_LN2_RST_N (0x1<<16) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to begin normal Operation on ln2.
58423 #define NWS_REG_COMMON_CONTROL_LN3_RST_N (0x1<<17) // Controls ln3_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to begin normal Operation on ln3.
58425 #define NWS_REG_COMMON_CONTROL_CM0_PD (0x3<<18) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
58427 #define NWS_REG_COMMON_CONTROL_CM1_PD (0x3<<20) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
58429 #define NWS_REG_COMMON_CONTROL_LN0_PD (0x3<<22) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
58431 #define NWS_REG_COMMON_CONTROL_LN1_PD (0x3<<24) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
58433 #define NWS_REG_COMMON_CONTROL_LN2_PD (0x3<<26) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
58435 #define NWS_REG_COMMON_CONTROL_LN3_PD (0x3<<28) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
58445 #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I (0x3<<0) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
58447 #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I (0x3<<2) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
58449 #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I (0x3<<4) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
58451 #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I (0x3<<6) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
58454 #define NWS_REG_COMMON_STATUS_ERR_O (0x1<<0) // 0x0 - No error 0x1 - Phy has internal error
58456 #define NWS_REG_COMMON_STATUS_CM0_OK_O (0x1<<1) // 0x1 - Indicates CMU0 PLL has locked to the reference clock and all output clocks are at the correct frequency
58458 #define NWS_REG_COMMON_STATUS_CM1_OK_O (0x1<<2) // 0x1 - Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency
58460 #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm0_rst_n_i and cm0_pd_i[1:0].
58462 #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm1_rst_n_i and cm1_pd_i[1:0].
58464 #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln0_rst_n_i and ln0_pd_i[1:0].
58466 #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln1_rst_n_i and ln1_pd_i[1:0].
58468 #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln2_rst_n_i and ln2_pd_i[1:0].
58470 #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln3_rst_n_i and ln3_pd_i[1:0].
58473 #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
58475 #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
58477 #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
58479 #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE (0x1<<5) // Informs the PHY that the received signal was lost.
58481 #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
58484 #define NWS_REG_LN0_STATUS_LN0_STAT_OK (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
58486 #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - data on the active bits of ln0_rxdata_o is valid.
58488 #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
58490 #define NWS_REG_LN0_STATUS_LN0_STAT_LOS (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins.
58492 #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins.
58495 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
58497 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
58499 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
58501 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
58503 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
58505 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
58507 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
58509 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
58511 #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
58514 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58516 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58518 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58520 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58522 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58524 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58526 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58528 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58530 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58532 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
58534 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
58536 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
58538 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
58540 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58542 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58544 #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
58547 #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
58549 #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
58551 #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
58553 #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE (0x1<<5) // Informs the PHY that the received signal was lost.
58555 #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
58558 #define NWS_REG_LN1_STATUS_LN1_STAT_OK (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
58560 #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - data on the active bits of ln1_rxdata_o is valid.
58562 #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
58564 #define NWS_REG_LN1_STATUS_LN1_STAT_LOS (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins.
58566 #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins.
58569 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
58571 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
58573 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
58575 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
58577 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
58579 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
58581 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
58583 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
58585 #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
58588 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58590 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58592 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58594 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58596 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58598 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58600 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58602 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58604 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58606 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
58608 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
58610 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
58612 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
58614 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58616 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58618 #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
58621 #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
58623 #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
58625 #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
58627 #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE (0x1<<5) // Informs the PHY that the received signal was lost.
58629 #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
58632 #define NWS_REG_LN2_STATUS_LN2_STAT_OK (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
58634 #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - data on the active bits of ln2_rxdata_o is valid.
58636 #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
58638 #define NWS_REG_LN2_STATUS_LN2_STAT_LOS (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins.
58640 #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins.
58643 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
58645 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
58647 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
58649 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
58651 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
58653 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
58655 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
58657 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
58659 #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
58662 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58664 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58666 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58668 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58670 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58672 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58674 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58676 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58678 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58680 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
58682 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
58684 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
58686 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
58688 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58690 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58692 #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
58695 #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
58697 #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
58699 #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
58701 #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE (0x1<<5) // Informs the PHY that the received signal was lost.
58703 #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
58706 #define NWS_REG_LN3_STATUS_LN3_STAT_OK (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
58708 #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - data on the active bits of ln3_rxdata_o is valid.
58710 #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
58712 #define NWS_REG_LN3_STATUS_LN3_STAT_LOS (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins.
58714 #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins.
58717 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
58719 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
58721 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
58723 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
58725 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
58727 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
58729 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
58731 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
58733 #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
58736 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58738 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58740 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58742 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58744 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58746 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58748 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58750 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58752 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
58754 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
58756 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
58758 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
58760 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
58762 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58764 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
58766 #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
58769 #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P0 (0x1<<0) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P0_SIGDET
58771 #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P1 (0x1<<1) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P1_SIGDET
58773 #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P2 (0x1<<2) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P2_SIGDET
58775 #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3 (0x1<<3) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P3_SIGDET
58778 #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P0 (0x1<<0) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P0_PHY_LASI_B
58780 #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P1 (0x1<<1) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P1_PHY_LASI_B
58782 #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P2 (0x1<<2) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P2_PHY_LASI_B
58784 #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3 (0x1<<3) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P3_PHY_LASI_B
58801 #define NWS_REG_DBG_FW_TRIGGER_ENABLE 0x700150UL //Access:RW DataWidth:0x1 // Debug only: FW trigger is set.
58803 #define NWS_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58805 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
58807 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
58809 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
58811 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
58813 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
58815 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
58817 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
58819 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
58821 #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
58824 #define NWS_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.ADDRESS_ERROR .
58826 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_CR2 .
58828 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_KR2 .
58830 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_CR4 .
58832 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_KR4 .
58834 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_GR .
58836 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_CR .
58838 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_KR .
58840 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_10G_KR .
58842 #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_1G_KX .
58845 #define NWS_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58847 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
58849 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
58851 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
58853 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
58855 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
58857 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
58859 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
58861 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
58863 #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
58866 #define NWS_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
58868 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
58870 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
58872 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
58874 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
58876 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
58878 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
58880 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
58882 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
58884 #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
58887 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
58889 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
58891 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
58893 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
58895 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
58897 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
58899 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
58901 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
58903 #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
58906 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_CR2 .
58908 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_KR2 .
58910 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_CR4 .
58912 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_KR4 .
58914 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_GR .
58916 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_CR .
58918 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_KR .
58920 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_10G_KR .
58922 #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_1G_KX .
58925 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
58927 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
58929 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
58931 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
58933 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
58935 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
58937 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
58939 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
58941 #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
58944 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
58946 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
58948 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
58950 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
58952 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
58954 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
58956 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
58958 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
58960 #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
58963 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
58965 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
58967 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
58969 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
58971 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
58973 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
58975 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
58977 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
58979 #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
58982 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_CR2 .
58984 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_KR2 .
58986 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_CR4 .
58988 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_KR4 .
58990 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_GR .
58992 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_CR .
58994 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_KR .
58996 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_10G_KR .
58998 #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_1G_KX .
59001 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
59003 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
59005 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
59007 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
59009 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
59011 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
59013 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
59015 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
59017 #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
59020 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
59022 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
59024 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
59026 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
59028 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
59030 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
59032 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
59034 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
59036 #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
59039 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
59041 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
59043 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
59045 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
59047 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
59049 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
59051 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
59053 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
59055 #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
59058 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_CR2 .
59060 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_KR2 .
59062 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_CR4 .
59064 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_KR4 .
59066 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_GR .
59068 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_CR .
59070 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_KR .
59072 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_10G_KR .
59074 #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_1G_KX .
59077 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
59079 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
59081 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
59083 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
59085 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
59087 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
59089 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
59091 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
59093 #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
59096 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2 (0x1<<1) // Autonegotiation resolved to 50g_cr2
59098 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2 (0x1<<2) // Autonegotiation resolved to 50g_kr2
59100 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4 (0x1<<3) // Autonegotiation resolved to 40g_cr4
59102 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4 (0x1<<4) // Autonegotiation resolved to 40g_kr4
59104 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR (0x1<<5) // Autonegotiation resolved to 25g_gr
59106 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR (0x1<<6) // Autonegotiation resolved to 25g_cr
59108 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR (0x1<<7) // Autonegotiation resolved to 25g_kr
59110 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR (0x1<<8) // Autonegotiation resolved to 10g_kr
59112 #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX (0x1<<9) // Autonegotiation resolved to 1g_kx
59115 #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
59117 #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
59119 #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
59121 #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
59131 #define NWM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
59133 #define NWM_REG_INT_STS_TX_OVERFLOW_0 (0x1<<1) // TX fifo overflow
59135 #define NWM_REG_INT_STS_TX_UNDERFLOW_0 (0x1<<2) // TX fifo underflow
59137 #define NWM_REG_INT_STS_TX_OVERFLOW_1 (0x1<<3) // TX fifo overflow
59139 #define NWM_REG_INT_STS_TX_UNDERFLOW_1 (0x1<<4) // TX fifo underflow
59141 #define NWM_REG_INT_STS_TX_OVERFLOW_2 (0x1<<5) // TX fifo overflow
59143 #define NWM_REG_INT_STS_TX_UNDERFLOW_2 (0x1<<6) // TX fifo underflow
59145 #define NWM_REG_INT_STS_TX_OVERFLOW_3 (0x1<<7) // TX fifo overflow
59147 #define NWM_REG_INT_STS_TX_UNDERFLOW_3 (0x1<<8) // TX fifo underflow
59149 #define NWM_REG_INT_STS_LN0_AT_10M (0x1<<16) // Lane 0 Resolved to 10Mb rate
59151 #define NWM_REG_INT_STS_LN0_AT_100M (0x1<<17) // Lane 0 Resolved to 100Mb rate
59153 #define NWM_REG_INT_STS_LN1_AT_10M (0x1<<18) // Lane 1 Resolved to 10Mb rate
59155 #define NWM_REG_INT_STS_LN1_AT_100M (0x1<<19) // Lane 1 Resolved to 100Mb rate
59157 #define NWM_REG_INT_STS_LN2_AT_10M (0x1<<20) // Lane 2 Resolved to 10Mb rate
59159 #define NWM_REG_INT_STS_LN2_AT_100M (0x1<<21) // Lane 2 Resolved to 100Mb rate
59161 #define NWM_REG_INT_STS_LN3_AT_10M (0x1<<22) // Lane 3 Resolved to 10Mb rate
59163 #define NWM_REG_INT_STS_LN3_AT_100M (0x1<<23) // Lane 3 Resolved to 100Mb rate
59166 #define NWM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.ADDRESS_ERROR .
59168 #define NWM_REG_INT_MASK_TX_OVERFLOW_0 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_0 .
59170 #define NWM_REG_INT_MASK_TX_UNDERFLOW_0 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_0 .
59172 #define NWM_REG_INT_MASK_TX_OVERFLOW_1 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_1 .
59174 #define NWM_REG_INT_MASK_TX_UNDERFLOW_1 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_1 .
59176 #define NWM_REG_INT_MASK_TX_OVERFLOW_2 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_2 .
59178 #define NWM_REG_INT_MASK_TX_UNDERFLOW_2 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_2 .
59180 #define NWM_REG_INT_MASK_TX_OVERFLOW_3 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_3 .
59182 #define NWM_REG_INT_MASK_TX_UNDERFLOW_3 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_3 .
59184 #define NWM_REG_INT_MASK_LN0_AT_10M (0x1<<16) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN0_AT_10M .
59186 #define NWM_REG_INT_MASK_LN0_AT_100M (0x1<<17) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN0_AT_100M .
59188 #define NWM_REG_INT_MASK_LN1_AT_10M (0x1<<18) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN1_AT_10M .
59190 #define NWM_REG_INT_MASK_LN1_AT_100M (0x1<<19) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN1_AT_100M .
59192 #define NWM_REG_INT_MASK_LN2_AT_10M (0x1<<20) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN2_AT_10M .
59194 #define NWM_REG_INT_MASK_LN2_AT_100M (0x1<<21) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN2_AT_100M .
59196 #define NWM_REG_INT_MASK_LN3_AT_10M (0x1<<22) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN3_AT_10M .
59198 #define NWM_REG_INT_MASK_LN3_AT_100M (0x1<<23) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN3_AT_100M .
59201 #define NWM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
59203 #define NWM_REG_INT_STS_WR_TX_OVERFLOW_0 (0x1<<1) // TX fifo overflow
59205 #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_0 (0x1<<2) // TX fifo underflow
59207 #define NWM_REG_INT_STS_WR_TX_OVERFLOW_1 (0x1<<3) // TX fifo overflow
59209 #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_1 (0x1<<4) // TX fifo underflow
59211 #define NWM_REG_INT_STS_WR_TX_OVERFLOW_2 (0x1<<5) // TX fifo overflow
59213 #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_2 (0x1<<6) // TX fifo underflow
59215 #define NWM_REG_INT_STS_WR_TX_OVERFLOW_3 (0x1<<7) // TX fifo overflow
59217 #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_3 (0x1<<8) // TX fifo underflow
59219 #define NWM_REG_INT_STS_WR_LN0_AT_10M (0x1<<16) // Lane 0 Resolved to 10Mb rate
59221 #define NWM_REG_INT_STS_WR_LN0_AT_100M (0x1<<17) // Lane 0 Resolved to 100Mb rate
59223 #define NWM_REG_INT_STS_WR_LN1_AT_10M (0x1<<18) // Lane 1 Resolved to 10Mb rate
59225 #define NWM_REG_INT_STS_WR_LN1_AT_100M (0x1<<19) // Lane 1 Resolved to 100Mb rate
59227 #define NWM_REG_INT_STS_WR_LN2_AT_10M (0x1<<20) // Lane 2 Resolved to 10Mb rate
59229 #define NWM_REG_INT_STS_WR_LN2_AT_100M (0x1<<21) // Lane 2 Resolved to 100Mb rate
59231 #define NWM_REG_INT_STS_WR_LN3_AT_10M (0x1<<22) // Lane 3 Resolved to 10Mb rate
59233 #define NWM_REG_INT_STS_WR_LN3_AT_100M (0x1<<23) // Lane 3 Resolved to 100Mb rate
59236 #define NWM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
59238 #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_0 (0x1<<1) // TX fifo overflow
59240 #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_0 (0x1<<2) // TX fifo underflow
59242 #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_1 (0x1<<3) // TX fifo overflow
59244 #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_1 (0x1<<4) // TX fifo underflow
59246 #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_2 (0x1<<5) // TX fifo overflow
59248 #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_2 (0x1<<6) // TX fifo underflow
59250 #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_3 (0x1<<7) // TX fifo overflow
59252 #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_3 (0x1<<8) // TX fifo underflow
59254 #define NWM_REG_INT_STS_CLR_LN0_AT_10M (0x1<<16) // Lane 0 Resolved to 10Mb rate
59256 #define NWM_REG_INT_STS_CLR_LN0_AT_100M (0x1<<17) // Lane 0 Resolved to 100Mb rate
59258 #define NWM_REG_INT_STS_CLR_LN1_AT_10M (0x1<<18) // Lane 1 Resolved to 10Mb rate
59260 #define NWM_REG_INT_STS_CLR_LN1_AT_100M (0x1<<19) // Lane 1 Resolved to 100Mb rate
59262 #define NWM_REG_INT_STS_CLR_LN2_AT_10M (0x1<<20) // Lane 2 Resolved to 10Mb rate
59264 #define NWM_REG_INT_STS_CLR_LN2_AT_100M (0x1<<21) // Lane 2 Resolved to 100Mb rate
59266 #define NWM_REG_INT_STS_CLR_LN3_AT_10M (0x1<<22) // Lane 3 Resolved to 10Mb rate
59268 #define NWM_REG_INT_STS_CLR_LN3_AT_100M (0x1<<23) // Lane 3 Resolved to 100Mb rate
59277 #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LOCAL_FAULT (0x1<<6) // Live Local Fault Indicator
59279 #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_REMOTE_FAULT (0x1<<7) // Live Remote Fault Indicator
59281 #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_INTERRUPT (0x1<<8) // Live Link Interrupt Indicator
59283 #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LPI_RECEIVED (0x1<<9) // Live LPI Received Indicator
59285 #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_HI_BER (0x1<<10) // Live Hi BER Indicator
59287 #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_STATUS (0x1<<11) // Live Link Status Indicator
59289 #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_BLOCK_LOCK (0x1<<12) // Live block lock Indicator
59293 #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LOCAL_FAULT (0x1<<6) // Live Local Fault Indicator
59295 #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_REMOTE_FAULT (0x1<<7) // Live Remote Fault Indicator
59297 #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_INTERRUPT (0x1<<8) // Live Link Interrupt Indicator
59299 #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LPI_RECEIVED (0x1<<9) // Live LPI Received Indicator
59301 #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_HI_BER (0x1<<10) // Live Hi BER Indicator
59303 #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_STATUS (0x1<<11) // Live Link Status Indicator
59305 #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_BLOCK_LOCK (0x1<<12) // Live block lock Indicator
59309 #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LOCAL_FAULT (0x1<<6) // Live Local Fault Indicator
59311 #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_REMOTE_FAULT (0x1<<7) // Live Remote Fault Indicator
59313 #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_INTERRUPT (0x1<<8) // Live Link Interrupt Indicator
59315 #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LPI_RECEIVED (0x1<<9) // Live LPI Received Indicator
59317 #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_HI_BER (0x1<<10) // Live Hi BER Indicator
59319 #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_STATUS (0x1<<11) // Live Link Status Indicator
59321 #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_BLOCK_LOCK (0x1<<12) // Live block lock Indicator
59325 #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LOCAL_FAULT (0x1<<6) // Live Local Fault Indicator
59327 #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_REMOTE_FAULT (0x1<<7) // Live Remote Fault Indicator
59329 #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_INTERRUPT (0x1<<8) // Live Link Interrupt Indicator
59331 #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LPI_RECEIVED (0x1<<9) // Live LPI Received Indicator
59333 #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_HI_BER (0x1<<10) // Live Hi BER Indicator
59335 #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_STATUS (0x1<<11) // Live Link Status Indicator
59337 #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_BLOCK_LOCK (0x1<<12) // Live block lock Indicator
59340 #define NWM_REG_PCS_SELECT_SG0_ENA (0x1<<0) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to 0, the 10/25/40/50Geth PCS is enabled.
59342 #define NWM_REG_PCS_SELECT_SG1_ENA (0x1<<1) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to 0, the 10/25/50Geth PCS is enabled.
59344 #define NWM_REG_PCS_SELECT_SG2_ENA (0x1<<2) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to 0, the 10/25Geth PCS is enabled.
59346 #define NWM_REG_PCS_SELECT_SG3_ENA (0x1<<3) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to 0, the 10/25Geth PCS is enabled.
59349 #define NWM_REG_SGMII_PCS_STATUS_SG0_RX_SYNC (0x1<<0) // Set to '1' to indicate successul link synchronization.
59351 #define NWM_REG_SGMII_PCS_STATUS_SG0_AN_DONE (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
59353 #define NWM_REG_SGMII_PCS_STATUS_SG1_RX_SYNC (0x1<<2) // Set to '1' to indicate successul link synchronization.
59355 #define NWM_REG_SGMII_PCS_STATUS_SG1_AN_DONE (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
59357 #define NWM_REG_SGMII_PCS_STATUS_SG2_RX_SYNC (0x1<<4) // Set to '1' to indicate successul link synchronization.
59359 #define NWM_REG_SGMII_PCS_STATUS_SG2_AN_DONE (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
59361 #define NWM_REG_SGMII_PCS_STATUS_SG3_RX_SYNC (0x1<<6) // Set to '1' to indicate successul link synchronization.
59363 #define NWM_REG_SGMII_PCS_STATUS_SG3_AN_DONE (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
59381 #define NWM_REG_XPCS_LPI_FAST_WAKE_CONTROL 0x800058UL //Access:RW DataWidth:0x1 // Controls the fast-wake mode for the LPI transmit and receive functions. When set to 1, the link is to use fast wake mechanisim. When set to 0, the link is to use the optional deep sleep mechanism for each direction. Should default to 1 and may only be cleared if the optional deep sleep mode is supported.
59387 #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_MODE (0x1<<5) // A variable reflecting the state of the LPI receive function.
59391 #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_ACTIVE (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
59398 #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_MODE (0x1<<5) // A variable reflecting the state of the LPI receive function.
59402 #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_ACTIVE (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
59409 #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_MODE (0x1<<5) // A variable reflecting the state of the LPI receive function.
59413 #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_ACTIVE (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
59420 #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_MODE (0x1<<5) // A variable reflecting the state of the LPI receive function.
59424 #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_ACTIVE (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
59427 #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_TX_LPI_ACTIVE (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
59429 #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_TXMODE_QUIET (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
59431 #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_RX_LPI_ACTIVE (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
59433 #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_RXMODE_QUIET (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
59436 #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_TX_LPI_ACTIVE (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
59438 #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_TXMODE_QUIET (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
59440 #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_RX_LPI_ACTIVE (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
59442 #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_RXMODE_QUIET (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
59445 #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_TX_LPI_ACTIVE (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
59447 #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_TXMODE_QUIET (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
59449 #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_RX_LPI_ACTIVE (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
59451 #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_RXMODE_QUIET (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
59454 #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_TX_LPI_ACTIVE (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
59456 #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_TXMODE_QUIET (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
59458 #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_RX_LPI_ACTIVE (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
59460 #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_RXMODE_QUIET (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
59479 #define NWM_REG_TX_FAULT_MAC0_TX_LOC_FAULT (0x1<<0) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
59481 #define NWM_REG_TX_FAULT_MAC0_TX_REM_FAULT (0x1<<1) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
59483 #define NWM_REG_TX_FAULT_MAC0_TX_LI_FAULT (0x1<<2) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
59485 #define NWM_REG_TX_FAULT_MAC1_TX_LOC_FAULT (0x1<<3) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
59487 #define NWM_REG_TX_FAULT_MAC1_TX_REM_FAULT (0x1<<4) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
59489 #define NWM_REG_TX_FAULT_MAC1_TX_LI_FAULT (0x1<<5) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
59491 #define NWM_REG_TX_FAULT_MAC2_TX_LOC_FAULT (0x1<<6) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
59493 #define NWM_REG_TX_FAULT_MAC2_TX_REM_FAULT (0x1<<7) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
59495 #define NWM_REG_TX_FAULT_MAC2_TX_LI_FAULT (0x1<<8) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
59497 #define NWM_REG_TX_FAULT_MAC3_TX_LOC_FAULT (0x1<<9) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
59499 #define NWM_REG_TX_FAULT_MAC3_TX_REM_FAULT (0x1<<10) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
59501 #define NWM_REG_TX_FAULT_MAC3_TX_LI_FAULT (0x1<<11) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
59538 #define NWM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
59540 #define NWM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
59542 #define NWM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
59544 #define NWM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
59546 #define NWM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
59548 #define NWM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
59550 #define NWM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
59552 #define NWM_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
59554 #define NWM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
59556 #define NWM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
59558 #define NWM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
59560 #define NWM_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
59562 #define NWM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
59564 #define NWM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
59566 #define NWM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
59568 #define NWM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
59570 #define NWM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
59572 #define NWM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
59574 #define NWM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
59576 #define NWM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
59578 #define NWM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
59580 #define NWM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
59582 #define NWM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
59584 #define NWM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
59586 #define NWM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
59588 #define NWM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
59590 #define NWM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
59592 #define NWM_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
59594 #define NWM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
59596 #define NWM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
59598 #define NWM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
59601 #define NWM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
59603 #define NWM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
59605 #define NWM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
59607 #define NWM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
59609 #define NWM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
59611 #define NWM_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
59613 #define NWM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
59615 #define NWM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
59617 #define NWM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
59619 #define NWM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
59621 #define NWM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
59623 #define NWM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
59625 #define NWM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
59627 #define NWM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
59629 #define NWM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
59631 #define NWM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
59633 #define NWM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
59635 #define NWM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
59637 #define NWM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
59639 #define NWM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
59641 #define NWM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
59643 #define NWM_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
59645 #define NWM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
59647 #define NWM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
59649 #define NWM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
59651 #define NWM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
59653 #define NWM_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
59655 #define NWM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
59657 #define NWM_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
59659 #define NWM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
59661 #define NWM_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
59664 #define NWM_REG_PRTY_MASK_H_2_MEM052_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM052_I_MEM_PRTY .
59666 #define NWM_REG_PRTY_MASK_H_2_MEM056_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM056_I_MEM_PRTY .
59668 #define NWM_REG_PRTY_MASK_H_2_MEM066_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM066_I_MEM_PRTY .
59670 #define NWM_REG_PRTY_MASK_H_2_MEM068_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM068_I_MEM_PRTY .
59672 #define NWM_REG_PRTY_MASK_H_2_MEM070_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM070_I_MEM_PRTY .
59674 #define NWM_REG_PRTY_MASK_H_2_MEM072_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM072_I_MEM_PRTY .
59676 #define NWM_REG_PRTY_MASK_H_2_MEM065_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM065_I_MEM_PRTY .
59678 #define NWM_REG_PRTY_MASK_H_2_MEM067_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM067_I_MEM_PRTY .
59680 #define NWM_REG_PRTY_MASK_H_2_MEM069_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM069_I_MEM_PRTY .
59682 #define NWM_REG_PRTY_MASK_H_2_MEM071_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM071_I_MEM_PRTY .
59717 #define PBF_REG_INIT 0xd80000UL //Access:RW DataWidth:0x1 // Init bit. When set the initial credits are copied to the credit registers (except the port credits). Should be set and then reset after the configuration of the block has ended.
59719 #define PBF_REG_IF_ENABLE_REG_DORQ_IF_ENABLE (0x1<<0) // Enables the dorq interface.
59721 #define PBF_REG_IF_ENABLE_REG_YSEM_IF_ENABLE (0x1<<1) // Enables the ysem interface.
59723 #define PBF_REG_IF_ENABLE_REG_PTU_REQ_IF_ENABLE (0x1<<2) // Enables the ptu_req interface.
59725 #define PBF_REG_IF_ENABLE_REG_PCM_IF_ENABLE (0x1<<3) // Enables the pcm interface.
59727 #define PBF_REG_IF_ENABLE_REG_TDIF_CMD_IF_ENABLE (0x1<<4) // Enables the tdif_cmd interface.
59729 #define PBF_REG_IF_ENABLE_REG_TDIF_RDATA_IF_ENABLE (0x1<<5) // Enables the tdif_rdata interface.
59731 #define PBF_REG_IF_ENABLE_REG_PSEM_IF_ENABLE (0x1<<6) // Enables the psem interface.
59733 #define PBF_REG_IF_ENABLE_REG_QM_LINE_CREDIT_IF_ENABLE (0x1<<7) // Enables the qm_line_credit interface.
59735 #define PBF_REG_IF_ENABLE_REG_TM_REQ_IF_ENABLE (0x1<<8) // Enables the tm_req interface.
59737 #define PBF_REG_IF_ENABLE_REG_PXP_INT_WRREQ_IF_ENABLE (0x1<<9) // Enables the pxp_int_wrreq interface.
59739 #define PBF_REG_IF_ENABLE_REG_BTB_DATA_IF_ENABLE (0x1<<10) // Enables the btb_data interface.
59741 #define PBF_REG_IF_ENABLE_REG_BTB_RLS_IF_ENABLE (0x1<<11) // Enables the btb_rls interface.
59743 #define PBF_REG_IF_ENABLE_REG_TCM_IF_ENABLE (0x1<<12) // Enables the tcm interface.
59745 #define PBF_REG_IF_ENABLE_REG_MCM_IF_ENABLE (0x1<<13) // Enables the mcm interface.
59747 #define PBF_REG_IF_ENABLE_REG_UCM_IF_ENABLE (0x1<<14) // Enables the ucm interface.
59749 #define PBF_REG_IF_ENABLE_REG_XCM_IF_ENABLE (0x1<<15) // Enables the xcm interface.
59751 #define PBF_REG_IF_ENABLE_REG_YCM_IF_ENABLE (0x1<<16) // Enables the ycm interface.
59753 #define PBF_REG_IF_ENABLE_REG_TCM_DONE_IF_ENABLE (0x1<<17) // Enables the tcm_done interface.
59755 #define PBF_REG_IF_ENABLE_REG_MCM_DONE_IF_ENABLE (0x1<<18) // Enables the mcm_done interface.
59757 #define PBF_REG_IF_ENABLE_REG_UCM_DONE_IF_ENABLE (0x1<<19) // Enables the ucm_done interface.
59759 #define PBF_REG_IF_ENABLE_REG_YCM_DONE_IF_ENABLE (0x1<<20) // Enables the ycm_done interface.
59779 #define PBF_REG_MEMCTRL_WR_RD_N 0xd80100UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
59783 #define PBF_REG_INT_STS 0xd80180UL //Access:R DataWidth:0x1 // Multi Field Register.
59784 #define PBF_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
59786 #define PBF_REG_INT_MASK 0xd80184UL //Access:RW DataWidth:0x1 // Multi Field Register.
59787 #define PBF_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PBF_REG_INT_STS.ADDRESS_ERROR .
59789 #define PBF_REG_INT_STS_WR 0xd80188UL //Access:WR DataWidth:0x1 // Multi Field Register.
59790 #define PBF_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
59792 #define PBF_REG_INT_STS_CLR 0xd8018cUL //Access:RC DataWidth:0x1 // Multi Field Register.
59793 #define PBF_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
59795 #define PBF_REG_PRTY_MASK 0xd80194UL //Access:RW DataWidth:0x1 // Multi Field Register.
59796 #define PBF_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS.DATAPATH_REGISTERS .
59799 #define PBF_REG_PRTY_MASK_H_0_MEM041_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM041_I_ECC_RF_INT .
59801 #define PBF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM042_I_ECC_RF_INT .
59803 #define PBF_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT .
59805 #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
59807 #define PBF_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT .
59809 #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT .
59811 #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM009_I_ECC_1_RF_INT .
59813 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_0_RF_INT .
59815 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_1_RF_INT .
59817 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_2_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_2_RF_INT .
59819 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_3_RF_INT (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_3_RF_INT .
59821 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_4_RF_INT (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_4_RF_INT .
59823 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_5_RF_INT (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_5_RF_INT .
59825 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_6_RF_INT (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_6_RF_INT .
59827 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_7_RF_INT (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_7_RF_INT .
59829 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_8_RF_INT (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_8_RF_INT .
59831 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_9_RF_INT (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_9_RF_INT .
59833 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_10_RF_INT (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_10_RF_INT .
59835 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_11_RF_INT (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_11_RF_INT .
59837 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_12_RF_INT (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_12_RF_INT .
59839 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_13_RF_INT (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_13_RF_INT .
59841 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_14_RF_INT (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_14_RF_INT .
59843 #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_15_RF_INT (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_15_RF_INT .
59845 #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
59847 #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
59849 #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
59851 #define PBF_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
59853 #define PBF_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
59855 #define PBF_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
59857 #define PBF_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
59859 #define PBF_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
59862 #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
59864 #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
59866 #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
59868 #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
59870 #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
59872 #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
59874 #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
59876 #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
59878 #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
59880 #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
59882 #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
59884 #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
59886 #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
59888 #define PBF_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
59890 #define PBF_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
59892 #define PBF_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
59894 #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
59896 #define PBF_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
59898 #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
59900 #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
59902 #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
59904 #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
59906 #define PBF_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
59908 #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
59910 #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
59912 #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
59914 #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
59919 #define PBF_REG_MEM_ECC_ENABLE_0_MEM041_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even
59921 #define PBF_REG_MEM_ECC_ENABLE_0_MEM042_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd
59923 #define PBF_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database
59925 #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer
59927 #define PBF_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database
59929 #define PBF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN (0x1<<5) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
59931 #define PBF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN (0x1<<6) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
59933 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN (0x1<<7) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer
59935 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN (0x1<<8) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer
59937 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_2_EN (0x1<<9) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer
59939 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_3_EN (0x1<<10) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer
59941 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_4_EN (0x1<<11) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer
59943 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_5_EN (0x1<<12) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer
59945 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_6_EN (0x1<<13) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer
59947 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_7_EN (0x1<<14) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer
59949 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_8_EN (0x1<<15) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer
59951 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_9_EN (0x1<<16) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer
59953 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_10_EN (0x1<<17) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer
59955 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_11_EN (0x1<<18) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer
59957 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_12_EN (0x1<<19) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer
59959 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_13_EN (0x1<<20) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer
59961 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_14_EN (0x1<<21) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer
59963 #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_15_EN (0x1<<22) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer
59966 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM041_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even
59968 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM042_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd
59970 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database
59972 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer
59974 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database
59976 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY (0x1<<5) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
59978 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY (0x1<<6) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
59980 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY (0x1<<7) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer
59982 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY (0x1<<8) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer
59984 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_2_PRTY (0x1<<9) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer
59986 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_3_PRTY (0x1<<10) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer
59988 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_4_PRTY (0x1<<11) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer
59990 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_5_PRTY (0x1<<12) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer
59992 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_6_PRTY (0x1<<13) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer
59994 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_7_PRTY (0x1<<14) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer
59996 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_8_PRTY (0x1<<15) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer
59998 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_9_PRTY (0x1<<16) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer
60000 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_10_PRTY (0x1<<17) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer
60002 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_11_PRTY (0x1<<18) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer
60004 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_12_PRTY (0x1<<19) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer
60006 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_13_PRTY (0x1<<20) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer
60008 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_14_PRTY (0x1<<21) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer
60010 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_15_PRTY (0x1<<22) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer
60013 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM041_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even
60015 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM042_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd
60017 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database
60019 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer
60021 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database
60023 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1
60025 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_1_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1
60027 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer
60029 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer
60031 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_2_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer
60033 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_3_CORRECT (0x1<<10) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer
60035 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_4_CORRECT (0x1<<11) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer
60037 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_5_CORRECT (0x1<<12) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer
60039 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_6_CORRECT (0x1<<13) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer
60041 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_7_CORRECT (0x1<<14) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer
60043 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_8_CORRECT (0x1<<15) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer
60045 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_9_CORRECT (0x1<<16) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer
60047 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_10_CORRECT (0x1<<17) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer
60049 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_11_CORRECT (0x1<<18) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer
60051 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_12_CORRECT (0x1<<19) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer
60053 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_13_CORRECT (0x1<<20) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer
60055 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_14_CORRECT (0x1<<21) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer
60057 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_15_CORRECT (0x1<<22) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer
60121 #define PBF_REG_NGE_COMP_VER 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compare the value of nge version to 2'b00. 0 - don't compare 1 - compare.
60154 #define PBF_REG_DROP_PKT_UPON_ERR 0xd80644UL //Access:RW DataWidth:0x1 // if set, packets with a PCIE/DIF error will be sent to BTB with a drop indication, otherwise will be sent with an error indication.
60164 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ0 0xd806a8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 0 (after ending the current command in process).
60173 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_VOQ0 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60175 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ0 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60182 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ1 0xd806e8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 1 (after ending the current command in process).
60191 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_VOQ1 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60193 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ1 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60200 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ2 0xd80728UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 2 (after ending the current command in process).
60209 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_VOQ2 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60211 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ2 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60218 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ3 0xd80768UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 3 (after ending the current command in process).
60227 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_VOQ3 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60229 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ3 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60236 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ4 0xd807a8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 4 (after ending the current command in process).
60245 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_VOQ4 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60247 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ4 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60254 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ5 0xd807e8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 5 (after ending the current command in process).
60263 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_VOQ5 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60265 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ5 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60272 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ6 0xd80828UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 6 (after ending the current command in process).
60281 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_VOQ6 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60283 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ6 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60290 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ7 0xd80868UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 7 (after ending the current command in process).
60299 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_VOQ7 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60301 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ7 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60308 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ8 0xd808a8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 8 (after ending the current command in process).
60317 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_VOQ8 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60319 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ8 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60326 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ9 0xd808e8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 9 (after ending the current command in process).
60335 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_VOQ9 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60337 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ9 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60344 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ10 0xd80928UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 10 (after ending the current command in process).
60353 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_VOQ10 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60355 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ10 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60362 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ11 0xd80968UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 11 (after ending the current command in process).
60371 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_VOQ11 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60373 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ11 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60380 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ12 0xd809a8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 12 (after ending the current command in process).
60389 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_VOQ12 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60391 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ12 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60398 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ13 0xd809e8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 13 (after ending the current command in process).
60407 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_VOQ13 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60409 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ13 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60416 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ14 0xd80a28UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 14 (after ending the current command in process).
60425 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_VOQ14 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60427 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ14 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60434 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ15 0xd80a68UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 15 (after ending the current command in process).
60443 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_VOQ15 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60445 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ15 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60452 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ16 0xd80aa8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 16 (after ending the current command in process).
60461 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_VOQ16 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60463 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ16 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60470 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ17 0xd80ae8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 17 (after ending the current command in process).
60479 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_VOQ17 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60481 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ17 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60488 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ18 0xd80b28UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 18 (after ending the current command in process).
60497 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_VOQ18 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60499 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ18 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60506 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ19 0xd80b68UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 19 (after ending the current command in process).
60515 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_VOQ19 (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60517 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ19 (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
60524 #define PBF_PB1_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60526 #define PBF_PB1_REG_INT_STS_EOP_ERROR (0x1<<1) // EOP check error.
60528 #define PBF_PB1_REG_INT_STS_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
60530 #define PBF_PB1_REG_INT_STS_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
60532 #define PBF_PB1_REG_INT_STS_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
60534 #define PBF_PB1_REG_INT_STS_TH_EXEC_ERROR (0x1<<5) //
60536 #define PBF_PB1_REG_INT_STS_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
60538 #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
60540 #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
60543 #define PBF_PB1_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
60545 #define PBF_PB1_REG_INT_MASK_EOP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
60547 #define PBF_PB1_REG_INT_MASK_IFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
60549 #define PBF_PB1_REG_INT_MASK_PFIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
60551 #define PBF_PB1_REG_INT_MASK_DB_BUF_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
60553 #define PBF_PB1_REG_INT_MASK_TH_EXEC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
60555 #define PBF_PB1_REG_INT_MASK_TQ_ERROR_WR (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
60557 #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_TH (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
60559 #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_IH (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
60562 #define PBF_PB1_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60564 #define PBF_PB1_REG_INT_STS_WR_EOP_ERROR (0x1<<1) // EOP check error.
60566 #define PBF_PB1_REG_INT_STS_WR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
60568 #define PBF_PB1_REG_INT_STS_WR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
60570 #define PBF_PB1_REG_INT_STS_WR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
60572 #define PBF_PB1_REG_INT_STS_WR_TH_EXEC_ERROR (0x1<<5) //
60574 #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
60576 #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
60578 #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
60581 #define PBF_PB1_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60583 #define PBF_PB1_REG_INT_STS_CLR_EOP_ERROR (0x1<<1) // EOP check error.
60585 #define PBF_PB1_REG_INT_STS_CLR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
60587 #define PBF_PB1_REG_INT_STS_CLR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
60589 #define PBF_PB1_REG_INT_STS_CLR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
60591 #define PBF_PB1_REG_INT_STS_CLR_TH_EXEC_ERROR (0x1<<5) //
60593 #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
60595 #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
60597 #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
60599 #define PBF_PB1_REG_PRTY_MASK 0xda0054UL //Access:RW DataWidth:0x1 // Multi Field Register.
60600 #define PBF_PB1_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
60603 #define PBF_PB1_REG_CONTROL_BYTE_ORDER_SWITCH (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
60605 #define PBF_PB1_REG_CONTROL_DB_IGNORE_ERROR (0x1<<1) // Indicates if to ignore the input error indication.
60607 #define PBF_PB1_REG_CONTROL_DONT_PASS_ERROR (0x1<<2) // Masks error on output of pb.
60609 #define PBF_PB1_REG_CONTROL_EOP_CHECK_DISABLE (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
60611 #define PBF_PB1_REG_CONTROL_CRC_COMPARE_DISABLE (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
60613 #define PBF_PB1_REG_CONTROL_EN_INPUTS (0x1<<5) // Enable inputs.
60615 #define PBF_PB1_REG_CONTROL_DISABLE_PB (0x1<<6) // Debug only: Disable PB.
60619 #define PBF_PB1_REG_CONTROL_RELAX_TH (0x1<<11) // Dbug only.
60621 #define PBF_PB1_REG_CONTROL_DUMMY_ERR_ALLOW (0x1<<12) // Dummy ingress error allow. When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
60635 #define PBF_PB1_REG_DB_EMPTY 0xda0500UL //Access:R DataWidth:0x1 // Data Buffer empty status.
60636 #define PBF_PB1_REG_DB_FULL 0xda0504UL //Access:R DataWidth:0x1 // Data Buffer full status.
60637 #define PBF_PB1_REG_TQ_EMPTY 0xda0508UL //Access:R DataWidth:0x1 // Task Queue empty status.
60638 #define PBF_PB1_REG_TQ_FULL 0xda050cUL //Access:R DataWidth:0x1 // Task Queue full status.
60639 #define PBF_PB1_REG_IFIFO_EMPTY 0xda0510UL //Access:R DataWidth:0x1 // Instruction FIFO empty status.
60640 #define PBF_PB1_REG_IFIFO_FULL 0xda0514UL //Access:R DataWidth:0x1 // Instruction FIFO full status.
60641 #define PBF_PB1_REG_PFIFO_EMPTY 0xda0518UL //Access:R DataWidth:0x1 // Parameter FIFO empty status.
60642 #define PBF_PB1_REG_PFIFO_FULL 0xda051cUL //Access:R DataWidth:0x1 // Parameter FIFO full status.
60643 #define PBF_PB1_REG_TQ_TH_EMPTY 0xda0520UL //Access:R DataWidth:0x1 // Task Queue empty status for task handler.
60664 #define PBF_PB2_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60666 #define PBF_PB2_REG_INT_STS_EOP_ERROR (0x1<<1) // EOP check error.
60668 #define PBF_PB2_REG_INT_STS_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
60670 #define PBF_PB2_REG_INT_STS_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
60672 #define PBF_PB2_REG_INT_STS_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
60674 #define PBF_PB2_REG_INT_STS_TH_EXEC_ERROR (0x1<<5) //
60676 #define PBF_PB2_REG_INT_STS_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
60678 #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
60680 #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
60683 #define PBF_PB2_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
60685 #define PBF_PB2_REG_INT_MASK_EOP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
60687 #define PBF_PB2_REG_INT_MASK_IFIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
60689 #define PBF_PB2_REG_INT_MASK_PFIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
60691 #define PBF_PB2_REG_INT_MASK_DB_BUF_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
60693 #define PBF_PB2_REG_INT_MASK_TH_EXEC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
60695 #define PBF_PB2_REG_INT_MASK_TQ_ERROR_WR (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
60697 #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_TH (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
60699 #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_IH (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
60702 #define PBF_PB2_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60704 #define PBF_PB2_REG_INT_STS_WR_EOP_ERROR (0x1<<1) // EOP check error.
60706 #define PBF_PB2_REG_INT_STS_WR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
60708 #define PBF_PB2_REG_INT_STS_WR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
60710 #define PBF_PB2_REG_INT_STS_WR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
60712 #define PBF_PB2_REG_INT_STS_WR_TH_EXEC_ERROR (0x1<<5) //
60714 #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
60716 #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
60718 #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
60721 #define PBF_PB2_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60723 #define PBF_PB2_REG_INT_STS_CLR_EOP_ERROR (0x1<<1) // EOP check error.
60725 #define PBF_PB2_REG_INT_STS_CLR_IFIFO_ERROR (0x1<<2) // Instruction FIFO error.
60727 #define PBF_PB2_REG_INT_STS_CLR_PFIFO_ERROR (0x1<<3) // Parameter FIFO error.
60729 #define PBF_PB2_REG_INT_STS_CLR_DB_BUF_ERROR (0x1<<4) // DB FIFO error.
60731 #define PBF_PB2_REG_INT_STS_CLR_TH_EXEC_ERROR (0x1<<5) //
60733 #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_WR (0x1<<6) // TQ write overflow.
60735 #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_TH (0x1<<7) // TQ read underflow by task handler.
60737 #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_IH (0x1<<8) // TQ read underflow by instruction handler.
60739 #define PBF_PB2_REG_PRTY_MASK 0xda4054UL //Access:RW DataWidth:0x1 // Multi Field Register.
60740 #define PBF_PB2_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
60743 #define PBF_PB2_REG_CONTROL_BYTE_ORDER_SWITCH (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
60745 #define PBF_PB2_REG_CONTROL_DB_IGNORE_ERROR (0x1<<1) // Indicates if to ignore the input error indication.
60747 #define PBF_PB2_REG_CONTROL_DONT_PASS_ERROR (0x1<<2) // Masks error on output of pb.
60749 #define PBF_PB2_REG_CONTROL_EOP_CHECK_DISABLE (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
60751 #define PBF_PB2_REG_CONTROL_CRC_COMPARE_DISABLE (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
60753 #define PBF_PB2_REG_CONTROL_EN_INPUTS (0x1<<5) // Enable inputs.
60755 #define PBF_PB2_REG_CONTROL_DISABLE_PB (0x1<<6) // Debug only: Disable PB.
60759 #define PBF_PB2_REG_CONTROL_RELAX_TH (0x1<<11) // Dbug only.
60761 #define PBF_PB2_REG_CONTROL_DUMMY_ERR_ALLOW (0x1<<12) // Dummy ingress error allow. When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
60775 #define PBF_PB2_REG_DB_EMPTY 0xda4500UL //Access:R DataWidth:0x1 // Data Buffer empty status.
60776 #define PBF_PB2_REG_DB_FULL 0xda4504UL //Access:R DataWidth:0x1 // Data Buffer full status.
60777 #define PBF_PB2_REG_TQ_EMPTY 0xda4508UL //Access:R DataWidth:0x1 // Task Queue empty status.
60778 #define PBF_PB2_REG_TQ_FULL 0xda450cUL //Access:R DataWidth:0x1 // Task Queue full status.
60779 #define PBF_PB2_REG_IFIFO_EMPTY 0xda4510UL //Access:R DataWidth:0x1 // Instruction FIFO empty status.
60780 #define PBF_PB2_REG_IFIFO_FULL 0xda4514UL //Access:R DataWidth:0x1 // Instruction FIFO full status.
60781 #define PBF_PB2_REG_PFIFO_EMPTY 0xda4518UL //Access:R DataWidth:0x1 // Parameter FIFO empty status.
60782 #define PBF_PB2_REG_PFIFO_FULL 0xda451cUL //Access:R DataWidth:0x1 // Parameter FIFO full status.
60783 #define PBF_PB2_REG_TQ_TH_EMPTY 0xda4520UL //Access:R DataWidth:0x1 // Task Queue empty status for task handler.
60805 #define BTB_REG_START_EN 0xdb000cUL //Access:RW DataWidth:0x1 // This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.
60807 #define BTB_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60809 #define BTB_REG_INT_STS_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
60811 #define BTB_REG_INT_STS_0_RC_PKT0_LEN_ERROR (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
60813 #define BTB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
60815 #define BTB_REG_INT_STS_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
60817 #define BTB_REG_INT_STS_0_RC_PKT1_LEN_ERROR (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
60819 #define BTB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
60821 #define BTB_REG_INT_STS_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
60823 #define BTB_REG_INT_STS_0_RC_PKT2_LEN_ERROR (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
60825 #define BTB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
60827 #define BTB_REG_INT_STS_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
60829 #define BTB_REG_INT_STS_0_RC_PKT3_LEN_ERROR (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
60831 #define BTB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
60833 #define BTB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
60835 #define BTB_REG_INT_STS_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
60837 #define BTB_REG_INT_STS_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
60840 #define BTB_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.ADDRESS_ERROR .
60842 #define BTB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
60844 #define BTB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_LEN_ERROR .
60846 #define BTB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
60848 #define BTB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
60850 #define BTB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_LEN_ERROR .
60852 #define BTB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
60854 #define BTB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
60856 #define BTB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_LEN_ERROR .
60858 #define BTB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
60860 #define BTB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
60862 #define BTB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_LEN_ERROR .
60864 #define BTB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
60866 #define BTB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
60868 #define BTB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
60870 #define BTB_REG_INT_MASK_0_LL_BLK_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.LL_BLK_ERROR .
60873 #define BTB_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60875 #define BTB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
60877 #define BTB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
60879 #define BTB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
60881 #define BTB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
60883 #define BTB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
60885 #define BTB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
60887 #define BTB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
60889 #define BTB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
60891 #define BTB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
60893 #define BTB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
60895 #define BTB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
60897 #define BTB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
60899 #define BTB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
60901 #define BTB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
60903 #define BTB_REG_INT_STS_WR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
60906 #define BTB_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
60908 #define BTB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
60910 #define BTB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
60912 #define BTB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
60914 #define BTB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
60916 #define BTB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
60918 #define BTB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
60920 #define BTB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
60922 #define BTB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
60924 #define BTB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
60926 #define BTB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
60928 #define BTB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
60930 #define BTB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
60932 #define BTB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR (0x1<<21) // SOP descriptor request from empty TC or port.
60934 #define BTB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
60936 #define BTB_REG_INT_STS_CLR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
60939 #define BTB_REG_INT_STS_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
60941 #define BTB_REG_INT_STS_1_FC_ALM_CALC_ERROR (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
60943 #define BTB_REG_INT_STS_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
60945 #define BTB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
60947 #define BTB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR (0x1<<5) // LEN FIFO error in write client 0.
60949 #define BTB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR (0x1<<6) // EOP FIFO error in write client 0.
60951 #define BTB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
60953 #define BTB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
60955 #define BTB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
60957 #define BTB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
60959 #define BTB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
60961 #define BTB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
60963 #define BTB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
60965 #define BTB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
60967 #define BTB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
60969 #define BTB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
60972 #define BTB_REG_INT_MASK_1_LL_ARB_CALC_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
60974 #define BTB_REG_INT_MASK_1_FC_ALM_CALC_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.FC_ALM_CALC_ERROR .
60976 #define BTB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
60978 #define BTB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
60980 #define BTB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LEN_FIFO_ERROR .
60982 #define BTB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_EOP_FIFO_ERROR .
60984 #define BTB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
60986 #define BTB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
60988 #define BTB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
60990 #define BTB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
60992 #define BTB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
60994 #define BTB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
60996 #define BTB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
60998 #define BTB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
61000 #define BTB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
61002 #define BTB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
61005 #define BTB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
61007 #define BTB_REG_INT_STS_WR_1_FC_ALM_CALC_ERROR (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
61009 #define BTB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
61011 #define BTB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
61013 #define BTB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR (0x1<<5) // LEN FIFO error in write client 0.
61015 #define BTB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR (0x1<<6) // EOP FIFO error in write client 0.
61017 #define BTB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
61019 #define BTB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
61021 #define BTB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
61023 #define BTB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
61025 #define BTB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
61027 #define BTB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
61029 #define BTB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
61031 #define BTB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
61033 #define BTB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
61035 #define BTB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
61038 #define BTB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block.
61040 #define BTB_REG_INT_STS_CLR_1_FC_ALM_CALC_ERROR (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
61042 #define BTB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR (0x1<<3) // Input FIFO error in write client 0.
61044 #define BTB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR (0x1<<4) // SOP FIFO error in write client 0.
61046 #define BTB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR (0x1<<5) // LEN FIFO error in write client 0.
61048 #define BTB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR (0x1<<6) // EOP FIFO error in write client 0.
61050 #define BTB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR (0x1<<7) // Queue FIFO error in write client 0.
61052 #define BTB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR (0x1<<8) // Free ointer FIFO error in write client 0.
61054 #define BTB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR (0x1<<9) // Next pointer FIFO error in write client 0.
61056 #define BTB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR (0x1<<10) // Start FIFO error in write client 0.
61058 #define BTB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR (0x1<<11) // Second descriptor FIFO error in write client 0.
61060 #define BTB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR (0x1<<12) // Packet available FIFO error in write client 0.
61062 #define BTB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR (0x1<<14) // Notify FIFO error in write client 0.
61064 #define BTB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR (0x1<<15) // LL req error in write client 0.
61066 #define BTB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
61068 #define BTB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
61071 #define BTB_REG_INT_STS_2_WC_DUP_UPD_DATA_FIFO_ERROR (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61073 #define BTB_REG_INT_STS_2_WC_DUP_RSP_DSCR_FIFO_ERROR (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61075 #define BTB_REG_INT_STS_2_WC_DUP_UPD_POINT_FIFO_ERROR (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61077 #define BTB_REG_INT_STS_2_WC_DUP_PKT_AVAIL_FIFO_ERROR (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61080 #define BTB_REG_INT_MASK_2_WC_DUP_UPD_DATA_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_UPD_DATA_FIFO_ERROR .
61082 #define BTB_REG_INT_MASK_2_WC_DUP_RSP_DSCR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_RSP_DSCR_FIFO_ERROR .
61084 #define BTB_REG_INT_MASK_2_WC_DUP_UPD_POINT_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_UPD_POINT_FIFO_ERROR .
61086 #define BTB_REG_INT_MASK_2_WC_DUP_PKT_AVAIL_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_PKT_AVAIL_FIFO_ERROR .
61089 #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_DATA_FIFO_ERROR (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61091 #define BTB_REG_INT_STS_WR_2_WC_DUP_RSP_DSCR_FIFO_ERROR (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61093 #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_POINT_FIFO_ERROR (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61095 #define BTB_REG_INT_STS_WR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61098 #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_DATA_FIFO_ERROR (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61100 #define BTB_REG_INT_STS_CLR_2_WC_DUP_RSP_DSCR_FIFO_ERROR (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61102 #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_POINT_FIFO_ERROR (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61104 #define BTB_REG_INT_STS_CLR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61107 #define BTB_REG_INT_STS_3_WC_DUP_PKT_AVAIL_CNT_ERROR (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61109 #define BTB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61111 #define BTB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61113 #define BTB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61115 #define BTB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61117 #define BTB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61119 #define BTB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61121 #define BTB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61123 #define BTB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61125 #define BTB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61127 #define BTB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61129 #define BTB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61131 #define BTB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61133 #define BTB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61135 #define BTB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61137 #define BTB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61139 #define BTB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61141 #define BTB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61143 #define BTB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61145 #define BTB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61147 #define BTB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61149 #define BTB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61151 #define BTB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61153 #define BTB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61155 #define BTB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61157 #define BTB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61159 #define BTB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61161 #define BTB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61163 #define BTB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61165 #define BTB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61167 #define BTB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61169 #define BTB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61172 #define BTB_REG_INT_MASK_3_WC_DUP_PKT_AVAIL_CNT_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.WC_DUP_PKT_AVAIL_CNT_ERROR .
61174 #define BTB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
61176 #define BTB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
61178 #define BTB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
61180 #define BTB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
61182 #define BTB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
61184 #define BTB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
61186 #define BTB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
61188 #define BTB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
61190 #define BTB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
61192 #define BTB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
61194 #define BTB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
61196 #define BTB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
61198 #define BTB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
61200 #define BTB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
61202 #define BTB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
61204 #define BTB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
61206 #define BTB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
61208 #define BTB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
61210 #define BTB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
61212 #define BTB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
61214 #define BTB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
61216 #define BTB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
61218 #define BTB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
61220 #define BTB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
61222 #define BTB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
61224 #define BTB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
61226 #define BTB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
61228 #define BTB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
61230 #define BTB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
61232 #define BTB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
61234 #define BTB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
61237 #define BTB_REG_INT_STS_WR_3_WC_DUP_PKT_AVAIL_CNT_ERROR (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61239 #define BTB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61241 #define BTB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61243 #define BTB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61245 #define BTB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61247 #define BTB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61249 #define BTB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61251 #define BTB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61253 #define BTB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61255 #define BTB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61257 #define BTB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61259 #define BTB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61261 #define BTB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61263 #define BTB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61265 #define BTB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61267 #define BTB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61269 #define BTB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61271 #define BTB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61273 #define BTB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61275 #define BTB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61277 #define BTB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61279 #define BTB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61281 #define BTB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61283 #define BTB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61285 #define BTB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61287 #define BTB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61289 #define BTB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61291 #define BTB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61293 #define BTB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61295 #define BTB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61297 #define BTB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61299 #define BTB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61302 #define BTB_REG_INT_STS_CLR_3_WC_DUP_PKT_AVAIL_CNT_ERROR (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
61304 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61306 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61308 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61310 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61312 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61314 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61316 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61318 #define BTB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
61320 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61322 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61324 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61326 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61328 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61330 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61332 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61334 #define BTB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
61336 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61338 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61340 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61342 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61344 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61346 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61348 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61350 #define BTB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
61352 #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61354 #define BTB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61356 #define BTB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61358 #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61360 #define BTB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61362 #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61364 #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61367 #define BTB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61369 #define BTB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
61371 #define BTB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
61373 #define BTB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
61375 #define BTB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client NIG main port 0 release fifo error
61377 #define BTB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client NIG LB port 0 release fifo error
61379 #define BTB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client NIG main port 1 release fifo error
61381 #define BTB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client NIG LB port 1 release fifo error
61383 #define BTB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client NIG main port 2 release fifo error
61385 #define BTB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // Read packet client NIG main port 2 release fifo error
61387 #define BTB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // Read packet client NIG main port 2 release fifo error
61389 #define BTB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // Read packet client NIG main port 2 release fifo error
61391 #define BTB_REG_INT_STS_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
61393 #define BTB_REG_INT_STS_4_RC_PKT4_LEN_ERROR (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
61395 #define BTB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
61397 #define BTB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61399 #define BTB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61401 #define BTB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61403 #define BTB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61405 #define BTB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61407 #define BTB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61409 #define BTB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61411 #define BTB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61414 #define BTB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
61416 #define BTB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
61418 #define BTB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
61420 #define BTB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
61422 #define BTB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
61424 #define BTB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
61426 #define BTB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
61428 #define BTB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
61430 #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
61432 #define BTB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT5_RLS_FIFO_ERROR .
61434 #define BTB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT6_RLS_FIFO_ERROR .
61436 #define BTB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT7_RLS_FIFO_ERROR .
61438 #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
61440 #define BTB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_LEN_ERROR .
61442 #define BTB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
61444 #define BTB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
61446 #define BTB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
61448 #define BTB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
61450 #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
61452 #define BTB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
61454 #define BTB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
61456 #define BTB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
61458 #define BTB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
61461 #define BTB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61463 #define BTB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
61465 #define BTB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
61467 #define BTB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
61469 #define BTB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client NIG main port 0 release fifo error
61471 #define BTB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client NIG LB port 0 release fifo error
61473 #define BTB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client NIG main port 1 release fifo error
61475 #define BTB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client NIG LB port 1 release fifo error
61477 #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client NIG main port 2 release fifo error
61479 #define BTB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // Read packet client NIG main port 2 release fifo error
61481 #define BTB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // Read packet client NIG main port 2 release fifo error
61483 #define BTB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // Read packet client NIG main port 2 release fifo error
61485 #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
61487 #define BTB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
61489 #define BTB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
61491 #define BTB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61493 #define BTB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61495 #define BTB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61497 #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61499 #define BTB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61501 #define BTB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61503 #define BTB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61505 #define BTB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61508 #define BTB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61510 #define BTB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR (0x1<<4) // Read SOP client queue FIFO error.
61512 #define BTB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR (0x1<<7) // Link list arbiter release FIFO error.
61514 #define BTB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR (0x1<<8) // Link list arbiter prefetch FIFO error.
61516 #define BTB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR (0x1<<9) // Read packet client NIG main port 0 release fifo error
61518 #define BTB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR (0x1<<10) // Read packet client NIG LB port 0 release fifo error
61520 #define BTB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR (0x1<<11) // Read packet client NIG main port 1 release fifo error
61522 #define BTB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR (0x1<<12) // Read packet client NIG LB port 1 release fifo error
61524 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR (0x1<<13) // Read packet client NIG main port 2 release fifo error
61526 #define BTB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR (0x1<<14) // Read packet client NIG main port 2 release fifo error
61528 #define BTB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR (0x1<<15) // Read packet client NIG main port 2 release fifo error
61530 #define BTB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR (0x1<<16) // Read packet client NIG main port 2 release fifo error
61532 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
61534 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
61536 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
61538 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61540 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61542 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61544 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61546 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61548 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61550 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61552 #define BTB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
61555 #define BTB_REG_INT_STS_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
61557 #define BTB_REG_INT_STS_5_RC_PKT5_LEN_ERROR (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
61559 #define BTB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
61561 #define BTB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // Read packet client5 side info FIFO error
61563 #define BTB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // Read packet client5 request FIFO error
61565 #define BTB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // Read packet client5 block FIFO error
61567 #define BTB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // Read packet client5 releases left FIFO error
61569 #define BTB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet client5 start pointer FIFO error
61571 #define BTB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet client5 second pointer FIFO
61573 #define BTB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // Read packet client5 response FIFO error
61575 #define BTB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // Read packet client5 descriptor FIFO error
61577 #define BTB_REG_INT_STS_5_RC_PKT6_RLS_ERROR (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
61579 #define BTB_REG_INT_STS_5_RC_PKT6_LEN_ERROR (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
61581 #define BTB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
61583 #define BTB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // Read packet client6 side info FIFO error
61585 #define BTB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // Read packet client6 request FIFO error
61587 #define BTB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // Read packet client6 block FIFO error
61589 #define BTB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // Read packet client6 releases left FIFO error
61591 #define BTB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // Read packet client6 start pointer FIFO error
61593 #define BTB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // Read packet client6 second pointer FIFO
61595 #define BTB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // Read packet client6 response FIFO error
61597 #define BTB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // Read packet client6 descriptor FIFO error
61599 #define BTB_REG_INT_STS_5_RC_PKT7_RLS_ERROR (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
61601 #define BTB_REG_INT_STS_5_RC_PKT7_LEN_ERROR (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
61603 #define BTB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
61605 #define BTB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // Read packet client7 side info FIFO error
61607 #define BTB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // Read packet client7 request FIFO error
61609 #define BTB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // Read packet client7 block FIFO error
61611 #define BTB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client7 releases left FIFO error
61613 #define BTB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client7 start pointer FIFO error
61615 #define BTB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client7 second pointer FIFO
61617 #define BTB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // Read packet client7 response FIFO error
61620 #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
61622 #define BTB_REG_INT_MASK_5_RC_PKT5_LEN_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_LEN_ERROR .
61624 #define BTB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_PROTOCOL_ERROR .
61626 #define BTB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_SIDE_FIFO_ERROR .
61628 #define BTB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_REQ_FIFO_ERROR .
61630 #define BTB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_BLK_FIFO_ERROR .
61632 #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RLS_LEFT_FIFO_ERROR .
61634 #define BTB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_STRT_PTR_FIFO_ERROR .
61636 #define BTB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_SECOND_PTR_FIFO_ERROR .
61638 #define BTB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RSP_FIFO_ERROR .
61640 #define BTB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_DSCR_FIFO_ERROR .
61642 #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RLS_ERROR .
61644 #define BTB_REG_INT_MASK_5_RC_PKT6_LEN_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_LEN_ERROR .
61646 #define BTB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_PROTOCOL_ERROR .
61648 #define BTB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_SIDE_FIFO_ERROR .
61650 #define BTB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_REQ_FIFO_ERROR .
61652 #define BTB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_BLK_FIFO_ERROR .
61654 #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RLS_LEFT_FIFO_ERROR .
61656 #define BTB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_STRT_PTR_FIFO_ERROR .
61658 #define BTB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_SECOND_PTR_FIFO_ERROR .
61660 #define BTB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RSP_FIFO_ERROR .
61662 #define BTB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_DSCR_FIFO_ERROR .
61664 #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RLS_ERROR .
61666 #define BTB_REG_INT_MASK_5_RC_PKT7_LEN_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_LEN_ERROR .
61668 #define BTB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_PROTOCOL_ERROR .
61670 #define BTB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_SIDE_FIFO_ERROR .
61672 #define BTB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_REQ_FIFO_ERROR .
61674 #define BTB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_BLK_FIFO_ERROR .
61676 #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RLS_LEFT_FIFO_ERROR .
61678 #define BTB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_STRT_PTR_FIFO_ERROR .
61680 #define BTB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_SECOND_PTR_FIFO_ERROR .
61682 #define BTB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RSP_FIFO_ERROR .
61685 #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
61687 #define BTB_REG_INT_STS_WR_5_RC_PKT5_LEN_ERROR (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
61689 #define BTB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
61691 #define BTB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // Read packet client5 side info FIFO error
61693 #define BTB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // Read packet client5 request FIFO error
61695 #define BTB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // Read packet client5 block FIFO error
61697 #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // Read packet client5 releases left FIFO error
61699 #define BTB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet client5 start pointer FIFO error
61701 #define BTB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet client5 second pointer FIFO
61703 #define BTB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // Read packet client5 response FIFO error
61705 #define BTB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // Read packet client5 descriptor FIFO error
61707 #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
61709 #define BTB_REG_INT_STS_WR_5_RC_PKT6_LEN_ERROR (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
61711 #define BTB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
61713 #define BTB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // Read packet client6 side info FIFO error
61715 #define BTB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // Read packet client6 request FIFO error
61717 #define BTB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // Read packet client6 block FIFO error
61719 #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // Read packet client6 releases left FIFO error
61721 #define BTB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // Read packet client6 start pointer FIFO error
61723 #define BTB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // Read packet client6 second pointer FIFO
61725 #define BTB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // Read packet client6 response FIFO error
61727 #define BTB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // Read packet client6 descriptor FIFO error
61729 #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
61731 #define BTB_REG_INT_STS_WR_5_RC_PKT7_LEN_ERROR (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
61733 #define BTB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
61735 #define BTB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // Read packet client7 side info FIFO error
61737 #define BTB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // Read packet client7 request FIFO error
61739 #define BTB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // Read packet client7 block FIFO error
61741 #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client7 releases left FIFO error
61743 #define BTB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client7 start pointer FIFO error
61745 #define BTB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client7 second pointer FIFO
61747 #define BTB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // Read packet client7 response FIFO error
61750 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
61752 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_LEN_ERROR (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
61754 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
61756 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR (0x1<<3) // Read packet client5 side info FIFO error
61758 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR (0x1<<4) // Read packet client5 request FIFO error
61760 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR (0x1<<5) // Read packet client5 block FIFO error
61762 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR (0x1<<6) // Read packet client5 releases left FIFO error
61764 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR (0x1<<7) // Read packet client5 start pointer FIFO error
61766 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR (0x1<<8) // Read packet client5 second pointer FIFO
61768 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR (0x1<<9) // Read packet client5 response FIFO error
61770 #define BTB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR (0x1<<10) // Read packet client5 descriptor FIFO error
61772 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
61774 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_LEN_ERROR (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
61776 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
61778 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR (0x1<<14) // Read packet client6 side info FIFO error
61780 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR (0x1<<15) // Read packet client6 request FIFO error
61782 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR (0x1<<16) // Read packet client6 block FIFO error
61784 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR (0x1<<17) // Read packet client6 releases left FIFO error
61786 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR (0x1<<18) // Read packet client6 start pointer FIFO error
61788 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR (0x1<<19) // Read packet client6 second pointer FIFO
61790 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR (0x1<<20) // Read packet client6 response FIFO error
61792 #define BTB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR (0x1<<21) // Read packet client6 descriptor FIFO error
61794 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
61796 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_LEN_ERROR (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
61798 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
61800 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR (0x1<<25) // Read packet client7 side info FIFO error
61802 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR (0x1<<26) // Read packet client7 request FIFO error
61804 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR (0x1<<27) // Read packet client7 block FIFO error
61806 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR (0x1<<28) // Read packet client7 releases left FIFO error
61808 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR (0x1<<29) // Read packet client7 start pointer FIFO error
61810 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR (0x1<<30) // Read packet client7 second pointer FIFO
61812 #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR (0x1<<31) // Read packet client7 response FIFO error
61814 #define BTB_REG_INT_STS_6 0xdb0150UL //Access:R DataWidth:0x1 // Multi Field Register.
61815 #define BTB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
61817 #define BTB_REG_INT_MASK_6 0xdb0154UL //Access:RW DataWidth:0x1 // Multi Field Register.
61818 #define BTB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
61820 #define BTB_REG_INT_STS_WR_6 0xdb0158UL //Access:WR DataWidth:0x1 // Multi Field Register.
61821 #define BTB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
61823 #define BTB_REG_INT_STS_CLR_6 0xdb015cUL //Access:RC DataWidth:0x1 // Multi Field Register.
61824 #define BTB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR (0x1<<0) // Packet available SYNC FIFO error
61826 #define BTB_REG_INT_STS_8 0xdb0184UL //Access:R DataWidth:0x1 // Multi Field Register.
61827 #define BTB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
61829 #define BTB_REG_INT_MASK_8 0xdb0188UL //Access:RW DataWidth:0x1 // Multi Field Register.
61830 #define BTB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
61832 #define BTB_REG_INT_STS_WR_8 0xdb018cUL //Access:WR DataWidth:0x1 // Multi Field Register.
61833 #define BTB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
61835 #define BTB_REG_INT_STS_CLR_8 0xdb0190UL //Access:RC DataWidth:0x1 // Multi Field Register.
61836 #define BTB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
61838 #define BTB_REG_INT_STS_9 0xdb019cUL //Access:R DataWidth:0x1 // Multi Field Register.
61839 #define BTB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
61841 #define BTB_REG_INT_MASK_9 0xdb01a0UL //Access:RW DataWidth:0x1 // Multi Field Register.
61842 #define BTB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
61844 #define BTB_REG_INT_STS_WR_9 0xdb01a4UL //Access:WR DataWidth:0x1 // Multi Field Register.
61845 #define BTB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
61847 #define BTB_REG_INT_STS_CLR_9 0xdb01a8UL //Access:RC DataWidth:0x1 // Multi Field Register.
61848 #define BTB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
61851 #define BTB_REG_INT_STS_10_WC0_SYNC_FIFO_PUSH_ERROR (0x1<<30) // WC input SYNC FIFO error
61854 #define BTB_REG_INT_MASK_10_WC0_SYNC_FIFO_PUSH_ERROR (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_10.WC0_SYNC_FIFO_PUSH_ERROR .
61857 #define BTB_REG_INT_STS_WR_10_WC0_SYNC_FIFO_PUSH_ERROR (0x1<<30) // WC input SYNC FIFO error
61860 #define BTB_REG_INT_STS_CLR_10_WC0_SYNC_FIFO_PUSH_ERROR (0x1<<30) // WC input SYNC FIFO error
61863 #define BTB_REG_INT_STS_11_RLS_SYNC_FIFO_PUSH_ERROR (0x1<<8) // Release SYNC FIFO error
61865 #define BTB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // Read packet client7 descriptor FIFO error
61868 #define BTB_REG_INT_MASK_11_RLS_SYNC_FIFO_PUSH_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_11.RLS_SYNC_FIFO_PUSH_ERROR .
61870 #define BTB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_11.RC_PKT7_DSCR_FIFO_ERROR .
61873 #define BTB_REG_INT_STS_WR_11_RLS_SYNC_FIFO_PUSH_ERROR (0x1<<8) // Release SYNC FIFO error
61875 #define BTB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // Read packet client7 descriptor FIFO error
61878 #define BTB_REG_INT_STS_CLR_11_RLS_SYNC_FIFO_PUSH_ERROR (0x1<<8) // Release SYNC FIFO error
61880 #define BTB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR (0x1<<18) // Read packet client7 descriptor FIFO error
61883 #define BTB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
61885 #define BTB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
61887 #define BTB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
61889 #define BTB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
61891 #define BTB_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<4) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.DATAPATH_REGISTERS .
61894 #define BTB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
61896 #define BTB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
61898 #define BTB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
61900 #define BTB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
61902 #define BTB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
61904 #define BTB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
61906 #define BTB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
61908 #define BTB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
61910 #define BTB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
61912 #define BTB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
61914 #define BTB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<10) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
61916 #define BTB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<11) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
61918 #define BTB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<12) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
61920 #define BTB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<13) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
61922 #define BTB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT (0x1<<14) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
61924 #define BTB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT (0x1<<15) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
61926 #define BTB_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
61928 #define BTB_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
61930 #define BTB_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
61932 #define BTB_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
61934 #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
61936 #define BTB_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
61938 #define BTB_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
61940 #define BTB_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
61942 #define BTB_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
61944 #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
61946 #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
61948 #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
61950 #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
61952 #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
61954 #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
61957 #define BTB_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61959 #define BTB_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61961 #define BTB_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN (0x1<<2) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61963 #define BTB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN (0x1<<3) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61965 #define BTB_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN (0x1<<4) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61967 #define BTB_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61969 #define BTB_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN (0x1<<6) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61971 #define BTB_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN (0x1<<7) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61973 #define BTB_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61975 #define BTB_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN (0x1<<9) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61977 #define BTB_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<10) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61979 #define BTB_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<11) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61981 #define BTB_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<12) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61983 #define BTB_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<13) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61985 #define BTB_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN (0x1<<14) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61987 #define BTB_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN (0x1<<15) // Enable ECC for memory ecc instance btb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61991 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61993 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61995 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY (0x1<<2) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61997 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY (0x1<<3) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
61999 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY (0x1<<4) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62001 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62003 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY (0x1<<6) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62005 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY (0x1<<7) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62007 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62009 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY (0x1<<9) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62011 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<10) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62013 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<11) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62015 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<12) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62017 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<13) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62019 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY (0x1<<14) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62021 #define BTB_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY (0x1<<15) // Set parity only for memory ecc instance btb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62025 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[0].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62027 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[1].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62029 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[2].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62031 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[3].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62033 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[4].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62035 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[5].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62037 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[6].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62039 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[7].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62041 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[8].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62043 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[9].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62045 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<10) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[10].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62047 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<11) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[11].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62049 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<12) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[12].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62051 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<13) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[13].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62053 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT (0x1<<14) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[14].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62055 #define BTB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT (0x1<<15) // Record if a correctable error occurred on memory ecc instance btb.BB_BANK_BB_GEN_FOR[15].BB_BANK_BB_GEN_IF.i_bb_bank.i_ecc in module btb_bb_bank_bigbear
62101 #define BTB_REG_WC_NO_DEAD_CYCLES_EN 0xdb0854UL //Access:RW DataWidth:0x1 // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles .B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset
62102 #define BTB_REG_WC_HIGHEST_PRI_EN 0xdb0858UL //Access:RW DataWidth:0x1 // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset
62103 #define BTB_REG_WC_LL_HIGH_PRI 0xdb085cUL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
62104 #define BTB_REG_BR_FIX_HIGH_PRI_COLLISION 0xdb0860UL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w.
62132 #define BTB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure.
62139 #define BTB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure.
62141 #define BTB_REG_OUT_IF_ENABLE_ALM_FULL_OUT_IF_EN (0x1<<11) // There is bit for almost full interfaces. When bit is set then almost full interface is enabled. When bit is reset then almost full will never be set. All bits of this register should be set after init procedure. ::/ALM_FULL_EN/d in Existance.
62143 #define BTB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN (0x1<<12) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set. This bit should be set after init procedure.
62145 #define BTB_REG_OUT_IF_ENABLE_RELEASE_OUT_IF_EN (0x1<<13) // There is bit for release interfaces. When bit is set then release interface is enabled. When bit is reset then release interface will never be set. This bit should be set after init procedure. ::/RLS_EN/d in Existance.
62152 #define BTB_REG_WC_BANDWIDTH_IF_FULL 0xdb099cUL //Access:R DataWidth:0x1 // Debug register. Full status each write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.
62185 #define BTB_REG_ALM_FULL 0xdb0a74UL //Access:R DataWidth:0x1 // Debug register. This is almost full output IF to PBF::/ALM_FULL_EN/d in Existance.
62207 #define MCP_REG_MCP_CONTROL_MCP_ISOLATE (0x1<<31) // This bit is set by the driver before it sets the MCP_RESET bit. When set this bit disables MCP's GRC Master interface. This bit should cleared by the driver when the MCP reset completes.
62212 #define MCP_REG_MCP_ATTENTION_STATUS_M2P_ATTN (0x1<<26) // Attention from the M2P Block.
62214 #define MCP_REG_MCP_ATTENTION_STATUS_SPAD_CACHE_ATTN (0x1<<27) // Illegal transaction occurred in the MCP cache block.
62216 #define MCP_REG_MCP_ATTENTION_STATUS_SMB_EVENT (0x1<<28) // Event from the SMBUS Block.
62218 #define MCP_REG_MCP_ATTENTION_STATUS_FLSH_EVENT (0x1<<29) // Event from the Flash Block.
62220 #define MCP_REG_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (0x1<<30) // This bit is set when the watchdog timer expires. This bit reflects state of the WATCHDOG_ATTN bit. When this bit is written as '1', the value will return to '0'. !!! Writing '1' has effect only after watchdog_reset register had been written !!!
62222 #define MCP_REG_MCP_ATTENTION_STATUS_CPU_EVENT (0x1<<31) // This bit is set any time an internal CPU event that requires the driver's attention happens.
62227 #define MCP_REG_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (0x1<<31) // When this bit is set by the driver it indicates to MCP that it should start incrementing the MCP_HEARTBEAT register. The MCP reports the increment period to the driver using MCP_HEARTBEAT_STATUS register.
62234 #define MCP_REG_MCP_HEARTBEAT_STATUS_VALID (0x1<<31) // When set this bit validates bits 10-0 of this register.
62239 #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (0x1<<30) // When set this bit causes MCP heartbeat counter to increment. Typically used by the MCP.
62241 #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (0x1<<31) // When set this bit resets the heartbeat counter. Typically used by the MCP or the driver.
62246 #define MCP_REG_WATCHDOG_RESET_WATCHDOG_2_RESET (0x1<<30) // When set this bit resets the watchdog timer #2. Typically used by the MCP or the driver.
62248 #define MCP_REG_WATCHDOG_RESET_WATCHDOG_RESET (0x1<<31) // When set this bit resets the watchdog timer #1. Typically used by the MCP or the driver.
62253 #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_2_ENABLE (0x1<<27) // When set this bit enables watchdog timer #2. Typically used by the driver
62255 #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_MASTER_WRITE_STALL_ENABLE (0x1<<28) // When this bit is set, expiration of watchdog timer will result in MCP losing ability to perform GRC master write operations. Default is for MCP to have GRC write capability even through a watchdog timer expiration.
62257 #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ATTN (0x1<<29) // When set indicates that watchdog timer has reached 0 and that it requires driver's attention. Low to high transition on this bit should generate MCP attention toward the HC which will send it back to the driver using driver status block. Cleared when the watchdog timer is reset.
62259 #define MCP_REG_WATCHDOG_CONTROL_MCP_RST_ENABLE (0x1<<30) // When set this bit enables the watchdog timer to reset the MCP instead of halting it. The watchdog hardware must set MCP_ISOLATE bit before it resets the MCP.
62261 #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ENABLE (0x1<<31) // When set this bit enables watchdog timer #1. Typically used by the driver.
62268 #define MCP_REG_ACCESS_LOCK_LOCK (0x1<<31) // Driver writes '1' to this bit in order to obtain the lock over the shared resources within the chip. The actual "lock" is implemented in hardware using the state machine that keeps track of who is the owner of the lock. Only the owner of the lock can release the lock. When read by the driver as '1' (after it was written with '1' it tells the driver that it obtained the lock. If read as '0' it means that the other driver holds the lock. Driver writes '0' to this bit to release the lock in case that it owns the lock.
62273 #define MCP_REG_TOE_ID_FUNCTION_ID (0x1<<31) // This bit tells driver the PCIE function that is associated with. '0' corresponds to even PCIE functions '1' to odd PCIE functions. Since the value is different for both functions, the reset value is shown as unknown.
62292 #define MCP_REG_MCP_DOORBELL_MCP_DOORBELL (0x1<<31) // Set by the driver to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doorbell Status register. Cleared by the MCP when it services the message.
62299 #define MCP_REG_MCP_VFID_VFID_VALID (0x1<<16) //
62303 #define MCP_REG_MCP_VFID_PATHID (0x1<<20) //
62307 #define MCP_REG_MCP_VFID_PATH_FORCE (0x1<<31) //
62318 #define MCP_REG_CPU_MODE_LOCAL_RST (0x1<<0) // When this bit is written to a 1, the processor will reset as if from power-up state. All "Reset" value of registers will be assigned.
62320 #define MCP_REG_CPU_MODE_STEP_ENA (0x1<<1) // When this bit is set, the processor is allowed to execute one cycle regardless of any halt conditions. If the halting condition still exists, the CPU will halt again after the one cycle, otherwise, it will resume normal operation.
62322 #define MCP_REG_CPU_MODE_PAGE_0_DATA_ENA (0x1<<2) // This bit enables the processor to halt and to latch the value of bit 3 of the state register when data references the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
62324 #define MCP_REG_CPU_MODE_PAGE_0_INST_ENA (0x1<<3) // This bit enables the processor to halt and to latch the value of bit 4 of the state register when an instruction references the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
62328 #define MCP_REG_CPU_MODE_MSG_BIT1 (0x1<<6) // This is a simple RW bit.
62330 #define MCP_REG_CPU_MODE_INTERRUPT_ENA (0x1<<7) // When this bit is set to 1, the interrupt is enabled. When this bit is zero, any interrupt will be ignored. This bit can also be set by writing the interrupt_enable register
62334 #define MCP_REG_CPU_MODE_SOFT_HALT (0x1<<10) // When this bit is set, the CPU will halt. This bit is cleared by an exception or reset. If the processor does not have a ROM, then this bit will reset to set so that no code is executed from the scratchpad. If the processor does have a ROM, this bit resets a cleared so that the processor executes from ROM after reset.
62336 #define MCP_REG_CPU_MODE_BAD_DATA_HALT_ENA (0x1<<11) // When this bit is set, the CPU will halt when any condition that causes bit 5 in the CPU state register to be set occurs. This bit is cleared by an interrupt.
62338 #define MCP_REG_CPU_MODE_BAD_INST_HALT_ENA (0x1<<12) // When this bit is set, the CPU will halt when any condition that causes bit 6 in the CPU state register to be set occurs. This bit is cleared by an interrupt.
62340 #define MCP_REG_CPU_MODE_FIO_ABORT_HALT_ENA (0x1<<13) // When this bit is set, the CPU will halt when a abort is indicated from any "Fast IO" space peripheral.
62342 #define MCP_REG_CPU_MODE_UNUSED2 (0x1<<14) //
62344 #define MCP_REG_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (0x1<<15) // When this bit is set, the CPU will halt when state bit 11 is set.
62347 #define MCP_REG_CPU_STATE_BREAKPOINT (0x1<<0) // This bit is set while the processor is halted due reaching a hardware breakpoint as enabled in the mode register. This bit is cleared by writing a 1 to this bit position.
62349 #define MCP_REG_CPU_STATE_UNUSED0 (0x1<<1) //
62351 #define MCP_REG_CPU_STATE_BAD_INST_HALTED (0x1<<2) // This bit is set while the processor is halted due fetching an invalid instruction. This bit is cleared by writing a 1 to this bit position.
62353 #define MCP_REG_CPU_STATE_PAGE_0_DATA_HALTED (0x1<<3) // This bit is set while the processor is halted due to accessing data within page 0 (the first 256 bytes) of memory. This bit is cleared by writing a 1 to this bit position.
62355 #define MCP_REG_CPU_STATE_PAGE_0_INST_HALTED (0x1<<4) // This bit is set while the processor is halted due to executing an instruction within page 0 (the first 256 bytes) of memory. This bit is cleared by writing a 1 to this bit position.
62357 #define MCP_REG_CPU_STATE_BAD_DATA_ADDR_HALTED (0x1<<5) // This bit is set while the processor is halted due to bad data reference address. This bit is cleared by writing a 1 to this bit position.
62359 #define MCP_REG_CPU_STATE_BAD_PC_HALTED (0x1<<6) // This bit is set while the processor is halted due to bad value in the Program Counter (PC). This bit is cleared by writing a 1 to this bit position.
62361 #define MCP_REG_CPU_STATE_ALIGN_HALTED (0x1<<7) // This bit is set while the processor is halted due to bad memory alignment problem on a load or store instruction. This bit is cleared by writing a 1 to this bit position.
62363 #define MCP_REG_CPU_STATE_FIO_ABORT_HALTED (0x1<<8) // This bit is set while the processor is halted due to the generation of a abort condition by one, or more, "Fast IO" devices within the CPU block. This will only happen if halt is enabled by bit 13 in the mode register.
62365 #define MCP_REG_CPU_STATE_UNUSED1 (0x1<<9) //
62367 #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1<<10) // This bit is set while the processor is halted due to the setting of bit 10 in the mode register.
62369 #define MCP_REG_CPU_STATE_SPAD_UNDERFLOW (0x1<<11) // This bit is each time an attempt is made to access the underflow area of the Scratchpad.
62371 #define MCP_REG_CPU_STATE_INTERRRUPT (0x1<<12) // This bit is each time an interrupt input is asserted, regardless of the interrupt enable bit (bit 7, mode).
62373 #define MCP_REG_CPU_STATE_UNUSED2 (0x1<<13) //
62375 #define MCP_REG_CPU_STATE_DATA_ACCESS_STALL (0x1<<14) // This bit is set while the processor is stalled due to data access.
62377 #define MCP_REG_CPU_STATE_INST_FETCH_STALL (0x1<<15) // This bit is set while the processor is stalled due to instruction fetch.
62381 #define MCP_REG_CPU_STATE_BLOCKED_READ (0x1<<31) // This bit indicates that a blocking data cache miss occurred, causing the CPU to stall while data is fetched from memory. This is intended as a debugging tool. No state is saved other than the fact that the miss occurred. This bit is cleared by writing a 1 to this bit position.
62384 #define MCP_REG_CPU_EVENT_MASK_BREAKPOINT_MASK (0x1<<0) // This bit enables breakpoints to generate Attention output.
62386 #define MCP_REG_CPU_EVENT_MASK_UNUSED0 (0x1<<1) //
62388 #define MCP_REG_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (0x1<<2) // This bit enables invalid instruction decodes to generate Attention output.
62390 #define MCP_REG_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (0x1<<3) // This bit enables page 0 data access to generate Attention output.
62392 #define MCP_REG_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (0x1<<4) // This bit enables page 0 instructions to generate Attention output.
62394 #define MCP_REG_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (0x1<<5) // This bit enables invalid data addresses to generate Attention output.
62396 #define MCP_REG_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (0x1<<6) // This bit enables invalid PC values to generate Attention output.
62398 #define MCP_REG_CPU_EVENT_MASK_ALIGN_HALTED_MASK (0x1<<7) // This bit enables alignment errors to generate Attention output.
62400 #define MCP_REG_CPU_EVENT_MASK_FIO_ABORT_MASK (0x1<<8) // This bit enables the attention output when bit 8 of the state register is set.
62402 #define MCP_REG_CPU_EVENT_MASK_UNUSED1 (0x1<<9) //
62404 #define MCP_REG_CPU_EVENT_MASK_SOFT_HALTED_MASK (0x1<<10) // This bit enables soft halts to generate Attention output.
62406 #define MCP_REG_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (0x1<<11) // This bit attention when bit 11 of the state register is set.
62408 #define MCP_REG_CPU_EVENT_MASK_INTERRUPT_MASK (0x1<<12) // This bit attention when bit 12 of the state register is set.
62417 #define MCP_REG_CPU_HW_BREAKPOINT_DISABLE (0x1<<0) // Reset: 1 When this bit is set, the hardware breakpoint feature is disabled.
62419 #define MCP_REG_CPU_HW_BREAKPOINT_UNUSED0 (0x1<<1) //
62426 #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_PEEK_EN (0x1<<11) // When this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is available on the visibility output pins. When this bit is '1', then the mux is controlled by 1_SEL.
62432 #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_PEEK_EN (0x1<<27) // When this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is available on the visibility output pins. When this bit is '1', then the mux is controlled by 1_SEL.
62437 #define MCP_REG_CPU_LAST_BRANCH_ADDR_UNUSED0 (0x1<<0) //
62439 #define MCP_REG_CPU_LAST_BRANCH_ADDR_TYPE (0x1<<1) // This bit indicates the type of branch that * was last taken.
62459 #define MCP_REG_MDIO_COMM_FAIL (0x1<<28) // This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.
62461 #define MCP_REG_MDIO_COMM_START_BUSY (0x1<<29) // This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the emac_status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. On chip versions before TetonII-B0, on the first read of this register when this bit returns to '0', the DATA value in the same read is invalid. A 2nd read must be executed to get the correct DATA value. This problem is fixed in TetonII, B0 and later.
62464 #define MCP_REG_MDIO_STATUS_LINK (0x1<<0) // This bit is updated by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the main link status bit if auto-polling of the MDIO is enabled.
62466 #define MCP_REG_MDIO_STATUS__10MB (0x1<<1) // This bit is manually controlled only. It is not effect at all by the MDIO interface. The value of this setting is not used for TetonII. The mode is completly determined from the mode register settings.
62469 #define MCP_REG_MDIO_MODE_UNUSED0 (0x1<<0) //
62471 #define MCP_REG_MDIO_MODE_SHORT_PREAMBLE (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated during auto-polling.
62475 #define MCP_REG_MDIO_MODE_AUTO_POLL (0x1<<4) // This bit enables auto-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register must not be set. The interface will automatically poll the PHY device and set the LINK bit in the mdio_status register according to bit 2 of the PHY register 1. The PHY address used is that programmed into the PHY_ADDR field of the mdio_comm register.
62479 #define MCP_REG_MDIO_MODE_BIT_BANG (0x1<<8) // If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed.
62481 #define MCP_REG_MDIO_MODE_MDIO (0x1<<9) // The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin.
62483 #define MCP_REG_MDIO_MODE_MDIO_OE (0x1<<10) // Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input.
62485 #define MCP_REG_MDIO_MODE_MDC (0x1<<11) // Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set.
62487 #define MCP_REG_MDIO_MODE_MDINT (0x1<<12) // The read value of this bit reflects the current state of the MDINT input pin from the Copper PHY. If the interrupt is asserted, this bit will be '0', otherwise, this bit will be '1'.
62489 #define MCP_REG_MDIO_MODE_EXT_MDINT (0x1<<13) // The read value of this bit reflects the current state of the External MDINT input pin. If the interrupt is asserted, this bit will be '0', otherwise, this bit will be '1'.
62497 #define MCP_REG_MDIO_MODE_CLAUSE_45 (0x1<<31) // When set to 1 this bit indicates that the current MDIO transaction will be executed as a Clause 45 transaction. When 0 the transaction is executed as a Clause 22 transaction. Value of this bit also determines the meaning of bits specified in bits [27:0] of the MDIO COMMAND register. This bit must be set to proper value before the link auto-polling function is enabled.
62500 #define MCP_REG_MDIO_AUTO_STATUS_AUTO_ERR (0x1<<0) // This bit is set each time an error is detected during a auto poll sequence. The bit is cleared by writing a '1' to this bit position.
62511 #define MCP_REG_UCINT_WARP_MODE_BYTE_SWAP (0x1<<8) // This field controls the swapping of the data register bytes when accessing the uC interface.
62525 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET0 (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for target 0.
62527 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET1 (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for target 1.
62529 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET2 (0x1<<2) // Write this bit as a '1' to set ext_uc_enable for target 2.
62533 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR0 (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable for target 0.
62535 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR1 (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target 1.
62537 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR2 (0x1<<10) // Write this bit as a '1' to clear ext_uc_enable for target 2.
62541 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE0 (0x1<<16) // Current status of ext_uc_enable for target 0.
62543 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE1 (0x1<<17) // Current status of ext_uc_enable for target 1.
62545 #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE2 (0x1<<18) // Current status of ext_uc_enable for target 2.
62556 #define MCP_REG_UCINT_PCIE_MODE_BYTE_SWAP (0x1<<8) // This field controls the swapping of the data register bytes when accessing the uC interface.
62570 #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET0 (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for target 0.
62572 #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET1 (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for target 1.
62576 #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR0 (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable for target 0.
62578 #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR1 (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target 1.
62582 #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE0 (0x1<<16) // Current status of ext_uc_enable for target 0.
62584 #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE1 (0x1<<17) // Current status of ext_uc_enable for target 1.
62605 #define MCP_REG_IMC_COMMAND_SOFT_RESET (0x1<<30) // Setting this bit will synchronously reset the entire IMC Block.
62607 #define MCP_REG_IMC_COMMAND_ENABLE (0x1<<31) // Setting this bit enables the IMC Block
62642 #define MCP_REG_M2P_M2P_STATUS_M2P_BUSY (0x1<<0) // This bit indicates that M2P is currently sending a packet. If this bit is set, no new data should be written to the FIFO memory or to the Header registers. This should be polled until it is clear once a VDM transfer is started before another can begin.
62644 #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_INUSE_ERROR (0x1<<1) // This bit indicates that in In-Use Error has occured. This is generated if a new VDM transfer is started when the m2p_busy bit was already set.
62646 #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_OVERFLOW_ERROR (0x1<<2) // This bit indicates that the packet FIFO was overwritten with too much data. The FIFO is designed to hold a max sized packet of 256 bytes.
62648 #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_UNDERFLOW_ERROR (0x1<<3) // This bit is set when the Length specified in the VDM header exceeded the amount of data in the Packet FIFO.
62650 #define MCP_REG_M2P_M2P_STATUS_M2P_ZERO_LENGTH_ERROR (0x1<<4) // This bit is set when a packet is transmitted while the VDM Length is set to 0x0.
62661 #define MCP_REG_M2P_M2P_COMMAND_SEND_PKT_TO_PXP (0x1<<0) // Setting this bit will transmit the VDM that was already loaded in the packet FIFO.
62686 #define MCP_REG_M2P_M2P_PATH_ID_PATH_ID (0x1<<0) // This bit selects whether the VDM will be sent to Engine 0 or Engine 1.
62698 #define MCP_REG_P2M_P2M_STATUS_P2M_ATTN_BIT (0x1<<31) // This bit shows the current status of the P2M Attention signal.
62701 #define MCP_REG_P2M_P2M_CONFIG_BACKPRESSURE_MODE (0x1<<0) // Setting this bit will cause the P2M block to assert backpressure to the PXP when the packet FIFO is full. If this bit is cleared, packets arriving when the FIFO is full are discarded.
62703 #define MCP_REG_P2M_P2M_CONFIG_DRAIN_MODE (0x1<<1) // When set, this bit forces P2M to constantly drain the packet FIFO and discard all received packets.
62705 #define MCP_REG_P2M_P2M_CONFIG_VID_FILTER_DISCARD (0x1<<2) // When set, this bit will cause any packet that doesn't match one of the two Vendor ID Filters to be discarded. If this bit isn't set, all packets that don't match will be accepted.
62712 #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_DISCARD (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
62714 #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_ENABLE (0x1<<17) // When set, this VID Filter is enabled.
62719 #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_DISCARD (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
62721 #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_ENABLE (0x1<<17) // When set, this VID Filter is enabled.
62728 #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_DISCARD (0x1<<16) // When set, packets matching the Tag Filter will be discarded.
62733 #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_UNUSED0 (0x1<<7) //
62766 #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_PATH_ID (0x1<<0) // This is the Path ID of the PCI Function on which the message arrived.
62778 #define MCP_REG_CACHE_PAGING_ENABLE_ENABLE (0x1<<0) // If this bit is cleared then the look-up is bypassed and the scratchpad is always accessed with the address that was provided by the MCP. When this bit is changed from 1 to 0, all appropriate status and valid bits are cleared.
62782 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62784 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62786 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_VALID (0x1<<2) // The data in this page is valid.
62791 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62793 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62795 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_VALID (0x1<<2) // The data in this page is valid.
62800 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62802 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62804 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_VALID (0x1<<2) // The data in this page is valid.
62809 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62811 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62813 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_VALID (0x1<<2) // The data in this page is valid.
62818 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62820 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62822 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_VALID (0x1<<2) // The data in this page is valid.
62827 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62829 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62831 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_VALID (0x1<<2) // The data in this page is valid.
62836 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62838 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62840 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_VALID (0x1<<2) // The data in this page is valid.
62845 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62847 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62849 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_VALID (0x1<<2) // The data in this page is valid.
62854 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62856 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62858 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_VALID (0x1<<2) // The data in this page is valid.
62863 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62865 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62867 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_VALID (0x1<<2) // The data in this page is valid.
62872 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62874 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62876 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_VALID (0x1<<2) // The data in this page is valid.
62881 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62883 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62885 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_VALID (0x1<<2) // The data in this page is valid.
62890 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62892 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62894 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_VALID (0x1<<2) // The data in this page is valid.
62899 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62901 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62903 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_VALID (0x1<<2) // The data in this page is valid.
62908 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62910 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62912 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_VALID (0x1<<2) // The data in this page is valid.
62917 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_LOCK (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
62919 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_ACTIVE (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
62921 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_VALID (0x1<<2) // The data in this page is valid.
62953 #define MCP_REG_CACHE_LAST_PAGE_0_VALID (0x1<<0) // The data in this register is valid.
62955 #define MCP_REG_CACHE_LAST_PAGE_0_IS_LAST (0x1<<1) // If set, this page is the most recently accessed.
62962 #define MCP_REG_CACHE_LAST_PAGE_1_VALID (0x1<<0) // The data in this register is valid.
62964 #define MCP_REG_CACHE_LAST_PAGE_1_IS_LAST (0x1<<1) // If set, this page is the most recently accessed.
62972 #define MCP_REG_CACHE_CACHE_ERROR_STATUS_OUT_OF_BOUNDS_READ (0x1<<0) // If set, Paging_enable is clear and read from address > StaticMemorySize + PageableMemorySize
62974 #define MCP_REG_CACHE_CACHE_ERROR_STATUS_ILLEGAL_FETCH (0x1<<1) // If set, a read attempt to a second page was detected while a page fetch was already in progress.
62977 #define MCP_REG_NVM_COMMAND_RST (0x1<<0) // When set, the entire NVM state machine is reset. This bit is self clearing.
62981 #define MCP_REG_NVM_COMMAND_DONE (0x1<<3) // Sequence completion bit that is asserted when the command requested by assertion of the doit bit has completed. done Will be cleared while the command is in progress. done Will stay asserted until doit is reasserted or the done bit is cleared by writing a 1 to the done bit. The done bit is the FLSH_ATTN signal.
62983 #define MCP_REG_NVM_COMMAND_DOIT (0x1<<4) // Command from software to start the defined command. The done bit must be clear before setting this bit. This bit is self clearing and will remain set while the command is active.
62985 #define MCP_REG_NVM_COMMAND_WR (0x1<<5) // The Write/Not_Read command bit. Set high to execute write or erase.
62987 #define MCP_REG_NVM_COMMAND_ERASE (0x1<<6) // The erase page/sector command bit. Set high to execute a page/sector erase_cmd. This bit is ignored if the WR bit is clear.
62989 #define MCP_REG_NVM_COMMAND_FIRST (0x1<<7) // This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set.
62991 #define MCP_REG_NVM_COMMAND_LAST (0x1<<8) // When this bit is set, the next command sequence will be interpreted as the last one of a burst and any cleanup work will be done. This means that the buffer will be written to flash memory if needed on a write.
62993 #define MCP_REG_NVM_COMMAND_ADDR_INCR (0x1<<9) // When this bit is set, the address in the address register will be incremented by 4 (1 word) after the command sequence has finished. Intended to be used for consecutive read or write access eliminating the need to update the address register on each access.
62997 #define MCP_REG_NVM_COMMAND_WREN (0x1<<16) // The write enable command bit. Set '1' will make flash interface state machine Generate wren_cmd to flash device through SPI interface to set Flash device to be write-enabled. Used for the device with protection function
62999 #define MCP_REG_NVM_COMMAND_WRDI (0x1<<17) // The write disable command bit. Set '1' will make flash interface state machine Generate wrdi_cmd to flash device through SPI interface to set Flash device to be write-disabled. Used for the device with protection function.
63001 #define MCP_REG_NVM_COMMAND_ERASE_ALL (0x1<<18) // The erase all/chip command bit. Set high to execute an all/chip erase_all_cmd. This bit is ignored if the WR bit is clear.
63003 #define MCP_REG_NVM_COMMAND_UNUSED2 (0x1<<19) //
63005 #define MCP_REG_NVM_COMMAND_RD_ID (0x1<<20) // The read ID command bit. When set, the flash controller will read the ID register from the external flash device. This is specifically for ST devices. Setting this bit for Atmel devices will give the same results as RD_STATUS.
63007 #define MCP_REG_NVM_COMMAND_RD_STATUS (0x1<<21) // The read status command bit. When set, the flash controller will read the status register from the external flash device
63009 #define MCP_REG_NVM_COMMAND_MODE_256 (0x1<<22) // The 256B page size mode disable bit. A 256 byte page mode has been added to the block. This mode is normally on. The mode helps convert a 264B page Atmel part to act more like a 256B page part. For reads, the controller transparently closes the page after byte location 0xFF and opens the next page. For writes, it is the FW or SW responsiblity to close the page at 0xFF and start a new operation on the next page. When this bit is written as '1' when the FIRST bit is set, the 256B page mode is disabled for the next operation. It is self-clearing when both the LAST bit is set and the DONE bit is asserted. Effects Atmel only. No effect with ST devices.
63020 #define MCP_REG_NVM_CFG1_FLASH_MODE (0x1<<0) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atmel o
63022 #define MCP_REG_NVM_CFG1_BUFFER_MODE (0x1<<1) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atmel or ST.
63024 #define MCP_REG_NVM_CFG1_PASS_MODE (0x1<<2) // Enable pass-thru mode to the byte level SPI state machine. When this mode is enabled, the controller can send/recieve single bytes at the SPI level. All upper level functions of the controller state machine are disabled.
63026 #define MCP_REG_NVM_CFG1_BITBANG_MODE (0x1<<3) // Enable bit-bang mode to control pins.
63034 #define MCP_REG_NVM_CFG1_UNUSED0 (0x1<<22) //
63036 #define MCP_REG_NVM_CFG1_STRAP_CONTROL_0 (0x1<<23) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH has already been configured.
63038 #define MCP_REG_NVM_CFG1_PROTECT_MODE (0x1<<24) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atmel or ST.
63040 #define MCP_REG_NVM_CFG1_FLASH_SIZE (0x1<<25) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atmel or ST.
63042 #define MCP_REG_NVM_CFG1_FW_USTRAP_1 (0x1<<26) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atmel or ST.
63044 #define MCP_REG_NVM_CFG1_FW_USTRAP_0 (0x1<<27) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atmel or ST.
63046 #define MCP_REG_NVM_CFG1_FW_USTRAP_2 (0x1<<28) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atmel or ST.
63048 #define MCP_REG_NVM_CFG1_FW_USTRAP_3 (0x1<<29) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atmel or ST.
63050 #define MCP_REG_NVM_CFG1_FW_FLASH_TYPE_EN (0x1<<30) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH has already been configured.This register has no hardware function, but can be modified by firmware.
63052 #define MCP_REG_NVM_CFG1_COMPAT_BYPASSS (0x1<<31) // Legacy bit. Acts as dummy R/W bit.
63073 #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET0 (0x1<<0) // Set Software Arbitration request Bit 0. This bit is set by writing a '1' to this bit position.
63075 #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET1 (0x1<<1) // Set Software Arbitration request Bit 1. This bit is set by writing a '1' to this bit position.
63077 #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET2 (0x1<<2) // Set Software Arbitration request Bit 2. This bit is set by writing a '1' to this bit position.
63079 #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET3 (0x1<<3) // Set Software Arbitration request Bit 3. This bit is set by writing a '1' to this bit position.
63081 #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR0 (0x1<<4) // Write this bit as a '1' to clear req0 bit.
63083 #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR1 (0x1<<5) // Write this bit as a '1' to clear req1 bit.
63085 #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR2 (0x1<<6) // Write this bit as a '1' to clear req2 bit.
63087 #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR3 (0x1<<7) // Write this bit as a '1' to clear req3 bit.
63089 #define MCP_REG_NVM_SW_ARB_ARB_ARB0 (0x1<<8) // when REQ0 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB0 must be written to clear this bit. At that point, the next Arb bit will read as 1. At any time, only one of the ARB[7:0] bits will be read as a 1. Arb0 has highest priority, and Arb7 has lowest priority.
63091 #define MCP_REG_NVM_SW_ARB_ARB_ARB1 (0x1<<9) // when REQ1 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB1 must be written to clear this bit.
63093 #define MCP_REG_NVM_SW_ARB_ARB_ARB2 (0x1<<10) // when REQ2 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB2 must be written to clear this bit.
63095 #define MCP_REG_NVM_SW_ARB_ARB_ARB3 (0x1<<11) // when REQ3 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB3 must be written to clear this bit.
63097 #define MCP_REG_NVM_SW_ARB_REQ0 (0x1<<12) // This is the current status of requester 0. When this bit is one, it means that REQ_SET0 has been set since REQ_CLR0.
63099 #define MCP_REG_NVM_SW_ARB_REQ1 (0x1<<13) // This is the current status of requester 1. When this bit is one, it means that REQ_SET1 has been set since REQ_CLR1.
63101 #define MCP_REG_NVM_SW_ARB_REQ2 (0x1<<14) // This is the current status of requester 2. When this bit is one, it means that REQ_SET2 has been set since REQ_CLR2.
63103 #define MCP_REG_NVM_SW_ARB_REQ3 (0x1<<15) // This is the current status of requester 3. When this bit is one, it means that REQ_SET3 has been set since REQ_CLR3.
63121 #define MCP_REG_NVM_CFG5_USE_BUFFER (0x1<<30) // When set to 1, write operations to Flash will use an internal 4KB sector buffer. Some Flash (Macronix, Winbond) only support PageProgram, which requires the Flash to be erased prior to programming. To make write operations identical across Flash devices, a buffer was added to store the sector data prior to an internally generated erase and then all data is written back to Flash including the write modifications. When cleared to 0, the buffer is unused.
63123 #define MCP_REG_NVM_CFG5_USE_LEGACY_SPI_FSM (0x1<<31) // Set to 1 to use legacy/previous flsh_spi_fsm. Clear to 0 to use latest flsh_spi_fsm.
63128 #define MCP_REG_NVM_CFG4_FLASH_VENDOR (0x1<<3) // This bit is self-configured on reset based on the strap values. It can be overriden.
63132 #define MCP_REG_NVM_CFG4_STATUS_BIT_POLARITY (0x1<<6) // This bit determines how the status bit of the device status register is interpreted by hardware. If 0, then 0 means "ready". If 1, then 1 means "ready". For Atmel, this defaults to 1. For ST, this defaults to 0. This value is self-configured on reset based on the strap values. It can be overriden.
63134 #define MCP_REG_NVM_CFG4_FAST (0x1<<7) // Fast Mode. When this bit is set in ST mode, fast read command is used. In Atmel mode, this bit should be set when using the 0xE8 read command. It should be cleared when using the 0x68 read command. This value is self-configured on reset based on the external device.
63136 #define MCP_REG_NVM_CFG4_SI_INPUT_RELAXED_TIMING (0x1<<8) // When this bit is set, the SI input from the external flash device is latched one cycle later than normal. This bit defaults to 0.
63138 #define MCP_REG_NVM_CFG4_PASS_MODE_RELAXED_TIMING (0x1<<9) // When this bit is set, the pass mode data is captured one cycle later than normal. If using pass mode, this bit should be set whenever the si_input_relaxed_timing bit is set. This bit defaults to 0.
63140 #define MCP_REG_NVM_CFG4_SR_TURNAROUND (0x1<<10) // When this bit is set, a turnaround cycle is inserted in between the address and data phases of a status read for Atmel devices. This bit should only be set when the legacy status read command (0x57) is used. This bit defaults to 0.
63148 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_BUFFER_RD (0x1<<23) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63150 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_ERASE (0x1<<24) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63152 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_FAST_READ (0x1<<25) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63154 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ (0x1<<26) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63156 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ_ID (0x1<<27) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63158 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_STATUS (0x1<<28) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63160 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRDI (0x1<<29) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63162 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WREN (0x1<<30) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63164 #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRITE (0x1<<31) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
63173 #define MCP_REG_NVM_RECONFIG_RECONFIG_DONE (0x1<<31) // This bit is 0 on reset. After software finishes reconfiguring FLSH, they will set this bit to 1 to indicate that FLSH has been reconfigured. This bit has no hardware functionality.
63176 #define MCP_REG_ERNGN_EXP_ROM_CTRL_ENA (0x1<<0) // Enable bit for the expansion ROM engine. When '1', the expansion ROM engine will automatically service expansion ROM requests. When this bit is cleared, the engine will not service a new request and the on chip cpu will have to take over the chores.
63178 #define MCP_REG_ERNGN_EXP_ROM_CTRL_BFRD (0x1<<1) // When this bit is set to '1', the expansion ROM engine will utilize the buffered mode address translation mode in the flash controller to adjust the address for flash devices with 264 byte blocks, spaced every 512 bytes.
63190 #define MCP_REG_ERNGN_EXP_ROM_CTRL_CACHE_VALID (0x1<<28) // This bit is set to '1' when the cache is valid.
63192 #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_TIMEOUT (0x1<<29) // This bit is set to '1' when an arbitration timeout happens.
63194 #define MCP_REG_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT (0x1<<30) // This bit is set to '1' when a read timeout happens.
63196 #define MCP_REG_ERNGN_EXP_ROM_CTRL_ACTIVE (0x1<<31) // This bit is set to '1' when the expansion ROM engine is actively operating on a expansion ROM request.
63217 #define MCP_REG_ERNGN_EXP_ROM_ADR_REQ (0x1<<31) // This bit will be set if there is a pending request for action. This bit is equivalent to the EXP_ROM_ATTN attention word bit.
63247 #define MCP_REG_ERNGN_IMG_LOADER0_CFG_AUTO_INC (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
63251 #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ARB_TO (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
63253 #define MCP_REG_ERNGN_IMG_LOADER0_CFG_READ_TO (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
63255 #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BUSY (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
63257 #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ACTIVE (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
63284 #define MCP_REG_ERNGN_IMG_LOADER1_CFG_AUTO_INC (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
63288 #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ARB_TO (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
63290 #define MCP_REG_ERNGN_IMG_LOADER1_CFG_READ_TO (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
63292 #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BUSY (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
63294 #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ACTIVE (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
63321 #define MCP_REG_ERNGN_IMG_LOADER2_CFG_AUTO_INC (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
63325 #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ARB_TO (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
63327 #define MCP_REG_ERNGN_IMG_LOADER2_CFG_READ_TO (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
63329 #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BUSY (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
63331 #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ACTIVE (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
63336 #define MCP_REG_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR (0x1<<7) // When this bit is set HW will service the ARP Assign Address command, set the AR_FLAG[1:0] and AV_FLAG[1:0] flags, and program the NIC_SMB_ADDR[1:0] values.
63338 #define MCP_REG_SMBUS_CONFIG_ARP_EN0 (0x1<<8) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslove NIC_SMB_ADDR0 using ARP.
63340 #define MCP_REG_SMBUS_CONFIG_ARP_EN1 (0x1<<9) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslove NIC_SMB_ADDR1 using ARP.
63348 #define MCP_REG_SMBUS_CONFIG_TIMESTAMP_CNT_EN (0x1<<26) // When this bit is '1' the TIMESTAMP counter is enabled. When '0' the counter holds its value.
63350 #define MCP_REG_SMBUS_CONFIG_PROMISCOUS_MODE (0x1<<27) // When this bit is '1' the SMBUS block responds to all SMBUS transactions regardless of the slave address.
63352 #define MCP_REG_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0 (0x1<<28) // When this bit is '1' the SMBUS block responds to slave address 7'b0000000.
63354 #define MCP_REG_SMBUS_CONFIG_BIT_BANG_EN (0x1<<29) // When this bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled using Bit-Bang Control Register.
63356 #define MCP_REG_SMBUS_CONFIG_SMB_EN (0x1<<30) // When this bit is '1', the SMBUS block is enabled for operation. When set the SMBUS block will abort current transaction in compliance with the SMBUS master and slave behavior at the end of the current transaction and stop responding to the SMBUS master/slave transactions.
63358 #define MCP_REG_SMBUS_CONFIG_RESET (0x1<<31) // When this bit is set it will reset SMBUS block to its default state.
63369 #define MCP_REG_SMBUS_TIMING_CONFIG_MODE_400 (0x1<<31) // When this bit is set the SMBUS block operates in 400KHz mode. When cleared SMBUS operates in 100KHz mode.
63374 #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0 (0x1<<7) // When this bit is '1' NIC_SMB_ADDR0 will be used as a slave address to match for incoming messages.
63378 #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1 (0x1<<15) // When this bit is '1' NIC_SMB_ADDR1 will be used as a slave address to match for incoming messages.
63382 #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2 (0x1<<23) // When this bit is '1' NIC_SMB_ADDR2 will be used as a slave address to match for incoming messages.
63386 #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3 (0x1<<31) // When this bit is '1' NIC_SMB_ADDR3 will be used as a slave address to match for incoming messages.
63393 #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED1 (0x1<<15) //
63399 #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH (0x1<<30) // When this bit is set HW will flush Master TX FIFO when current TX transaction completes.
63401 #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH (0x1<<31) // When this bit is set HW will flush Master RX FIFO when the current RX transaction completes.
63408 #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED1 (0x1<<15) //
63414 #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH (0x1<<30) // When this bit is set HW will flush Slave TX FIFO when current TX transaction completes.
63416 #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH (0x1<<31) // When this bit is set HW will flush Slave RX FIFO when the current RX transaction completes.
63421 #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit controlls the output enable for the SMBDAT pin. When this bit is '0', the SMBDAT pin will drive low. When this bit is '1', the SMBDAT pin will float.
63423 #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN (0x1<<29) // This bit reflects the current input value of the SMBDAT pin. When the SMBDAT pin is high, this bit will read as '1'. When the SMBDAT pin is low, this pin will read as '0'.
63425 #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit controlls the output enable for the CLK pin. When this bit is '0', the CLK pin will drive low. When this bit is '1', the CLK pin will float.
63427 #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN (0x1<<31) // This bit reflects the current input value of the SMBCLK pin. When the SMBCLK pin is high, this bit will read as '1'. When the SMBCLK pin is low, this pin will read as '0'.
63448 #define MCP_REG_SMBUS_MASTER_COMMAND_PEC (0x1<<8) // PEC should be checked or calculated for this transaction.
63458 #define MCP_REG_SMBUS_MASTER_COMMAND_ABORT (0x1<<30) // Transaction Abort. This bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW will abort transaction in compliance with the SMBUS rules and clear the bit when done.
63460 #define MCP_REG_SMBUS_MASTER_COMMAND_START_BUSY (0x1<<31) // This bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results.
63465 #define MCP_REG_SMBUS_SLAVE_COMMAND_PEC (0x1<<8) // PEC should be calculated for this transaction.
63473 #define MCP_REG_SMBUS_SLAVE_COMMAND_ABORT (0x1<<30) // Transaction Abort. This bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW will abort transaction in compliance with the SMBUS rules and clear the bit when done. When set and the slave transaction is received the HW will ACK the address and float the bus thereafter.
63475 #define MCP_REG_SMBUS_SLAVE_COMMAND_START (0x1<<31) // _BUSY This bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results. Used only for read response.
63478 #define MCP_REG_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN (0x1<<0) // When set enables Watchdog Timer to generate smbus event.
63480 #define MCP_REG_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN (0x1<<1) // When set enables Heartbeat Timer to generate smbus event.
63482 #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN (0x1<<2) // When set enables ASF Sensor Poll Timer to generate smbus event.
63484 #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN (0x1<<3) // When set enables Legacy Sensor Poll Timer to generate smbus event.
63486 #define MCP_REG_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN (0x1<<4) // When set enables Retransmit Timer to generate smbus event.
63490 #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN (0x1<<20) // When set enables hardware to generate smbus event any time and ARP command is received and ARP_EN0 or ARP_EN1 bit is set.
63492 #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN (0x1<<21) // Enables SLAVE_RD_EVENT to generate smbus event.
63494 #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN (0x1<<22) // When set enables generation of a smbus event when Slave Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
63496 #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN (0x1<<23) // When set enables generation of a smbus event on slave START_BUSY 1 to 0 transition.
63498 #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN (0x1<<24) // Enables SLAVE_RX_EVENT to generate smbus event.
63500 #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN (0x1<<25) // When set enables SLAVE_RX_THRESHOLD_HIT to generate smbus event.
63502 #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN (0x1<<26) // When set enables SLAVE_RX_FIFO_FULL to generate smbus event.
63504 #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN (0x1<<27) // When set enables generation of a smbus event when Master Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
63506 #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN (0x1<<28) // When set enables generation of a smbus event on master START_BUSY 1 to 0 transition.
63508 #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN (0x1<<29) // When set enables MASTER_RX_EVENT to generate smbus event.
63510 #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN (0x1<<30) // When set enables MASTER_RX_THRESHOLD_HIT to generate smbus event.
63512 #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN (0x1<<31) // When set enables MASTER_RX_FIFO_FULL to generate smbus event.
63515 #define MCP_REG_SMBUS_EVENT_STATUS_WATCHDOG_TO (0x1<<0) // This bit changes to '1' each time the WATCHDOG timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63517 #define MCP_REG_SMBUS_EVENT_STATUS_HEARTBEAT_TO (0x1<<1) // This bit changes to '1' each time the HEARTBEAT timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63519 #define MCP_REG_SMBUS_EVENT_STATUS_POLL_ASF_TO (0x1<<2) // This bit changes to '1' each time the POLL_ASF timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63521 #define MCP_REG_SMBUS_EVENT_STATUS_POLL_LEGACY_TO (0x1<<3) // This bit changes to '1' each time the POLL_LEGACY timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63523 #define MCP_REG_SMBUS_EVENT_STATUS_RETRANSMIT_TO (0x1<<4) // This bit changes to '1' each time the RETRANSMIT timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63527 #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT (0x1<<20) // This bit set when slave hardware received an ARP command and ARP_EN0 or ARP_EN1 bit is set.
63529 #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT (0x1<<21) // This bit is set when slave hardware detected read transaction directed toward the SMBUS block. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63531 #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN (0x1<<22) // This bit is set when Slave Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
63533 #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_START_BUSY (0x1<<23) // This bit is set when slave START_BUSY transitions from 1 to 0. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
63535 #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT (0x1<<24) // This bit is set when the slave receive FIFO holds at least one valid transaction. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63537 #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT (0x1<<25) // This bit is set when the slave receive FIFO is equal to or larger than the Slave RX_FIFO_THRESHOLD. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63539 #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL (0x1<<26) // This bit is set when the slave receive FIFO become full. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63541 #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN (0x1<<27) // This bit is set when Master Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
63543 #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_START_BUSY (0x1<<28) // This bit is set when master START_BUSY transitions from 1 to 0. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
63545 #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_EVENT (0x1<<29) // This bit is set when the master receive FIFO holds at least one valid transaction. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63547 #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT (0x1<<30) // This bit is set when the master receive FIFO is equal to or larger than the Master RX_FIFO_THRESHOLD. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63549 #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL (0x1<<31) // This bit is set when the master receive FIFO become full. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
63556 #define MCP_REG_SMBUS_MASTER_DATA_WRITE_WR_STATUS (0x1<<31) // 0 - Byte other then last in an WMBUS transaction 1 - End of SMBUS transaction
63563 #define MCP_REG_SMBUS_MASTER_DATA_READ_PEC_ERR (0x1<<29) // PEC error. This bit indicates status of the PEC checking. HW will check the PEC only in case where PEC bit in SMBUS Master Command Register was set for rhe transaction This field is valid only when RD_STATUS = 2'b11.
63572 #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_WR_STATUS (0x1<<31) // Enumeration:
63584 #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG0 (0x1<<0) // This bit should be set by firmware before ARP_EN0 bit is set. This bit is typically set to '1' based on the NVRAM content that is if device supports Persistent Slave Address and cleared otherwise.
63586 #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG0 (0x1<<1) // This bit should be set by firmware before ARP_EN0 bit is set. This bit is typically initialized to '0'.
63590 #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG1 (0x1<<4) // This bit should be set by firmware before ARP_EN1 bit is set. This bit is typically set to '1' based on the NVRAM content that is if device supports Persistent Slave Address and cleared otherwise.
63592 #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG1 (0x1<<5) // This bit should be set by firmware before ARP_EN1 bit is set. This bit is typically initialized to '0'.
63668 #define MCP_REG_TO_BMB_FIFO_COMMAND_FLUSH (0x1<<0) // Setting this bit to '1' will flush the packet in the FIFO.
63670 #define MCP_REG_TO_BMB_FIFO_COMMAND__ERROR (0x1<<1) // Setting this bit to '1' will set the error bit for the packet.
63681 #define MCP_REG_TO_BMB_FIFO_STATUS_WRITE_DONE (0x1<<0) // This bit indicates that the write to BMB has been completed.
63689 #define MCP_REG_FRM_BMB_FIFO_COMMAND_READ_DONE (0x1<<0) // Setting this bit to '1' will indicate that FW has completed read of the packet.
63693 #define MCP_REG_FRM_BMB_FIFO_COMMAND_FLUSH (0x1<<4) // Setting this bit to '1' will flush the current packet in the FIFO
63695 #define MCP_REG_FRM_BMB_FIFO_COMMAND_CLR_PKT_COUNTERS (0x1<<5) // Setting this bit to '1' will clear all packet available counters in the BMB read client interface
63698 #define MCP_REG_FRM_BMB_FIFO_STATUS_BUSY (0x1<<0) // This bit indicates that the FIFO is busy
63700 #define MCP_REG_FRM_BMB_FIFO_STATUS_UNUSED0 (0x1<<1) //
63704 #define MCP_REG_FRM_BMB_FIFO_STATUS_DATA_VALID (0x1<<4) // This bit indicates that the data is valid.
63706 #define MCP_REG_FRM_BMB_FIFO_STATUS_SOP (0x1<<5) // This bit indicates that the next data is the SOP of the packet.
63708 #define MCP_REG_FRM_BMB_FIFO_STATUS_EOP (0x1<<6) // This bit indicates that the next data is the EOP of the packet.
63710 #define MCP_REG_FRM_BMB_FIFO_STATUS_ERR (0x1<<7) // This bit indicates that the packet was received with an error.
63731 #define XSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN (0x1<<0) // Enable for input command from STORM.
63733 #define XSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
63735 #define XSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
63737 #define XSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
63739 #define XSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
63741 #define XSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
63743 #define XSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
63745 #define XSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
63747 #define XSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
63749 #define XSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
63751 #define XSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
63753 #define XSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
63755 #define XSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
63757 #define XSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN (0x1<<13) // Enable for input completion message from PRM in prm_if block.
63759 #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN (0x1<<14) // Enable for input ack to CCFC load credit counter.
63761 #define XSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN (0x1<<15) // Enable for input ack to TCFC load credit counter.
63763 #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN (0x1<<16) // Enable for input response from CCFC in CCFC block.
63765 #define XSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
63767 #define XSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
63769 #define XSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN (0x1<<19) // Enable for input full from qm in SDM_INP block.
63772 #define XSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN (0x1<<0) // Enable for input response from TCFC in TCFC block.
63774 #define XSDM_REG_ENABLE_IN2_CM_ACK_IN_EN (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
63776 #define XSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
63779 #define XSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
63781 #define XSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN (0x1<<1) // Enable for output thread ready to the SEMI.
63783 #define XSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN (0x1<<2) // Enable the output thread release to the SEMI.
63785 #define XSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN (0x1<<3) // Enable for output load request to CCFC.
63787 #define XSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN (0x1<<4) // Enable for output load request to TCFC.
63789 #define XSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN (0x1<<5) // Enable for output increment to CCFC activity counter.
63791 #define XSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN (0x1<<6) // Enable for output decrement to TCFC activity counter.
63793 #define XSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
63795 #define XSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
63797 #define XSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
63799 #define XSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
63801 #define XSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
63803 #define XSDM_REG_ENABLE_OUT1_PXP_OUT_EN (0x1<<12) // Enable for output write to pxp in DMA_DST block.
63805 #define XSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
63807 #define XSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
63809 #define XSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN (0x1<<15) // Enable for output external full to SEMI block.
63811 #define XSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN (0x1<<16) // Enable for output done to async PXP host IF.
63813 #define XSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN (0x1<<17) // Enable the output done (ack) to PRM.
63815 #define XSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN (0x1<<18) // Enable for output message to CM in SDM_CM block.
63817 #define XSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
63819 #define XSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
63822 #define XSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN (0x1<<0) // Enable for output command to qm in SDM_INP block.
63824 #define XSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
63826 #define XSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
63829 #define XSDM_REG_DISABLE_ENGINE_DISABLE_DMA (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
63831 #define XSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
63833 #define XSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
63835 #define XSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
63837 #define XSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
63839 #define XSDM_REG_DISABLE_ENGINE_DISABLE_NOP (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
63841 #define XSDM_REG_DISABLE_ENGINE_DISABLE_GRC (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
63843 #define XSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
63845 #define XSDM_REG_DISABLE_ENGINE_DISABLE_PRM (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
63847 #define XSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
63850 #define XSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
63852 #define XSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
63854 #define XSDM_REG_INT_STS_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
63856 #define XSDM_REG_INT_STS_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
63858 #define XSDM_REG_INT_STS_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
63860 #define XSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
63862 #define XSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
63864 #define XSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
63866 #define XSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
63868 #define XSDM_REG_INT_STS_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
63870 #define XSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
63872 #define XSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
63874 #define XSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
63876 #define XSDM_REG_INT_STS_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
63878 #define XSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
63880 #define XSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
63882 #define XSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
63884 #define XSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
63886 #define XSDM_REG_INT_STS_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
63888 #define XSDM_REG_INT_STS_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
63890 #define XSDM_REG_INT_STS_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
63892 #define XSDM_REG_INT_STS_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
63894 #define XSDM_REG_INT_STS_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
63896 #define XSDM_REG_INT_STS_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
63898 #define XSDM_REG_INT_STS_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
63900 #define XSDM_REG_INT_STS_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
63902 #define XSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
63904 #define XSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
63907 #define XSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.ADDRESS_ERROR .
63909 #define XSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.INP_QUEUE_ERROR .
63911 #define XSDM_REG_INT_MASK_DELAY_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DELAY_FIFO_ERROR .
63913 #define XSDM_REG_INT_MASK_ASYNC_HOST_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.ASYNC_HOST_ERROR .
63915 #define XSDM_REG_INT_MASK_PRM_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.PRM_FIFO_ERROR .
63917 #define XSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
63919 #define XSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
63921 #define XSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
63923 #define XSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
63925 #define XSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
63927 #define XSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
63929 #define XSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
63931 #define XSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
63933 #define XSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
63935 #define XSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
63937 #define XSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
63939 #define XSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
63941 #define XSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
63943 #define XSDM_REG_INT_MASK_CM_DELAY_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CM_DELAY_ERROR .
63945 #define XSDM_REG_INT_MASK_SH_DELAY_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.SH_DELAY_ERROR .
63947 #define XSDM_REG_INT_MASK_CMPL_PEND_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CMPL_PEND_ERROR .
63949 #define XSDM_REG_INT_MASK_CPRM_PEND_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CPRM_PEND_ERROR .
63951 #define XSDM_REG_INT_MASK_TIMER_ADDR_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TIMER_ADDR_ERROR .
63953 #define XSDM_REG_INT_MASK_TIMER_PEND_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TIMER_PEND_ERROR .
63955 #define XSDM_REG_INT_MASK_DORQ_DPM_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DORQ_DPM_ERROR .
63957 #define XSDM_REG_INT_MASK_DST_PXP_DONE_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
63959 #define XSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
63961 #define XSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
63964 #define XSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
63966 #define XSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
63968 #define XSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
63970 #define XSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
63972 #define XSDM_REG_INT_STS_WR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
63974 #define XSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
63976 #define XSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
63978 #define XSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
63980 #define XSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
63982 #define XSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
63984 #define XSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
63986 #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
63988 #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
63990 #define XSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
63992 #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
63994 #define XSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
63996 #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
63998 #define XSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
64000 #define XSDM_REG_INT_STS_WR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
64002 #define XSDM_REG_INT_STS_WR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
64004 #define XSDM_REG_INT_STS_WR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
64006 #define XSDM_REG_INT_STS_WR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
64008 #define XSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
64010 #define XSDM_REG_INT_STS_WR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
64012 #define XSDM_REG_INT_STS_WR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
64014 #define XSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
64016 #define XSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64018 #define XSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64021 #define XSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
64023 #define XSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
64025 #define XSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
64027 #define XSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
64029 #define XSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
64031 #define XSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
64033 #define XSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
64035 #define XSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
64037 #define XSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
64039 #define XSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
64041 #define XSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
64043 #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
64045 #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
64047 #define XSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
64049 #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
64051 #define XSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
64053 #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
64055 #define XSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
64057 #define XSDM_REG_INT_STS_CLR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
64059 #define XSDM_REG_INT_STS_CLR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
64061 #define XSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
64063 #define XSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
64065 #define XSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
64067 #define XSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
64069 #define XSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
64071 #define XSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
64073 #define XSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64075 #define XSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64078 #define XSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
64080 #define XSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
64082 #define XSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
64084 #define XSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
64086 #define XSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
64088 #define XSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
64090 #define XSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
64092 #define XSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
64094 #define XSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
64096 #define XSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
64100 #define XSDM_REG_TIMERS_TICK_ENABLE 0xf80404UL //Access:RW DataWidth:0x1 // Enable for tick counter.
64137 #define XSDM_REG_INT_CMPL_PEND_FULL 0xf80c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
64138 #define XSDM_REG_INT_CPRM_PEND_FULL 0xf80c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
64139 #define XSDM_REG_QM_FULL 0xf80c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
64140 #define XSDM_REG_DELAY_FIFO_FULL 0xf80c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
64141 #define XSDM_REG_TIMERS_PEND_FULL 0xf80c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
64142 #define XSDM_REG_TIMERS_ADDR_FULL 0xf80c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
64143 #define XSDM_REG_RSP_PXP_RDATA_FULL 0xf80c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
64144 #define XSDM_REG_RSP_BRB_RDATA_FULL 0xf80c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
64145 #define XSDM_REG_RSP_INT_RAM_RDATA_FULL 0xf80c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
64146 #define XSDM_REG_RSP_BRB_PEND_FULL 0xf80c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
64147 #define XSDM_REG_RSP_INT_RAM_PEND_FULL 0xf80c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
64148 #define XSDM_REG_RSP_BRB_IF_FULL 0xf80c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
64149 #define XSDM_REG_RSP_PXP_IF_FULL 0xf80c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
64150 #define XSDM_REG_DST_PXP_IMMED_FULL 0xf80c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
64151 #define XSDM_REG_DST_PXP_DST_PEND_FULL 0xf80c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
64152 #define XSDM_REG_DST_PXP_SRC_PEND_FULL 0xf80c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
64153 #define XSDM_REG_DST_BRB_SRC_PEND_FULL 0xf80c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
64154 #define XSDM_REG_DST_BRB_SRC_ADDR_FULL 0xf80c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
64155 #define XSDM_REG_DST_PXP_LINK_FULL 0xf80c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
64156 #define XSDM_REG_DST_INT_RAM_WAIT_FULL 0xf80c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
64157 #define XSDM_REG_DST_PAS_BUF_WAIT_FULL 0xf80c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
64158 #define XSDM_REG_DST_PXP_IF_FULL 0xf80c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
64159 #define XSDM_REG_DST_INT_RAM_IF_FULL 0xf80c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
64160 #define XSDM_REG_DST_PAS_BUF_IF_FULL 0xf80c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
64161 #define XSDM_REG_SH_DELAY_FULL 0xf80c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
64162 #define XSDM_REG_CM_DELAY_FULL 0xf80c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
64163 #define XSDM_REG_CMSG_QUE_FULL 0xf80c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
64164 #define XSDM_REG_CCFC_LOAD_PEND_FULL 0xf80c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface block.
64165 #define XSDM_REG_TCFC_LOAD_PEND_FULL 0xf80c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface block.
64166 #define XSDM_REG_ASYNC_HOST_FULL 0xf80c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
64167 #define XSDM_REG_PRM_FIFO_FULL 0xf80c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
64168 #define XSDM_REG_RMT_XCM_FIFO_FULL 0xf80c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interface).
64169 #define XSDM_REG_RMT_YCM_FIFO_FULL 0xf80c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interface).
64170 #define XSDM_REG_INT_CMPL_PEND_EMPTY 0xf80d00UL //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
64171 #define XSDM_REG_INT_CPRM_PEND_EMPTY 0xf80d04UL //Access:R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
64173 #define XSDM_REG_DELAY_FIFO_EMPTY 0xf80d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
64174 #define XSDM_REG_TIMERS_PEND_EMPTY 0xf80d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
64175 #define XSDM_REG_TIMERS_ADDR_EMPTY 0xf80d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
64176 #define XSDM_REG_RSP_PXP_RDATA_EMPTY 0xf80d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
64177 #define XSDM_REG_RSP_BRB_RDATA_EMPTY 0xf80d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
64178 #define XSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xf80d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
64179 #define XSDM_REG_RSP_BRB_PEND_EMPTY 0xf80d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
64180 #define XSDM_REG_RSP_INT_RAM_PEND_EMPTY 0xf80d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
64181 #define XSDM_REG_DST_PXP_IMMED_EMPTY 0xf80d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
64182 #define XSDM_REG_DST_PXP_DST_PEND_EMPTY 0xf80d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
64183 #define XSDM_REG_DST_PXP_SRC_PEND_EMPTY 0xf80d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
64184 #define XSDM_REG_DST_BRB_SRC_PEND_EMPTY 0xf80d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
64185 #define XSDM_REG_DST_BRB_SRC_ADDR_EMPTY 0xf80d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
64186 #define XSDM_REG_DST_PXP_LINK_EMPTY 0xf80d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
64187 #define XSDM_REG_DST_INT_RAM_WAIT_EMPTY 0xf80d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
64188 #define XSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xf80d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
64189 #define XSDM_REG_SH_DELAY_EMPTY 0xf80d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
64190 #define XSDM_REG_CM_DELAY_EMPTY 0xf80d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
64191 #define XSDM_REG_CMSG_QUE_EMPTY 0xf80d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
64192 #define XSDM_REG_CCFC_LOAD_PEND_EMPTY 0xf80d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
64193 #define XSDM_REG_TCFC_LOAD_PEND_EMPTY 0xf80d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
64194 #define XSDM_REG_ASYNC_HOST_EMPTY 0xf80d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
64195 #define XSDM_REG_PRM_FIFO_EMPTY 0xf80d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
64196 #define XSDM_REG_RMT_XCM_FIFO_EMPTY 0xf80d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM path).
64197 #define XSDM_REG_RMT_YCM_FIFO_EMPTY 0xf80d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM path).
64230 #define YSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN (0x1<<0) // Enable for input command from STORM.
64232 #define YSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
64234 #define YSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
64236 #define YSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
64238 #define YSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
64240 #define YSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
64242 #define YSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
64244 #define YSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
64246 #define YSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
64248 #define YSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
64250 #define YSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
64252 #define YSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
64254 #define YSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
64256 #define YSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN (0x1<<13) // Enable for input completion message from PRM in prm_if block.
64258 #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN (0x1<<14) // Enable for input ack to CCFC load credit counter.
64260 #define YSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN (0x1<<15) // Enable for input ack to TCFC load credit counter.
64262 #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN (0x1<<16) // Enable for input response from CCFC in CCFC block.
64264 #define YSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
64266 #define YSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
64268 #define YSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN (0x1<<19) // Enable for input full from qm in SDM_INP block.
64271 #define YSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN (0x1<<0) // Enable for input response from TCFC in TCFC block.
64273 #define YSDM_REG_ENABLE_IN2_CM_ACK_IN_EN (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
64275 #define YSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
64278 #define YSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
64280 #define YSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN (0x1<<1) // Enable for output thread ready to the SEMI.
64282 #define YSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN (0x1<<2) // Enable the output thread release to the SEMI.
64284 #define YSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN (0x1<<3) // Enable for output load request to CCFC.
64286 #define YSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN (0x1<<4) // Enable for output load request to TCFC.
64288 #define YSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN (0x1<<5) // Enable for output increment to CCFC activity counter.
64290 #define YSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN (0x1<<6) // Enable for output decrement to TCFC activity counter.
64292 #define YSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
64294 #define YSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
64296 #define YSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
64298 #define YSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
64300 #define YSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
64302 #define YSDM_REG_ENABLE_OUT1_PXP_OUT_EN (0x1<<12) // Enable for output write to pxp in DMA_DST block.
64304 #define YSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
64306 #define YSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
64308 #define YSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN (0x1<<15) // Enable for output external full to SEMI block.
64310 #define YSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN (0x1<<16) // Enable for output done to async PXP host IF.
64312 #define YSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN (0x1<<17) // Enable the output done (ack) to PRM.
64314 #define YSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN (0x1<<18) // Enable for output message to CM in SDM_CM block.
64316 #define YSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
64318 #define YSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
64321 #define YSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN (0x1<<0) // Enable for output command to qm in SDM_INP block.
64323 #define YSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
64325 #define YSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
64328 #define YSDM_REG_DISABLE_ENGINE_DISABLE_DMA (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
64330 #define YSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
64332 #define YSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
64334 #define YSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
64336 #define YSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
64338 #define YSDM_REG_DISABLE_ENGINE_DISABLE_NOP (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
64340 #define YSDM_REG_DISABLE_ENGINE_DISABLE_GRC (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
64342 #define YSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
64344 #define YSDM_REG_DISABLE_ENGINE_DISABLE_PRM (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
64346 #define YSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
64349 #define YSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
64351 #define YSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
64353 #define YSDM_REG_INT_STS_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
64355 #define YSDM_REG_INT_STS_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
64357 #define YSDM_REG_INT_STS_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
64359 #define YSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
64361 #define YSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
64363 #define YSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
64365 #define YSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
64367 #define YSDM_REG_INT_STS_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
64369 #define YSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
64371 #define YSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
64373 #define YSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
64375 #define YSDM_REG_INT_STS_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
64377 #define YSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
64379 #define YSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
64381 #define YSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
64383 #define YSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
64385 #define YSDM_REG_INT_STS_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
64387 #define YSDM_REG_INT_STS_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
64389 #define YSDM_REG_INT_STS_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
64391 #define YSDM_REG_INT_STS_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
64393 #define YSDM_REG_INT_STS_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
64395 #define YSDM_REG_INT_STS_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
64397 #define YSDM_REG_INT_STS_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
64399 #define YSDM_REG_INT_STS_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
64401 #define YSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64403 #define YSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64406 #define YSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.ADDRESS_ERROR .
64408 #define YSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.INP_QUEUE_ERROR .
64410 #define YSDM_REG_INT_MASK_DELAY_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DELAY_FIFO_ERROR .
64412 #define YSDM_REG_INT_MASK_ASYNC_HOST_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.ASYNC_HOST_ERROR .
64414 #define YSDM_REG_INT_MASK_PRM_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.PRM_FIFO_ERROR .
64416 #define YSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
64418 #define YSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
64420 #define YSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
64422 #define YSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
64424 #define YSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
64426 #define YSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
64428 #define YSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
64430 #define YSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
64432 #define YSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
64434 #define YSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
64436 #define YSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
64438 #define YSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
64440 #define YSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
64442 #define YSDM_REG_INT_MASK_CM_DELAY_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CM_DELAY_ERROR .
64444 #define YSDM_REG_INT_MASK_SH_DELAY_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.SH_DELAY_ERROR .
64446 #define YSDM_REG_INT_MASK_CMPL_PEND_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CMPL_PEND_ERROR .
64448 #define YSDM_REG_INT_MASK_CPRM_PEND_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CPRM_PEND_ERROR .
64450 #define YSDM_REG_INT_MASK_TIMER_ADDR_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TIMER_ADDR_ERROR .
64452 #define YSDM_REG_INT_MASK_TIMER_PEND_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TIMER_PEND_ERROR .
64454 #define YSDM_REG_INT_MASK_DORQ_DPM_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DORQ_DPM_ERROR .
64456 #define YSDM_REG_INT_MASK_DST_PXP_DONE_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
64458 #define YSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
64460 #define YSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
64463 #define YSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
64465 #define YSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
64467 #define YSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
64469 #define YSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
64471 #define YSDM_REG_INT_STS_WR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
64473 #define YSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
64475 #define YSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
64477 #define YSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
64479 #define YSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
64481 #define YSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
64483 #define YSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
64485 #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
64487 #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
64489 #define YSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
64491 #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
64493 #define YSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
64495 #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
64497 #define YSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
64499 #define YSDM_REG_INT_STS_WR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
64501 #define YSDM_REG_INT_STS_WR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
64503 #define YSDM_REG_INT_STS_WR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
64505 #define YSDM_REG_INT_STS_WR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
64507 #define YSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
64509 #define YSDM_REG_INT_STS_WR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
64511 #define YSDM_REG_INT_STS_WR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
64513 #define YSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
64515 #define YSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64517 #define YSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64520 #define YSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
64522 #define YSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
64524 #define YSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
64526 #define YSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
64528 #define YSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
64530 #define YSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
64532 #define YSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
64534 #define YSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
64536 #define YSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
64538 #define YSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
64540 #define YSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
64542 #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
64544 #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
64546 #define YSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
64548 #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
64550 #define YSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
64552 #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
64554 #define YSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
64556 #define YSDM_REG_INT_STS_CLR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
64558 #define YSDM_REG_INT_STS_CLR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
64560 #define YSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
64562 #define YSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
64564 #define YSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
64566 #define YSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
64568 #define YSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
64570 #define YSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
64572 #define YSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64574 #define YSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64577 #define YSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
64579 #define YSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
64581 #define YSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
64583 #define YSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
64585 #define YSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
64587 #define YSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
64589 #define YSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
64591 #define YSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
64593 #define YSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
64597 #define YSDM_REG_TIMERS_TICK_ENABLE 0xf90404UL //Access:RW DataWidth:0x1 // Enable for tick counter.
64635 #define YSDM_REG_INT_CMPL_PEND_FULL 0xf90c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
64636 #define YSDM_REG_INT_CPRM_PEND_FULL 0xf90c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
64637 #define YSDM_REG_QM_FULL 0xf90c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
64638 #define YSDM_REG_DELAY_FIFO_FULL 0xf90c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
64639 #define YSDM_REG_TIMERS_PEND_FULL 0xf90c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
64640 #define YSDM_REG_TIMERS_ADDR_FULL 0xf90c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
64641 #define YSDM_REG_RSP_PXP_RDATA_FULL 0xf90c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
64642 #define YSDM_REG_RSP_BRB_RDATA_FULL 0xf90c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
64643 #define YSDM_REG_RSP_INT_RAM_RDATA_FULL 0xf90c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
64644 #define YSDM_REG_RSP_BRB_PEND_FULL 0xf90c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
64645 #define YSDM_REG_RSP_INT_RAM_PEND_FULL 0xf90c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
64646 #define YSDM_REG_RSP_BRB_IF_FULL 0xf90c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
64647 #define YSDM_REG_RSP_PXP_IF_FULL 0xf90c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
64648 #define YSDM_REG_DST_PXP_IMMED_FULL 0xf90c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
64649 #define YSDM_REG_DST_PXP_DST_PEND_FULL 0xf90c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
64650 #define YSDM_REG_DST_PXP_SRC_PEND_FULL 0xf90c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
64651 #define YSDM_REG_DST_BRB_SRC_PEND_FULL 0xf90c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
64652 #define YSDM_REG_DST_BRB_SRC_ADDR_FULL 0xf90c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
64653 #define YSDM_REG_DST_PXP_LINK_FULL 0xf90c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
64654 #define YSDM_REG_DST_INT_RAM_WAIT_FULL 0xf90c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
64655 #define YSDM_REG_DST_PAS_BUF_WAIT_FULL 0xf90c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
64656 #define YSDM_REG_DST_PXP_IF_FULL 0xf90c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
64657 #define YSDM_REG_DST_INT_RAM_IF_FULL 0xf90c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
64658 #define YSDM_REG_DST_PAS_BUF_IF_FULL 0xf90c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
64659 #define YSDM_REG_SH_DELAY_FULL 0xf90c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
64660 #define YSDM_REG_CM_DELAY_FULL 0xf90c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
64661 #define YSDM_REG_CMSG_QUE_FULL 0xf90c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
64662 #define YSDM_REG_CCFC_LOAD_PEND_FULL 0xf90c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface block.
64663 #define YSDM_REG_TCFC_LOAD_PEND_FULL 0xf90c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface block.
64664 #define YSDM_REG_ASYNC_HOST_FULL 0xf90c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
64665 #define YSDM_REG_PRM_FIFO_FULL 0xf90c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
64666 #define YSDM_REG_RMT_XCM_FIFO_FULL 0xf90c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interface).
64667 #define YSDM_REG_RMT_YCM_FIFO_FULL 0xf90c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interface).
64668 #define YSDM_REG_INT_CMPL_PEND_EMPTY 0xf90d00UL //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
64669 #define YSDM_REG_INT_CPRM_PEND_EMPTY 0xf90d04UL //Access:R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
64671 #define YSDM_REG_DELAY_FIFO_EMPTY 0xf90d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
64672 #define YSDM_REG_TIMERS_PEND_EMPTY 0xf90d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
64673 #define YSDM_REG_TIMERS_ADDR_EMPTY 0xf90d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
64674 #define YSDM_REG_RSP_PXP_RDATA_EMPTY 0xf90d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
64675 #define YSDM_REG_RSP_BRB_RDATA_EMPTY 0xf90d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
64676 #define YSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xf90d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
64677 #define YSDM_REG_RSP_BRB_PEND_EMPTY 0xf90d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
64678 #define YSDM_REG_RSP_INT_RAM_PEND_EMPTY 0xf90d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
64679 #define YSDM_REG_DST_PXP_IMMED_EMPTY 0xf90d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
64680 #define YSDM_REG_DST_PXP_DST_PEND_EMPTY 0xf90d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
64681 #define YSDM_REG_DST_PXP_SRC_PEND_EMPTY 0xf90d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
64682 #define YSDM_REG_DST_BRB_SRC_PEND_EMPTY 0xf90d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
64683 #define YSDM_REG_DST_BRB_SRC_ADDR_EMPTY 0xf90d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
64684 #define YSDM_REG_DST_PXP_LINK_EMPTY 0xf90d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
64685 #define YSDM_REG_DST_INT_RAM_WAIT_EMPTY 0xf90d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
64686 #define YSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xf90d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
64687 #define YSDM_REG_SH_DELAY_EMPTY 0xf90d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
64688 #define YSDM_REG_CM_DELAY_EMPTY 0xf90d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
64689 #define YSDM_REG_CMSG_QUE_EMPTY 0xf90d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
64690 #define YSDM_REG_CCFC_LOAD_PEND_EMPTY 0xf90d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
64691 #define YSDM_REG_TCFC_LOAD_PEND_EMPTY 0xf90d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
64692 #define YSDM_REG_ASYNC_HOST_EMPTY 0xf90d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
64693 #define YSDM_REG_PRM_FIFO_EMPTY 0xf90d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
64694 #define YSDM_REG_RMT_XCM_FIFO_EMPTY 0xf90d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM path).
64695 #define YSDM_REG_RMT_YCM_FIFO_EMPTY 0xf90d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM path).
64728 #define PSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN (0x1<<0) // Enable for input command from STORM.
64730 #define PSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
64732 #define PSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
64734 #define PSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
64736 #define PSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
64738 #define PSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
64740 #define PSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
64742 #define PSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
64744 #define PSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
64746 #define PSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
64748 #define PSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
64750 #define PSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
64752 #define PSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
64754 #define PSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN (0x1<<13) // Enable for input completion message from PRM in prm_if block.
64756 #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN (0x1<<14) // Enable for input ack to CCFC load credit counter.
64758 #define PSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN (0x1<<15) // Enable for input ack to TCFC load credit counter.
64760 #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN (0x1<<16) // Enable for input response from CCFC in CCFC block.
64762 #define PSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
64764 #define PSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
64766 #define PSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN (0x1<<19) // Enable for input full from qm in SDM_INP block.
64769 #define PSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN (0x1<<0) // Enable for input response from TCFC in TCFC block.
64771 #define PSDM_REG_ENABLE_IN2_CM_ACK_IN_EN (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
64773 #define PSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
64776 #define PSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
64778 #define PSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN (0x1<<1) // Enable for output thread ready to the SEMI.
64780 #define PSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN (0x1<<2) // Enable the output thread release to the SEMI.
64782 #define PSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN (0x1<<3) // Enable for output load request to CCFC.
64784 #define PSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN (0x1<<4) // Enable for output load request to TCFC.
64786 #define PSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN (0x1<<5) // Enable for output increment to CCFC activity counter.
64788 #define PSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN (0x1<<6) // Enable for output decrement to TCFC activity counter.
64790 #define PSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
64792 #define PSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
64794 #define PSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
64796 #define PSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
64798 #define PSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
64800 #define PSDM_REG_ENABLE_OUT1_PXP_OUT_EN (0x1<<12) // Enable for output write to pxp in DMA_DST block.
64802 #define PSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
64804 #define PSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
64806 #define PSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN (0x1<<15) // Enable for output external full to SEMI block.
64808 #define PSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN (0x1<<16) // Enable for output done to async PXP host IF.
64810 #define PSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN (0x1<<17) // Enable the output done (ack) to PRM.
64812 #define PSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN (0x1<<18) // Enable for output message to CM in SDM_CM block.
64814 #define PSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
64816 #define PSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
64819 #define PSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN (0x1<<0) // Enable for output command to qm in SDM_INP block.
64821 #define PSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
64823 #define PSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
64826 #define PSDM_REG_DISABLE_ENGINE_DISABLE_DMA (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
64828 #define PSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
64830 #define PSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
64832 #define PSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
64834 #define PSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
64836 #define PSDM_REG_DISABLE_ENGINE_DISABLE_NOP (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
64838 #define PSDM_REG_DISABLE_ENGINE_DISABLE_GRC (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
64840 #define PSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
64842 #define PSDM_REG_DISABLE_ENGINE_DISABLE_PRM (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
64844 #define PSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
64847 #define PSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
64849 #define PSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
64851 #define PSDM_REG_INT_STS_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
64853 #define PSDM_REG_INT_STS_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
64855 #define PSDM_REG_INT_STS_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
64857 #define PSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
64859 #define PSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
64861 #define PSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
64863 #define PSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
64865 #define PSDM_REG_INT_STS_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
64867 #define PSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
64869 #define PSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
64871 #define PSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
64873 #define PSDM_REG_INT_STS_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
64875 #define PSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
64877 #define PSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
64879 #define PSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
64881 #define PSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
64883 #define PSDM_REG_INT_STS_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
64885 #define PSDM_REG_INT_STS_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
64887 #define PSDM_REG_INT_STS_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
64889 #define PSDM_REG_INT_STS_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
64891 #define PSDM_REG_INT_STS_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
64893 #define PSDM_REG_INT_STS_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
64895 #define PSDM_REG_INT_STS_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
64897 #define PSDM_REG_INT_STS_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
64899 #define PSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64901 #define PSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
64904 #define PSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.ADDRESS_ERROR .
64906 #define PSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.INP_QUEUE_ERROR .
64908 #define PSDM_REG_INT_MASK_DELAY_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DELAY_FIFO_ERROR .
64910 #define PSDM_REG_INT_MASK_ASYNC_HOST_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.ASYNC_HOST_ERROR .
64912 #define PSDM_REG_INT_MASK_PRM_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.PRM_FIFO_ERROR .
64914 #define PSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
64916 #define PSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
64918 #define PSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
64920 #define PSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
64922 #define PSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
64924 #define PSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
64926 #define PSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
64928 #define PSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
64930 #define PSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
64932 #define PSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
64934 #define PSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
64936 #define PSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
64938 #define PSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
64940 #define PSDM_REG_INT_MASK_CM_DELAY_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CM_DELAY_ERROR .
64942 #define PSDM_REG_INT_MASK_SH_DELAY_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.SH_DELAY_ERROR .
64944 #define PSDM_REG_INT_MASK_CMPL_PEND_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CMPL_PEND_ERROR .
64946 #define PSDM_REG_INT_MASK_CPRM_PEND_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CPRM_PEND_ERROR .
64948 #define PSDM_REG_INT_MASK_TIMER_ADDR_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TIMER_ADDR_ERROR .
64950 #define PSDM_REG_INT_MASK_TIMER_PEND_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TIMER_PEND_ERROR .
64952 #define PSDM_REG_INT_MASK_DORQ_DPM_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DORQ_DPM_ERROR .
64954 #define PSDM_REG_INT_MASK_DST_PXP_DONE_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
64956 #define PSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
64958 #define PSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
64961 #define PSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
64963 #define PSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
64965 #define PSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
64967 #define PSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
64969 #define PSDM_REG_INT_STS_WR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
64971 #define PSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
64973 #define PSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
64975 #define PSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
64977 #define PSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
64979 #define PSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
64981 #define PSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
64983 #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
64985 #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
64987 #define PSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
64989 #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
64991 #define PSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
64993 #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
64995 #define PSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
64997 #define PSDM_REG_INT_STS_WR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
64999 #define PSDM_REG_INT_STS_WR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
65001 #define PSDM_REG_INT_STS_WR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
65003 #define PSDM_REG_INT_STS_WR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
65005 #define PSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
65007 #define PSDM_REG_INT_STS_WR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
65009 #define PSDM_REG_INT_STS_WR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
65011 #define PSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
65013 #define PSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65015 #define PSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65018 #define PSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
65020 #define PSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
65022 #define PSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
65024 #define PSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
65026 #define PSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
65028 #define PSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
65030 #define PSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
65032 #define PSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
65034 #define PSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
65036 #define PSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
65038 #define PSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
65040 #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
65042 #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
65044 #define PSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
65046 #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
65048 #define PSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
65050 #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
65052 #define PSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
65054 #define PSDM_REG_INT_STS_CLR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
65056 #define PSDM_REG_INT_STS_CLR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
65058 #define PSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
65060 #define PSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
65062 #define PSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
65064 #define PSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
65066 #define PSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
65068 #define PSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
65070 #define PSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65072 #define PSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65075 #define PSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
65077 #define PSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
65079 #define PSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
65081 #define PSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
65083 #define PSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
65085 #define PSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
65087 #define PSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
65089 #define PSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
65091 #define PSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
65095 #define PSDM_REG_TIMERS_TICK_ENABLE 0xfa0404UL //Access:RW DataWidth:0x1 // Enable for tick counter.
65131 #define PSDM_REG_INT_CMPL_PEND_FULL 0xfa0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
65132 #define PSDM_REG_INT_CPRM_PEND_FULL 0xfa0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
65133 #define PSDM_REG_QM_FULL 0xfa0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
65134 #define PSDM_REG_DELAY_FIFO_FULL 0xfa0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
65135 #define PSDM_REG_TIMERS_PEND_FULL 0xfa0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
65136 #define PSDM_REG_TIMERS_ADDR_FULL 0xfa0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
65137 #define PSDM_REG_RSP_PXP_RDATA_FULL 0xfa0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
65138 #define PSDM_REG_RSP_BRB_RDATA_FULL 0xfa0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
65139 #define PSDM_REG_RSP_INT_RAM_RDATA_FULL 0xfa0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
65140 #define PSDM_REG_RSP_BRB_PEND_FULL 0xfa0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
65141 #define PSDM_REG_RSP_INT_RAM_PEND_FULL 0xfa0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
65142 #define PSDM_REG_RSP_BRB_IF_FULL 0xfa0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
65143 #define PSDM_REG_RSP_PXP_IF_FULL 0xfa0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
65144 #define PSDM_REG_DST_PXP_IMMED_FULL 0xfa0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
65145 #define PSDM_REG_DST_PXP_DST_PEND_FULL 0xfa0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
65146 #define PSDM_REG_DST_PXP_SRC_PEND_FULL 0xfa0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
65147 #define PSDM_REG_DST_BRB_SRC_PEND_FULL 0xfa0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
65148 #define PSDM_REG_DST_BRB_SRC_ADDR_FULL 0xfa0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
65149 #define PSDM_REG_DST_PXP_LINK_FULL 0xfa0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
65150 #define PSDM_REG_DST_INT_RAM_WAIT_FULL 0xfa0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
65151 #define PSDM_REG_DST_PAS_BUF_WAIT_FULL 0xfa0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
65152 #define PSDM_REG_DST_PXP_IF_FULL 0xfa0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
65153 #define PSDM_REG_DST_INT_RAM_IF_FULL 0xfa0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
65154 #define PSDM_REG_DST_PAS_BUF_IF_FULL 0xfa0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
65155 #define PSDM_REG_SH_DELAY_FULL 0xfa0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
65156 #define PSDM_REG_CM_DELAY_FULL 0xfa0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
65157 #define PSDM_REG_CMSG_QUE_FULL 0xfa0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
65158 #define PSDM_REG_CCFC_LOAD_PEND_FULL 0xfa0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface block.
65159 #define PSDM_REG_TCFC_LOAD_PEND_FULL 0xfa0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface block.
65160 #define PSDM_REG_ASYNC_HOST_FULL 0xfa0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
65161 #define PSDM_REG_PRM_FIFO_FULL 0xfa0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
65162 #define PSDM_REG_RMT_XCM_FIFO_FULL 0xfa0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interface).
65163 #define PSDM_REG_RMT_YCM_FIFO_FULL 0xfa0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interface).
65164 #define PSDM_REG_INT_CMPL_PEND_EMPTY 0xfa0d00UL //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
65165 #define PSDM_REG_INT_CPRM_PEND_EMPTY 0xfa0d04UL //Access:R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
65167 #define PSDM_REG_DELAY_FIFO_EMPTY 0xfa0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
65168 #define PSDM_REG_TIMERS_PEND_EMPTY 0xfa0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
65169 #define PSDM_REG_TIMERS_ADDR_EMPTY 0xfa0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
65170 #define PSDM_REG_RSP_PXP_RDATA_EMPTY 0xfa0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
65171 #define PSDM_REG_RSP_BRB_RDATA_EMPTY 0xfa0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
65172 #define PSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xfa0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
65173 #define PSDM_REG_RSP_BRB_PEND_EMPTY 0xfa0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
65174 #define PSDM_REG_RSP_INT_RAM_PEND_EMPTY 0xfa0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
65175 #define PSDM_REG_DST_PXP_IMMED_EMPTY 0xfa0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
65176 #define PSDM_REG_DST_PXP_DST_PEND_EMPTY 0xfa0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
65177 #define PSDM_REG_DST_PXP_SRC_PEND_EMPTY 0xfa0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
65178 #define PSDM_REG_DST_BRB_SRC_PEND_EMPTY 0xfa0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
65179 #define PSDM_REG_DST_BRB_SRC_ADDR_EMPTY 0xfa0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
65180 #define PSDM_REG_DST_PXP_LINK_EMPTY 0xfa0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
65181 #define PSDM_REG_DST_INT_RAM_WAIT_EMPTY 0xfa0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
65182 #define PSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xfa0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
65183 #define PSDM_REG_SH_DELAY_EMPTY 0xfa0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
65184 #define PSDM_REG_CM_DELAY_EMPTY 0xfa0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
65185 #define PSDM_REG_CMSG_QUE_EMPTY 0xfa0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
65186 #define PSDM_REG_CCFC_LOAD_PEND_EMPTY 0xfa0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
65187 #define PSDM_REG_TCFC_LOAD_PEND_EMPTY 0xfa0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
65188 #define PSDM_REG_ASYNC_HOST_EMPTY 0xfa0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
65189 #define PSDM_REG_PRM_FIFO_EMPTY 0xfa0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
65190 #define PSDM_REG_RMT_XCM_FIFO_EMPTY 0xfa0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM path).
65191 #define PSDM_REG_RMT_YCM_FIFO_EMPTY 0xfa0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM path).
65224 #define TSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN (0x1<<0) // Enable for input command from STORM.
65226 #define TSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
65228 #define TSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
65230 #define TSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
65232 #define TSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
65234 #define TSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
65236 #define TSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
65238 #define TSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
65240 #define TSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
65242 #define TSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
65244 #define TSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
65246 #define TSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
65248 #define TSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
65250 #define TSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN (0x1<<13) // Enable for input completion message from PRM in prm_if block.
65252 #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN (0x1<<14) // Enable for input ack to CCFC load credit counter.
65254 #define TSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN (0x1<<15) // Enable for input ack to TCFC load credit counter.
65256 #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN (0x1<<16) // Enable for input response from CCFC in CCFC block.
65258 #define TSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
65260 #define TSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
65262 #define TSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN (0x1<<19) // Enable for input full from qm in SDM_INP block.
65265 #define TSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN (0x1<<0) // Enable for input response from TCFC in TCFC block.
65267 #define TSDM_REG_ENABLE_IN2_CM_ACK_IN_EN (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
65269 #define TSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
65272 #define TSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
65274 #define TSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN (0x1<<1) // Enable for output thread ready to the SEMI.
65276 #define TSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN (0x1<<2) // Enable the output thread release to the SEMI.
65278 #define TSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN (0x1<<3) // Enable for output load request to CCFC.
65280 #define TSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN (0x1<<4) // Enable for output load request to TCFC.
65282 #define TSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN (0x1<<5) // Enable for output increment to CCFC activity counter.
65284 #define TSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN (0x1<<6) // Enable for output decrement to TCFC activity counter.
65286 #define TSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
65288 #define TSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
65290 #define TSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
65292 #define TSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
65294 #define TSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
65296 #define TSDM_REG_ENABLE_OUT1_PXP_OUT_EN (0x1<<12) // Enable for output write to pxp in DMA_DST block.
65298 #define TSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
65300 #define TSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
65302 #define TSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN (0x1<<15) // Enable for output external full to SEMI block.
65304 #define TSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN (0x1<<16) // Enable for output done to async PXP host IF.
65306 #define TSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN (0x1<<17) // Enable the output done (ack) to PRM.
65308 #define TSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN (0x1<<18) // Enable for output message to CM in SDM_CM block.
65310 #define TSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
65312 #define TSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
65315 #define TSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN (0x1<<0) // Enable for output command to qm in SDM_INP block.
65317 #define TSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
65319 #define TSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
65322 #define TSDM_REG_DISABLE_ENGINE_DISABLE_DMA (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
65324 #define TSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
65326 #define TSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
65328 #define TSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
65330 #define TSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
65332 #define TSDM_REG_DISABLE_ENGINE_DISABLE_NOP (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
65334 #define TSDM_REG_DISABLE_ENGINE_DISABLE_GRC (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
65336 #define TSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
65338 #define TSDM_REG_DISABLE_ENGINE_DISABLE_PRM (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
65340 #define TSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
65343 #define TSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
65345 #define TSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
65347 #define TSDM_REG_INT_STS_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
65349 #define TSDM_REG_INT_STS_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
65351 #define TSDM_REG_INT_STS_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
65353 #define TSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
65355 #define TSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
65357 #define TSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
65359 #define TSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
65361 #define TSDM_REG_INT_STS_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
65363 #define TSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
65365 #define TSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
65367 #define TSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
65369 #define TSDM_REG_INT_STS_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
65371 #define TSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
65373 #define TSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
65375 #define TSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
65377 #define TSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
65379 #define TSDM_REG_INT_STS_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
65381 #define TSDM_REG_INT_STS_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
65383 #define TSDM_REG_INT_STS_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
65385 #define TSDM_REG_INT_STS_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
65387 #define TSDM_REG_INT_STS_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
65389 #define TSDM_REG_INT_STS_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
65391 #define TSDM_REG_INT_STS_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
65393 #define TSDM_REG_INT_STS_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
65395 #define TSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65397 #define TSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65400 #define TSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.ADDRESS_ERROR .
65402 #define TSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.INP_QUEUE_ERROR .
65404 #define TSDM_REG_INT_MASK_DELAY_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DELAY_FIFO_ERROR .
65406 #define TSDM_REG_INT_MASK_ASYNC_HOST_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.ASYNC_HOST_ERROR .
65408 #define TSDM_REG_INT_MASK_PRM_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.PRM_FIFO_ERROR .
65410 #define TSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
65412 #define TSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
65414 #define TSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
65416 #define TSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
65418 #define TSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
65420 #define TSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
65422 #define TSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
65424 #define TSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
65426 #define TSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
65428 #define TSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
65430 #define TSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
65432 #define TSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
65434 #define TSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
65436 #define TSDM_REG_INT_MASK_CM_DELAY_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CM_DELAY_ERROR .
65438 #define TSDM_REG_INT_MASK_SH_DELAY_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.SH_DELAY_ERROR .
65440 #define TSDM_REG_INT_MASK_CMPL_PEND_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CMPL_PEND_ERROR .
65442 #define TSDM_REG_INT_MASK_CPRM_PEND_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CPRM_PEND_ERROR .
65444 #define TSDM_REG_INT_MASK_TIMER_ADDR_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TIMER_ADDR_ERROR .
65446 #define TSDM_REG_INT_MASK_TIMER_PEND_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TIMER_PEND_ERROR .
65448 #define TSDM_REG_INT_MASK_DORQ_DPM_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DORQ_DPM_ERROR .
65450 #define TSDM_REG_INT_MASK_DST_PXP_DONE_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
65452 #define TSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
65454 #define TSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
65457 #define TSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
65459 #define TSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
65461 #define TSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
65463 #define TSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
65465 #define TSDM_REG_INT_STS_WR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
65467 #define TSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
65469 #define TSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
65471 #define TSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
65473 #define TSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
65475 #define TSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
65477 #define TSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
65479 #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
65481 #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
65483 #define TSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
65485 #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
65487 #define TSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
65489 #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
65491 #define TSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
65493 #define TSDM_REG_INT_STS_WR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
65495 #define TSDM_REG_INT_STS_WR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
65497 #define TSDM_REG_INT_STS_WR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
65499 #define TSDM_REG_INT_STS_WR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
65501 #define TSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
65503 #define TSDM_REG_INT_STS_WR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
65505 #define TSDM_REG_INT_STS_WR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
65507 #define TSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
65509 #define TSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65511 #define TSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65514 #define TSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
65516 #define TSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
65518 #define TSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
65520 #define TSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
65522 #define TSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
65524 #define TSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
65526 #define TSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
65528 #define TSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
65530 #define TSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
65532 #define TSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
65534 #define TSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
65536 #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
65538 #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
65540 #define TSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
65542 #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
65544 #define TSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
65546 #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
65548 #define TSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
65550 #define TSDM_REG_INT_STS_CLR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
65552 #define TSDM_REG_INT_STS_CLR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
65554 #define TSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
65556 #define TSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
65558 #define TSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
65560 #define TSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
65562 #define TSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
65564 #define TSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
65566 #define TSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65568 #define TSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65571 #define TSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
65573 #define TSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
65575 #define TSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
65577 #define TSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
65579 #define TSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
65581 #define TSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
65583 #define TSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
65585 #define TSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
65587 #define TSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
65589 #define TSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
65593 #define TSDM_REG_TIMERS_TICK_ENABLE 0xfb0404UL //Access:RW DataWidth:0x1 // Enable for tick counter.
65629 #define TSDM_REG_INT_CMPL_PEND_FULL 0xfb0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
65630 #define TSDM_REG_INT_CPRM_PEND_FULL 0xfb0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
65631 #define TSDM_REG_QM_FULL 0xfb0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
65632 #define TSDM_REG_DELAY_FIFO_FULL 0xfb0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
65633 #define TSDM_REG_TIMERS_PEND_FULL 0xfb0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
65634 #define TSDM_REG_TIMERS_ADDR_FULL 0xfb0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
65635 #define TSDM_REG_RSP_PXP_RDATA_FULL 0xfb0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
65636 #define TSDM_REG_RSP_BRB_RDATA_FULL 0xfb0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
65637 #define TSDM_REG_RSP_INT_RAM_RDATA_FULL 0xfb0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
65638 #define TSDM_REG_RSP_BRB_PEND_FULL 0xfb0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
65639 #define TSDM_REG_RSP_INT_RAM_PEND_FULL 0xfb0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
65640 #define TSDM_REG_RSP_BRB_IF_FULL 0xfb0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
65641 #define TSDM_REG_RSP_PXP_IF_FULL 0xfb0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
65642 #define TSDM_REG_DST_PXP_IMMED_FULL 0xfb0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
65643 #define TSDM_REG_DST_PXP_DST_PEND_FULL 0xfb0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
65644 #define TSDM_REG_DST_PXP_SRC_PEND_FULL 0xfb0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
65645 #define TSDM_REG_DST_BRB_SRC_PEND_FULL 0xfb0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
65646 #define TSDM_REG_DST_BRB_SRC_ADDR_FULL 0xfb0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
65647 #define TSDM_REG_DST_PXP_LINK_FULL 0xfb0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
65648 #define TSDM_REG_DST_INT_RAM_WAIT_FULL 0xfb0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
65649 #define TSDM_REG_DST_PAS_BUF_WAIT_FULL 0xfb0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
65650 #define TSDM_REG_DST_PXP_IF_FULL 0xfb0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
65651 #define TSDM_REG_DST_INT_RAM_IF_FULL 0xfb0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
65652 #define TSDM_REG_DST_PAS_BUF_IF_FULL 0xfb0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
65653 #define TSDM_REG_SH_DELAY_FULL 0xfb0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
65654 #define TSDM_REG_CM_DELAY_FULL 0xfb0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
65655 #define TSDM_REG_CMSG_QUE_FULL 0xfb0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
65656 #define TSDM_REG_CCFC_LOAD_PEND_FULL 0xfb0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface block.
65657 #define TSDM_REG_TCFC_LOAD_PEND_FULL 0xfb0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface block.
65658 #define TSDM_REG_ASYNC_HOST_FULL 0xfb0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
65659 #define TSDM_REG_PRM_FIFO_FULL 0xfb0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
65660 #define TSDM_REG_RMT_XCM_FIFO_FULL 0xfb0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interface).
65661 #define TSDM_REG_RMT_YCM_FIFO_FULL 0xfb0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interface).
65662 #define TSDM_REG_INT_CMPL_PEND_EMPTY 0xfb0d00UL //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
65663 #define TSDM_REG_INT_CPRM_PEND_EMPTY 0xfb0d04UL //Access:R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
65665 #define TSDM_REG_DELAY_FIFO_EMPTY 0xfb0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
65666 #define TSDM_REG_TIMERS_PEND_EMPTY 0xfb0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
65667 #define TSDM_REG_TIMERS_ADDR_EMPTY 0xfb0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
65668 #define TSDM_REG_RSP_PXP_RDATA_EMPTY 0xfb0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
65669 #define TSDM_REG_RSP_BRB_RDATA_EMPTY 0xfb0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
65670 #define TSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xfb0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
65671 #define TSDM_REG_RSP_BRB_PEND_EMPTY 0xfb0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
65672 #define TSDM_REG_RSP_INT_RAM_PEND_EMPTY 0xfb0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
65673 #define TSDM_REG_DST_PXP_IMMED_EMPTY 0xfb0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
65674 #define TSDM_REG_DST_PXP_DST_PEND_EMPTY 0xfb0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
65675 #define TSDM_REG_DST_PXP_SRC_PEND_EMPTY 0xfb0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
65676 #define TSDM_REG_DST_BRB_SRC_PEND_EMPTY 0xfb0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
65677 #define TSDM_REG_DST_BRB_SRC_ADDR_EMPTY 0xfb0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
65678 #define TSDM_REG_DST_PXP_LINK_EMPTY 0xfb0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
65679 #define TSDM_REG_DST_INT_RAM_WAIT_EMPTY 0xfb0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
65680 #define TSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xfb0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
65681 #define TSDM_REG_SH_DELAY_EMPTY 0xfb0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
65682 #define TSDM_REG_CM_DELAY_EMPTY 0xfb0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
65683 #define TSDM_REG_CMSG_QUE_EMPTY 0xfb0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
65684 #define TSDM_REG_CCFC_LOAD_PEND_EMPTY 0xfb0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
65685 #define TSDM_REG_TCFC_LOAD_PEND_EMPTY 0xfb0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
65686 #define TSDM_REG_ASYNC_HOST_EMPTY 0xfb0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
65687 #define TSDM_REG_PRM_FIFO_EMPTY 0xfb0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
65688 #define TSDM_REG_RMT_XCM_FIFO_EMPTY 0xfb0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM path).
65689 #define TSDM_REG_RMT_YCM_FIFO_EMPTY 0xfb0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM path).
65722 #define MSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN (0x1<<0) // Enable for input command from STORM.
65724 #define MSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
65726 #define MSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
65728 #define MSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
65730 #define MSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
65732 #define MSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
65734 #define MSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
65736 #define MSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
65738 #define MSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
65740 #define MSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
65742 #define MSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
65744 #define MSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
65746 #define MSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
65748 #define MSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN (0x1<<13) // Enable for input completion message from PRM in prm_if block.
65750 #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN (0x1<<14) // Enable for input ack to CCFC load credit counter.
65752 #define MSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN (0x1<<15) // Enable for input ack to TCFC load credit counter.
65754 #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN (0x1<<16) // Enable for input response from CCFC in CCFC block.
65756 #define MSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
65758 #define MSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
65760 #define MSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN (0x1<<19) // Enable for input full from qm in SDM_INP block.
65763 #define MSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN (0x1<<0) // Enable for input response from TCFC in TCFC block.
65765 #define MSDM_REG_ENABLE_IN2_CM_ACK_IN_EN (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
65767 #define MSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
65770 #define MSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
65772 #define MSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN (0x1<<1) // Enable for output thread ready to the SEMI.
65774 #define MSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN (0x1<<2) // Enable the output thread release to the SEMI.
65776 #define MSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN (0x1<<3) // Enable for output load request to CCFC.
65778 #define MSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN (0x1<<4) // Enable for output load request to TCFC.
65780 #define MSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN (0x1<<5) // Enable for output increment to CCFC activity counter.
65782 #define MSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN (0x1<<6) // Enable for output decrement to TCFC activity counter.
65784 #define MSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
65786 #define MSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
65788 #define MSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
65790 #define MSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
65792 #define MSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
65794 #define MSDM_REG_ENABLE_OUT1_PXP_OUT_EN (0x1<<12) // Enable for output write to pxp in DMA_DST block.
65796 #define MSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
65798 #define MSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
65800 #define MSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN (0x1<<15) // Enable for output external full to SEMI block.
65802 #define MSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN (0x1<<16) // Enable for output done to async PXP host IF.
65804 #define MSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN (0x1<<17) // Enable the output done (ack) to PRM.
65806 #define MSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN (0x1<<18) // Enable for output message to CM in SDM_CM block.
65808 #define MSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
65810 #define MSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
65813 #define MSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN (0x1<<0) // Enable for output command to qm in SDM_INP block.
65815 #define MSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
65817 #define MSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
65820 #define MSDM_REG_DISABLE_ENGINE_DISABLE_DMA (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
65822 #define MSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
65824 #define MSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
65826 #define MSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
65828 #define MSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
65830 #define MSDM_REG_DISABLE_ENGINE_DISABLE_NOP (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
65832 #define MSDM_REG_DISABLE_ENGINE_DISABLE_GRC (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
65834 #define MSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
65836 #define MSDM_REG_DISABLE_ENGINE_DISABLE_PRM (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
65838 #define MSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
65841 #define MSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
65843 #define MSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
65845 #define MSDM_REG_INT_STS_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
65847 #define MSDM_REG_INT_STS_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
65849 #define MSDM_REG_INT_STS_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
65851 #define MSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
65853 #define MSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
65855 #define MSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
65857 #define MSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
65859 #define MSDM_REG_INT_STS_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
65861 #define MSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
65863 #define MSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
65865 #define MSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
65867 #define MSDM_REG_INT_STS_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
65869 #define MSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
65871 #define MSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
65873 #define MSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
65875 #define MSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
65877 #define MSDM_REG_INT_STS_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
65879 #define MSDM_REG_INT_STS_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
65881 #define MSDM_REG_INT_STS_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
65883 #define MSDM_REG_INT_STS_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
65885 #define MSDM_REG_INT_STS_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
65887 #define MSDM_REG_INT_STS_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
65889 #define MSDM_REG_INT_STS_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
65891 #define MSDM_REG_INT_STS_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
65893 #define MSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65895 #define MSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
65898 #define MSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.ADDRESS_ERROR .
65900 #define MSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.INP_QUEUE_ERROR .
65902 #define MSDM_REG_INT_MASK_DELAY_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DELAY_FIFO_ERROR .
65904 #define MSDM_REG_INT_MASK_ASYNC_HOST_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.ASYNC_HOST_ERROR .
65906 #define MSDM_REG_INT_MASK_PRM_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.PRM_FIFO_ERROR .
65908 #define MSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
65910 #define MSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
65912 #define MSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
65914 #define MSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
65916 #define MSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
65918 #define MSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
65920 #define MSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
65922 #define MSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
65924 #define MSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
65926 #define MSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
65928 #define MSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
65930 #define MSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
65932 #define MSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
65934 #define MSDM_REG_INT_MASK_CM_DELAY_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CM_DELAY_ERROR .
65936 #define MSDM_REG_INT_MASK_SH_DELAY_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.SH_DELAY_ERROR .
65938 #define MSDM_REG_INT_MASK_CMPL_PEND_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CMPL_PEND_ERROR .
65940 #define MSDM_REG_INT_MASK_CPRM_PEND_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CPRM_PEND_ERROR .
65942 #define MSDM_REG_INT_MASK_TIMER_ADDR_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TIMER_ADDR_ERROR .
65944 #define MSDM_REG_INT_MASK_TIMER_PEND_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TIMER_PEND_ERROR .
65946 #define MSDM_REG_INT_MASK_DORQ_DPM_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DORQ_DPM_ERROR .
65948 #define MSDM_REG_INT_MASK_DST_PXP_DONE_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
65950 #define MSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
65952 #define MSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
65955 #define MSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
65957 #define MSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
65959 #define MSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
65961 #define MSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
65963 #define MSDM_REG_INT_STS_WR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
65965 #define MSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
65967 #define MSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
65969 #define MSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
65971 #define MSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
65973 #define MSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
65975 #define MSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
65977 #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
65979 #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
65981 #define MSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
65983 #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
65985 #define MSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
65987 #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
65989 #define MSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
65991 #define MSDM_REG_INT_STS_WR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
65993 #define MSDM_REG_INT_STS_WR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
65995 #define MSDM_REG_INT_STS_WR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
65997 #define MSDM_REG_INT_STS_WR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
65999 #define MSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
66001 #define MSDM_REG_INT_STS_WR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
66003 #define MSDM_REG_INT_STS_WR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
66005 #define MSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
66007 #define MSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66009 #define MSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66012 #define MSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
66014 #define MSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
66016 #define MSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
66018 #define MSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
66020 #define MSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
66022 #define MSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
66024 #define MSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
66026 #define MSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
66028 #define MSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
66030 #define MSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
66032 #define MSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
66034 #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
66036 #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
66038 #define MSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
66040 #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
66042 #define MSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
66044 #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
66046 #define MSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
66048 #define MSDM_REG_INT_STS_CLR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
66050 #define MSDM_REG_INT_STS_CLR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
66052 #define MSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
66054 #define MSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
66056 #define MSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
66058 #define MSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
66060 #define MSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
66062 #define MSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
66064 #define MSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66066 #define MSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66069 #define MSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
66071 #define MSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
66073 #define MSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
66075 #define MSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66077 #define MSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
66079 #define MSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
66081 #define MSDM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
66083 #define MSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
66085 #define MSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
66087 #define MSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66089 #define MSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
66093 #define MSDM_REG_TIMERS_TICK_ENABLE 0xfc0404UL //Access:RW DataWidth:0x1 // Enable for tick counter.
66131 #define MSDM_REG_INT_CMPL_PEND_FULL 0xfc0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
66132 #define MSDM_REG_INT_CPRM_PEND_FULL 0xfc0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
66133 #define MSDM_REG_QM_FULL 0xfc0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
66134 #define MSDM_REG_DELAY_FIFO_FULL 0xfc0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
66135 #define MSDM_REG_TIMERS_PEND_FULL 0xfc0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
66136 #define MSDM_REG_TIMERS_ADDR_FULL 0xfc0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
66137 #define MSDM_REG_RSP_PXP_RDATA_FULL 0xfc0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
66138 #define MSDM_REG_RSP_BRB_RDATA_FULL 0xfc0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
66139 #define MSDM_REG_RSP_INT_RAM_RDATA_FULL 0xfc0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
66140 #define MSDM_REG_RSP_BRB_PEND_FULL 0xfc0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
66141 #define MSDM_REG_RSP_INT_RAM_PEND_FULL 0xfc0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
66142 #define MSDM_REG_RSP_BRB_IF_FULL 0xfc0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
66143 #define MSDM_REG_RSP_PXP_IF_FULL 0xfc0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
66144 #define MSDM_REG_DST_PXP_IMMED_FULL 0xfc0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
66145 #define MSDM_REG_DST_PXP_DST_PEND_FULL 0xfc0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
66146 #define MSDM_REG_DST_PXP_SRC_PEND_FULL 0xfc0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
66147 #define MSDM_REG_DST_BRB_SRC_PEND_FULL 0xfc0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
66148 #define MSDM_REG_DST_BRB_SRC_ADDR_FULL 0xfc0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
66149 #define MSDM_REG_DST_PXP_LINK_FULL 0xfc0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
66150 #define MSDM_REG_DST_INT_RAM_WAIT_FULL 0xfc0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
66151 #define MSDM_REG_DST_PAS_BUF_WAIT_FULL 0xfc0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
66152 #define MSDM_REG_DST_PXP_IF_FULL 0xfc0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
66153 #define MSDM_REG_DST_INT_RAM_IF_FULL 0xfc0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
66154 #define MSDM_REG_DST_PAS_BUF_IF_FULL 0xfc0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
66155 #define MSDM_REG_SH_DELAY_FULL 0xfc0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
66156 #define MSDM_REG_CM_DELAY_FULL 0xfc0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
66157 #define MSDM_REG_CMSG_QUE_FULL 0xfc0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
66158 #define MSDM_REG_CCFC_LOAD_PEND_FULL 0xfc0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface block.
66159 #define MSDM_REG_TCFC_LOAD_PEND_FULL 0xfc0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface block.
66160 #define MSDM_REG_ASYNC_HOST_FULL 0xfc0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
66161 #define MSDM_REG_PRM_FIFO_FULL 0xfc0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
66162 #define MSDM_REG_RMT_XCM_FIFO_FULL 0xfc0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interface).
66163 #define MSDM_REG_RMT_YCM_FIFO_FULL 0xfc0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interface).
66164 #define MSDM_REG_INT_CMPL_PEND_EMPTY 0xfc0d00UL //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
66165 #define MSDM_REG_INT_CPRM_PEND_EMPTY 0xfc0d04UL //Access:R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
66167 #define MSDM_REG_DELAY_FIFO_EMPTY 0xfc0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
66168 #define MSDM_REG_TIMERS_PEND_EMPTY 0xfc0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
66169 #define MSDM_REG_TIMERS_ADDR_EMPTY 0xfc0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
66170 #define MSDM_REG_RSP_PXP_RDATA_EMPTY 0xfc0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
66171 #define MSDM_REG_RSP_BRB_RDATA_EMPTY 0xfc0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
66172 #define MSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xfc0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
66173 #define MSDM_REG_RSP_BRB_PEND_EMPTY 0xfc0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
66174 #define MSDM_REG_RSP_INT_RAM_PEND_EMPTY 0xfc0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
66175 #define MSDM_REG_DST_PXP_IMMED_EMPTY 0xfc0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
66176 #define MSDM_REG_DST_PXP_DST_PEND_EMPTY 0xfc0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
66177 #define MSDM_REG_DST_PXP_SRC_PEND_EMPTY 0xfc0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
66178 #define MSDM_REG_DST_BRB_SRC_PEND_EMPTY 0xfc0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
66179 #define MSDM_REG_DST_BRB_SRC_ADDR_EMPTY 0xfc0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
66180 #define MSDM_REG_DST_PXP_LINK_EMPTY 0xfc0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
66181 #define MSDM_REG_DST_INT_RAM_WAIT_EMPTY 0xfc0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
66182 #define MSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xfc0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
66183 #define MSDM_REG_SH_DELAY_EMPTY 0xfc0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
66184 #define MSDM_REG_CM_DELAY_EMPTY 0xfc0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
66185 #define MSDM_REG_CMSG_QUE_EMPTY 0xfc0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
66186 #define MSDM_REG_CCFC_LOAD_PEND_EMPTY 0xfc0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
66187 #define MSDM_REG_TCFC_LOAD_PEND_EMPTY 0xfc0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
66188 #define MSDM_REG_ASYNC_HOST_EMPTY 0xfc0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
66189 #define MSDM_REG_PRM_FIFO_EMPTY 0xfc0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
66190 #define MSDM_REG_RMT_XCM_FIFO_EMPTY 0xfc0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM path).
66191 #define MSDM_REG_RMT_YCM_FIFO_EMPTY 0xfc0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM path).
66224 #define USDM_REG_ENABLE_IN1_EXT_STORE_IN_EN (0x1<<0) // Enable for input command from STORM.
66226 #define USDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
66228 #define USDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
66230 #define USDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
66232 #define USDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
66234 #define USDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
66236 #define USDM_REG_ENABLE_IN1_PXP_DONE_IN_EN (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
66238 #define USDM_REG_ENABLE_IN1_PXP_FULL_IN_EN (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
66240 #define USDM_REG_ENABLE_IN1_PXP_DATA_IN_EN (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
66242 #define USDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
66244 #define USDM_REG_ENABLE_IN1_PXP_ACK_IN_EN (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
66246 #define USDM_REG_ENABLE_IN1_BRB_DATA_IN_EN (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
66248 #define USDM_REG_ENABLE_IN1_PXP_REQ_IN_EN (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
66250 #define USDM_REG_ENABLE_IN1_PRM_REQ_IN_EN (0x1<<13) // Enable for input completion message from PRM in prm_if block.
66252 #define USDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN (0x1<<14) // Enable for input ack to CCFC load credit counter.
66254 #define USDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN (0x1<<15) // Enable for input ack to TCFC load credit counter.
66256 #define USDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN (0x1<<16) // Enable for input response from CCFC in CCFC block.
66258 #define USDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
66260 #define USDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
66262 #define USDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN (0x1<<19) // Enable for input full from qm in SDM_INP block.
66265 #define USDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN (0x1<<0) // Enable for input response from TCFC in TCFC block.
66267 #define USDM_REG_ENABLE_IN2_CM_ACK_IN_EN (0x1<<1) // Enable for input acknowledge from Cm in SDM_CM block.
66269 #define USDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
66272 #define USDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
66274 #define USDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN (0x1<<1) // Enable for output thread ready to the SEMI.
66276 #define USDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN (0x1<<2) // Enable the output thread release to the SEMI.
66278 #define USDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN (0x1<<3) // Enable for output load request to CCFC.
66280 #define USDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN (0x1<<4) // Enable for output load request to TCFC.
66282 #define USDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN (0x1<<5) // Enable for output increment to CCFC activity counter.
66284 #define USDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN (0x1<<6) // Enable for output decrement to TCFC activity counter.
66286 #define USDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
66288 #define USDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
66290 #define USDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
66292 #define USDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
66294 #define USDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
66296 #define USDM_REG_ENABLE_OUT1_PXP_OUT_EN (0x1<<12) // Enable for output write to pxp in DMA_DST block.
66298 #define USDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
66300 #define USDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
66302 #define USDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN (0x1<<15) // Enable for output external full to SEMI block.
66304 #define USDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN (0x1<<16) // Enable for output done to async PXP host IF.
66306 #define USDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN (0x1<<17) // Enable the output done (ack) to PRM.
66308 #define USDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN (0x1<<18) // Enable for output message to CM in SDM_CM block.
66310 #define USDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
66312 #define USDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
66315 #define USDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN (0x1<<0) // Enable for output command to qm in SDM_INP block.
66317 #define USDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
66319 #define USDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
66322 #define USDM_REG_DISABLE_ENGINE_DISABLE_DMA (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
66324 #define USDM_REG_DISABLE_ENGINE_DISABLE_TIMERS (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
66326 #define USDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
66328 #define USDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
66330 #define USDM_REG_DISABLE_ENGINE_DISABLE_INT_WR (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
66332 #define USDM_REG_DISABLE_ENGINE_DISABLE_NOP (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
66334 #define USDM_REG_DISABLE_ENGINE_DISABLE_GRC (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
66336 #define USDM_REG_DISABLE_ENGINE_DISABLE_ASYNC (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
66338 #define USDM_REG_DISABLE_ENGINE_DISABLE_PRM (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
66340 #define USDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
66343 #define USDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
66345 #define USDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
66347 #define USDM_REG_INT_STS_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
66349 #define USDM_REG_INT_STS_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
66351 #define USDM_REG_INT_STS_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
66353 #define USDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
66355 #define USDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
66357 #define USDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
66359 #define USDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
66361 #define USDM_REG_INT_STS_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
66363 #define USDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
66365 #define USDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
66367 #define USDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
66369 #define USDM_REG_INT_STS_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
66371 #define USDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
66373 #define USDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
66375 #define USDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
66377 #define USDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
66379 #define USDM_REG_INT_STS_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
66381 #define USDM_REG_INT_STS_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
66383 #define USDM_REG_INT_STS_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
66385 #define USDM_REG_INT_STS_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
66387 #define USDM_REG_INT_STS_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
66389 #define USDM_REG_INT_STS_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
66391 #define USDM_REG_INT_STS_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
66393 #define USDM_REG_INT_STS_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
66395 #define USDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66397 #define USDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66400 #define USDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.ADDRESS_ERROR .
66402 #define USDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.INP_QUEUE_ERROR .
66404 #define USDM_REG_INT_MASK_DELAY_FIFO_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DELAY_FIFO_ERROR .
66406 #define USDM_REG_INT_MASK_ASYNC_HOST_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.ASYNC_HOST_ERROR .
66408 #define USDM_REG_INT_MASK_PRM_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.PRM_FIFO_ERROR .
66410 #define USDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
66412 #define USDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
66414 #define USDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
66416 #define USDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
66418 #define USDM_REG_INT_MASK_DST_PXP_IMMED_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
66420 #define USDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
66422 #define USDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
66424 #define USDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
66426 #define USDM_REG_INT_MASK_RSP_BRB_PEND_ERROR (0x1<<13) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
66428 #define USDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR (0x1<<14) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
66430 #define USDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR (0x1<<15) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
66432 #define USDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
66434 #define USDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR (0x1<<17) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
66436 #define USDM_REG_INT_MASK_CM_DELAY_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CM_DELAY_ERROR .
66438 #define USDM_REG_INT_MASK_SH_DELAY_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.SH_DELAY_ERROR .
66440 #define USDM_REG_INT_MASK_CMPL_PEND_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CMPL_PEND_ERROR .
66442 #define USDM_REG_INT_MASK_CPRM_PEND_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CPRM_PEND_ERROR .
66444 #define USDM_REG_INT_MASK_TIMER_ADDR_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TIMER_ADDR_ERROR .
66446 #define USDM_REG_INT_MASK_TIMER_PEND_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TIMER_PEND_ERROR .
66448 #define USDM_REG_INT_MASK_DORQ_DPM_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DORQ_DPM_ERROR .
66450 #define USDM_REG_INT_MASK_DST_PXP_DONE_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_DONE_ERROR .
66452 #define USDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
66454 #define USDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
66457 #define USDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
66459 #define USDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
66461 #define USDM_REG_INT_STS_WR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
66463 #define USDM_REG_INT_STS_WR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
66465 #define USDM_REG_INT_STS_WR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
66467 #define USDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
66469 #define USDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
66471 #define USDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
66473 #define USDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
66475 #define USDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
66477 #define USDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
66479 #define USDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
66481 #define USDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
66483 #define USDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
66485 #define USDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
66487 #define USDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
66489 #define USDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
66491 #define USDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
66493 #define USDM_REG_INT_STS_WR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
66495 #define USDM_REG_INT_STS_WR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
66497 #define USDM_REG_INT_STS_WR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
66499 #define USDM_REG_INT_STS_WR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
66501 #define USDM_REG_INT_STS_WR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
66503 #define USDM_REG_INT_STS_WR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
66505 #define USDM_REG_INT_STS_WR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
66507 #define USDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
66509 #define USDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66511 #define USDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66514 #define USDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
66516 #define USDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error.
66518 #define USDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
66520 #define USDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
66522 #define USDM_REG_INT_STS_CLR_PRM_FIFO_ERROR (0x1<<4) // FIFO in PRM interface sub-module reported an error.
66524 #define USDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
66526 #define USDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
66528 #define USDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
66530 #define USDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
66532 #define USDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
66534 #define USDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
66536 #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR (0x1<<11) // BRB src pend fifo error in DMA_DST block.
66538 #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR (0x1<<12) // BRB src addr fifo error in DMA_DST block.
66540 #define USDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
66542 #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
66544 #define USDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR (0x1<<15) // Read data firo in DMA_RSP block for BRB.
66546 #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
66548 #define USDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR (0x1<<17) // PXP read data fifo error in DMA_RSP block.
66550 #define USDM_REG_INT_STS_CLR_CM_DELAY_ERROR (0x1<<18) // Delay CM fifo error in CM block.
66552 #define USDM_REG_INT_STS_CLR_SH_DELAY_ERROR (0x1<<19) // Delay shared fifo error in CM block.
66554 #define USDM_REG_INT_STS_CLR_CMPL_PEND_ERROR (0x1<<20) // Error in completion pending FIFO in internal write block.
66556 #define USDM_REG_INT_STS_CLR_CPRM_PEND_ERROR (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
66558 #define USDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR (0x1<<22) // Address fifo error in timer block.
66560 #define USDM_REG_INT_STS_CLR_TIMER_PEND_ERROR (0x1<<23) // Pending fifo error in timer block.
66562 #define USDM_REG_INT_STS_CLR_DORQ_DPM_ERROR (0x1<<24) // Dpm fifo error in dorq I/F block.
66564 #define USDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR (0x1<<25) // PXP done fifo error in DMA_dst block.
66566 #define USDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66568 #define USDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface
66571 #define USDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
66573 #define USDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
66575 #define USDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66577 #define USDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
66579 #define USDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
66581 #define USDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
66583 #define USDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
66585 #define USDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
66587 #define USDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66589 #define USDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
66593 #define USDM_REG_TIMERS_TICK_ENABLE 0xfd0404UL //Access:RW DataWidth:0x1 // Enable for tick counter.
66631 #define USDM_REG_INT_CMPL_PEND_FULL 0xfd0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block.
66632 #define USDM_REG_INT_CPRM_PEND_FULL 0xfd0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block.
66633 #define USDM_REG_QM_FULL 0xfd0c0cUL //Access:R DataWidth:0x1 // QM IF full in sdm_inp block.
66634 #define USDM_REG_DELAY_FIFO_FULL 0xfd0c10UL //Access:R DataWidth:0x1 // Delay FIFO full in sdm_inp block.
66635 #define USDM_REG_TIMERS_PEND_FULL 0xfd0c14UL //Access:R DataWidth:0x1 // Pending FIFO full in sdm_timers block.
66636 #define USDM_REG_TIMERS_ADDR_FULL 0xfd0c18UL //Access:R DataWidth:0x1 // Address FIFO full in sdm_timers block.
66637 #define USDM_REG_RSP_PXP_RDATA_FULL 0xfd0c1cUL //Access:R DataWidth:0x1 // PXP rd_data fifo full in sdm_dma_rsp block.
66638 #define USDM_REG_RSP_BRB_RDATA_FULL 0xfd0c20UL //Access:R DataWidth:0x1 // BRB read data fifo full in sdm_dma_rsp block.
66639 #define USDM_REG_RSP_INT_RAM_RDATA_FULL 0xfd0c24UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo full in sdm_dma_rsp block.
66640 #define USDM_REG_RSP_BRB_PEND_FULL 0xfd0c28UL //Access:R DataWidth:0x1 // BRB pending fifo full in sdm_dma_rsp block.
66641 #define USDM_REG_RSP_INT_RAM_PEND_FULL 0xfd0c2cUL //Access:R DataWidth:0x1 // Int_ram pending fifo full in sdm_dma_rsp block.
66642 #define USDM_REG_RSP_BRB_IF_FULL 0xfd0c30UL //Access:R DataWidth:0x1 // BRB interface is full in sdm_dma_rsp block.
66643 #define USDM_REG_RSP_PXP_IF_FULL 0xfd0c34UL //Access:R DataWidth:0x1 // PXP interface is full in sdm_dma_rsp block.
66644 #define USDM_REG_DST_PXP_IMMED_FULL 0xfd0c38UL //Access:R DataWidth:0x1 // PXP immediate fifo full in sdm_dma_dst block.
66645 #define USDM_REG_DST_PXP_DST_PEND_FULL 0xfd0c3cUL //Access:R DataWidth:0x1 // PXP destination pending fifo full in sdm_dma_dst block.
66646 #define USDM_REG_DST_PXP_SRC_PEND_FULL 0xfd0c40UL //Access:R DataWidth:0x1 // PXP source pending fifo full in sdm_dma_dst block.
66647 #define USDM_REG_DST_BRB_SRC_PEND_FULL 0xfd0c44UL //Access:R DataWidth:0x1 // BRB source pending fifo full in sdm_dma_dst block.
66648 #define USDM_REG_DST_BRB_SRC_ADDR_FULL 0xfd0c48UL //Access:R DataWidth:0x1 // BRB source address fifo full in sdm_dma_dst block.
66649 #define USDM_REG_DST_PXP_LINK_FULL 0xfd0c4cUL //Access:R DataWidth:0x1 // PXP link list full in sdm_dma_dst block.
66650 #define USDM_REG_DST_INT_RAM_WAIT_FULL 0xfd0c50UL //Access:R DataWidth:0x1 // Int_ram_wait fifo full in sdm_dma_dst block.
66651 #define USDM_REG_DST_PAS_BUF_WAIT_FULL 0xfd0c54UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo full in sdm_dma_dst block.
66652 #define USDM_REG_DST_PXP_IF_FULL 0xfd0c58UL //Access:R DataWidth:0x1 // PXP if full in sdm_dma_dst block.
66653 #define USDM_REG_DST_INT_RAM_IF_FULL 0xfd0c5cUL //Access:R DataWidth:0x1 // Int_ram if full in sdm_dma_dst block.
66654 #define USDM_REG_DST_PAS_BUF_IF_FULL 0xfd0c60UL //Access:R DataWidth:0x1 // Pas_buf if full in sdm_dma_dst block.
66655 #define USDM_REG_SH_DELAY_FULL 0xfd0c64UL //Access:R DataWidth:0x1 // Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
66656 #define USDM_REG_CM_DELAY_FULL 0xfd0c68UL //Access:R DataWidth:0x1 // CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
66657 #define USDM_REG_CMSG_QUE_FULL 0xfd0c6cUL //Access:R DataWidth:0x1 // Completion message queue fifo full in sdm_cm block.
66658 #define USDM_REG_CCFC_LOAD_PEND_FULL 0xfd0c70UL //Access:R DataWidth:0x1 // CCFC load pending fifo full in the CCFC interface block.
66659 #define USDM_REG_TCFC_LOAD_PEND_FULL 0xfd0c74UL //Access:R DataWidth:0x1 // TCFC load pending fifo full in the TCFC interface block.
66660 #define USDM_REG_ASYNC_HOST_FULL 0xfd0c78UL //Access:R DataWidth:0x1 // Async fifo full in sdm_async block.
66661 #define USDM_REG_PRM_FIFO_FULL 0xfd0c7cUL //Access:R DataWidth:0x1 // PRM FIFO full in PRM interface block.
66662 #define USDM_REG_RMT_XCM_FIFO_FULL 0xfd0c80UL //Access:R DataWidth:0x1 // Remote XCM FIFO full (exist only in MSDM => XCM interface).
66663 #define USDM_REG_RMT_YCM_FIFO_FULL 0xfd0c84UL //Access:R DataWidth:0x1 // Remote YCM FIFO full (exist only in MSDM => YCM interface).
66664 #define USDM_REG_INT_CMPL_PEND_EMPTY 0xfd0d00UL //Access:R DataWidth:0x1 // Internal write completion pending empty in internal write block.
66665 #define USDM_REG_INT_CPRM_PEND_EMPTY 0xfd0d04UL //Access:R DataWidth:0x1 // Internal write completion parameter pending empty in internal write block.
66667 #define USDM_REG_DELAY_FIFO_EMPTY 0xfd0d0cUL //Access:R DataWidth:0x1 // Delay FIFO empty in sdm_inp block.
66668 #define USDM_REG_TIMERS_PEND_EMPTY 0xfd0d10UL //Access:R DataWidth:0x1 // Pending FIFO empty in sdm_timers block.
66669 #define USDM_REG_TIMERS_ADDR_EMPTY 0xfd0d14UL //Access:R DataWidth:0x1 // Address FIFO empty in sdm_timers block.
66670 #define USDM_REG_RSP_PXP_RDATA_EMPTY 0xfd0d18UL //Access:R DataWidth:0x1 // PXP rd_data fifo empty in sdm_dma_rsp block.
66671 #define USDM_REG_RSP_BRB_RDATA_EMPTY 0xfd0d1cUL //Access:R DataWidth:0x1 // BRB read data fifo empty in sdm_dma_rsp block.
66672 #define USDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xfd0d20UL //Access:R DataWidth:0x1 // Int_ram rd_data fifo empty in sdm_dma_rsp block.
66673 #define USDM_REG_RSP_BRB_PEND_EMPTY 0xfd0d24UL //Access:R DataWidth:0x1 // BRB pending fifo empty in sdm_dma_rsp block.
66674 #define USDM_REG_RSP_INT_RAM_PEND_EMPTY 0xfd0d28UL //Access:R DataWidth:0x1 // Int_ram pending fifo empty in sdm_dma_rsp block.
66675 #define USDM_REG_DST_PXP_IMMED_EMPTY 0xfd0d2cUL //Access:R DataWidth:0x1 // PXP immediate fifo empty in sdm_dma_dst block.
66676 #define USDM_REG_DST_PXP_DST_PEND_EMPTY 0xfd0d30UL //Access:R DataWidth:0x1 // PXP destination pending fifo empty in sdm_dma_dst block.
66677 #define USDM_REG_DST_PXP_SRC_PEND_EMPTY 0xfd0d34UL //Access:R DataWidth:0x1 // PXP source pending fifo empty in sdm_dma_dst block.
66678 #define USDM_REG_DST_BRB_SRC_PEND_EMPTY 0xfd0d38UL //Access:R DataWidth:0x1 // BRB source pending fifo empty in sdm_dma_dst block.
66679 #define USDM_REG_DST_BRB_SRC_ADDR_EMPTY 0xfd0d3cUL //Access:R DataWidth:0x1 // BRB source address fifo empty in sdm_dma_dst block.
66680 #define USDM_REG_DST_PXP_LINK_EMPTY 0xfd0d40UL //Access:R DataWidth:0x1 // PXP link list empty in sdm_dma_dst block.
66681 #define USDM_REG_DST_INT_RAM_WAIT_EMPTY 0xfd0d44UL //Access:R DataWidth:0x1 // Int_ram_wait fifo empty in sdm_dma_dst block.
66682 #define USDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xfd0d48UL //Access:R DataWidth:0x1 // Pas_buf_wait fifo empty in sdm_dma_dst block.
66683 #define USDM_REG_SH_DELAY_EMPTY 0xfd0d4cUL //Access:R DataWidth:0x1 // Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.
66684 #define USDM_REG_CM_DELAY_EMPTY 0xfd0d50UL //Access:R DataWidth:0x1 // CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.
66685 #define USDM_REG_CMSG_QUE_EMPTY 0xfd0d54UL //Access:R DataWidth:0x1 // Completion message queue fifo empty in sdm_dma_dst block.
66686 #define USDM_REG_CCFC_LOAD_PEND_EMPTY 0xfd0d58UL //Access:R DataWidth:0x1 // CCFC load pending fifo empty in sdm_ccfc block.
66687 #define USDM_REG_TCFC_LOAD_PEND_EMPTY 0xfd0d5cUL //Access:R DataWidth:0x1 // TCFC load pending fifo empty in sdm_tcfc block.
66688 #define USDM_REG_ASYNC_HOST_EMPTY 0xfd0d60UL //Access:R DataWidth:0x1 // Async fifo empty in sdm_async block.
66689 #define USDM_REG_PRM_FIFO_EMPTY 0xfd0d64UL //Access:R DataWidth:0x1 // PRM FIFO empty in sdm_prm_if block.
66690 #define USDM_REG_RMT_XCM_FIFO_EMPTY 0xfd0d68UL //Access:R DataWidth:0x1 // Remote XCM FIFO empty (exist only within MSDM => XCM path).
66691 #define USDM_REG_RMT_YCM_FIFO_EMPTY 0xfd0d6cUL //Access:R DataWidth:0x1 // Remote YCM FIFO empty (exist only within MSDM => YCM path).
66723 #define XCM_REG_INIT 0x1000000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
66724 #define XCM_REG_QM_ACT_ST_CNT_INIT 0x1000004UL //Access:W DataWidth:0x1 // QM Active State counter initialization trigger.
66725 #define XCM_REG_QM_ACT_ST_CNT_INIT_DONE 0x1000008UL //Access:RC DataWidth:0x1 // QM Active State counter initialization done.
66751 #define XCM_REG_EXCLUSIVE_FLG_0 0x10000c8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66752 #define XCM_REG_EXCLUSIVE_FLG_1 0x10000ccUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66753 #define XCM_REG_EXCLUSIVE_FLG_2 0x10000d0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66754 #define XCM_REG_EXCLUSIVE_FLG_3 0x10000d4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66755 #define XCM_REG_EXCLUSIVE_FLG_4 0x10000d8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66756 #define XCM_REG_EXCLUSIVE_FLG_5 0x10000dcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66757 #define XCM_REG_EXCLUSIVE_FLG_6 0x10000e0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66758 #define XCM_REG_EXCLUSIVE_FLG_7 0x10000e4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66759 #define XCM_REG_EXCLUSIVE_FLG_8 0x10000e8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66760 #define XCM_REG_EXCLUSIVE_FLG_9 0x10000ecUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66761 #define XCM_REG_EXCLUSIVE_FLG_10 0x10000f0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66762 #define XCM_REG_EXCLUSIVE_FLG_11 0x10000f4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66763 #define XCM_REG_EXCLUSIVE_FLG_12 0x10000f8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66764 #define XCM_REG_EXCLUSIVE_FLG_13 0x10000fcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66765 #define XCM_REG_EXCLUSIVE_FLG_14 0x1000100UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66766 #define XCM_REG_EXCLUSIVE_FLG_15 0x1000104UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
66793 #define XCM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
66795 #define XCM_REG_INT_STS_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
66797 #define XCM_REG_INT_STS_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
66799 #define XCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
66801 #define XCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
66803 #define XCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR (0x1<<5) // Write to full XSDM input buffer.
66805 #define XCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR (0x1<<6) // Read from empty XSDM input buffer.
66807 #define XCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR (0x1<<7) // Write to full YSDM input buffer.
66809 #define XCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR (0x1<<8) // Read from empty YSDM input buffer.
66811 #define XCM_REG_INT_STS_0_IS_USDM_OVFL_ERR (0x1<<9) // Write to full USDM input buffer.
66813 #define XCM_REG_INT_STS_0_IS_USDM_UNDER_ERR (0x1<<10) // Read from empty USDM input buffer.
66815 #define XCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR (0x1<<11) // Write to full Msem input buffer.
66817 #define XCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR (0x1<<12) // Read from empty Msem input buffer.
66819 #define XCM_REG_INT_STS_0_IS_USEM_OVFL_ERR (0x1<<13) // Write to full Usem input buffer.
66821 #define XCM_REG_INT_STS_0_IS_USEM_UNDER_ERR (0x1<<14) // Read from empty Usem input buffer.
66823 #define XCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR (0x1<<15) // Write to full Ysem input buffer.
66825 #define XCM_REG_INT_STS_0_EXT_LD_UNDER_ERR (0x1<<16) // Read from empty External read buffer.
66827 #define XCM_REG_INT_STS_0_EXT_LD_OVFL_ERR (0x1<<17) // Write to fully External read buffer.
66829 #define XCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
66831 #define XCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
66834 #define XCM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.ADDRESS_ERROR .
66836 #define XCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
66838 #define XCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
66840 #define XCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
66842 #define XCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
66844 #define XCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_XSDM_OVFL_ERR .
66846 #define XCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_XSDM_UNDER_ERR .
66848 #define XCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
66850 #define XCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
66852 #define XCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
66854 #define XCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
66856 #define XCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR (0x1<<11) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
66858 #define XCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
66860 #define XCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR (0x1<<13) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
66862 #define XCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR (0x1<<14) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
66864 #define XCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR (0x1<<15) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
66866 #define XCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR (0x1<<16) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
66868 #define XCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR (0x1<<17) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
66870 #define XCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON (0x1<<18) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
66872 #define XCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
66875 #define XCM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
66877 #define XCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
66879 #define XCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
66881 #define XCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
66883 #define XCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
66885 #define XCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR (0x1<<5) // Write to full XSDM input buffer.
66887 #define XCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR (0x1<<6) // Read from empty XSDM input buffer.
66889 #define XCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR (0x1<<7) // Write to full YSDM input buffer.
66891 #define XCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR (0x1<<8) // Read from empty YSDM input buffer.
66893 #define XCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR (0x1<<9) // Write to full USDM input buffer.
66895 #define XCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR (0x1<<10) // Read from empty USDM input buffer.
66897 #define XCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR (0x1<<11) // Write to full Msem input buffer.
66899 #define XCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR (0x1<<12) // Read from empty Msem input buffer.
66901 #define XCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR (0x1<<13) // Write to full Usem input buffer.
66903 #define XCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR (0x1<<14) // Read from empty Usem input buffer.
66905 #define XCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR (0x1<<15) // Write to full Ysem input buffer.
66907 #define XCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR (0x1<<16) // Read from empty External read buffer.
66909 #define XCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR (0x1<<17) // Write to fully External read buffer.
66911 #define XCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
66913 #define XCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
66916 #define XCM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
66918 #define XCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
66920 #define XCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
66922 #define XCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
66924 #define XCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
66926 #define XCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR (0x1<<5) // Write to full XSDM input buffer.
66928 #define XCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR (0x1<<6) // Read from empty XSDM input buffer.
66930 #define XCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR (0x1<<7) // Write to full YSDM input buffer.
66932 #define XCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR (0x1<<8) // Read from empty YSDM input buffer.
66934 #define XCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR (0x1<<9) // Write to full USDM input buffer.
66936 #define XCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR (0x1<<10) // Read from empty USDM input buffer.
66938 #define XCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR (0x1<<11) // Write to full Msem input buffer.
66940 #define XCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR (0x1<<12) // Read from empty Msem input buffer.
66942 #define XCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR (0x1<<13) // Write to full Usem input buffer.
66944 #define XCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR (0x1<<14) // Read from empty Usem input buffer.
66946 #define XCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR (0x1<<15) // Write to full Ysem input buffer.
66948 #define XCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR (0x1<<16) // Read from empty External read buffer.
66950 #define XCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR (0x1<<17) // Write to fully External read buffer.
66952 #define XCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
66954 #define XCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
66957 #define XCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
66959 #define XCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR (0x1<<1) // Write to full Dorq input buffer.
66961 #define XCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR (0x1<<2) // Read from empty Dorq input buffer.
66963 #define XCM_REG_INT_STS_1_IS_PBF_OVFL_ERR (0x1<<3) // Write to full Pbf input buffer.
66965 #define XCM_REG_INT_STS_1_IS_PBF_UNDER_ERR (0x1<<4) // Read from empty Pbf input buffer.
66967 #define XCM_REG_INT_STS_1_IS_TM_OVFL_ERR (0x1<<5) // Write to full TM input buffer.
66969 #define XCM_REG_INT_STS_1_IS_TM_UNDER_ERR (0x1<<6) // Read from empty TM input buffer.
66971 #define XCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR (0x1<<7) // Write to full QM input buffer.
66973 #define XCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR (0x1<<8) // Read from empty QM input buffer.
66975 #define XCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR (0x1<<9) // Write to full QM input buffer.
66977 #define XCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR (0x1<<10) // Read from empty QM input buffer.
66979 #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0 (0x1<<11) // Write to full GRC input buffer bits [31:0].
66981 #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0 (0x1<<12) // Read from empty GRC input buffer bits [31:0].
66983 #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1 (0x1<<13) // Write to full GRC input buffer bits [63:32].
66985 #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1 (0x1<<14) // Read from empty GRC input buffer bits [63:32].
66987 #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2 (0x1<<15) // Write to full GRC input buffer bits [95:64].
66989 #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2 (0x1<<16) // Read from empty GRC input buffer bits [95:64].
66991 #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3 (0x1<<17) // Write to full GRC input buffer bits [127:96].
66993 #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3 (0x1<<18) // Read from empty GRC input buffer bits [127:96].
66995 #define XCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL (0x1<<19) // In-process Table overflow.
66997 #define XCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
66999 #define XCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
67001 #define XCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
67003 #define XCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
67005 #define XCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // Input message first descriptor fields violation.
67008 #define XCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
67010 #define XCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
67012 #define XCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
67014 #define XCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
67016 #define XCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
67018 #define XCM_REG_INT_MASK_1_IS_TM_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
67020 #define XCM_REG_INT_MASK_1_IS_TM_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
67022 #define XCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
67024 #define XCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
67026 #define XCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
67028 #define XCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
67030 #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0 (0x1<<11) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
67032 #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0 (0x1<<12) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
67034 #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1 (0x1<<13) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
67036 #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1 (0x1<<14) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
67038 #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2 (0x1<<15) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
67040 #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2 (0x1<<16) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
67042 #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3 (0x1<<17) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
67044 #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3 (0x1<<18) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
67046 #define XCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL (0x1<<19) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
67048 #define XCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL (0x1<<20) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
67050 #define XCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL (0x1<<21) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
67052 #define XCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL (0x1<<22) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
67054 #define XCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL (0x1<<23) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
67056 #define XCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
67059 #define XCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
67061 #define XCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR (0x1<<1) // Write to full Dorq input buffer.
67063 #define XCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR (0x1<<2) // Read from empty Dorq input buffer.
67065 #define XCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR (0x1<<3) // Write to full Pbf input buffer.
67067 #define XCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR (0x1<<4) // Read from empty Pbf input buffer.
67069 #define XCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR (0x1<<5) // Write to full TM input buffer.
67071 #define XCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR (0x1<<6) // Read from empty TM input buffer.
67073 #define XCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR (0x1<<7) // Write to full QM input buffer.
67075 #define XCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR (0x1<<8) // Read from empty QM input buffer.
67077 #define XCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR (0x1<<9) // Write to full QM input buffer.
67079 #define XCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR (0x1<<10) // Read from empty QM input buffer.
67081 #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0 (0x1<<11) // Write to full GRC input buffer bits [31:0].
67083 #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0 (0x1<<12) // Read from empty GRC input buffer bits [31:0].
67085 #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1 (0x1<<13) // Write to full GRC input buffer bits [63:32].
67087 #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1 (0x1<<14) // Read from empty GRC input buffer bits [63:32].
67089 #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2 (0x1<<15) // Write to full GRC input buffer bits [95:64].
67091 #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2 (0x1<<16) // Read from empty GRC input buffer bits [95:64].
67093 #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3 (0x1<<17) // Write to full GRC input buffer bits [127:96].
67095 #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3 (0x1<<18) // Read from empty GRC input buffer bits [127:96].
67097 #define XCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL (0x1<<19) // In-process Table overflow.
67099 #define XCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
67101 #define XCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
67103 #define XCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
67105 #define XCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
67107 #define XCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // Input message first descriptor fields violation.
67110 #define XCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
67112 #define XCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR (0x1<<1) // Write to full Dorq input buffer.
67114 #define XCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR (0x1<<2) // Read from empty Dorq input buffer.
67116 #define XCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR (0x1<<3) // Write to full Pbf input buffer.
67118 #define XCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR (0x1<<4) // Read from empty Pbf input buffer.
67120 #define XCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR (0x1<<5) // Write to full TM input buffer.
67122 #define XCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR (0x1<<6) // Read from empty TM input buffer.
67124 #define XCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR (0x1<<7) // Write to full QM input buffer.
67126 #define XCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR (0x1<<8) // Read from empty QM input buffer.
67128 #define XCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR (0x1<<9) // Write to full QM input buffer.
67130 #define XCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR (0x1<<10) // Read from empty QM input buffer.
67132 #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0 (0x1<<11) // Write to full GRC input buffer bits [31:0].
67134 #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0 (0x1<<12) // Read from empty GRC input buffer bits [31:0].
67136 #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1 (0x1<<13) // Write to full GRC input buffer bits [63:32].
67138 #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1 (0x1<<14) // Read from empty GRC input buffer bits [63:32].
67140 #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2 (0x1<<15) // Write to full GRC input buffer bits [95:64].
67142 #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2 (0x1<<16) // Read from empty GRC input buffer bits [95:64].
67144 #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3 (0x1<<17) // Write to full GRC input buffer bits [127:96].
67146 #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3 (0x1<<18) // Read from empty GRC input buffer bits [127:96].
67148 #define XCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL (0x1<<19) // In-process Table overflow.
67150 #define XCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
67152 #define XCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
67154 #define XCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
67156 #define XCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
67158 #define XCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // Input message first descriptor fields violation.
67161 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
67163 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
67165 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_UNDER (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
67167 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_OVFL (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
67169 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_UNDER (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
67171 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_OVFL (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
67173 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_DROP_UNDER (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
67175 #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_ILLEG_PQNUM (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
67178 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_MSG_PRCS_UNDER .
67180 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_MSG_PRCS_OVFL .
67182 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_UNDER (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_EXT_LD_UNDER .
67184 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_OVFL (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_EXT_LD_OVFL .
67186 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_UNDER (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_RBC_UNDER .
67188 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_OVFL (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_RBC_OVFL .
67190 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_DROP_UNDER (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_DROP_UNDER .
67192 #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_ILLEG_PQNUM (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_ILLEG_PQNUM .
67195 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
67197 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
67199 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_UNDER (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
67201 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_OVFL (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
67203 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_UNDER (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
67205 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_OVFL (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
67207 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_DROP_UNDER (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
67209 #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_ILLEG_PQNUM (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
67212 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
67214 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
67216 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_UNDER (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
67218 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_OVFL (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
67220 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_UNDER (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
67222 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_OVFL (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
67224 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_DROP_UNDER (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
67226 #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
67229 #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_ECC_RF_INT .
67231 #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
67233 #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
67235 #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_2_RF_INT .
67237 #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_3_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_3_RF_INT .
67239 #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
67241 #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_0_RF_INT .
67243 #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_1_RF_INT .
67245 #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_ECC_RF_INT .
67247 #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
67249 #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
67251 #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
67253 #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
67255 #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
67257 #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
67259 #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
67261 #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
67263 #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
67265 #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
67267 #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
67269 #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
67271 #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
67273 #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
67275 #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
67277 #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
67279 #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
67281 #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
67283 #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
67285 #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
67287 #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
67289 #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
67291 #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_ECC_RF_INT .
67293 #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_0_RF_INT .
67295 #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_1_RF_INT .
67297 #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT .
67299 #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
67301 #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
67303 #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
67306 #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
67308 #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
67310 #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
67312 #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
67314 #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
67316 #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
67318 #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
67320 #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
67322 #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
67324 #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
67326 #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
67328 #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
67330 #define XCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
67333 #define XCM_REG_MEM_ECC_ENABLE_0_MEM036_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
67335 #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7
67337 #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7
67339 #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_2_EN (0x1<<3) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_con_ctx_0_7
67341 #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_3_EN (0x1<<4) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_con_ctx_0_7
67343 #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8
67345 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN (0x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
67347 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
67349 #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
67351 #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
67353 #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_0_EN (0x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
67355 #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_1_EN (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
67357 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
67360 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM036_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
67362 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7
67364 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7
67366 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_2_PRTY (0x1<<3) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_con_ctx_0_7
67368 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_3_PRTY (0x1<<4) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_con_ctx_0_7
67370 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8
67372 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY (0x1<<6) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
67374 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
67376 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
67378 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
67380 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_0_PRTY (0x1<<6) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
67382 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_1_PRTY (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
67384 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
67387 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM036_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
67389 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7
67391 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7
67393 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_2_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_2 in module xcm_mem_agg_con_ctx_0_7
67395 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_3_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_3 in module xcm_mem_agg_con_ctx_0_7
67397 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8
67399 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
67401 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
67403 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
67405 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram
67407 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_0_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13
67409 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_1_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13
67411 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14
67414 #define XCM_REG_IFEN 0x1000400UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
67463 #define XCM_REG_STORM_FRWRD_MODE 0x1000658UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67464 #define XCM_REG_XSDM_FRWRD_MODE 0x1000660UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67465 #define XCM_REG_YSDM_FRWRD_MODE 0x1000664UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67466 #define XCM_REG_USDM_FRWRD_MODE 0x1000668UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67467 #define XCM_REG_MSEM_FRWRD_MODE 0x100066cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67468 #define XCM_REG_USEM_FRWRD_MODE 0x1000670UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67469 #define XCM_REG_DORQ_FRWRD_MODE 0x1000678UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67470 #define XCM_REG_PBF_FRWRD_MODE 0x100067cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67471 #define XCM_REG_SDM_ERR_HANDLE_EN 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
67472 #define XCM_REG_DIR_BYP_EN 0x1000684UL //Access:RW DataWidth:0x1 // Direct bypass enable.
67484 #define XCM_REG_XX_IA_GROUP_PR0 0x100071cUL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
67485 #define XCM_REG_XX_IA_GROUP_PR1 0x1000720UL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
67506 #define XCM_REG_UNLOCK_MISS 0x1000794UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
67508 #define XCM_REG_ERR_EXCLUSIVE_FLG 0x100079cUL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error.
67534 #define XCM_REG_SM_CON_BUF_CRD_AGGST 0x1000844UL //Access:RW DataWidth:0x1 // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
67544 #define XCM_REG_IN_PRCS_TBL_ALMOST_FULL 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost full.
67546 #define XCM_REG_TMCON_CURR_ST 0x1000a18UL //Access:R DataWidth:0x1 // TM connection output FSM current state.
67547 #define XCM_REG_CCFC_CURR_ST 0x1000a1cUL //Access:R DataWidth:0x1 // CFC connection output FSM current state.
67549 #define XCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1000a24UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
67572 #define XCM_REG_XSDM_LENGTH_MIS 0x1000aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at XSDM interface.
67573 #define XCM_REG_YSDM_LENGTH_MIS 0x1000ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface.
67574 #define XCM_REG_USDM_LENGTH_MIS 0x1000ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at USDM interface.
67575 #define XCM_REG_DORQ_LENGTH_MIS 0x1000ab8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at the dorq interface.
67576 #define XCM_REG_PBF_LENGTH_MIS 0x1000abcUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface.
67577 #define XCM_REG_GRC_BUF_EMPTY 0x1000ac0UL //Access:R DataWidth:0x1 // Input Stage GRC buffer is empty.
67604 #define XCM_REG_QM_ACT_ST_CURR_ST 0x1000b4cUL //Access:R DataWidth:0x1 // QM Active State output FSM.
67745 #define XCM_REG_QM_CON_USE_ST_FLG_0 0x1000484UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67746 #define XCM_REG_QM_CON_USE_ST_FLG_1 0x1000488UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67747 #define XCM_REG_QM_CON_USE_ST_FLG_2 0x100048cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67748 #define XCM_REG_QM_CON_USE_ST_FLG_3 0x1000490UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67749 #define XCM_REG_QM_CON_USE_ST_FLG_4 0x1000494UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67750 #define XCM_REG_QM_CON_USE_ST_FLG_5 0x1000498UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67751 #define XCM_REG_QM_CON_USE_ST_FLG_6 0x100049cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67752 #define XCM_REG_QM_CON_USE_ST_FLG_7 0x10004a0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67753 #define XCM_REG_QM_CON_USE_ST_FLG_8 0x1001da0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67754 #define XCM_REG_QM_CON_USE_ST_FLG_9 0x1001da4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67755 #define XCM_REG_QM_CON_USE_ST_FLG_10 0x1001da8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67756 #define XCM_REG_QM_CON_USE_ST_FLG_11 0x1001dacUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67757 #define XCM_REG_QM_CON_USE_ST_FLG_12 0x1001db0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67758 #define XCM_REG_QM_CON_USE_ST_FLG_13 0x1001db4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67759 #define XCM_REG_QM_CON_USE_ST_FLG_14 0x1001db8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67760 #define XCM_REG_QM_CON_USE_ST_FLG_15 0x1001dbcUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
67761 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_0 0x1000444UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67762 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_1 0x1000448UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67763 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_2 0x100044cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67764 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_3 0x1000450UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67765 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_4 0x1000454UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67766 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_5 0x1000458UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67767 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_6 0x100045cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67768 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_7 0x1000460UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67769 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_8 0x1001de0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67770 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_9 0x1001de4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67771 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_10 0x1001de8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67772 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_11 0x1001decUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67773 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_12 0x1001df0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67774 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_13 0x1001df4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67775 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_14 0x1001df8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67776 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_15 0x1001dfcUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
67777 #define XCM_REG_EN_QINDEX_20_MERGE_0 0x1001e00UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67778 #define XCM_REG_EN_QINDEX_20_MERGE_1 0x1001e04UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67779 #define XCM_REG_EN_QINDEX_20_MERGE_2 0x1001e08UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67780 #define XCM_REG_EN_QINDEX_20_MERGE_3 0x1001e0cUL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67781 #define XCM_REG_EN_QINDEX_20_MERGE_4 0x1001e10UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67782 #define XCM_REG_EN_QINDEX_20_MERGE_5 0x1001e14UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67783 #define XCM_REG_EN_QINDEX_20_MERGE_6 0x1001e18UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67784 #define XCM_REG_EN_QINDEX_20_MERGE_7 0x1001e1cUL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67785 #define XCM_REG_EN_QINDEX_20_MERGE_8 0x1001e20UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67786 #define XCM_REG_EN_QINDEX_20_MERGE_9 0x1001e24UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67787 #define XCM_REG_EN_QINDEX_20_MERGE_10 0x1001e28UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67788 #define XCM_REG_EN_QINDEX_20_MERGE_11 0x1001e2cUL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67789 #define XCM_REG_EN_QINDEX_20_MERGE_12 0x1001e30UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67790 #define XCM_REG_EN_QINDEX_20_MERGE_13 0x1001e34UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67791 #define XCM_REG_EN_QINDEX_20_MERGE_14 0x1001e38UL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67792 #define XCM_REG_EN_QINDEX_20_MERGE_15 0x1001e3cUL //Access:RW DataWidth:0x1 // Enables QIndex 2 and 0 merge in XCM per connection type.
67794 #define XCM_REG_MSDM_FRWRD_MODE 0x100065cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67795 #define XCM_REG_MSDM_LENGTH_MIS 0x1000aa8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at MSDM interface.
67802 #define XCM_REG_YSEM_FRWRD_MODE 0x1000674UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
67812 #define YCM_REG_INIT 0x1080000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
67838 #define YCM_REG_EXCLUSIVE_FLG_0 0x10800c8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67839 #define YCM_REG_EXCLUSIVE_FLG_1 0x10800ccUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67840 #define YCM_REG_EXCLUSIVE_FLG_2 0x10800d0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67841 #define YCM_REG_EXCLUSIVE_FLG_3 0x10800d4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67842 #define YCM_REG_EXCLUSIVE_FLG_4 0x10800d8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67843 #define YCM_REG_EXCLUSIVE_FLG_5 0x10800dcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67844 #define YCM_REG_EXCLUSIVE_FLG_6 0x10800e0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67845 #define YCM_REG_EXCLUSIVE_FLG_7 0x10800e4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67846 #define YCM_REG_EXCLUSIVE_FLG_8 0x10800e8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67847 #define YCM_REG_EXCLUSIVE_FLG_9 0x10800ecUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67848 #define YCM_REG_EXCLUSIVE_FLG_10 0x10800f0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67849 #define YCM_REG_EXCLUSIVE_FLG_11 0x10800f4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67850 #define YCM_REG_EXCLUSIVE_FLG_12 0x10800f8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67851 #define YCM_REG_EXCLUSIVE_FLG_13 0x10800fcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67852 #define YCM_REG_EXCLUSIVE_FLG_14 0x1080100UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67853 #define YCM_REG_EXCLUSIVE_FLG_15 0x1080104UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
67858 #define YCM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
67860 #define YCM_REG_INT_STS_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
67862 #define YCM_REG_INT_STS_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
67864 #define YCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
67866 #define YCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
67868 #define YCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
67870 #define YCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
67872 #define YCM_REG_INT_STS_0_IS_XYLD_OVFL_ERR (0x1<<7) // Write to full XYLD input buffer.
67874 #define YCM_REG_INT_STS_0_IS_XYLD_UNDER_ERR (0x1<<8) // Read from empty XYLD input buffer.
67876 #define YCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR (0x1<<9) // Write to full Msem input buffer.
67878 #define YCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR (0x1<<10) // Read from empty Msem input buffer.
67880 #define YCM_REG_INT_STS_0_IS_USEM_OVFL_ERR (0x1<<11) // Write to full Usem input buffer.
67882 #define YCM_REG_INT_STS_0_IS_USEM_UNDER_ERR (0x1<<12) // Read from empty Usem input buffer.
67884 #define YCM_REG_INT_STS_0_EXT_LD_UNDER_ERR (0x1<<13) // Read from empty External read buffer.
67886 #define YCM_REG_INT_STS_0_EXT_LD_OVFL_ERR (0x1<<14) // Write to fully External read buffer.
67888 #define YCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON (0x1<<15) // Affinity type = 2 (connection based) but connection doesn't exist.
67890 #define YCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK (0x1<<16) // Affinity type = 3 (task based) but task doesn't exist.
67893 #define YCM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.ADDRESS_ERROR .
67895 #define YCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
67897 #define YCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
67899 #define YCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
67901 #define YCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
67903 #define YCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
67905 #define YCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
67907 #define YCM_REG_INT_MASK_0_IS_XYLD_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_XYLD_OVFL_ERR .
67909 #define YCM_REG_INT_MASK_0_IS_XYLD_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_XYLD_UNDER_ERR .
67911 #define YCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
67913 #define YCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
67915 #define YCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR (0x1<<11) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
67917 #define YCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
67919 #define YCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR (0x1<<13) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
67921 #define YCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR (0x1<<14) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
67923 #define YCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON (0x1<<15) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
67925 #define YCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK (0x1<<16) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
67928 #define YCM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
67930 #define YCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
67932 #define YCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
67934 #define YCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
67936 #define YCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
67938 #define YCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
67940 #define YCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
67942 #define YCM_REG_INT_STS_WR_0_IS_XYLD_OVFL_ERR (0x1<<7) // Write to full XYLD input buffer.
67944 #define YCM_REG_INT_STS_WR_0_IS_XYLD_UNDER_ERR (0x1<<8) // Read from empty XYLD input buffer.
67946 #define YCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR (0x1<<9) // Write to full Msem input buffer.
67948 #define YCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR (0x1<<10) // Read from empty Msem input buffer.
67950 #define YCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR (0x1<<11) // Write to full Usem input buffer.
67952 #define YCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR (0x1<<12) // Read from empty Usem input buffer.
67954 #define YCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR (0x1<<13) // Read from empty External read buffer.
67956 #define YCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR (0x1<<14) // Write to fully External read buffer.
67958 #define YCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON (0x1<<15) // Affinity type = 2 (connection based) but connection doesn't exist.
67960 #define YCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK (0x1<<16) // Affinity type = 3 (task based) but task doesn't exist.
67963 #define YCM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
67965 #define YCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
67967 #define YCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
67969 #define YCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
67971 #define YCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
67973 #define YCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
67975 #define YCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
67977 #define YCM_REG_INT_STS_CLR_0_IS_XYLD_OVFL_ERR (0x1<<7) // Write to full XYLD input buffer.
67979 #define YCM_REG_INT_STS_CLR_0_IS_XYLD_UNDER_ERR (0x1<<8) // Read from empty XYLD input buffer.
67981 #define YCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR (0x1<<9) // Write to full Msem input buffer.
67983 #define YCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR (0x1<<10) // Read from empty Msem input buffer.
67985 #define YCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR (0x1<<11) // Write to full Usem input buffer.
67987 #define YCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR (0x1<<12) // Read from empty Usem input buffer.
67989 #define YCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR (0x1<<13) // Read from empty External read buffer.
67991 #define YCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR (0x1<<14) // Write to fully External read buffer.
67993 #define YCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON (0x1<<15) // Affinity type = 2 (connection based) but connection doesn't exist.
67995 #define YCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK (0x1<<16) // Affinity type = 3 (task based) but task doesn't exist.
67998 #define YCM_REG_INT_STS_1_IS_PBF_OVFL_ERR (0x1<<0) // Write to full Pbf input buffer.
68000 #define YCM_REG_INT_STS_1_IS_PBF_UNDER_ERR (0x1<<1) // Read from empty Pbf input buffer.
68002 #define YCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR (0x1<<2) // Write to full QM input buffer.
68004 #define YCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR (0x1<<3) // Read from empty QM input buffer.
68006 #define YCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR (0x1<<4) // Write to full QM input buffer.
68008 #define YCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR (0x1<<5) // Read from empty QM input buffer.
68010 #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0 (0x1<<6) // Write to full GRC input buffer bits [31:0].
68012 #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0 (0x1<<7) // Read from empty GRC input buffer bits [31:0].
68014 #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1 (0x1<<8) // Write to full GRC input buffer bits [63:32].
68016 #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1 (0x1<<9) // Read from empty GRC input buffer bits [63:32].
68018 #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2 (0x1<<10) // Write to full GRC input buffer bits [95:64].
68020 #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2 (0x1<<11) // Read from empty GRC input buffer bits [95:64].
68022 #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3 (0x1<<12) // Write to full GRC input buffer bits [127:96].
68024 #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3 (0x1<<13) // Read from empty GRC input buffer bits [127:96].
68026 #define YCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL (0x1<<14) // In-process Table overflow.
68028 #define YCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
68030 #define YCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
68032 #define YCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
68034 #define YCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
68036 #define YCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL (0x1<<19) // Message Processor Storm Task Data buffer overflow.
68038 #define YCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL (0x1<<20) // Message Processor Storm Task Command buffer overflow.
68040 #define YCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE (0x1<<21) // Input message first descriptor fields violation.
68042 #define YCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE (0x1<<22) // Input message second descriptor fields violation.
68045 #define YCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
68047 #define YCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
68049 #define YCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
68051 #define YCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
68053 #define YCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
68055 #define YCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
68057 #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0 (0x1<<6) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
68059 #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0 (0x1<<7) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
68061 #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1 (0x1<<8) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
68063 #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1 (0x1<<9) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
68065 #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2 (0x1<<10) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
68067 #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2 (0x1<<11) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
68069 #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3 (0x1<<12) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
68071 #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3 (0x1<<13) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
68073 #define YCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL (0x1<<14) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
68075 #define YCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL (0x1<<15) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
68077 #define YCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL (0x1<<16) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
68079 #define YCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL (0x1<<17) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
68081 #define YCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL (0x1<<18) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
68083 #define YCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL (0x1<<19) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
68085 #define YCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL (0x1<<20) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
68087 #define YCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE (0x1<<21) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
68089 #define YCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE (0x1<<22) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
68092 #define YCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR (0x1<<0) // Write to full Pbf input buffer.
68094 #define YCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR (0x1<<1) // Read from empty Pbf input buffer.
68096 #define YCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR (0x1<<2) // Write to full QM input buffer.
68098 #define YCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR (0x1<<3) // Read from empty QM input buffer.
68100 #define YCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR (0x1<<4) // Write to full QM input buffer.
68102 #define YCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR (0x1<<5) // Read from empty QM input buffer.
68104 #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0 (0x1<<6) // Write to full GRC input buffer bits [31:0].
68106 #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0 (0x1<<7) // Read from empty GRC input buffer bits [31:0].
68108 #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1 (0x1<<8) // Write to full GRC input buffer bits [63:32].
68110 #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1 (0x1<<9) // Read from empty GRC input buffer bits [63:32].
68112 #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2 (0x1<<10) // Write to full GRC input buffer bits [95:64].
68114 #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2 (0x1<<11) // Read from empty GRC input buffer bits [95:64].
68116 #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3 (0x1<<12) // Write to full GRC input buffer bits [127:96].
68118 #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3 (0x1<<13) // Read from empty GRC input buffer bits [127:96].
68120 #define YCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL (0x1<<14) // In-process Table overflow.
68122 #define YCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
68124 #define YCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
68126 #define YCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
68128 #define YCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
68130 #define YCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL (0x1<<19) // Message Processor Storm Task Data buffer overflow.
68132 #define YCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL (0x1<<20) // Message Processor Storm Task Command buffer overflow.
68134 #define YCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE (0x1<<21) // Input message first descriptor fields violation.
68136 #define YCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE (0x1<<22) // Input message second descriptor fields violation.
68139 #define YCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR (0x1<<0) // Write to full Pbf input buffer.
68141 #define YCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR (0x1<<1) // Read from empty Pbf input buffer.
68143 #define YCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR (0x1<<2) // Write to full QM input buffer.
68145 #define YCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR (0x1<<3) // Read from empty QM input buffer.
68147 #define YCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR (0x1<<4) // Write to full QM input buffer.
68149 #define YCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR (0x1<<5) // Read from empty QM input buffer.
68151 #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0 (0x1<<6) // Write to full GRC input buffer bits [31:0].
68153 #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0 (0x1<<7) // Read from empty GRC input buffer bits [31:0].
68155 #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1 (0x1<<8) // Write to full GRC input buffer bits [63:32].
68157 #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1 (0x1<<9) // Read from empty GRC input buffer bits [63:32].
68159 #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2 (0x1<<10) // Write to full GRC input buffer bits [95:64].
68161 #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2 (0x1<<11) // Read from empty GRC input buffer bits [95:64].
68163 #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3 (0x1<<12) // Write to full GRC input buffer bits [127:96].
68165 #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3 (0x1<<13) // Read from empty GRC input buffer bits [127:96].
68167 #define YCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL (0x1<<14) // In-process Table overflow.
68169 #define YCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
68171 #define YCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
68173 #define YCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
68175 #define YCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
68177 #define YCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL (0x1<<19) // Message Processor Storm Task Data buffer overflow.
68179 #define YCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL (0x1<<20) // Message Processor Storm Task Command buffer overflow.
68181 #define YCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE (0x1<<21) // Input message first descriptor fields violation.
68183 #define YCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE (0x1<<22) // Input message second descriptor fields violation.
68185 #define YCM_REG_INT_STS_2 0x10801a0UL //Access:R DataWidth:0x1 // Multi Field Register.
68186 #define YCM_REG_INT_STS_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
68188 #define YCM_REG_INT_MASK_2 0x10801a4UL //Access:RW DataWidth:0x1 // Multi Field Register.
68189 #define YCM_REG_INT_MASK_2_QMREG_MORE4 (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_2.QMREG_MORE4 .
68191 #define YCM_REG_INT_STS_WR_2 0x10801a8UL //Access:WR DataWidth:0x1 // Multi Field Register.
68192 #define YCM_REG_INT_STS_WR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
68194 #define YCM_REG_INT_STS_CLR_2 0x10801acUL //Access:RC DataWidth:0x1 // Multi Field Register.
68195 #define YCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
68198 #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT .
68200 #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
68202 #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
68204 #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT .
68206 #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_1_RF_INT .
68208 #define YCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT .
68210 #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
68212 #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
68214 #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT .
68216 #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT .
68218 #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
68220 #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
68222 #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
68224 #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
68226 #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
68228 #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
68230 #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
68232 #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
68234 #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
68236 #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
68238 #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
68240 #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
68242 #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
68244 #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
68246 #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
68248 #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
68250 #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
68252 #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
68254 #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0 (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
68256 #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1 (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
68258 #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
68260 #define YCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
68262 #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
68264 #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
68266 #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
68268 #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
68270 #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
68272 #define YCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
68274 #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
68276 #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
68278 #define YCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
68281 #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
68283 #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
68285 #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
68287 #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
68292 #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
68294 #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx
68296 #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx
68298 #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
68300 #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_1_EN (0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
68302 #define YCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
68304 #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<6) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx
68306 #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<7) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_task_ctx
68308 #define YCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
68310 #define YCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
68312 #define YCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
68314 #define YCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
68316 #define YCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_1_EN (0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
68318 #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
68320 #define YCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
68322 #define YCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
68325 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
68327 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx
68329 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx
68331 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY (0x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
68333 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_1_PRTY (0x1<<4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
68335 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
68337 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<6) // Set parity only for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx
68339 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<7) // Set parity only for memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_task_ctx
68341 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY (0x1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
68343 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY (0x1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
68345 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
68347 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY (0x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
68349 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_1_PRTY (0x1<<4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
68351 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
68353 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY (0x1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
68355 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY (0x1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
68358 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
68360 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx
68362 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx
68364 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
68366 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_1_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
68368 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
68370 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx
68372 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_task_ctx.i_ecc_1 in module ycm_mem_agg_task_ctx
68374 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
68376 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
68378 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram
68380 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1
68382 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_1_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_1 in module ycm_mem_sm_con_ctx_0_1
68384 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_2.i_ecc in module ycm_mem_sm_con_ctx_2
68386 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx
68388 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx
68391 #define YCM_REG_IFEN 0x1080400UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
68408 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_0 0x10804a4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68409 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_1 0x10804a8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68410 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_2 0x10804acUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68411 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_3 0x10804b0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68412 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_4 0x10804b4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68413 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_5 0x10804b8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68414 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_6 0x10804bcUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68415 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_7 0x10804c0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
68432 #define YCM_REG_QM_TASK_USE_ST_FLG_0 0x1080544UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
68433 #define YCM_REG_QM_TASK_USE_ST_FLG_1 0x1080548UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
68434 #define YCM_REG_QM_TASK_USE_ST_FLG_2 0x108054cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
68435 #define YCM_REG_QM_TASK_USE_ST_FLG_3 0x1080550UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
68436 #define YCM_REG_QM_TASK_USE_ST_FLG_4 0x1080554UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
68437 #define YCM_REG_QM_TASK_USE_ST_FLG_5 0x1080558UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
68438 #define YCM_REG_QM_TASK_USE_ST_FLG_6 0x108055cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
68439 #define YCM_REG_QM_TASK_USE_ST_FLG_7 0x1080560UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
68457 #define YCM_REG_STORM_FRWRD_MODE 0x1080648UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
68458 #define YCM_REG_YSDM_FRWRD_MODE 0x1080650UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
68459 #define YCM_REG_XYLD_FRWRD_MODE 0x1080654UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
68460 #define YCM_REG_MSEM_FRWRD_MODE 0x1080658UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
68461 #define YCM_REG_USEM_FRWRD_MODE 0x108065cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
68462 #define YCM_REG_PBF_FRWRD_MODE 0x1080660UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
68463 #define YCM_REG_SDM_ERR_HANDLE_EN 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
68464 #define YCM_REG_DIR_BYP_EN 0x1080668UL //Access:RW DataWidth:0x1 // Direct bypass enable.
68479 #define YCM_REG_XX_IA_GROUP_PR0 0x108071cUL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
68480 #define YCM_REG_XX_IA_GROUP_PR1 0x1080720UL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
68504 #define YCM_REG_UNLOCK_MISS 0x10807a0UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
68506 #define YCM_REG_ERR_EXCLUSIVE_FLG 0x10807a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error.
68542 #define YCM_REG_SM_CON_BUF_CRD_AGGST 0x108086cUL //Access:RW DataWidth:0x1 // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
68551 #define YCM_REG_SM_TASK_BUF_CRD_AGGST 0x1080890UL //Access:RW DataWidth:0x1 // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
68593 #define YCM_REG_IN_PRCS_TBL_ALMOST_FULL 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost full.
68596 #define YCM_REG_CCFC_CURR_ST 0x1080a1cUL //Access:R DataWidth:0x1 // CFC connection output FSM current state.
68597 #define YCM_REG_TCFC_CURR_ST 0x1080a20UL //Access:R DataWidth:0x1 // CFC task output FSM current state.
68599 #define YCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1080a28UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
68600 #define YCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1080a2cUL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID.
68620 #define YCM_REG_TCFC_INCLOCK_INIT_CRD 0x1080a90UL //Access:RW DataWidth:0x1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter.
68624 #define YCM_REG_YSDM_LENGTH_MIS 0x1080aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface.
68625 #define YCM_REG_PBF_LENGTH_MIS 0x1080ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface.
68626 #define YCM_REG_XYLD_LENGTH_MIS 0x1080ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at XYLD interface.
68627 #define YCM_REG_GRC_BUF_EMPTY 0x1080ab8UL //Access:R DataWidth:0x1 // Input Stage GRC buffer is empty.
68763 #define YCM_REG_QM_CON_USE_ST_FLG_0 0x1080524UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68764 #define YCM_REG_QM_CON_USE_ST_FLG_1 0x1080528UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68765 #define YCM_REG_QM_CON_USE_ST_FLG_2 0x108052cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68766 #define YCM_REG_QM_CON_USE_ST_FLG_3 0x1080530UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68767 #define YCM_REG_QM_CON_USE_ST_FLG_4 0x1080534UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68768 #define YCM_REG_QM_CON_USE_ST_FLG_5 0x1080538UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68769 #define YCM_REG_QM_CON_USE_ST_FLG_6 0x108053cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68770 #define YCM_REG_QM_CON_USE_ST_FLG_7 0x1080540UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68771 #define YCM_REG_QM_CON_USE_ST_FLG_8 0x1081e60UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68772 #define YCM_REG_QM_CON_USE_ST_FLG_9 0x1081e64UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68773 #define YCM_REG_QM_CON_USE_ST_FLG_10 0x1081e68UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68774 #define YCM_REG_QM_CON_USE_ST_FLG_11 0x1081e6cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68775 #define YCM_REG_QM_CON_USE_ST_FLG_12 0x1081e70UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68776 #define YCM_REG_QM_CON_USE_ST_FLG_13 0x1081e74UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68777 #define YCM_REG_QM_CON_USE_ST_FLG_14 0x1081e78UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68778 #define YCM_REG_QM_CON_USE_ST_FLG_15 0x1081e7cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
68779 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_0 0x1080464UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68780 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_1 0x1080468UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68781 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_2 0x108046cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68782 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_3 0x1080470UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68783 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_4 0x1080474UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68784 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_5 0x1080478UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68785 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_6 0x108047cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68786 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_7 0x1080480UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68787 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_8 0x1081ea0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68788 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_9 0x1081ea4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68789 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_10 0x1081ea8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68790 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_11 0x1081eacUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68791 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_12 0x1081eb0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68792 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_13 0x1081eb4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68793 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_14 0x1081eb8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68794 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_15 0x1081ebcUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
68796 #define YCM_REG_MSDM_FRWRD_MODE 0x108064cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
68797 #define YCM_REG_MSDM_LENGTH_MIS 0x1080aa8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at MSDM interface.
68814 #define PCM_REG_INIT 0x1100000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
68825 #define PCM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
68827 #define PCM_REG_INT_STS_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
68829 #define PCM_REG_INT_STS_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
68831 #define PCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR (0x1<<3) // Write to full TSDM input buffer.
68833 #define PCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR (0x1<<4) // Read from empty TSDM input buffer.
68835 #define PCM_REG_INT_STS_0_EXT_LD_UNDER_ERR (0x1<<5) // Read from empty External read buffer.
68837 #define PCM_REG_INT_STS_0_EXT_LD_OVFL_ERR (0x1<<6) // Write to fully External read buffer.
68839 #define PCM_REG_INT_STS_0_IS_YPLD_OVFL_ERR (0x1<<7) // Write to full YPLD input buffer.
68841 #define PCM_REG_INT_STS_0_IS_YPLD_UNDER_ERR (0x1<<8) // Read from empty YPLD input buffer.
68843 #define PCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON (0x1<<9) // Affinity type = 2 (connection based) but connection doesn't exist.
68845 #define PCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK (0x1<<10) // Affinity type = 3 (task based) but task doesn't exist.
68848 #define PCM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.ADDRESS_ERROR .
68850 #define PCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
68852 #define PCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
68854 #define PCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_PSDM_OVFL_ERR .
68856 #define PCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_PSDM_UNDER_ERR .
68858 #define PCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
68860 #define PCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
68862 #define PCM_REG_INT_MASK_0_IS_YPLD_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_YPLD_OVFL_ERR .
68864 #define PCM_REG_INT_MASK_0_IS_YPLD_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_YPLD_UNDER_ERR .
68866 #define PCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON (0x1<<9) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
68868 #define PCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK (0x1<<10) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
68871 #define PCM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
68873 #define PCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
68875 #define PCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
68877 #define PCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR (0x1<<3) // Write to full TSDM input buffer.
68879 #define PCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR (0x1<<4) // Read from empty TSDM input buffer.
68881 #define PCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR (0x1<<5) // Read from empty External read buffer.
68883 #define PCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR (0x1<<6) // Write to fully External read buffer.
68885 #define PCM_REG_INT_STS_WR_0_IS_YPLD_OVFL_ERR (0x1<<7) // Write to full YPLD input buffer.
68887 #define PCM_REG_INT_STS_WR_0_IS_YPLD_UNDER_ERR (0x1<<8) // Read from empty YPLD input buffer.
68889 #define PCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON (0x1<<9) // Affinity type = 2 (connection based) but connection doesn't exist.
68891 #define PCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK (0x1<<10) // Affinity type = 3 (task based) but task doesn't exist.
68894 #define PCM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
68896 #define PCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
68898 #define PCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
68900 #define PCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR (0x1<<3) // Write to full TSDM input buffer.
68902 #define PCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR (0x1<<4) // Read from empty TSDM input buffer.
68904 #define PCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR (0x1<<5) // Read from empty External read buffer.
68906 #define PCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR (0x1<<6) // Write to fully External read buffer.
68908 #define PCM_REG_INT_STS_CLR_0_IS_YPLD_OVFL_ERR (0x1<<7) // Write to full YPLD input buffer.
68910 #define PCM_REG_INT_STS_CLR_0_IS_YPLD_UNDER_ERR (0x1<<8) // Read from empty YPLD input buffer.
68912 #define PCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON (0x1<<9) // Affinity type = 2 (connection based) but connection doesn't exist.
68914 #define PCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK (0x1<<10) // Affinity type = 3 (task based) but task doesn't exist.
68917 #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0 (0x1<<2) // Write to full GRC input buffer bits [31:0].
68919 #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0 (0x1<<3) // Read from empty GRC input buffer bits [31:0].
68921 #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1 (0x1<<4) // Write to full GRC input buffer bits [63:32].
68923 #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1 (0x1<<5) // Read from empty GRC input buffer bits [63:32].
68925 #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2 (0x1<<6) // Write to full GRC input buffer bits [95:64].
68927 #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2 (0x1<<7) // Read from empty GRC input buffer bits [95:64].
68929 #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3 (0x1<<8) // Write to full GRC input buffer bits [127:96].
68931 #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3 (0x1<<9) // Read from empty GRC input buffer bits [127:96].
68933 #define PCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL (0x1<<10) // In-process Table overflow.
68935 #define PCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
68937 #define PCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
68939 #define PCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE (0x1<<13) // Input message first descriptor fields violation.
68941 #define PCM_REG_INT_STS_1_IS_PBF_OVFL_ERR (0x1<<0) // Write to full Pbf input buffer.
68943 #define PCM_REG_INT_STS_1_IS_PBF_UNDER_ERR (0x1<<1) // Read from empty Pbf input buffer.
68946 #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0 (0x1<<2) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
68948 #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0 (0x1<<3) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
68950 #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1 (0x1<<4) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
68952 #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1 (0x1<<5) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
68954 #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2 (0x1<<6) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
68956 #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2 (0x1<<7) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
68958 #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3 (0x1<<8) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
68960 #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3 (0x1<<9) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
68962 #define PCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL (0x1<<10) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
68964 #define PCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL (0x1<<11) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
68966 #define PCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL (0x1<<12) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
68968 #define PCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE (0x1<<13) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
68970 #define PCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
68972 #define PCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
68975 #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0 (0x1<<2) // Write to full GRC input buffer bits [31:0].
68977 #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0 (0x1<<3) // Read from empty GRC input buffer bits [31:0].
68979 #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1 (0x1<<4) // Write to full GRC input buffer bits [63:32].
68981 #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1 (0x1<<5) // Read from empty GRC input buffer bits [63:32].
68983 #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2 (0x1<<6) // Write to full GRC input buffer bits [95:64].
68985 #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2 (0x1<<7) // Read from empty GRC input buffer bits [95:64].
68987 #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3 (0x1<<8) // Write to full GRC input buffer bits [127:96].
68989 #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3 (0x1<<9) // Read from empty GRC input buffer bits [127:96].
68991 #define PCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL (0x1<<10) // In-process Table overflow.
68993 #define PCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
68995 #define PCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
68997 #define PCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE (0x1<<13) // Input message first descriptor fields violation.
68999 #define PCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR (0x1<<0) // Write to full Pbf input buffer.
69001 #define PCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR (0x1<<1) // Read from empty Pbf input buffer.
69004 #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0 (0x1<<2) // Write to full GRC input buffer bits [31:0].
69006 #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0 (0x1<<3) // Read from empty GRC input buffer bits [31:0].
69008 #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1 (0x1<<4) // Write to full GRC input buffer bits [63:32].
69010 #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1 (0x1<<5) // Read from empty GRC input buffer bits [63:32].
69012 #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2 (0x1<<6) // Write to full GRC input buffer bits [95:64].
69014 #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2 (0x1<<7) // Read from empty GRC input buffer bits [95:64].
69016 #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3 (0x1<<8) // Write to full GRC input buffer bits [127:96].
69018 #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3 (0x1<<9) // Read from empty GRC input buffer bits [127:96].
69020 #define PCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL (0x1<<10) // In-process Table overflow.
69022 #define PCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
69024 #define PCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
69026 #define PCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE (0x1<<13) // Input message first descriptor fields violation.
69028 #define PCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR (0x1<<0) // Write to full Pbf input buffer.
69030 #define PCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR (0x1<<1) // Read from empty Pbf input buffer.
69032 #define PCM_REG_INT_STS_2 0x11001a0UL //Access:R DataWidth:0x1 // Multi Field Register.
69033 #define PCM_REG_INT_STS_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
69035 #define PCM_REG_INT_MASK_2 0x11001a4UL //Access:RW DataWidth:0x1 // Multi Field Register.
69036 #define PCM_REG_INT_MASK_2_QMREG_MORE4 (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_2.QMREG_MORE4 .
69038 #define PCM_REG_INT_STS_WR_2 0x11001a8UL //Access:WR DataWidth:0x1 // Multi Field Register.
69039 #define PCM_REG_INT_STS_WR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
69041 #define PCM_REG_INT_STS_CLR_2 0x11001acUL //Access:RC DataWidth:0x1 // Multi Field Register.
69042 #define PCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
69045 #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
69047 #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_0_RF_INT .
69049 #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_1_RF_INT .
69051 #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
69053 #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
69055 #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
69057 #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
69059 #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
69061 #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
69063 #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
69065 #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
69067 #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
69069 #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
69071 #define PCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
69073 #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
69075 #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
69077 #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT .
69079 #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_1_RF_INT .
69081 #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
69088 #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
69090 #define PCM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
69092 #define PCM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
69094 #define PCM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
69096 #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
69098 #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
69101 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
69103 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
69105 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
69107 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
69109 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
69111 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
69114 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
69116 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
69118 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
69120 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram
69122 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx
69124 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx
69127 #define PCM_REG_IFEN 0x1100400UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
69139 #define PCM_REG_STORM_FRWRD_MODE 0x1100630UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
69140 #define PCM_REG_PBF_FRWRD_MODE 0x1100638UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
69141 #define PCM_REG_SDM_ERR_HANDLE_EN 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
69142 #define PCM_REG_DIR_BYP_EN 0x1100640UL //Access:RW DataWidth:0x1 // Direct bypass enable.
69153 #define PCM_REG_XX_IA_GROUP_PR0 0x110071cUL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
69154 #define PCM_REG_XX_IA_GROUP_PR1 0x1100720UL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
69170 #define PCM_REG_UNLOCK_MISS 0x1100760UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
69172 #define PCM_REG_ERR_EXCLUSIVE_FLG 0x1100768UL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error.
69177 #define PCM_REG_SM_CON_BUF_CRD_AGGST 0x1100830UL //Access:RW DataWidth:0x1 // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
69184 #define PCM_REG_IN_PRCS_TBL_ALMOST_FULL 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost full.
69185 #define PCM_REG_CCFC_CURR_ST 0x1100a14UL //Access:R DataWidth:0x1 // CFC connection output FSM current state.
69187 #define PCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1100a1cUL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
69191 #define PCM_REG_PBF_LENGTH_MIS 0x1100aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface.
69192 #define PCM_REG_GRC_BUF_EMPTY 0x1100ab0UL //Access:R DataWidth:0x1 // Input Stage GRC buffer is empty.
69233 #define PCM_REG_PSDM_FRWRD_MODE 0x1100634UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
69234 #define PCM_REG_PSDM_LENGTH_MIS 0x1100aa8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PSDM interface.
69241 #define PCM_REG_YPLD_LENGTH_MIS 0x11017c4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YPLD interface.
69249 #define TCM_REG_INIT 0x1180000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
69275 #define TCM_REG_EXCLUSIVE_FLG_0 0x11800c8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69276 #define TCM_REG_EXCLUSIVE_FLG_1 0x11800ccUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69277 #define TCM_REG_EXCLUSIVE_FLG_2 0x11800d0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69278 #define TCM_REG_EXCLUSIVE_FLG_3 0x11800d4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69279 #define TCM_REG_EXCLUSIVE_FLG_4 0x11800d8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69280 #define TCM_REG_EXCLUSIVE_FLG_5 0x11800dcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69281 #define TCM_REG_EXCLUSIVE_FLG_6 0x11800e0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69282 #define TCM_REG_EXCLUSIVE_FLG_7 0x11800e4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69283 #define TCM_REG_EXCLUSIVE_FLG_8 0x11800e8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69284 #define TCM_REG_EXCLUSIVE_FLG_9 0x11800ecUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69285 #define TCM_REG_EXCLUSIVE_FLG_10 0x11800f0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69286 #define TCM_REG_EXCLUSIVE_FLG_11 0x11800f4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69287 #define TCM_REG_EXCLUSIVE_FLG_12 0x11800f8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69288 #define TCM_REG_EXCLUSIVE_FLG_13 0x11800fcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69289 #define TCM_REG_EXCLUSIVE_FLG_14 0x1180100UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69290 #define TCM_REG_EXCLUSIVE_FLG_15 0x1180104UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
69304 #define TCM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
69306 #define TCM_REG_INT_STS_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
69308 #define TCM_REG_INT_STS_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
69310 #define TCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
69312 #define TCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
69314 #define TCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR (0x1<<3) // Write to full TSDM input buffer.
69316 #define TCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR (0x1<<4) // Read from empty TSDM input buffer.
69318 #define TCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR (0x1<<7) // Write to full PSDM input buffer.
69320 #define TCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR (0x1<<8) // Read from empty PSDM input buffer.
69322 #define TCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR (0x1<<5) // Write to full Msem input buffer.
69324 #define TCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR (0x1<<6) // Read from empty Msem input buffer.
69326 #define TCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR (0x1<<7) // Write to full Ysem input buffer.
69328 #define TCM_REG_INT_STS_0_EXT_LD_UNDER_ERR (0x1<<12) // Read from empty External read buffer.
69330 #define TCM_REG_INT_STS_0_EXT_LD_OVFL_ERR (0x1<<13) // Write to fully External read buffer.
69332 #define TCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON (0x1<<14) // Affinity type = 2 (connection based) but connection doesn't exist.
69334 #define TCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK (0x1<<15) // Affinity type = 3 (task based) but task doesn't exist.
69337 #define TCM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.ADDRESS_ERROR .
69339 #define TCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
69341 #define TCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
69343 #define TCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
69345 #define TCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
69347 #define TCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_OVFL_ERR .
69349 #define TCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_UNDER_ERR .
69351 #define TCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_PSDM_OVFL_ERR .
69353 #define TCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_PSDM_UNDER_ERR .
69355 #define TCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
69357 #define TCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
69359 #define TCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
69361 #define TCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
69363 #define TCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR (0x1<<13) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
69365 #define TCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON (0x1<<14) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
69367 #define TCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK (0x1<<15) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
69370 #define TCM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
69372 #define TCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
69374 #define TCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
69376 #define TCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
69378 #define TCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
69380 #define TCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR (0x1<<3) // Write to full TSDM input buffer.
69382 #define TCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR (0x1<<4) // Read from empty TSDM input buffer.
69384 #define TCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR (0x1<<7) // Write to full PSDM input buffer.
69386 #define TCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR (0x1<<8) // Read from empty PSDM input buffer.
69388 #define TCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR (0x1<<5) // Write to full Msem input buffer.
69390 #define TCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR (0x1<<6) // Read from empty Msem input buffer.
69392 #define TCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR (0x1<<7) // Write to full Ysem input buffer.
69394 #define TCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR (0x1<<12) // Read from empty External read buffer.
69396 #define TCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR (0x1<<13) // Write to fully External read buffer.
69398 #define TCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON (0x1<<14) // Affinity type = 2 (connection based) but connection doesn't exist.
69400 #define TCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK (0x1<<15) // Affinity type = 3 (task based) but task doesn't exist.
69403 #define TCM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
69405 #define TCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
69407 #define TCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
69409 #define TCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
69411 #define TCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
69413 #define TCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR (0x1<<3) // Write to full TSDM input buffer.
69415 #define TCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR (0x1<<4) // Read from empty TSDM input buffer.
69417 #define TCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR (0x1<<7) // Write to full PSDM input buffer.
69419 #define TCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR (0x1<<8) // Read from empty PSDM input buffer.
69421 #define TCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR (0x1<<5) // Write to full Msem input buffer.
69423 #define TCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR (0x1<<6) // Read from empty Msem input buffer.
69425 #define TCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR (0x1<<7) // Write to full Ysem input buffer.
69427 #define TCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR (0x1<<12) // Read from empty External read buffer.
69429 #define TCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR (0x1<<13) // Write to fully External read buffer.
69431 #define TCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON (0x1<<14) // Affinity type = 2 (connection based) but connection doesn't exist.
69433 #define TCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK (0x1<<15) // Affinity type = 3 (task based) but task doesn't exist.
69436 #define TCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
69438 #define TCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR (0x1<<1) // Write to full Dorq input buffer.
69440 #define TCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR (0x1<<2) // Read from empty Dorq input buffer.
69442 #define TCM_REG_INT_STS_1_IS_PBF_OVFL_ERR (0x1<<3) // Write to full Pbf input buffer.
69444 #define TCM_REG_INT_STS_1_IS_PBF_UNDER_ERR (0x1<<4) // Read from empty Pbf input buffer.
69446 #define TCM_REG_INT_STS_1_IS_PTLD_OVFL_ERR (0x1<<5) // Write to full PTLD input buffer.
69448 #define TCM_REG_INT_STS_1_IS_PTLD_UNDER_ERR (0x1<<6) // Read from empty PTLD input buffer.
69450 #define TCM_REG_INT_STS_1_IS_TM_OVFL_ERR (0x1<<7) // Write to full TM input buffer.
69452 #define TCM_REG_INT_STS_1_IS_TM_UNDER_ERR (0x1<<8) // Read from empty TM input buffer.
69454 #define TCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR (0x1<<9) // Write to full QM input buffer.
69456 #define TCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR (0x1<<10) // Read from empty QM input buffer.
69458 #define TCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR (0x1<<11) // Write to full QM input buffer.
69460 #define TCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR (0x1<<12) // Read from empty QM input buffer.
69462 #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0 (0x1<<13) // Write to full GRC input buffer bits [31:0].
69464 #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0 (0x1<<14) // Read from empty GRC input buffer bits [31:0].
69466 #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1 (0x1<<15) // Write to full GRC input buffer bits [63:32].
69468 #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1 (0x1<<16) // Read from empty GRC input buffer bits [63:32].
69470 #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2 (0x1<<17) // Write to full GRC input buffer bits [95:64].
69472 #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2 (0x1<<18) // Read from empty GRC input buffer bits [95:64].
69474 #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3 (0x1<<19) // Write to full GRC input buffer bits [127:96].
69476 #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3 (0x1<<20) // Read from empty GRC input buffer bits [127:96].
69478 #define TCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL (0x1<<21) // In-process Table overflow.
69480 #define TCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
69482 #define TCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
69484 #define TCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
69486 #define TCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
69488 #define TCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
69490 #define TCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
69492 #define TCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL (0x1<<28) // Message Processor Storm Task Data buffer overflow.
69494 #define TCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL (0x1<<29) // Message Processor Storm Task Command buffer overflow.
69496 #define TCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE (0x1<<30) // Input message first descriptor fields violation.
69498 #define TCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE (0x1<<31) // Input message second descriptor fields violation.
69500 #define TCM_REG_INT_STS_1_IS_PRS_OVFL_ERR (0x1<<5) // Write to full Pbf input buffer.
69502 #define TCM_REG_INT_STS_1_IS_PRS_UNDER_ERR (0x1<<6) // Read from empty Pbf input buffer.
69505 #define TCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
69507 #define TCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
69509 #define TCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
69511 #define TCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
69513 #define TCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
69515 #define TCM_REG_INT_MASK_1_IS_PTLD_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PTLD_OVFL_ERR .
69517 #define TCM_REG_INT_MASK_1_IS_PTLD_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PTLD_UNDER_ERR .
69519 #define TCM_REG_INT_MASK_1_IS_TM_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
69521 #define TCM_REG_INT_MASK_1_IS_TM_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
69523 #define TCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
69525 #define TCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
69527 #define TCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR (0x1<<11) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
69529 #define TCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
69531 #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0 (0x1<<13) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
69533 #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0 (0x1<<14) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
69535 #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1 (0x1<<15) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
69537 #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1 (0x1<<16) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
69539 #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2 (0x1<<17) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
69541 #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2 (0x1<<18) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
69543 #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3 (0x1<<19) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
69545 #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3 (0x1<<20) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
69547 #define TCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL (0x1<<21) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
69549 #define TCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL (0x1<<22) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
69551 #define TCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL (0x1<<23) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
69553 #define TCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL (0x1<<24) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
69555 #define TCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL (0x1<<25) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
69557 #define TCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL (0x1<<26) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
69559 #define TCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL (0x1<<27) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
69561 #define TCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL (0x1<<28) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
69563 #define TCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL (0x1<<29) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
69565 #define TCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE (0x1<<30) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
69567 #define TCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE (0x1<<31) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
69569 #define TCM_REG_INT_MASK_1_IS_PRS_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PRS_OVFL_ERR .
69571 #define TCM_REG_INT_MASK_1_IS_PRS_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PRS_UNDER_ERR .
69574 #define TCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
69576 #define TCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR (0x1<<1) // Write to full Dorq input buffer.
69578 #define TCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR (0x1<<2) // Read from empty Dorq input buffer.
69580 #define TCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR (0x1<<3) // Write to full Pbf input buffer.
69582 #define TCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR (0x1<<4) // Read from empty Pbf input buffer.
69584 #define TCM_REG_INT_STS_WR_1_IS_PTLD_OVFL_ERR (0x1<<5) // Write to full PTLD input buffer.
69586 #define TCM_REG_INT_STS_WR_1_IS_PTLD_UNDER_ERR (0x1<<6) // Read from empty PTLD input buffer.
69588 #define TCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR (0x1<<7) // Write to full TM input buffer.
69590 #define TCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR (0x1<<8) // Read from empty TM input buffer.
69592 #define TCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR (0x1<<9) // Write to full QM input buffer.
69594 #define TCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR (0x1<<10) // Read from empty QM input buffer.
69596 #define TCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR (0x1<<11) // Write to full QM input buffer.
69598 #define TCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR (0x1<<12) // Read from empty QM input buffer.
69600 #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0 (0x1<<13) // Write to full GRC input buffer bits [31:0].
69602 #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0 (0x1<<14) // Read from empty GRC input buffer bits [31:0].
69604 #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1 (0x1<<15) // Write to full GRC input buffer bits [63:32].
69606 #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1 (0x1<<16) // Read from empty GRC input buffer bits [63:32].
69608 #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2 (0x1<<17) // Write to full GRC input buffer bits [95:64].
69610 #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2 (0x1<<18) // Read from empty GRC input buffer bits [95:64].
69612 #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3 (0x1<<19) // Write to full GRC input buffer bits [127:96].
69614 #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3 (0x1<<20) // Read from empty GRC input buffer bits [127:96].
69616 #define TCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL (0x1<<21) // In-process Table overflow.
69618 #define TCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
69620 #define TCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
69622 #define TCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
69624 #define TCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
69626 #define TCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
69628 #define TCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
69630 #define TCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL (0x1<<28) // Message Processor Storm Task Data buffer overflow.
69632 #define TCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL (0x1<<29) // Message Processor Storm Task Command buffer overflow.
69634 #define TCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE (0x1<<30) // Input message first descriptor fields violation.
69636 #define TCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE (0x1<<31) // Input message second descriptor fields violation.
69638 #define TCM_REG_INT_STS_WR_1_IS_PRS_OVFL_ERR (0x1<<5) // Write to full Pbf input buffer.
69640 #define TCM_REG_INT_STS_WR_1_IS_PRS_UNDER_ERR (0x1<<6) // Read from empty Pbf input buffer.
69643 #define TCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
69645 #define TCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR (0x1<<1) // Write to full Dorq input buffer.
69647 #define TCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR (0x1<<2) // Read from empty Dorq input buffer.
69649 #define TCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR (0x1<<3) // Write to full Pbf input buffer.
69651 #define TCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR (0x1<<4) // Read from empty Pbf input buffer.
69653 #define TCM_REG_INT_STS_CLR_1_IS_PTLD_OVFL_ERR (0x1<<5) // Write to full PTLD input buffer.
69655 #define TCM_REG_INT_STS_CLR_1_IS_PTLD_UNDER_ERR (0x1<<6) // Read from empty PTLD input buffer.
69657 #define TCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR (0x1<<7) // Write to full TM input buffer.
69659 #define TCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR (0x1<<8) // Read from empty TM input buffer.
69661 #define TCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR (0x1<<9) // Write to full QM input buffer.
69663 #define TCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR (0x1<<10) // Read from empty QM input buffer.
69665 #define TCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR (0x1<<11) // Write to full QM input buffer.
69667 #define TCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR (0x1<<12) // Read from empty QM input buffer.
69669 #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0 (0x1<<13) // Write to full GRC input buffer bits [31:0].
69671 #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0 (0x1<<14) // Read from empty GRC input buffer bits [31:0].
69673 #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1 (0x1<<15) // Write to full GRC input buffer bits [63:32].
69675 #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1 (0x1<<16) // Read from empty GRC input buffer bits [63:32].
69677 #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2 (0x1<<17) // Write to full GRC input buffer bits [95:64].
69679 #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2 (0x1<<18) // Read from empty GRC input buffer bits [95:64].
69681 #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3 (0x1<<19) // Write to full GRC input buffer bits [127:96].
69683 #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3 (0x1<<20) // Read from empty GRC input buffer bits [127:96].
69685 #define TCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL (0x1<<21) // In-process Table overflow.
69687 #define TCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
69689 #define TCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
69691 #define TCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
69693 #define TCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
69695 #define TCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
69697 #define TCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
69699 #define TCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL (0x1<<28) // Message Processor Storm Task Data buffer overflow.
69701 #define TCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL (0x1<<29) // Message Processor Storm Task Command buffer overflow.
69703 #define TCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE (0x1<<30) // Input message first descriptor fields violation.
69705 #define TCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE (0x1<<31) // Input message second descriptor fields violation.
69707 #define TCM_REG_INT_STS_CLR_1_IS_PRS_OVFL_ERR (0x1<<5) // Write to full Pbf input buffer.
69709 #define TCM_REG_INT_STS_CLR_1_IS_PRS_UNDER_ERR (0x1<<6) // Read from empty Pbf input buffer.
69711 #define TCM_REG_INT_STS_2 0x11801a0UL //Access:R DataWidth:0x1 // Multi Field Register.
69712 #define TCM_REG_INT_STS_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
69714 #define TCM_REG_INT_MASK_2 0x11801a4UL //Access:RW DataWidth:0x1 // Multi Field Register.
69715 #define TCM_REG_INT_MASK_2_QMREG_MORE4 (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_2.QMREG_MORE4 .
69717 #define TCM_REG_INT_STS_WR_2 0x11801a8UL //Access:WR DataWidth:0x1 // Multi Field Register.
69718 #define TCM_REG_INT_STS_WR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
69720 #define TCM_REG_INT_STS_CLR_2 0x11801acUL //Access:RC DataWidth:0x1 // Multi Field Register.
69721 #define TCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
69724 #define TCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
69726 #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
69728 #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
69730 #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT .
69732 #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_1_RF_INT .
69734 #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
69736 #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
69738 #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
69740 #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
69742 #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
69744 #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
69746 #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
69748 #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
69750 #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
69752 #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
69754 #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
69756 #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
69758 #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
69760 #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
69762 #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
69764 #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
69766 #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
69768 #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
69770 #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
69772 #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
69774 #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
69776 #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
69778 #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
69780 #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0 (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
69782 #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1 (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
69784 #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
69786 #define TCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
69788 #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
69790 #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
69792 #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
69794 #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
69796 #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
69798 #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
69800 #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
69802 #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
69805 #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
69807 #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
69809 #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
69812 #define TCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
69814 #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx.i_ecc_0 in module tcm_mem_agg_con_ctx
69816 #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx.i_ecc_1 in module tcm_mem_agg_con_ctx
69818 #define TCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN (0x1<<3) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
69820 #define TCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_1_EN (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
69822 #define TCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<5) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx
69824 #define TCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<6) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx
69826 #define TCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN (0x1<<7) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
69828 #define TCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
69830 #define TCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
69832 #define TCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN (0x1<<3) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
69834 #define TCM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_1_EN (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
69836 #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN (0x1<<7) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
69838 #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
69841 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
69843 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance tcm.i_agg_con_ctx.i_ecc_0 in module tcm_mem_agg_con_ctx
69845 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance tcm.i_agg_con_ctx.i_ecc_1 in module tcm_mem_agg_con_ctx
69847 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY (0x1<<3) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
69849 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_1_PRTY (0x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
69851 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<5) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx
69853 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<6) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx
69855 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY (0x1<<7) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
69857 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY (0x1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
69859 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
69861 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY (0x1<<3) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
69863 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_1_PRTY (0x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
69865 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY (0x1<<7) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
69867 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY (0x1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
69870 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
69872 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_con_ctx.i_ecc_0 in module tcm_mem_agg_con_ctx
69874 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_con_ctx.i_ecc_1 in module tcm_mem_agg_con_ctx
69876 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
69878 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_1_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
69880 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx
69882 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx
69884 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
69886 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
69888 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram
69890 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx
69892 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_1_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx
69894 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx
69896 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx
69899 #define TCM_REG_IFEN 0x1180400UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
69916 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_0 0x11804a4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69917 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_1 0x11804a8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69918 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_2 0x11804acUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69919 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_3 0x11804b0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69920 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_4 0x11804b4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69921 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_5 0x11804b8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69922 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_6 0x11804bcUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69923 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_7 0x11804c0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
69924 #define TCM_REG_QM_TASK_USE_ST_FLG_0 0x1180504UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
69925 #define TCM_REG_QM_TASK_USE_ST_FLG_1 0x1180508UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
69926 #define TCM_REG_QM_TASK_USE_ST_FLG_2 0x118050cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
69927 #define TCM_REG_QM_TASK_USE_ST_FLG_3 0x1180510UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
69928 #define TCM_REG_QM_TASK_USE_ST_FLG_4 0x1180514UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
69929 #define TCM_REG_QM_TASK_USE_ST_FLG_5 0x1180518UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
69930 #define TCM_REG_QM_TASK_USE_ST_FLG_6 0x118051cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
69931 #define TCM_REG_QM_TASK_USE_ST_FLG_7 0x1180520UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
69968 #define TCM_REG_STORM_FRWRD_MODE 0x118064cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
69969 #define TCM_REG_MSEM_FRWRD_MODE 0x1180654UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
69970 #define TCM_REG_DORQ_FRWRD_MODE 0x118065cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
69971 #define TCM_REG_PBF_FRWRD_MODE 0x1180660UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
69972 #define TCM_REG_SDM_ERR_HANDLE_EN 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
69973 #define TCM_REG_DIR_BYP_EN 0x1180668UL //Access:RW DataWidth:0x1 // Direct bypass enable.
69988 #define TCM_REG_XX_IA_GROUP_PR0 0x118071cUL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
69989 #define TCM_REG_XX_IA_GROUP_PR1 0x1180720UL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
70013 #define TCM_REG_UNLOCK_MISS 0x11807a0UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
70015 #define TCM_REG_ERR_EXCLUSIVE_FLG 0x11807a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error.
70051 #define TCM_REG_SM_CON_BUF_CRD_AGGST 0x118086cUL //Access:RW DataWidth:0x1 // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
70060 #define TCM_REG_SM_TASK_BUF_CRD_AGGST 0x1180890UL //Access:RW DataWidth:0x1 // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
70095 #define TCM_REG_IN_PRCS_TBL_ALMOST_FULL 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost full.
70098 #define TCM_REG_TMCON_CURR_ST 0x1180a1cUL //Access:R DataWidth:0x1 // TM connection output FSM current state.
70099 #define TCM_REG_TMTASK_CURR_ST 0x1180a20UL //Access:R DataWidth:0x1 // TM task output FSM current state.
70100 #define TCM_REG_CCFC_CURR_ST 0x1180a24UL //Access:R DataWidth:0x1 // CFC connection output FSM current state.
70101 #define TCM_REG_TCFC_CURR_ST 0x1180a28UL //Access:R DataWidth:0x1 // CFC task output FSM current state.
70103 #define TCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1180a30UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
70104 #define TCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1180a34UL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID.
70127 #define TCM_REG_DORQ_LENGTH_MIS 0x1180aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at the dorq interface.
70128 #define TCM_REG_PBF_LENGTH_MIS 0x1180ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface.
70129 #define TCM_REG_PRS_LENGTH_MIS 0x1180ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PRS interface.
70130 #define TCM_REG_GRC_BUF_EMPTY 0x1180ab8UL //Access:R DataWidth:0x1 // Input Stage GRC buffer is empty.
70283 #define TCM_REG_QM_CON_USE_ST_FLG_0 0x11804e4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70284 #define TCM_REG_QM_CON_USE_ST_FLG_1 0x11804e8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70285 #define TCM_REG_QM_CON_USE_ST_FLG_2 0x11804ecUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70286 #define TCM_REG_QM_CON_USE_ST_FLG_3 0x11804f0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70287 #define TCM_REG_QM_CON_USE_ST_FLG_4 0x11804f4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70288 #define TCM_REG_QM_CON_USE_ST_FLG_5 0x11804f8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70289 #define TCM_REG_QM_CON_USE_ST_FLG_6 0x11804fcUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70290 #define TCM_REG_QM_CON_USE_ST_FLG_7 0x1180500UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70291 #define TCM_REG_QM_CON_USE_ST_FLG_8 0x1181aa0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70292 #define TCM_REG_QM_CON_USE_ST_FLG_9 0x1181aa4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70293 #define TCM_REG_QM_CON_USE_ST_FLG_10 0x1181aa8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70294 #define TCM_REG_QM_CON_USE_ST_FLG_11 0x1181aacUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70295 #define TCM_REG_QM_CON_USE_ST_FLG_12 0x1181ab0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70296 #define TCM_REG_QM_CON_USE_ST_FLG_13 0x1181ab4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70297 #define TCM_REG_QM_CON_USE_ST_FLG_14 0x1181ab8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70298 #define TCM_REG_QM_CON_USE_ST_FLG_15 0x1181abcUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
70299 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_0 0x1180464UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70300 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_1 0x1180468UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70301 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_2 0x118046cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70302 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_3 0x1180470UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70303 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_4 0x1180474UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70304 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_5 0x1180478UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70305 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_6 0x118047cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70306 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_7 0x1180480UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70307 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_8 0x1181ae0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70308 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_9 0x1181ae4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70309 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_10 0x1181ae8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70310 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_11 0x1181aecUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70311 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_12 0x1181af0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70312 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_13 0x1181af4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70313 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_14 0x1181af8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70314 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_15 0x1181afcUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
70316 #define TCM_REG_TSDM_FRWRD_MODE 0x1180650UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
70317 #define TCM_REG_TSDM_LENGTH_MIS 0x1180aa8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at TSDM interface.
70324 #define TCM_REG_PSDM_FRWRD_MODE 0x1181b84UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
70325 #define TCM_REG_PSDM_LENGTH_MIS 0x1181b88UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PSDM interface.
70332 #define TCM_REG_MSDM_FRWRD_MODE 0x1181c04UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
70333 #define TCM_REG_MSDM_LENGTH_MIS 0x1181c08UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at MSDM interface.
70340 #define TCM_REG_YSEM_FRWRD_MODE 0x1180658UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
70347 #define TCM_REG_PTLD_LENGTH_MIS 0x1181e04UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PTLD interface.
70363 #define MCM_REG_INIT 0x1200000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
70389 #define MCM_REG_EXCLUSIVE_FLG_0 0x12000c8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70390 #define MCM_REG_EXCLUSIVE_FLG_1 0x12000ccUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70391 #define MCM_REG_EXCLUSIVE_FLG_2 0x12000d0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70392 #define MCM_REG_EXCLUSIVE_FLG_3 0x12000d4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70393 #define MCM_REG_EXCLUSIVE_FLG_4 0x12000d8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70394 #define MCM_REG_EXCLUSIVE_FLG_5 0x12000dcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70395 #define MCM_REG_EXCLUSIVE_FLG_6 0x12000e0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70396 #define MCM_REG_EXCLUSIVE_FLG_7 0x12000e4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70397 #define MCM_REG_EXCLUSIVE_FLG_8 0x12000e8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70398 #define MCM_REG_EXCLUSIVE_FLG_9 0x12000ecUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70399 #define MCM_REG_EXCLUSIVE_FLG_10 0x12000f0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70400 #define MCM_REG_EXCLUSIVE_FLG_11 0x12000f4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70401 #define MCM_REG_EXCLUSIVE_FLG_12 0x12000f8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70402 #define MCM_REG_EXCLUSIVE_FLG_13 0x12000fcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70403 #define MCM_REG_EXCLUSIVE_FLG_14 0x1200100UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70404 #define MCM_REG_EXCLUSIVE_FLG_15 0x1200104UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
70409 #define MCM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
70411 #define MCM_REG_INT_STS_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
70413 #define MCM_REG_INT_STS_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
70415 #define MCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
70417 #define MCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
70419 #define MCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
70421 #define MCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
70423 #define MCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR (0x1<<7) // Write to full TSDM input buffer.
70425 #define MCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR (0x1<<8) // Read from empty TSDM input buffer.
70427 #define MCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR (0x1<<9) // Write to full PSDM input buffer.
70429 #define MCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR (0x1<<10) // Read from empty PSDM input buffer.
70431 #define MCM_REG_INT_STS_0_IS_USDM_OVFL_ERR (0x1<<7) // Write to full USDM input buffer.
70433 #define MCM_REG_INT_STS_0_IS_USDM_UNDER_ERR (0x1<<8) // Read from empty USDM input buffer.
70435 #define MCM_REG_INT_STS_0_IS_TMLD_OVFL_ERR (0x1<<9) // Write to full TMLD input buffer.
70437 #define MCM_REG_INT_STS_0_IS_TMLD_UNDER_ERR (0x1<<10) // Read from empty TMLD input buffer.
70439 #define MCM_REG_INT_STS_0_IS_USEM_OVFL_ERR (0x1<<11) // Write to full Usem input buffer.
70441 #define MCM_REG_INT_STS_0_IS_USEM_UNDER_ERR (0x1<<12) // Read from empty Usem input buffer.
70443 #define MCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR (0x1<<13) // Write to full Ysem input buffer.
70445 #define MCM_REG_INT_STS_0_EXT_LD_UNDER_ERR (0x1<<18) // Read from empty External read buffer.
70447 #define MCM_REG_INT_STS_0_EXT_LD_OVFL_ERR (0x1<<19) // Write to fully External read buffer.
70449 #define MCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON (0x1<<20) // Affinity type = 2 (connection based) but connection doesn't exist.
70451 #define MCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK (0x1<<21) // Affinity type = 3 (task based) but task doesn't exist.
70454 #define MCM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.ADDRESS_ERROR .
70456 #define MCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
70458 #define MCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
70460 #define MCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
70462 #define MCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
70464 #define MCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
70466 #define MCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
70468 #define MCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TSDM_OVFL_ERR .
70470 #define MCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TSDM_UNDER_ERR .
70472 #define MCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_PSDM_OVFL_ERR .
70474 #define MCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_PSDM_UNDER_ERR .
70476 #define MCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
70478 #define MCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
70480 #define MCM_REG_INT_MASK_0_IS_TMLD_OVFL_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_OVFL_ERR .
70482 #define MCM_REG_INT_MASK_0_IS_TMLD_UNDER_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_UNDER_ERR .
70484 #define MCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR (0x1<<11) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
70486 #define MCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
70488 #define MCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR (0x1<<13) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
70490 #define MCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR (0x1<<18) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
70492 #define MCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR (0x1<<19) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
70494 #define MCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON (0x1<<20) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
70496 #define MCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK (0x1<<21) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
70499 #define MCM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
70501 #define MCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
70503 #define MCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
70505 #define MCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
70507 #define MCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
70509 #define MCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
70511 #define MCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
70513 #define MCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR (0x1<<7) // Write to full TSDM input buffer.
70515 #define MCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR (0x1<<8) // Read from empty TSDM input buffer.
70517 #define MCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR (0x1<<9) // Write to full PSDM input buffer.
70519 #define MCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR (0x1<<10) // Read from empty PSDM input buffer.
70521 #define MCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR (0x1<<7) // Write to full USDM input buffer.
70523 #define MCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR (0x1<<8) // Read from empty USDM input buffer.
70525 #define MCM_REG_INT_STS_WR_0_IS_TMLD_OVFL_ERR (0x1<<9) // Write to full TMLD input buffer.
70527 #define MCM_REG_INT_STS_WR_0_IS_TMLD_UNDER_ERR (0x1<<10) // Read from empty TMLD input buffer.
70529 #define MCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR (0x1<<11) // Write to full Usem input buffer.
70531 #define MCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR (0x1<<12) // Read from empty Usem input buffer.
70533 #define MCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR (0x1<<13) // Write to full Ysem input buffer.
70535 #define MCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR (0x1<<18) // Read from empty External read buffer.
70537 #define MCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR (0x1<<19) // Write to fully External read buffer.
70539 #define MCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON (0x1<<20) // Affinity type = 2 (connection based) but connection doesn't exist.
70541 #define MCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK (0x1<<21) // Affinity type = 3 (task based) but task doesn't exist.
70544 #define MCM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
70546 #define MCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
70548 #define MCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
70550 #define MCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR (0x1<<3) // Write to full MSDM input buffer.
70552 #define MCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR (0x1<<4) // Read from empty MSDM input buffer.
70554 #define MCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
70556 #define MCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
70558 #define MCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR (0x1<<7) // Write to full TSDM input buffer.
70560 #define MCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR (0x1<<8) // Read from empty TSDM input buffer.
70562 #define MCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR (0x1<<9) // Write to full PSDM input buffer.
70564 #define MCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR (0x1<<10) // Read from empty PSDM input buffer.
70566 #define MCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR (0x1<<7) // Write to full USDM input buffer.
70568 #define MCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR (0x1<<8) // Read from empty USDM input buffer.
70570 #define MCM_REG_INT_STS_CLR_0_IS_TMLD_OVFL_ERR (0x1<<9) // Write to full TMLD input buffer.
70572 #define MCM_REG_INT_STS_CLR_0_IS_TMLD_UNDER_ERR (0x1<<10) // Read from empty TMLD input buffer.
70574 #define MCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR (0x1<<11) // Write to full Usem input buffer.
70576 #define MCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR (0x1<<12) // Read from empty Usem input buffer.
70578 #define MCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR (0x1<<13) // Write to full Ysem input buffer.
70580 #define MCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR (0x1<<18) // Read from empty External read buffer.
70582 #define MCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR (0x1<<19) // Write to fully External read buffer.
70584 #define MCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON (0x1<<20) // Affinity type = 2 (connection based) but connection doesn't exist.
70586 #define MCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK (0x1<<21) // Affinity type = 3 (task based) but task doesn't exist.
70589 #define MCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
70591 #define MCM_REG_INT_STS_1_IS_PBF_OVFL_ERR (0x1<<1) // Write to full Pbf input buffer.
70593 #define MCM_REG_INT_STS_1_IS_PBF_UNDER_ERR (0x1<<2) // Read from empty Pbf input buffer.
70595 #define MCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR (0x1<<3) // Write to full QM input buffer.
70597 #define MCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR (0x1<<4) // Read from empty QM input buffer.
70599 #define MCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR (0x1<<5) // Write to full QM input buffer.
70601 #define MCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR (0x1<<6) // Read from empty QM input buffer.
70603 #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0 (0x1<<7) // Write to full GRC input buffer bits [31:0].
70605 #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0 (0x1<<8) // Read from empty GRC input buffer bits [31:0].
70607 #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1 (0x1<<9) // Write to full GRC input buffer bits [63:32].
70609 #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1 (0x1<<10) // Read from empty GRC input buffer bits [63:32].
70611 #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2 (0x1<<11) // Write to full GRC input buffer bits [95:64].
70613 #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2 (0x1<<12) // Read from empty GRC input buffer bits [95:64].
70615 #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3 (0x1<<13) // Write to full GRC input buffer bits [127:96].
70617 #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3 (0x1<<14) // Read from empty GRC input buffer bits [127:96].
70619 #define MCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL (0x1<<15) // In-process Table overflow.
70621 #define MCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
70623 #define MCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
70625 #define MCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
70627 #define MCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
70629 #define MCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
70631 #define MCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
70633 #define MCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL (0x1<<22) // Message Processor Storm Task Data buffer overflow.
70635 #define MCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL (0x1<<23) // Message Processor Storm Task Command buffer overflow.
70637 #define MCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // Input message first descriptor fields violation.
70639 #define MCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE (0x1<<25) // Input message second descriptor fields violation.
70642 #define MCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
70644 #define MCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
70646 #define MCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
70648 #define MCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
70650 #define MCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
70652 #define MCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
70654 #define MCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
70656 #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0 (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
70658 #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0 (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
70660 #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1 (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
70662 #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1 (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
70664 #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2 (0x1<<11) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
70666 #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2 (0x1<<12) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
70668 #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3 (0x1<<13) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
70670 #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3 (0x1<<14) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
70672 #define MCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL (0x1<<15) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
70674 #define MCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL (0x1<<16) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
70676 #define MCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL (0x1<<17) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
70678 #define MCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL (0x1<<18) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
70680 #define MCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL (0x1<<19) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
70682 #define MCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL (0x1<<20) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
70684 #define MCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL (0x1<<21) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
70686 #define MCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL (0x1<<22) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
70688 #define MCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL (0x1<<23) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
70690 #define MCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
70692 #define MCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE (0x1<<25) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
70695 #define MCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
70697 #define MCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR (0x1<<1) // Write to full Pbf input buffer.
70699 #define MCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR (0x1<<2) // Read from empty Pbf input buffer.
70701 #define MCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR (0x1<<3) // Write to full QM input buffer.
70703 #define MCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR (0x1<<4) // Read from empty QM input buffer.
70705 #define MCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR (0x1<<5) // Write to full QM input buffer.
70707 #define MCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR (0x1<<6) // Read from empty QM input buffer.
70709 #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0 (0x1<<7) // Write to full GRC input buffer bits [31:0].
70711 #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0 (0x1<<8) // Read from empty GRC input buffer bits [31:0].
70713 #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1 (0x1<<9) // Write to full GRC input buffer bits [63:32].
70715 #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1 (0x1<<10) // Read from empty GRC input buffer bits [63:32].
70717 #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2 (0x1<<11) // Write to full GRC input buffer bits [95:64].
70719 #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2 (0x1<<12) // Read from empty GRC input buffer bits [95:64].
70721 #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3 (0x1<<13) // Write to full GRC input buffer bits [127:96].
70723 #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3 (0x1<<14) // Read from empty GRC input buffer bits [127:96].
70725 #define MCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL (0x1<<15) // In-process Table overflow.
70727 #define MCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
70729 #define MCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
70731 #define MCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
70733 #define MCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
70735 #define MCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
70737 #define MCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
70739 #define MCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL (0x1<<22) // Message Processor Storm Task Data buffer overflow.
70741 #define MCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL (0x1<<23) // Message Processor Storm Task Command buffer overflow.
70743 #define MCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // Input message first descriptor fields violation.
70745 #define MCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE (0x1<<25) // Input message second descriptor fields violation.
70748 #define MCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
70750 #define MCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR (0x1<<1) // Write to full Pbf input buffer.
70752 #define MCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR (0x1<<2) // Read from empty Pbf input buffer.
70754 #define MCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR (0x1<<3) // Write to full QM input buffer.
70756 #define MCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR (0x1<<4) // Read from empty QM input buffer.
70758 #define MCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR (0x1<<5) // Write to full QM input buffer.
70760 #define MCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR (0x1<<6) // Read from empty QM input buffer.
70762 #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0 (0x1<<7) // Write to full GRC input buffer bits [31:0].
70764 #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0 (0x1<<8) // Read from empty GRC input buffer bits [31:0].
70766 #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1 (0x1<<9) // Write to full GRC input buffer bits [63:32].
70768 #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1 (0x1<<10) // Read from empty GRC input buffer bits [63:32].
70770 #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2 (0x1<<11) // Write to full GRC input buffer bits [95:64].
70772 #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2 (0x1<<12) // Read from empty GRC input buffer bits [95:64].
70774 #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3 (0x1<<13) // Write to full GRC input buffer bits [127:96].
70776 #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3 (0x1<<14) // Read from empty GRC input buffer bits [127:96].
70778 #define MCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL (0x1<<15) // In-process Table overflow.
70780 #define MCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
70782 #define MCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
70784 #define MCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
70786 #define MCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
70788 #define MCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
70790 #define MCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
70792 #define MCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL (0x1<<22) // Message Processor Storm Task Data buffer overflow.
70794 #define MCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL (0x1<<23) // Message Processor Storm Task Command buffer overflow.
70796 #define MCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE (0x1<<24) // Input message first descriptor fields violation.
70798 #define MCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE (0x1<<25) // Input message second descriptor fields violation.
70800 #define MCM_REG_INT_STS_2 0x12001a0UL //Access:R DataWidth:0x1 // Multi Field Register.
70801 #define MCM_REG_INT_STS_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
70803 #define MCM_REG_INT_MASK_2 0x12001a4UL //Access:RW DataWidth:0x1 // Multi Field Register.
70804 #define MCM_REG_INT_MASK_2_QMREG_MORE4 (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_2.QMREG_MORE4 .
70806 #define MCM_REG_INT_STS_WR_2 0x12001a8UL //Access:WR DataWidth:0x1 // Multi Field Register.
70807 #define MCM_REG_INT_STS_WR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
70809 #define MCM_REG_INT_STS_CLR_2 0x12001acUL //Access:RC DataWidth:0x1 // Multi Field Register.
70810 #define MCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
70813 #define MCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
70815 #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
70817 #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
70819 #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
70821 #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
70823 #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
70825 #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT .
70827 #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT .
70829 #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
70831 #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
70833 #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
70835 #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
70837 #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
70839 #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
70841 #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
70843 #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
70845 #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
70847 #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
70849 #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
70851 #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
70853 #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
70855 #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
70857 #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
70859 #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
70861 #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
70863 #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
70865 #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
70867 #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
70869 #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0 (0x1<<28) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
70871 #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1 (0x1<<29) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
70873 #define MCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<30) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
70876 #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
70878 #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
70880 #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
70882 #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
70887 #define MCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram
70889 #define MCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx
70891 #define MCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN (0x1<<2) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx
70893 #define MCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN (0x1<<3) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx
70895 #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<4) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx.i_ecc_0 in module mcm_mem_agg_task_ctx
70897 #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<5) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx.i_ecc_1 in module mcm_mem_agg_task_ctx
70899 #define MCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN (0x1<<6) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_task_ctx_0_5
70901 #define MCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN (0x1<<7) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_task_ctx_0_5
70903 #define MCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6
70906 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram
70908 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx
70910 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY (0x1<<2) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx
70912 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY (0x1<<3) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx
70914 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<4) // Set parity only for memory ecc instance mcm.i_agg_task_ctx.i_ecc_0 in module mcm_mem_agg_task_ctx
70916 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<5) // Set parity only for memory ecc instance mcm.i_agg_task_ctx.i_ecc_1 in module mcm_mem_agg_task_ctx
70918 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY (0x1<<6) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_task_ctx_0_5
70920 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY (0x1<<7) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_task_ctx_0_5
70922 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6
70925 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram
70927 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx
70929 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx
70931 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx
70933 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_task_ctx.i_ecc_0 in module mcm_mem_agg_task_ctx
70935 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_task_ctx.i_ecc_1 in module mcm_mem_agg_task_ctx
70937 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_0 in module mcm_mem_sm_task_ctx_0_5
70939 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx_0_5.i_ecc_1 in module mcm_mem_sm_task_ctx_0_5
70941 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6
70944 #define MCM_REG_IFEN 0x1200400UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
70961 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_0 0x12004a4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70962 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_1 0x12004a8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70963 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_2 0x12004acUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70964 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_3 0x12004b0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70965 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_4 0x12004b4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70966 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_5 0x12004b8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70967 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_6 0x12004bcUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70968 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_7 0x12004c0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
70985 #define MCM_REG_QM_TASK_USE_ST_FLG_0 0x1200544UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
70986 #define MCM_REG_QM_TASK_USE_ST_FLG_1 0x1200548UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
70987 #define MCM_REG_QM_TASK_USE_ST_FLG_2 0x120054cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
70988 #define MCM_REG_QM_TASK_USE_ST_FLG_3 0x1200550UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
70989 #define MCM_REG_QM_TASK_USE_ST_FLG_4 0x1200554UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
70990 #define MCM_REG_QM_TASK_USE_ST_FLG_5 0x1200558UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
70991 #define MCM_REG_QM_TASK_USE_ST_FLG_6 0x120055cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
70992 #define MCM_REG_QM_TASK_USE_ST_FLG_7 0x1200560UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
71015 #define MCM_REG_STORM_FRWRD_MODE 0x120064cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71016 #define MCM_REG_YSDM_FRWRD_MODE 0x1200654UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71017 #define MCM_REG_USDM_FRWRD_MODE 0x1200658UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71018 #define MCM_REG_TMLD_FRWRD_MODE 0x120065cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71019 #define MCM_REG_USEM_FRWRD_MODE 0x1200660UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71020 #define MCM_REG_PBF_FRWRD_MODE 0x1200668UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71021 #define MCM_REG_SDM_ERR_HANDLE_EN 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
71022 #define MCM_REG_DIR_BYP_EN 0x1200670UL //Access:RW DataWidth:0x1 // Direct bypass enable.
71037 #define MCM_REG_XX_IA_GROUP_PR0 0x120071cUL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
71038 #define MCM_REG_XX_IA_GROUP_PR1 0x1200720UL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
71062 #define MCM_REG_UNLOCK_MISS 0x12007a0UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
71064 #define MCM_REG_ERR_EXCLUSIVE_FLG 0x12007a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error.
71094 #define MCM_REG_AGG_CON_FIC_BUF_FILL_LVL 0x1200854UL //Access:R DataWidth:0x1 // Aggregation Connection FIC buffer fill level (in messages).
71100 #define MCM_REG_SM_CON_BUF_CRD_AGGST 0x120086cUL //Access:RW DataWidth:0x1 // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
71109 #define MCM_REG_SM_TASK_BUF_CRD_AGGST 0x1200890UL //Access:RW DataWidth:0x1 // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
71146 #define MCM_REG_IN_PRCS_TBL_ALMOST_FULL 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost full.
71149 #define MCM_REG_CCFC_CURR_ST 0x1200a1cUL //Access:R DataWidth:0x1 // CFC connection output FSM current state.
71150 #define MCM_REG_TCFC_CURR_ST 0x1200a20UL //Access:R DataWidth:0x1 // CFC task output FSM current state.
71152 #define MCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1200a28UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
71153 #define MCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1200a2cUL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID.
71173 #define MCM_REG_TCFC_INCLOCK_INIT_CRD 0x1200a90UL //Access:RW DataWidth:0x1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter.
71177 #define MCM_REG_YSDM_LENGTH_MIS 0x1200aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface.
71178 #define MCM_REG_USDM_LENGTH_MIS 0x1200ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at USDM interface.
71179 #define MCM_REG_PBF_LENGTH_MIS 0x1200ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface.
71180 #define MCM_REG_TMLD_LENGTH_MIS 0x1200ab8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at TMLD interface.
71181 #define MCM_REG_GRC_BUF_EMPTY 0x1200abcUL //Access:R DataWidth:0x1 // Input Stage GRC buffer is empty.
71255 #define MCM_REG_AGG_CON_CTX_SIZE_0 0x12008a0UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less or 1.
71256 #define MCM_REG_AGG_CON_CTX_SIZE_1 0x12008a4UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71257 #define MCM_REG_AGG_CON_CTX_SIZE_2 0x12008a8UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71258 #define MCM_REG_AGG_CON_CTX_SIZE_3 0x12008acUL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71259 #define MCM_REG_AGG_CON_CTX_SIZE_4 0x12008b0UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71260 #define MCM_REG_AGG_CON_CTX_SIZE_5 0x12008b4UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71261 #define MCM_REG_AGG_CON_CTX_SIZE_6 0x12008b8UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71262 #define MCM_REG_AGG_CON_CTX_SIZE_7 0x12008bcUL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71263 #define MCM_REG_AGG_CON_CTX_SIZE_8 0x1201d60UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less or 1.
71264 #define MCM_REG_AGG_CON_CTX_SIZE_9 0x1201d64UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71265 #define MCM_REG_AGG_CON_CTX_SIZE_10 0x1201d68UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71266 #define MCM_REG_AGG_CON_CTX_SIZE_11 0x1201d6cUL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71267 #define MCM_REG_AGG_CON_CTX_SIZE_12 0x1201d70UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71268 #define MCM_REG_AGG_CON_CTX_SIZE_13 0x1201d74UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71269 #define MCM_REG_AGG_CON_CTX_SIZE_14 0x1201d78UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71270 #define MCM_REG_AGG_CON_CTX_SIZE_15 0x1201d7cUL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.
71319 #define MCM_REG_QM_CON_USE_ST_FLG_0 0x1200524UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71320 #define MCM_REG_QM_CON_USE_ST_FLG_1 0x1200528UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71321 #define MCM_REG_QM_CON_USE_ST_FLG_2 0x120052cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71322 #define MCM_REG_QM_CON_USE_ST_FLG_3 0x1200530UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71323 #define MCM_REG_QM_CON_USE_ST_FLG_4 0x1200534UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71324 #define MCM_REG_QM_CON_USE_ST_FLG_5 0x1200538UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71325 #define MCM_REG_QM_CON_USE_ST_FLG_6 0x120053cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71326 #define MCM_REG_QM_CON_USE_ST_FLG_7 0x1200540UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71327 #define MCM_REG_QM_CON_USE_ST_FLG_8 0x1201e60UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71328 #define MCM_REG_QM_CON_USE_ST_FLG_9 0x1201e64UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71329 #define MCM_REG_QM_CON_USE_ST_FLG_10 0x1201e68UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71330 #define MCM_REG_QM_CON_USE_ST_FLG_11 0x1201e6cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71331 #define MCM_REG_QM_CON_USE_ST_FLG_12 0x1201e70UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71332 #define MCM_REG_QM_CON_USE_ST_FLG_13 0x1201e74UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71333 #define MCM_REG_QM_CON_USE_ST_FLG_14 0x1201e78UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71334 #define MCM_REG_QM_CON_USE_ST_FLG_15 0x1201e7cUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
71335 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_0 0x1200464UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71336 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_1 0x1200468UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71337 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_2 0x120046cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71338 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_3 0x1200470UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71339 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_4 0x1200474UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71340 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_5 0x1200478UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71341 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_6 0x120047cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71342 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_7 0x1200480UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71343 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_8 0x1201ea0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71344 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_9 0x1201ea4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71345 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_10 0x1201ea8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71346 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_11 0x1201eacUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71347 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_12 0x1201eb0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71348 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_13 0x1201eb4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71349 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_14 0x1201eb8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71350 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_15 0x1201ebcUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
71354 #define MCM_REG_TSDM_FRWRD_MODE 0x1202804UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71355 #define MCM_REG_TSDM_LENGTH_MIS 0x1202808UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at TSDM interface.
71362 #define MCM_REG_PSDM_FRWRD_MODE 0x1202884UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71363 #define MCM_REG_PSDM_LENGTH_MIS 0x1202888UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PSDM interface.
71370 #define MCM_REG_MSDM_FRWRD_MODE 0x1200650UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71371 #define MCM_REG_MSDM_LENGTH_MIS 0x1200aa8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at MSDM interface.
71378 #define MCM_REG_YSEM_FRWRD_MODE 0x1200664UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
71391 #define UCM_REG_INIT 0x1280000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
71392 #define UCM_REG_MEMCTRL_WR_RD_N 0x1280040UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
71421 #define UCM_REG_EXCLUSIVE_FLG_0 0x12800e8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71422 #define UCM_REG_EXCLUSIVE_FLG_1 0x12800ecUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71423 #define UCM_REG_EXCLUSIVE_FLG_2 0x12800f0UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71424 #define UCM_REG_EXCLUSIVE_FLG_3 0x12800f4UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71425 #define UCM_REG_EXCLUSIVE_FLG_4 0x12800f8UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71426 #define UCM_REG_EXCLUSIVE_FLG_5 0x12800fcUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71427 #define UCM_REG_EXCLUSIVE_FLG_6 0x1280100UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71428 #define UCM_REG_EXCLUSIVE_FLG_7 0x1280104UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71429 #define UCM_REG_EXCLUSIVE_FLG_8 0x1280108UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71430 #define UCM_REG_EXCLUSIVE_FLG_9 0x128010cUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71431 #define UCM_REG_EXCLUSIVE_FLG_10 0x1280110UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71432 #define UCM_REG_EXCLUSIVE_FLG_11 0x1280114UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71433 #define UCM_REG_EXCLUSIVE_FLG_12 0x1280118UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71434 #define UCM_REG_EXCLUSIVE_FLG_13 0x128011cUL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71435 #define UCM_REG_EXCLUSIVE_FLG_14 0x1280120UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71436 #define UCM_REG_EXCLUSIVE_FLG_15 0x1280124UL //Access:RW DataWidth:0x1 // Exclusive flag per connection type.
71447 #define UCM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
71449 #define UCM_REG_INT_STS_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
71451 #define UCM_REG_INT_STS_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
71453 #define UCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR (0x1<<3) // Write to full XSDM input buffer.
71455 #define UCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR (0x1<<4) // Read from empty XSDM input buffer.
71457 #define UCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
71459 #define UCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
71461 #define UCM_REG_INT_STS_0_IS_USDM_OVFL_ERR (0x1<<7) // Write to full USDM input buffer.
71463 #define UCM_REG_INT_STS_0_IS_USDM_UNDER_ERR (0x1<<8) // Read from empty USDM input buffer.
71465 #define UCM_REG_INT_STS_0_IS_RDIF_OVFL_ERR (0x1<<9) // Write to full RDIF input buffer.
71467 #define UCM_REG_INT_STS_0_IS_RDIF_UNDER_ERR (0x1<<10) // Read from empty RDIF input buffer.
71469 #define UCM_REG_INT_STS_0_IS_TDIF_OVFL_ERR (0x1<<11) // Write to full TDIF input buffer.
71471 #define UCM_REG_INT_STS_0_IS_TDIF_UNDER_ERR (0x1<<12) // Read from empty TDIF input buffer.
71473 #define UCM_REG_INT_STS_0_IS_MULD_OVFL_ERR (0x1<<13) // Write to full MULD input buffer.
71475 #define UCM_REG_INT_STS_0_IS_MULD_UNDER_ERR (0x1<<14) // Read from empty MULD input buffer.
71477 #define UCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR (0x1<<15) // Write to full Ysem input buffer.
71479 #define UCM_REG_INT_STS_0_EXT_LD_UNDER_ERR (0x1<<16) // Read from empty External read buffer.
71481 #define UCM_REG_INT_STS_0_EXT_LD_OVFL_ERR (0x1<<17) // Write to fully External read buffer.
71483 #define UCM_REG_INT_STS_0_AFFINITY_TYPE_NO_CON (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
71485 #define UCM_REG_INT_STS_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
71487 #define UCM_REG_INT_STS_0_IS_YULD_OVFL_ERR (0x1<<15) // Write to full YULD input buffer.
71489 #define UCM_REG_INT_STS_0_IS_YULD_UNDER_ERR (0x1<<16) // Read from empty YULD input buffer.
71492 #define UCM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.ADDRESS_ERROR .
71494 #define UCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
71496 #define UCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
71498 #define UCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_XSDM_OVFL_ERR .
71500 #define UCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_XSDM_UNDER_ERR .
71502 #define UCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
71504 #define UCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
71506 #define UCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
71508 #define UCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
71510 #define UCM_REG_INT_MASK_0_IS_RDIF_OVFL_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_RDIF_OVFL_ERR .
71512 #define UCM_REG_INT_MASK_0_IS_RDIF_UNDER_ERR (0x1<<10) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_RDIF_UNDER_ERR .
71514 #define UCM_REG_INT_MASK_0_IS_TDIF_OVFL_ERR (0x1<<11) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_TDIF_OVFL_ERR .
71516 #define UCM_REG_INT_MASK_0_IS_TDIF_UNDER_ERR (0x1<<12) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_TDIF_UNDER_ERR .
71518 #define UCM_REG_INT_MASK_0_IS_MULD_OVFL_ERR (0x1<<13) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_MULD_OVFL_ERR .
71520 #define UCM_REG_INT_MASK_0_IS_MULD_UNDER_ERR (0x1<<14) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_MULD_UNDER_ERR .
71522 #define UCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
71524 #define UCM_REG_INT_MASK_0_EXT_LD_UNDER_ERR (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.EXT_LD_UNDER_ERR .
71526 #define UCM_REG_INT_MASK_0_EXT_LD_OVFL_ERR (0x1<<17) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.EXT_LD_OVFL_ERR .
71528 #define UCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_CON (0x1<<18) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.AFFINITY_TYPE_NO_CON .
71530 #define UCM_REG_INT_MASK_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.AFFINITY_TYPE_NO_TASK .
71532 #define UCM_REG_INT_MASK_0_IS_YULD_OVFL_ERR (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YULD_OVFL_ERR .
71534 #define UCM_REG_INT_MASK_0_IS_YULD_UNDER_ERR (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YULD_UNDER_ERR .
71537 #define UCM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
71539 #define UCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
71541 #define UCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
71543 #define UCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR (0x1<<3) // Write to full XSDM input buffer.
71545 #define UCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR (0x1<<4) // Read from empty XSDM input buffer.
71547 #define UCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
71549 #define UCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
71551 #define UCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR (0x1<<7) // Write to full USDM input buffer.
71553 #define UCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR (0x1<<8) // Read from empty USDM input buffer.
71555 #define UCM_REG_INT_STS_WR_0_IS_RDIF_OVFL_ERR (0x1<<9) // Write to full RDIF input buffer.
71557 #define UCM_REG_INT_STS_WR_0_IS_RDIF_UNDER_ERR (0x1<<10) // Read from empty RDIF input buffer.
71559 #define UCM_REG_INT_STS_WR_0_IS_TDIF_OVFL_ERR (0x1<<11) // Write to full TDIF input buffer.
71561 #define UCM_REG_INT_STS_WR_0_IS_TDIF_UNDER_ERR (0x1<<12) // Read from empty TDIF input buffer.
71563 #define UCM_REG_INT_STS_WR_0_IS_MULD_OVFL_ERR (0x1<<13) // Write to full MULD input buffer.
71565 #define UCM_REG_INT_STS_WR_0_IS_MULD_UNDER_ERR (0x1<<14) // Read from empty MULD input buffer.
71567 #define UCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR (0x1<<15) // Write to full Ysem input buffer.
71569 #define UCM_REG_INT_STS_WR_0_EXT_LD_UNDER_ERR (0x1<<16) // Read from empty External read buffer.
71571 #define UCM_REG_INT_STS_WR_0_EXT_LD_OVFL_ERR (0x1<<17) // Write to fully External read buffer.
71573 #define UCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_CON (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
71575 #define UCM_REG_INT_STS_WR_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
71577 #define UCM_REG_INT_STS_WR_0_IS_YULD_OVFL_ERR (0x1<<15) // Write to full YULD input buffer.
71579 #define UCM_REG_INT_STS_WR_0_IS_YULD_UNDER_ERR (0x1<<16) // Read from empty YULD input buffer.
71582 #define UCM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
71584 #define UCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR (0x1<<1) // Write to full STORM input buffer.
71586 #define UCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR (0x1<<2) // Read from empty STORM input buffer.
71588 #define UCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR (0x1<<3) // Write to full XSDM input buffer.
71590 #define UCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR (0x1<<4) // Read from empty XSDM input buffer.
71592 #define UCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR (0x1<<5) // Write to full YSDM input buffer.
71594 #define UCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR (0x1<<6) // Read from empty YSDM input buffer.
71596 #define UCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR (0x1<<7) // Write to full USDM input buffer.
71598 #define UCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR (0x1<<8) // Read from empty USDM input buffer.
71600 #define UCM_REG_INT_STS_CLR_0_IS_RDIF_OVFL_ERR (0x1<<9) // Write to full RDIF input buffer.
71602 #define UCM_REG_INT_STS_CLR_0_IS_RDIF_UNDER_ERR (0x1<<10) // Read from empty RDIF input buffer.
71604 #define UCM_REG_INT_STS_CLR_0_IS_TDIF_OVFL_ERR (0x1<<11) // Write to full TDIF input buffer.
71606 #define UCM_REG_INT_STS_CLR_0_IS_TDIF_UNDER_ERR (0x1<<12) // Read from empty TDIF input buffer.
71608 #define UCM_REG_INT_STS_CLR_0_IS_MULD_OVFL_ERR (0x1<<13) // Write to full MULD input buffer.
71610 #define UCM_REG_INT_STS_CLR_0_IS_MULD_UNDER_ERR (0x1<<14) // Read from empty MULD input buffer.
71612 #define UCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR (0x1<<15) // Write to full Ysem input buffer.
71614 #define UCM_REG_INT_STS_CLR_0_EXT_LD_UNDER_ERR (0x1<<16) // Read from empty External read buffer.
71616 #define UCM_REG_INT_STS_CLR_0_EXT_LD_OVFL_ERR (0x1<<17) // Write to fully External read buffer.
71618 #define UCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_CON (0x1<<18) // Affinity type = 2 (connection based) but connection doesn't exist.
71620 #define UCM_REG_INT_STS_CLR_0_AFFINITY_TYPE_NO_TASK (0x1<<19) // Affinity type = 3 (task based) but task doesn't exist.
71622 #define UCM_REG_INT_STS_CLR_0_IS_YULD_OVFL_ERR (0x1<<15) // Write to full YULD input buffer.
71624 #define UCM_REG_INT_STS_CLR_0_IS_YULD_UNDER_ERR (0x1<<16) // Read from empty YULD input buffer.
71627 #define UCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
71629 #define UCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR (0x1<<0) // Write to full Dorq input buffer.
71631 #define UCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR (0x1<<1) // Read from empty Dorq input buffer.
71633 #define UCM_REG_INT_STS_1_IS_PBF_OVFL_ERR (0x1<<2) // Write to full Pbf input buffer.
71635 #define UCM_REG_INT_STS_1_IS_PBF_UNDER_ERR (0x1<<3) // Read from empty Pbf input buffer.
71637 #define UCM_REG_INT_STS_1_IS_TM_OVFL_ERR (0x1<<4) // Write to full TM input buffer.
71639 #define UCM_REG_INT_STS_1_IS_TM_UNDER_ERR (0x1<<5) // Read from empty TM input buffer.
71641 #define UCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR (0x1<<6) // Write to full QM input buffer.
71643 #define UCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR (0x1<<7) // Read from empty QM input buffer.
71645 #define UCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR (0x1<<8) // Write to full QM input buffer.
71647 #define UCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR (0x1<<9) // Read from empty QM input buffer.
71649 #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0 (0x1<<10) // Write to full GRC input buffer bits [31:0].
71651 #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0 (0x1<<11) // Read from empty GRC input buffer bits [31:0].
71653 #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1 (0x1<<12) // Write to full GRC input buffer bits [63:32].
71655 #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1 (0x1<<13) // Read from empty GRC input buffer bits [63:32].
71657 #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2 (0x1<<14) // Write to full GRC input buffer bits [95:64].
71659 #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2 (0x1<<15) // Read from empty GRC input buffer bits [95:64].
71661 #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3 (0x1<<16) // Write to full GRC input buffer bits [127:96].
71663 #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3 (0x1<<17) // Read from empty GRC input buffer bits [127:96].
71665 #define UCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL (0x1<<18) // In-process Table overflow.
71667 #define UCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
71669 #define UCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
71671 #define UCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
71673 #define UCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
71675 #define UCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
71677 #define UCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
71679 #define UCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL (0x1<<25) // Message Processor Storm Task Data buffer overflow.
71681 #define UCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL (0x1<<26) // Message Processor Storm Task Command buffer overflow.
71683 #define UCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE (0x1<<27) // Input message first descriptor fields violation.
71685 #define UCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE (0x1<<28) // Input message second descriptor fields violation.
71688 #define UCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
71690 #define UCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
71692 #define UCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
71694 #define UCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
71696 #define UCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
71698 #define UCM_REG_INT_MASK_1_IS_TM_OVFL_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
71700 #define UCM_REG_INT_MASK_1_IS_TM_UNDER_ERR (0x1<<5) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
71702 #define UCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR (0x1<<6) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
71704 #define UCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR (0x1<<7) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
71706 #define UCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR (0x1<<8) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
71708 #define UCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR (0x1<<9) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
71710 #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0 (0x1<<10) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
71712 #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0 (0x1<<11) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
71714 #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1 (0x1<<12) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
71716 #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1 (0x1<<13) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
71718 #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2 (0x1<<14) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
71720 #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2 (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
71722 #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3 (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
71724 #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3 (0x1<<17) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
71726 #define UCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL (0x1<<18) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
71728 #define UCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL (0x1<<19) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
71730 #define UCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL (0x1<<20) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
71732 #define UCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL (0x1<<21) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
71734 #define UCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL (0x1<<22) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
71736 #define UCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL (0x1<<23) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
71738 #define UCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL (0x1<<24) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
71740 #define UCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL (0x1<<25) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
71742 #define UCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL (0x1<<26) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
71744 #define UCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE (0x1<<27) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
71746 #define UCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE (0x1<<28) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
71749 #define UCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
71751 #define UCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR (0x1<<0) // Write to full Dorq input buffer.
71753 #define UCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR (0x1<<1) // Read from empty Dorq input buffer.
71755 #define UCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR (0x1<<2) // Write to full Pbf input buffer.
71757 #define UCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR (0x1<<3) // Read from empty Pbf input buffer.
71759 #define UCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR (0x1<<4) // Write to full TM input buffer.
71761 #define UCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR (0x1<<5) // Read from empty TM input buffer.
71763 #define UCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR (0x1<<6) // Write to full QM input buffer.
71765 #define UCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR (0x1<<7) // Read from empty QM input buffer.
71767 #define UCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR (0x1<<8) // Write to full QM input buffer.
71769 #define UCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR (0x1<<9) // Read from empty QM input buffer.
71771 #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0 (0x1<<10) // Write to full GRC input buffer bits [31:0].
71773 #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0 (0x1<<11) // Read from empty GRC input buffer bits [31:0].
71775 #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1 (0x1<<12) // Write to full GRC input buffer bits [63:32].
71777 #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1 (0x1<<13) // Read from empty GRC input buffer bits [63:32].
71779 #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2 (0x1<<14) // Write to full GRC input buffer bits [95:64].
71781 #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2 (0x1<<15) // Read from empty GRC input buffer bits [95:64].
71783 #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3 (0x1<<16) // Write to full GRC input buffer bits [127:96].
71785 #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3 (0x1<<17) // Read from empty GRC input buffer bits [127:96].
71787 #define UCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL (0x1<<18) // In-process Table overflow.
71789 #define UCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
71791 #define UCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
71793 #define UCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
71795 #define UCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
71797 #define UCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
71799 #define UCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
71801 #define UCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL (0x1<<25) // Message Processor Storm Task Data buffer overflow.
71803 #define UCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL (0x1<<26) // Message Processor Storm Task Command buffer overflow.
71805 #define UCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE (0x1<<27) // Input message first descriptor fields violation.
71807 #define UCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE (0x1<<28) // Input message second descriptor fields violation.
71810 #define UCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR (0x1<<0) // Read from empty Ysem input buffer.
71812 #define UCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR (0x1<<0) // Write to full Dorq input buffer.
71814 #define UCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR (0x1<<1) // Read from empty Dorq input buffer.
71816 #define UCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR (0x1<<2) // Write to full Pbf input buffer.
71818 #define UCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR (0x1<<3) // Read from empty Pbf input buffer.
71820 #define UCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR (0x1<<4) // Write to full TM input buffer.
71822 #define UCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR (0x1<<5) // Read from empty TM input buffer.
71824 #define UCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR (0x1<<6) // Write to full QM input buffer.
71826 #define UCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR (0x1<<7) // Read from empty QM input buffer.
71828 #define UCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR (0x1<<8) // Write to full QM input buffer.
71830 #define UCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR (0x1<<9) // Read from empty QM input buffer.
71832 #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0 (0x1<<10) // Write to full GRC input buffer bits [31:0].
71834 #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0 (0x1<<11) // Read from empty GRC input buffer bits [31:0].
71836 #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1 (0x1<<12) // Write to full GRC input buffer bits [63:32].
71838 #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1 (0x1<<13) // Read from empty GRC input buffer bits [63:32].
71840 #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2 (0x1<<14) // Write to full GRC input buffer bits [95:64].
71842 #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2 (0x1<<15) // Read from empty GRC input buffer bits [95:64].
71844 #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3 (0x1<<16) // Write to full GRC input buffer bits [127:96].
71846 #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3 (0x1<<17) // Read from empty GRC input buffer bits [127:96].
71848 #define UCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL (0x1<<18) // In-process Table overflow.
71850 #define UCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
71852 #define UCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
71854 #define UCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
71856 #define UCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
71858 #define UCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
71860 #define UCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
71862 #define UCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL (0x1<<25) // Message Processor Storm Task Data buffer overflow.
71864 #define UCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL (0x1<<26) // Message Processor Storm Task Command buffer overflow.
71866 #define UCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE (0x1<<27) // Input message first descriptor fields violation.
71868 #define UCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE (0x1<<28) // Input message second descriptor fields violation.
71870 #define UCM_REG_INT_STS_2 0x12801a0UL //Access:R DataWidth:0x1 // Multi Field Register.
71871 #define UCM_REG_INT_STS_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
71873 #define UCM_REG_INT_MASK_2 0x12801a4UL //Access:RW DataWidth:0x1 // Multi Field Register.
71874 #define UCM_REG_INT_MASK_2_QMREG_MORE4 (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_2.QMREG_MORE4 .
71876 #define UCM_REG_INT_STS_WR_2 0x12801a8UL //Access:WR DataWidth:0x1 // Multi Field Register.
71877 #define UCM_REG_INT_STS_WR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
71879 #define UCM_REG_INT_STS_CLR_2 0x12801acUL //Access:RC DataWidth:0x1 // Multi Field Register.
71880 #define UCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations.
71883 #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM030_I_ECC_RF_INT .
71885 #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
71887 #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
71889 #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
71891 #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
71893 #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
71895 #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_0_RF_INT (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_ECC_0_RF_INT .
71897 #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_1_RF_INT (0x1<<7) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_ECC_1_RF_INT .
71899 #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT (0x1<<8) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
71901 #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_0_RF_INT .
71903 #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT (0x1<<10) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_1_RF_INT .
71905 #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT (0x1<<11) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
71907 #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
71909 #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
71911 #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
71913 #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
71915 #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
71917 #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<17) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
71919 #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
71921 #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
71923 #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
71925 #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
71927 #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
71929 #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
71931 #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
71933 #define UCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY (0x1<<25) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
71935 #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
71937 #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
71939 #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
71941 #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
71943 #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0 (0x1<<30) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 .
71946 #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1 (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY_1 .
71948 #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
71950 #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
71952 #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
71954 #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
71956 #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
71958 #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
71963 #define UCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram
71965 #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx
71967 #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx
71969 #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN (0x1<<3) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11
71971 #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN (0x1<<4) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11
71973 #define UCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_con_ctx_12
71975 #define UCM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_0_EN (0x1<<6) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_task_ctx_0_1
71977 #define UCM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_1_EN (0x1<<7) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_task_ctx_0_1
71979 #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN (0x1<<8) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2
71981 #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN (0x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1
71983 #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN (0x1<<10) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1
71985 #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN (0x1<<11) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2
71988 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram
71990 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx
71992 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx
71994 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY (0x1<<3) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11
71996 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY (0x1<<4) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11
71998 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_con_ctx_12
72000 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_0_PRTY (0x1<<6) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_task_ctx_0_1
72002 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_1_PRTY (0x1<<7) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_task_ctx_0_1
72004 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY (0x1<<8) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2
72006 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY (0x1<<9) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1
72008 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY (0x1<<10) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1
72010 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY (0x1<<11) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2
72013 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram
72015 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx
72017 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx
72019 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11
72021 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11
72023 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_12.i_ecc in module ucm_mem_sm_con_ctx_12
72025 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_0_CORRECT (0x1<<6) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_0 in module ucm_mem_agg_task_ctx_0_1
72027 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_1_CORRECT (0x1<<7) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx_0_1.i_ecc_1 in module ucm_mem_agg_task_ctx_0_1
72029 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT (0x1<<8) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2
72031 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT (0x1<<9) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1
72033 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT (0x1<<10) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1
72035 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT (0x1<<11) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2
72038 #define UCM_REG_IFEN 0x1280400UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
72055 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_0 0x12804a4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72056 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_1 0x12804a8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72057 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_2 0x12804acUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72058 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_3 0x12804b0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72059 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_4 0x12804b4UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72060 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_5 0x12804b8UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72061 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_6 0x12804bcUL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72062 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_7 0x12804c0UL //Access:RW DataWidth:0x1 // QM storm task context load_store per task type.
72063 #define UCM_REG_QM_TASK_USE_ST_FLG_0 0x1280504UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
72064 #define UCM_REG_QM_TASK_USE_ST_FLG_1 0x1280508UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
72065 #define UCM_REG_QM_TASK_USE_ST_FLG_2 0x128050cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
72066 #define UCM_REG_QM_TASK_USE_ST_FLG_3 0x1280510UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
72067 #define UCM_REG_QM_TASK_USE_ST_FLG_4 0x1280514UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
72068 #define UCM_REG_QM_TASK_USE_ST_FLG_5 0x1280518UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
72069 #define UCM_REG_QM_TASK_USE_ST_FLG_6 0x128051cUL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.
72070 #define UCM_REG_QM_TASK_USE_ST_FLG_7 0x1280520UL //Access:RW DataWidth:0x1 // QM Task use state flag per connection type. Should be all 0 for PCM and XCM.
72101 #define UCM_REG_STORM_FRWRD_MODE 0x1280658UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72102 #define UCM_REG_XSDM_FRWRD_MODE 0x128065cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72103 #define UCM_REG_YSDM_FRWRD_MODE 0x1280660UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72104 #define UCM_REG_PSDM_FRWRD_MODE 0x1280664UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72105 #define UCM_REG_USDM_FRWRD_MODE 0x1280668UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72106 #define UCM_REG_RDIF_FRWRD_MODE 0x128066cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72107 #define UCM_REG_TDIF_FRWRD_MODE 0x1280670UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72108 #define UCM_REG_MULD_FRWRD_MODE 0x1280674UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72109 #define UCM_REG_YULD_FRWRD_MODE 0x1280678UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72110 #define UCM_REG_DORQ_FRWRD_MODE 0x128067cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72111 #define UCM_REG_PBF_FRWRD_MODE 0x1280680UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72112 #define UCM_REG_SDM_ERR_HANDLE_EN 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message.
72113 #define UCM_REG_DIR_BYP_EN 0x1280688UL //Access:RW DataWidth:0x1 // Direct bypass enable.
72128 #define UCM_REG_XX_IA_GROUP_PR0 0x128071cUL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
72129 #define UCM_REG_XX_IA_GROUP_PR1 0x1280720UL //Access:RW DataWidth:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
72153 #define UCM_REG_UNLOCK_MISS 0x12807a0UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.
72155 #define UCM_REG_ERR_EXCLUSIVE_FLG 0x12807a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error.
72191 #define UCM_REG_SM_CON_BUF_CRD_AGGST 0x128086cUL //Access:RW DataWidth:0x1 // Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
72200 #define UCM_REG_SM_TASK_BUF_CRD_AGGST 0x1280890UL //Access:RW DataWidth:0x1 // Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
72247 #define UCM_REG_IN_PRCS_TBL_ALMOST_FULL 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost full.
72250 #define UCM_REG_TMCON_CURR_ST 0x1280a1cUL //Access:R DataWidth:0x1 // TM connection output FSM current state.
72251 #define UCM_REG_TMTASK_CURR_ST 0x1280a20UL //Access:R DataWidth:0x1 // TM task output FSM current state.
72252 #define UCM_REG_CCFC_CURR_ST 0x1280a24UL //Access:R DataWidth:0x1 // CFC connection output FSM current state.
72253 #define UCM_REG_TCFC_CURR_ST 0x1280a28UL //Access:R DataWidth:0x1 // CFC task output FSM current state.
72255 #define UCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1280a30UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID.
72256 #define UCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1280a34UL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID.
72279 #define UCM_REG_XSDM_LENGTH_MIS 0x1280aa8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at XSDM interface.
72280 #define UCM_REG_YSDM_LENGTH_MIS 0x1280aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface.
72281 #define UCM_REG_USDM_LENGTH_MIS 0x1280ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at USDM interface.
72282 #define UCM_REG_DORQ_LENGTH_MIS 0x1280ab4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at the dorq interface.
72283 #define UCM_REG_PBF_LENGTH_MIS 0x1280ab8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface.
72284 #define UCM_REG_RDIF_LENGTH_MIS 0x1280abcUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at RDIF interface.
72285 #define UCM_REG_TDIF_LENGTH_MIS 0x1280ac0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at TDIF interface.
72286 #define UCM_REG_MULD_LENGTH_MIS 0x1280ac4UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at MULD interface.
72287 #define UCM_REG_YULD_LENGTH_MIS 0x1280ac8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YULD interface.
72288 #define UCM_REG_GRC_BUF_EMPTY 0x1280accUL //Access:R DataWidth:0x1 // Input Stage GRC buffer is empty.
72466 #define UCM_REG_QM_CON_USE_ST_FLG_0 0x12804e4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72467 #define UCM_REG_QM_CON_USE_ST_FLG_1 0x12804e8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72468 #define UCM_REG_QM_CON_USE_ST_FLG_2 0x12804ecUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72469 #define UCM_REG_QM_CON_USE_ST_FLG_3 0x12804f0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72470 #define UCM_REG_QM_CON_USE_ST_FLG_4 0x12804f4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72471 #define UCM_REG_QM_CON_USE_ST_FLG_5 0x12804f8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72472 #define UCM_REG_QM_CON_USE_ST_FLG_6 0x12804fcUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72473 #define UCM_REG_QM_CON_USE_ST_FLG_7 0x1280500UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72474 #define UCM_REG_QM_CON_USE_ST_FLG_8 0x1281da0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72475 #define UCM_REG_QM_CON_USE_ST_FLG_9 0x1281da4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72476 #define UCM_REG_QM_CON_USE_ST_FLG_10 0x1281da8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72477 #define UCM_REG_QM_CON_USE_ST_FLG_11 0x1281dacUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72478 #define UCM_REG_QM_CON_USE_ST_FLG_12 0x1281db0UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72479 #define UCM_REG_QM_CON_USE_ST_FLG_13 0x1281db4UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72480 #define UCM_REG_QM_CON_USE_ST_FLG_14 0x1281db8UL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72481 #define UCM_REG_QM_CON_USE_ST_FLG_15 0x1281dbcUL //Access:RW DataWidth:0x1 // QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.
72482 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_0 0x1280464UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72483 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_1 0x1280468UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72484 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_2 0x128046cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72485 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_3 0x1280470UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72486 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_4 0x1280474UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72487 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_5 0x1280478UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72488 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_6 0x128047cUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72489 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_7 0x1280480UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72490 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_8 0x1281de0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72491 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_9 0x1281de4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72492 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_10 0x1281de8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72493 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_11 0x1281decUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72494 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_12 0x1281df0UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72495 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_13 0x1281df4UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72496 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_14 0x1281df8UL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72497 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_15 0x1281dfcUL //Access:RW DataWidth:0x1 // QM storm connection context load_store per connection type.
72503 #define UCM_REG_YSEM_FRWRD_MODE 0x128280cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
72518 #define XSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN (0x1<<0) // Full input from external IF to LS input enable.
72520 #define XSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN (0x1<<1) // Read data from external LS IF input enable.
72522 #define XSEM_REG_ENABLE_IN_FIC_ENABLE_IN (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
72524 #define XSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
72526 #define XSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN (0x1<<4) // General interface input enable.
72528 #define XSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN (0x1<<5) // External passive write input enable.
72530 #define XSEM_REG_ENABLE_IN_RAM_ENABLE_IN (0x1<<6) // Data input enable to RAM.
72532 #define XSEM_REG_ENABLE_IN_STALL_ENABLE_IN (0x1<<7) // Enable for stall input from all external STORM instances.
72534 #define XSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN (0x1<<8) // Thread ready bus input enable.
72536 #define XSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
72539 #define XSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT (0x1<<0) // Read request output enable from external LS IF.
72541 #define XSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT (0x1<<1) // Write request output enable from external LS IF.
72543 #define XSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
72545 #define XSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT (0x1<<3) // Passive full output enable.
72547 #define XSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT (0x1<<4) // Data output enable to RAM.
72549 #define XSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
72551 #define XSEM_REG_FIC_DISABLE 0x140000cUL //Access:RW DataWidth:0x1 // Disables input messages from all FIC interfaces. May be updated during run_time by the microcode.
72552 #define XSEM_REG_PAS_DISABLE 0x1400010UL //Access:RW DataWidth:0x1 // Disables input messages from the passive buffer May be updated during run_time by the microcode.
72554 #define XSEM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
72556 #define XSEM_REG_INT_STS_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
72558 #define XSEM_REG_INT_STS_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
72560 #define XSEM_REG_INT_STS_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
72562 #define XSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
72564 #define XSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
72566 #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
72568 #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
72570 #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
72572 #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
72574 #define XSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
72576 #define XSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
72578 #define XSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
72580 #define XSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
72582 #define XSEM_REG_INT_STS_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
72584 #define XSEM_REG_INT_STS_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
72586 #define XSEM_REG_INT_STS_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
72588 #define XSEM_REG_INT_STS_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
72590 #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
72592 #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
72594 #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
72596 #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
72598 #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
72600 #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
72602 #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
72604 #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
72606 #define XSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
72608 #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
72610 #define XSEM_REG_INT_STS_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
72612 #define XSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
72614 #define XSEM_REG_INT_STS_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
72616 #define XSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
72619 #define XSEM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.ADDRESS_ERROR .
72621 #define XSEM_REG_INT_MASK_0_FIC_LAST_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_LAST_ERROR .
72623 #define XSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
72625 #define XSEM_REG_INT_MASK_0_FIC_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
72627 #define XSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
72629 #define XSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
72631 #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
72633 #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
72635 #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
72637 #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
72639 #define XSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
72641 #define XSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
72643 #define XSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
72645 #define XSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO (0x1<<13) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
72647 #define XSEM_REG_INT_MASK_0_CAM_OUT_FIFO (0x1<<14) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_OUT_FIFO .
72649 #define XSEM_REG_INT_MASK_0_FIN_FIFO (0x1<<15) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIN_FIFO .
72651 #define XSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
72653 #define XSEM_REG_INT_MASK_0_THREAD_OVERRUN (0x1<<17) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.THREAD_OVERRUN .
72655 #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
72657 #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
72659 #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
72661 #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
72663 #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
72665 #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
72667 #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
72669 #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
72671 #define XSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
72673 #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
72675 #define XSEM_REG_INT_MASK_0_DBG_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
72677 #define XSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO (0x1<<29) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
72679 #define XSEM_REG_INT_MASK_0_VFC_INTERRUPT (0x1<<30) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.VFC_INTERRUPT .
72681 #define XSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
72684 #define XSEM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
72686 #define XSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
72688 #define XSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
72690 #define XSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
72692 #define XSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
72694 #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
72696 #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
72698 #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
72700 #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
72702 #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
72704 #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
72706 #define XSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
72708 #define XSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
72710 #define XSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
72712 #define XSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
72714 #define XSEM_REG_INT_STS_WR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
72716 #define XSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
72718 #define XSEM_REG_INT_STS_WR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
72720 #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
72722 #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
72724 #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
72726 #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
72728 #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
72730 #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
72732 #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
72734 #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
72736 #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
72738 #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
72740 #define XSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
72742 #define XSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
72744 #define XSEM_REG_INT_STS_WR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
72746 #define XSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
72749 #define XSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
72751 #define XSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
72753 #define XSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
72755 #define XSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
72757 #define XSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
72759 #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
72761 #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
72763 #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
72765 #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
72767 #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
72769 #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
72771 #define XSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
72773 #define XSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
72775 #define XSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
72777 #define XSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
72779 #define XSEM_REG_INT_STS_CLR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
72781 #define XSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
72783 #define XSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
72785 #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
72787 #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
72789 #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
72791 #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
72793 #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
72795 #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
72797 #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
72799 #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
72801 #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
72803 #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
72805 #define XSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
72807 #define XSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
72809 #define XSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
72811 #define XSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
72814 #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
72816 #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
72818 #define XSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
72820 #define XSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
72822 #define XSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
72824 #define XSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
72826 #define XSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
72828 #define XSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
72830 #define XSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
72832 #define XSEM_REG_INT_STS_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
72834 #define XSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
72836 #define XSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
72838 #define XSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
72841 #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
72843 #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
72845 #define XSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
72847 #define XSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
72849 #define XSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
72851 #define XSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
72853 #define XSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
72855 #define XSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
72857 #define XSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
72859 #define XSEM_REG_INT_MASK_1_INVLD_FOC_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
72861 #define XSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
72863 #define XSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
72865 #define XSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
72868 #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
72870 #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
72872 #define XSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
72874 #define XSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
72876 #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
72878 #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
72880 #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
72882 #define XSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
72884 #define XSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
72886 #define XSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
72888 #define XSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
72890 #define XSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
72892 #define XSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
72895 #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
72897 #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
72899 #define XSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
72901 #define XSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
72903 #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
72905 #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
72907 #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
72909 #define XSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
72911 #define XSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
72913 #define XSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
72915 #define XSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
72917 #define XSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
72919 #define XSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
72922 #define XSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
72924 #define XSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR (0x1<<1) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
72926 #define XSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR (0x1<<2) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
72929 #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
72931 #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
72933 #define XSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
72935 #define XSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
72937 #define XSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
72939 #define XSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
72941 #define XSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
72944 #define XSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
72946 #define XSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
72949 #define XSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
72951 #define XSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
72954 #define XSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
72956 #define XSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
72960 #define XSEM_REG_VF_ERROR 0x1400408UL //Access:WR DataWidth:0x1 // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
72961 #define XSEM_REG_PF_ERROR 0x140040cUL //Access:WR DataWidth:0x1 // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
72965 #define XSEM_REG_CLEAR_STALL 0x1400444UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
72970 #define XSEM_REG_ALLOW_LP_SLEEP_THRD 0x1400458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
72978 #define XSEM_REG_FIC_EMPTY_CT_MODE 0x1400620UL //Access:RW DataWidth:0x1 // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
72982 #define XSEM_REG_FULL_FOC_DRA_STRT_EN 0x14006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
72987 #define XSEM_REG_INVLD_PAS_WR_EN 0x1400900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
72991 #define XSEM_REG_ARB_AS_DEF 0x1400a00UL //Access:RW DataWidth:0x3 // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
73005 #define XSEM_REG_ORDER_EMPTY 0x1400d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
73016 #define XSEM_REG_DRA_EMPTY 0x1401100UL //Access:R DataWidth:0x1 // Dra_empty.
73017 #define XSEM_REG_EXT_PAS_EMPTY 0x1401104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
73018 #define XSEM_REG_FIC_EMPTY 0x1401120UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
73020 #define XSEM_REG_SLOW_DBG_EMPTY 0x1401140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
73021 #define XSEM_REG_SLOW_DRA_FIN_EMPTY 0x1401144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
73022 #define XSEM_REG_SLOW_DRA_RD_EMPTY 0x1401148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
73023 #define XSEM_REG_SLOW_DRA_WR_EMPTY 0x140114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
73024 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x1401150UL //Access:R DataWidth:0x1 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
73025 #define XSEM_REG_SLOW_EXT_LOAD_EMPTY 0x1401154UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is empty in sem_slow_ls_ext.
73026 #define XSEM_REG_SLOW_RAM_RD_EMPTY 0x1401158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
73027 #define XSEM_REG_SLOW_RAM_WR_EMPTY 0x140115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
73028 #define XSEM_REG_SYNC_DBG_EMPTY 0x1401160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
73029 #define XSEM_REG_THREAD_FIFO_EMPTY 0x1401164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
73030 #define XSEM_REG_ORD_ID_FIFO_EMPTY 0x1401168UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
73031 #define XSEM_REG_EXT_PAS_FULL 0x1401200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
73032 #define XSEM_REG_EXT_STORE_IF_FULL 0x1401204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
73033 #define XSEM_REG_FIC_FULL 0x1401220UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
73035 #define XSEM_REG_PAS_IF_FULL 0x1401240UL //Access:R DataWidth:0x1 // Full from passive buffer asserted toward SDM.
73036 #define XSEM_REG_RAM_IF_FULL 0x1401244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
73037 #define XSEM_REG_SLOW_DBG_ALM_FULL 0x1401248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
73038 #define XSEM_REG_SLOW_DBG_FULL 0x140124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
73039 #define XSEM_REG_SLOW_DRA_FIN_FULL 0x1401250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (never may be active).
73040 #define XSEM_REG_SLOW_DRA_RD_FULL 0x1401254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
73041 #define XSEM_REG_SLOW_DRA_WR_FULL 0x1401258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
73042 #define XSEM_REG_SLOW_EXT_STORE_FULL 0x140125cUL //Access:R DataWidth:0x1 // EXT_STORE FIFO is full in sem_slow_ls_ext.
73043 #define XSEM_REG_SLOW_EXT_LOAD_FULL 0x1401260UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is full in sem_slow_ls_ext.
73044 #define XSEM_REG_SLOW_RAM_RD_FULL 0x1401264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
73045 #define XSEM_REG_SLOW_RAM_WR_ALM_FULL 0x1401268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
73046 #define XSEM_REG_SLOW_RAM_WR_FULL 0x140126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
73047 #define XSEM_REG_SYNC_DBG_FULL 0x1401270UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.
73048 #define XSEM_REG_THREAD_FIFO_FULL 0x1401274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
73049 #define XSEM_REG_ORD_ID_FIFO_FULL 0x1401278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
73051 #define XSEM_REG_THREAD_INTER_CNT_ENABLE 0x1401304UL //Access:RW DataWidth:0x1 // Enable for start count of thread_inter_cnt.
73053 #define XSEM_REG_SLOW_DBG_ACTIVE 0x1401400UL //Access:RW DataWidth:0x1 // Debug mode is active.
73056 #define XSEM_REG_DBG_EACH_CYLE 0x140140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is a change.
73058 #define XSEM_REG_DBG_IF_FULL 0x1401414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
73059 #define XSEM_REG_DBG_MODE0_CFG 0x1401418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
73061 #define XSEM_REG_DBG_MODE1_CFG 0x1401420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
73083 #define YSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN (0x1<<0) // Full input from external IF to LS input enable.
73085 #define YSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN (0x1<<1) // Read data from external LS IF input enable.
73087 #define YSEM_REG_ENABLE_IN_FIC_ENABLE_IN (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
73089 #define YSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
73091 #define YSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN (0x1<<4) // General interface input enable.
73093 #define YSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN (0x1<<5) // External passive write input enable.
73095 #define YSEM_REG_ENABLE_IN_RAM_ENABLE_IN (0x1<<6) // Data input enable to RAM.
73097 #define YSEM_REG_ENABLE_IN_STALL_ENABLE_IN (0x1<<7) // Enable for stall input from all external STORM instances.
73099 #define YSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN (0x1<<8) // Thread ready bus input enable.
73101 #define YSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
73104 #define YSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT (0x1<<0) // Read request output enable from external LS IF.
73106 #define YSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT (0x1<<1) // Write request output enable from external LS IF.
73108 #define YSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
73110 #define YSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT (0x1<<3) // Passive full output enable.
73112 #define YSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT (0x1<<4) // Data output enable to RAM.
73114 #define YSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
73116 #define YSEM_REG_FIC_DISABLE 0x150000cUL //Access:RW DataWidth:0x1 // Disables input messages from all FIC interfaces. May be updated during run_time by the microcode.
73117 #define YSEM_REG_PAS_DISABLE 0x1500010UL //Access:RW DataWidth:0x1 // Disables input messages from the passive buffer May be updated during run_time by the microcode.
73119 #define YSEM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
73121 #define YSEM_REG_INT_STS_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
73123 #define YSEM_REG_INT_STS_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
73125 #define YSEM_REG_INT_STS_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
73127 #define YSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
73129 #define YSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
73131 #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
73133 #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
73135 #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
73137 #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
73139 #define YSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
73141 #define YSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
73143 #define YSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
73145 #define YSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
73147 #define YSEM_REG_INT_STS_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
73149 #define YSEM_REG_INT_STS_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
73151 #define YSEM_REG_INT_STS_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
73153 #define YSEM_REG_INT_STS_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
73155 #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
73157 #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
73159 #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
73161 #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
73163 #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
73165 #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
73167 #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
73169 #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
73171 #define YSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
73173 #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
73175 #define YSEM_REG_INT_STS_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
73177 #define YSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
73179 #define YSEM_REG_INT_STS_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
73181 #define YSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
73184 #define YSEM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.ADDRESS_ERROR .
73186 #define YSEM_REG_INT_MASK_0_FIC_LAST_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_LAST_ERROR .
73188 #define YSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
73190 #define YSEM_REG_INT_MASK_0_FIC_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
73192 #define YSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
73194 #define YSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
73196 #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
73198 #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
73200 #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
73202 #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
73204 #define YSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
73206 #define YSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
73208 #define YSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
73210 #define YSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO (0x1<<13) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
73212 #define YSEM_REG_INT_MASK_0_CAM_OUT_FIFO (0x1<<14) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_OUT_FIFO .
73214 #define YSEM_REG_INT_MASK_0_FIN_FIFO (0x1<<15) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIN_FIFO .
73216 #define YSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
73218 #define YSEM_REG_INT_MASK_0_THREAD_OVERRUN (0x1<<17) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.THREAD_OVERRUN .
73220 #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
73222 #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
73224 #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
73226 #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
73228 #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
73230 #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
73232 #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
73234 #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
73236 #define YSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
73238 #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
73240 #define YSEM_REG_INT_MASK_0_DBG_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
73242 #define YSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO (0x1<<29) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
73244 #define YSEM_REG_INT_MASK_0_VFC_INTERRUPT (0x1<<30) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.VFC_INTERRUPT .
73246 #define YSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
73249 #define YSEM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
73251 #define YSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
73253 #define YSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
73255 #define YSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
73257 #define YSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
73259 #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
73261 #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
73263 #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
73265 #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
73267 #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
73269 #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
73271 #define YSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
73273 #define YSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
73275 #define YSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
73277 #define YSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
73279 #define YSEM_REG_INT_STS_WR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
73281 #define YSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
73283 #define YSEM_REG_INT_STS_WR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
73285 #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
73287 #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
73289 #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
73291 #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
73293 #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
73295 #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
73297 #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
73299 #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
73301 #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
73303 #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
73305 #define YSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
73307 #define YSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
73309 #define YSEM_REG_INT_STS_WR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
73311 #define YSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
73314 #define YSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
73316 #define YSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
73318 #define YSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
73320 #define YSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
73322 #define YSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
73324 #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
73326 #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
73328 #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
73330 #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
73332 #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
73334 #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
73336 #define YSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
73338 #define YSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
73340 #define YSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
73342 #define YSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
73344 #define YSEM_REG_INT_STS_CLR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
73346 #define YSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
73348 #define YSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
73350 #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
73352 #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
73354 #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
73356 #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
73358 #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
73360 #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
73362 #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
73364 #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
73366 #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
73368 #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
73370 #define YSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
73372 #define YSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
73374 #define YSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
73376 #define YSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
73379 #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
73381 #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
73383 #define YSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
73385 #define YSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
73387 #define YSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
73389 #define YSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
73391 #define YSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
73393 #define YSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
73395 #define YSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
73397 #define YSEM_REG_INT_STS_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
73399 #define YSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
73401 #define YSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
73403 #define YSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
73406 #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
73408 #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
73410 #define YSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
73412 #define YSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
73414 #define YSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
73416 #define YSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
73418 #define YSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
73420 #define YSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
73422 #define YSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
73424 #define YSEM_REG_INT_MASK_1_INVLD_FOC_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
73426 #define YSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
73428 #define YSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
73430 #define YSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
73433 #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
73435 #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
73437 #define YSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
73439 #define YSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
73441 #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
73443 #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
73445 #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
73447 #define YSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
73449 #define YSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
73451 #define YSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
73453 #define YSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
73455 #define YSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
73457 #define YSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
73460 #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
73462 #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
73464 #define YSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
73466 #define YSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
73468 #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
73470 #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
73472 #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
73474 #define YSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
73476 #define YSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
73478 #define YSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
73480 #define YSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
73482 #define YSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
73484 #define YSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
73487 #define YSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
73489 #define YSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR (0x1<<1) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
73491 #define YSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR (0x1<<2) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
73494 #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
73496 #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
73498 #define YSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
73500 #define YSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
73502 #define YSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
73504 #define YSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
73506 #define YSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
73509 #define YSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_buf_ram_ysem
73511 #define YSEM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_buf_ram_ysem
73514 #define YSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_buf_ram_ysem
73516 #define YSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_buf_ram_ysem
73519 #define YSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_0 in module sem_slow_pas_buf_ram_ysem
73521 #define YSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_ecc_1 in module sem_slow_pas_buf_ram_ysem
73525 #define YSEM_REG_VF_ERROR 0x1500408UL //Access:WR DataWidth:0x1 // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
73526 #define YSEM_REG_PF_ERROR 0x150040cUL //Access:WR DataWidth:0x1 // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
73530 #define YSEM_REG_CLEAR_STALL 0x1500444UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
73535 #define YSEM_REG_ALLOW_LP_SLEEP_THRD 0x1500458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
73543 #define YSEM_REG_FIC_EMPTY_CT_MODE 0x1500620UL //Access:RW DataWidth:0x1 // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
73547 #define YSEM_REG_FULL_FOC_DRA_STRT_EN 0x15006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
73552 #define YSEM_REG_INVLD_PAS_WR_EN 0x1500900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
73556 #define YSEM_REG_ARB_AS_DEF 0x1500a00UL //Access:RW DataWidth:0x3 // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
73570 #define YSEM_REG_ORDER_EMPTY 0x1500d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
73581 #define YSEM_REG_DRA_EMPTY 0x1501100UL //Access:R DataWidth:0x1 // Dra_empty.
73582 #define YSEM_REG_EXT_PAS_EMPTY 0x1501104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
73583 #define YSEM_REG_FIC_EMPTY 0x1501120UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
73585 #define YSEM_REG_SLOW_DBG_EMPTY 0x1501140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
73586 #define YSEM_REG_SLOW_DRA_FIN_EMPTY 0x1501144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
73587 #define YSEM_REG_SLOW_DRA_RD_EMPTY 0x1501148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
73588 #define YSEM_REG_SLOW_DRA_WR_EMPTY 0x150114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
73589 #define YSEM_REG_SLOW_EXT_STORE_EMPTY 0x1501150UL //Access:R DataWidth:0x1 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
73590 #define YSEM_REG_SLOW_EXT_LOAD_EMPTY 0x1501154UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is empty in sem_slow_ls_ext.
73591 #define YSEM_REG_SLOW_RAM_RD_EMPTY 0x1501158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
73592 #define YSEM_REG_SLOW_RAM_WR_EMPTY 0x150115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
73593 #define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
73594 #define YSEM_REG_THREAD_FIFO_EMPTY 0x1501164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
73595 #define YSEM_REG_ORD_ID_FIFO_EMPTY 0x1501168UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
73596 #define YSEM_REG_EXT_PAS_FULL 0x1501200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
73597 #define YSEM_REG_EXT_STORE_IF_FULL 0x1501204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
73598 #define YSEM_REG_FIC_FULL 0x1501220UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
73600 #define YSEM_REG_PAS_IF_FULL 0x1501240UL //Access:R DataWidth:0x1 // Full from passive buffer asserted toward SDM.
73601 #define YSEM_REG_RAM_IF_FULL 0x1501244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
73602 #define YSEM_REG_SLOW_DBG_ALM_FULL 0x1501248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
73603 #define YSEM_REG_SLOW_DBG_FULL 0x150124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
73604 #define YSEM_REG_SLOW_DRA_FIN_FULL 0x1501250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (never may be active).
73605 #define YSEM_REG_SLOW_DRA_RD_FULL 0x1501254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
73606 #define YSEM_REG_SLOW_DRA_WR_FULL 0x1501258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
73607 #define YSEM_REG_SLOW_EXT_STORE_FULL 0x150125cUL //Access:R DataWidth:0x1 // EXT_STORE FIFO is full in sem_slow_ls_ext.
73608 #define YSEM_REG_SLOW_EXT_LOAD_FULL 0x1501260UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is full in sem_slow_ls_ext.
73609 #define YSEM_REG_SLOW_RAM_RD_FULL 0x1501264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
73610 #define YSEM_REG_SLOW_RAM_WR_ALM_FULL 0x1501268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
73611 #define YSEM_REG_SLOW_RAM_WR_FULL 0x150126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
73612 #define YSEM_REG_SYNC_DBG_FULL 0x1501270UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.
73613 #define YSEM_REG_THREAD_FIFO_FULL 0x1501274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
73614 #define YSEM_REG_ORD_ID_FIFO_FULL 0x1501278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
73616 #define YSEM_REG_THREAD_INTER_CNT_ENABLE 0x1501304UL //Access:RW DataWidth:0x1 // Enable for start count of thread_inter_cnt.
73618 #define YSEM_REG_SLOW_DBG_ACTIVE 0x1501400UL //Access:RW DataWidth:0x1 // Debug mode is active.
73621 #define YSEM_REG_DBG_EACH_CYLE 0x150140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is a change.
73623 #define YSEM_REG_DBG_IF_FULL 0x1501414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
73624 #define YSEM_REG_DBG_MODE0_CFG 0x1501418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
73626 #define YSEM_REG_DBG_MODE1_CFG 0x1501420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
73648 #define PSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN (0x1<<0) // Full input from external IF to LS input enable.
73650 #define PSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN (0x1<<1) // Read data from external LS IF input enable.
73652 #define PSEM_REG_ENABLE_IN_FIC_ENABLE_IN (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
73654 #define PSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
73656 #define PSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN (0x1<<4) // General interface input enable.
73658 #define PSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN (0x1<<5) // External passive write input enable.
73660 #define PSEM_REG_ENABLE_IN_RAM_ENABLE_IN (0x1<<6) // Data input enable to RAM.
73662 #define PSEM_REG_ENABLE_IN_STALL_ENABLE_IN (0x1<<7) // Enable for stall input from all external STORM instances.
73664 #define PSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN (0x1<<8) // Thread ready bus input enable.
73666 #define PSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
73669 #define PSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT (0x1<<0) // Read request output enable from external LS IF.
73671 #define PSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT (0x1<<1) // Write request output enable from external LS IF.
73673 #define PSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
73675 #define PSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT (0x1<<3) // Passive full output enable.
73677 #define PSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT (0x1<<4) // Data output enable to RAM.
73679 #define PSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
73681 #define PSEM_REG_FIC_DISABLE 0x160000cUL //Access:RW DataWidth:0x1 // Disables input messages from all FIC interfaces. May be updated during run_time by the microcode.
73682 #define PSEM_REG_PAS_DISABLE 0x1600010UL //Access:RW DataWidth:0x1 // Disables input messages from the passive buffer May be updated during run_time by the microcode.
73684 #define PSEM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
73686 #define PSEM_REG_INT_STS_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
73688 #define PSEM_REG_INT_STS_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
73690 #define PSEM_REG_INT_STS_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
73692 #define PSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
73694 #define PSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
73696 #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
73698 #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
73700 #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
73702 #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
73704 #define PSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
73706 #define PSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
73708 #define PSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
73710 #define PSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
73712 #define PSEM_REG_INT_STS_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
73714 #define PSEM_REG_INT_STS_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
73716 #define PSEM_REG_INT_STS_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
73718 #define PSEM_REG_INT_STS_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
73720 #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
73722 #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
73724 #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
73726 #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
73728 #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
73730 #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
73732 #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
73734 #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
73736 #define PSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
73738 #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
73740 #define PSEM_REG_INT_STS_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
73742 #define PSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
73744 #define PSEM_REG_INT_STS_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
73746 #define PSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
73749 #define PSEM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.ADDRESS_ERROR .
73751 #define PSEM_REG_INT_MASK_0_FIC_LAST_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_LAST_ERROR .
73753 #define PSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
73755 #define PSEM_REG_INT_MASK_0_FIC_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
73757 #define PSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
73759 #define PSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
73761 #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
73763 #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
73765 #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
73767 #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
73769 #define PSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
73771 #define PSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
73773 #define PSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
73775 #define PSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO (0x1<<13) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
73777 #define PSEM_REG_INT_MASK_0_CAM_OUT_FIFO (0x1<<14) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_OUT_FIFO .
73779 #define PSEM_REG_INT_MASK_0_FIN_FIFO (0x1<<15) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIN_FIFO .
73781 #define PSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
73783 #define PSEM_REG_INT_MASK_0_THREAD_OVERRUN (0x1<<17) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.THREAD_OVERRUN .
73785 #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
73787 #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
73789 #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
73791 #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
73793 #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
73795 #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
73797 #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
73799 #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
73801 #define PSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
73803 #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
73805 #define PSEM_REG_INT_MASK_0_DBG_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
73807 #define PSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO (0x1<<29) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
73809 #define PSEM_REG_INT_MASK_0_VFC_INTERRUPT (0x1<<30) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.VFC_INTERRUPT .
73811 #define PSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
73814 #define PSEM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
73816 #define PSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
73818 #define PSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
73820 #define PSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
73822 #define PSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
73824 #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
73826 #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
73828 #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
73830 #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
73832 #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
73834 #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
73836 #define PSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
73838 #define PSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
73840 #define PSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
73842 #define PSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
73844 #define PSEM_REG_INT_STS_WR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
73846 #define PSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
73848 #define PSEM_REG_INT_STS_WR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
73850 #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
73852 #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
73854 #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
73856 #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
73858 #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
73860 #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
73862 #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
73864 #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
73866 #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
73868 #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
73870 #define PSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
73872 #define PSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
73874 #define PSEM_REG_INT_STS_WR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
73876 #define PSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
73879 #define PSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
73881 #define PSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
73883 #define PSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
73885 #define PSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
73887 #define PSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
73889 #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
73891 #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
73893 #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
73895 #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
73897 #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
73899 #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
73901 #define PSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
73903 #define PSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
73905 #define PSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
73907 #define PSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
73909 #define PSEM_REG_INT_STS_CLR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
73911 #define PSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
73913 #define PSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
73915 #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
73917 #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
73919 #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
73921 #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
73923 #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
73925 #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
73927 #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
73929 #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
73931 #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
73933 #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
73935 #define PSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
73937 #define PSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
73939 #define PSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
73941 #define PSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
73944 #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
73946 #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
73948 #define PSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
73950 #define PSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
73952 #define PSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
73954 #define PSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
73956 #define PSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
73958 #define PSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
73960 #define PSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
73962 #define PSEM_REG_INT_STS_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
73964 #define PSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
73966 #define PSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
73968 #define PSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
73971 #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
73973 #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
73975 #define PSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
73977 #define PSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
73979 #define PSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
73981 #define PSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
73983 #define PSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
73985 #define PSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
73987 #define PSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
73989 #define PSEM_REG_INT_MASK_1_INVLD_FOC_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
73991 #define PSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
73993 #define PSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
73995 #define PSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
73998 #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
74000 #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
74002 #define PSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
74004 #define PSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
74006 #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
74008 #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
74010 #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
74012 #define PSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
74014 #define PSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
74016 #define PSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
74018 #define PSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
74020 #define PSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
74022 #define PSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
74025 #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
74027 #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
74029 #define PSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
74031 #define PSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
74033 #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
74035 #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
74037 #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
74039 #define PSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
74041 #define PSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
74043 #define PSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
74045 #define PSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
74047 #define PSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
74049 #define PSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
74052 #define PSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
74054 #define PSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR (0x1<<1) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
74056 #define PSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR (0x1<<2) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
74059 #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
74061 #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
74063 #define PSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
74065 #define PSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
74067 #define PSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
74069 #define PSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
74072 #define PSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_buf_ram_psem
74074 #define PSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_buf_ram_psem
74077 #define PSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_buf_ram_psem
74079 #define PSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_buf_ram_psem
74082 #define PSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_0 in module sem_slow_pas_buf_ram_psem
74084 #define PSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_ecc_1 in module sem_slow_pas_buf_ram_psem
74088 #define PSEM_REG_VF_ERROR 0x1600408UL //Access:WR DataWidth:0x1 // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
74089 #define PSEM_REG_PF_ERROR 0x160040cUL //Access:WR DataWidth:0x1 // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
74093 #define PSEM_REG_CLEAR_STALL 0x1600444UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
74098 #define PSEM_REG_ALLOW_LP_SLEEP_THRD 0x1600458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
74105 #define PSEM_REG_FIC_EMPTY_CT_MODE 0x1600620UL //Access:RW DataWidth:0x1 // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
74109 #define PSEM_REG_FULL_FOC_DRA_STRT_EN 0x16006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
74114 #define PSEM_REG_INVLD_PAS_WR_EN 0x1600900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
74118 #define PSEM_REG_ARB_AS_DEF 0x1600a00UL //Access:RW DataWidth:0x3 // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
74132 #define PSEM_REG_ORDER_EMPTY 0x1600d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
74138 #define PSEM_REG_PF_NUM_ORDER_BASE 0x1600e10UL //Access:RW DataWidth:0x1 // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.
74143 #define PSEM_REG_DRA_EMPTY 0x1601100UL //Access:R DataWidth:0x1 // Dra_empty.
74144 #define PSEM_REG_EXT_PAS_EMPTY 0x1601104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
74145 #define PSEM_REG_FIC_EMPTY 0x1601120UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
74146 #define PSEM_REG_SLOW_DBG_EMPTY 0x1601140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
74147 #define PSEM_REG_SLOW_DRA_FIN_EMPTY 0x1601144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
74148 #define PSEM_REG_SLOW_DRA_RD_EMPTY 0x1601148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
74149 #define PSEM_REG_SLOW_DRA_WR_EMPTY 0x160114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
74150 #define PSEM_REG_SLOW_EXT_STORE_EMPTY 0x1601150UL //Access:R DataWidth:0x1 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
74151 #define PSEM_REG_SLOW_EXT_LOAD_EMPTY 0x1601154UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is empty in sem_slow_ls_ext.
74152 #define PSEM_REG_SLOW_RAM_RD_EMPTY 0x1601158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
74153 #define PSEM_REG_SLOW_RAM_WR_EMPTY 0x160115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
74154 #define PSEM_REG_SYNC_DBG_EMPTY 0x1601160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
74155 #define PSEM_REG_THREAD_FIFO_EMPTY 0x1601164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
74156 #define PSEM_REG_ORD_ID_FIFO_EMPTY 0x1601168UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
74157 #define PSEM_REG_EXT_PAS_FULL 0x1601200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
74158 #define PSEM_REG_EXT_STORE_IF_FULL 0x1601204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
74159 #define PSEM_REG_FIC_FULL 0x1601220UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
74160 #define PSEM_REG_PAS_IF_FULL 0x1601240UL //Access:R DataWidth:0x1 // Full from passive buffer asserted toward SDM.
74161 #define PSEM_REG_RAM_IF_FULL 0x1601244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
74162 #define PSEM_REG_SLOW_DBG_ALM_FULL 0x1601248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
74163 #define PSEM_REG_SLOW_DBG_FULL 0x160124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
74164 #define PSEM_REG_SLOW_DRA_FIN_FULL 0x1601250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (never may be active).
74165 #define PSEM_REG_SLOW_DRA_RD_FULL 0x1601254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
74166 #define PSEM_REG_SLOW_DRA_WR_FULL 0x1601258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
74167 #define PSEM_REG_SLOW_EXT_STORE_FULL 0x160125cUL //Access:R DataWidth:0x1 // EXT_STORE FIFO is full in sem_slow_ls_ext.
74168 #define PSEM_REG_SLOW_EXT_LOAD_FULL 0x1601260UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is full in sem_slow_ls_ext.
74169 #define PSEM_REG_SLOW_RAM_RD_FULL 0x1601264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
74170 #define PSEM_REG_SLOW_RAM_WR_ALM_FULL 0x1601268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
74171 #define PSEM_REG_SLOW_RAM_WR_FULL 0x160126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
74172 #define PSEM_REG_SYNC_DBG_FULL 0x1601270UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.
74173 #define PSEM_REG_THREAD_FIFO_FULL 0x1601274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
74174 #define PSEM_REG_ORD_ID_FIFO_FULL 0x1601278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
74176 #define PSEM_REG_THREAD_INTER_CNT_ENABLE 0x1601304UL //Access:RW DataWidth:0x1 // Enable for start count of thread_inter_cnt.
74178 #define PSEM_REG_SLOW_DBG_ACTIVE 0x1601400UL //Access:RW DataWidth:0x1 // Debug mode is active.
74181 #define PSEM_REG_DBG_EACH_CYLE 0x160140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is a change.
74183 #define PSEM_REG_DBG_IF_FULL 0x1601414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
74184 #define PSEM_REG_DBG_MODE0_CFG 0x1601418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
74186 #define PSEM_REG_DBG_MODE1_CFG 0x1601420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
74208 #define TSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN (0x1<<0) // Full input from external IF to LS input enable.
74210 #define TSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN (0x1<<1) // Read data from external LS IF input enable.
74212 #define TSEM_REG_ENABLE_IN_FIC_ENABLE_IN (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
74214 #define TSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
74216 #define TSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN (0x1<<4) // General interface input enable.
74218 #define TSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN (0x1<<5) // External passive write input enable.
74220 #define TSEM_REG_ENABLE_IN_RAM_ENABLE_IN (0x1<<6) // Data input enable to RAM.
74222 #define TSEM_REG_ENABLE_IN_STALL_ENABLE_IN (0x1<<7) // Enable for stall input from all external STORM instances.
74224 #define TSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN (0x1<<8) // Thread ready bus input enable.
74226 #define TSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
74229 #define TSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT (0x1<<0) // Read request output enable from external LS IF.
74231 #define TSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT (0x1<<1) // Write request output enable from external LS IF.
74233 #define TSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
74235 #define TSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT (0x1<<3) // Passive full output enable.
74237 #define TSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT (0x1<<4) // Data output enable to RAM.
74239 #define TSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
74241 #define TSEM_REG_FIC_DISABLE 0x170000cUL //Access:RW DataWidth:0x1 // Disables input messages from all FIC interfaces. May be updated during run_time by the microcode.
74242 #define TSEM_REG_PAS_DISABLE 0x1700010UL //Access:RW DataWidth:0x1 // Disables input messages from the passive buffer May be updated during run_time by the microcode.
74244 #define TSEM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
74246 #define TSEM_REG_INT_STS_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
74248 #define TSEM_REG_INT_STS_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
74250 #define TSEM_REG_INT_STS_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
74252 #define TSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
74254 #define TSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
74256 #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
74258 #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
74260 #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
74262 #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
74264 #define TSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
74266 #define TSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
74268 #define TSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
74270 #define TSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
74272 #define TSEM_REG_INT_STS_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
74274 #define TSEM_REG_INT_STS_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
74276 #define TSEM_REG_INT_STS_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
74278 #define TSEM_REG_INT_STS_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
74280 #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
74282 #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
74284 #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
74286 #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
74288 #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
74290 #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
74292 #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
74294 #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
74296 #define TSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
74298 #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
74300 #define TSEM_REG_INT_STS_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
74302 #define TSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
74304 #define TSEM_REG_INT_STS_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
74306 #define TSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
74309 #define TSEM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.ADDRESS_ERROR .
74311 #define TSEM_REG_INT_MASK_0_FIC_LAST_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_LAST_ERROR .
74313 #define TSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
74315 #define TSEM_REG_INT_MASK_0_FIC_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
74317 #define TSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
74319 #define TSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
74321 #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
74323 #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
74325 #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
74327 #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
74329 #define TSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
74331 #define TSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
74333 #define TSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
74335 #define TSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO (0x1<<13) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
74337 #define TSEM_REG_INT_MASK_0_CAM_OUT_FIFO (0x1<<14) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_OUT_FIFO .
74339 #define TSEM_REG_INT_MASK_0_FIN_FIFO (0x1<<15) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIN_FIFO .
74341 #define TSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
74343 #define TSEM_REG_INT_MASK_0_THREAD_OVERRUN (0x1<<17) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.THREAD_OVERRUN .
74345 #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
74347 #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
74349 #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
74351 #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
74353 #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
74355 #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
74357 #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
74359 #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
74361 #define TSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
74363 #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
74365 #define TSEM_REG_INT_MASK_0_DBG_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
74367 #define TSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO (0x1<<29) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
74369 #define TSEM_REG_INT_MASK_0_VFC_INTERRUPT (0x1<<30) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.VFC_INTERRUPT .
74371 #define TSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
74374 #define TSEM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
74376 #define TSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
74378 #define TSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
74380 #define TSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
74382 #define TSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
74384 #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
74386 #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
74388 #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
74390 #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
74392 #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
74394 #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
74396 #define TSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
74398 #define TSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
74400 #define TSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
74402 #define TSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
74404 #define TSEM_REG_INT_STS_WR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
74406 #define TSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
74408 #define TSEM_REG_INT_STS_WR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
74410 #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
74412 #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
74414 #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
74416 #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
74418 #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
74420 #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
74422 #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
74424 #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
74426 #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
74428 #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
74430 #define TSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
74432 #define TSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
74434 #define TSEM_REG_INT_STS_WR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
74436 #define TSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
74439 #define TSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
74441 #define TSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
74443 #define TSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
74445 #define TSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
74447 #define TSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
74449 #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
74451 #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
74453 #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
74455 #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
74457 #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
74459 #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
74461 #define TSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
74463 #define TSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
74465 #define TSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
74467 #define TSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
74469 #define TSEM_REG_INT_STS_CLR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
74471 #define TSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
74473 #define TSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
74475 #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
74477 #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
74479 #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
74481 #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
74483 #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
74485 #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
74487 #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
74489 #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
74491 #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
74493 #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
74495 #define TSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
74497 #define TSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
74499 #define TSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
74501 #define TSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
74504 #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
74506 #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
74508 #define TSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
74510 #define TSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
74512 #define TSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
74514 #define TSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
74516 #define TSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
74518 #define TSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
74520 #define TSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
74522 #define TSEM_REG_INT_STS_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
74524 #define TSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
74526 #define TSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
74528 #define TSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
74531 #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
74533 #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
74535 #define TSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
74537 #define TSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
74539 #define TSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
74541 #define TSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
74543 #define TSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
74545 #define TSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
74547 #define TSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
74549 #define TSEM_REG_INT_MASK_1_INVLD_FOC_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
74551 #define TSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
74553 #define TSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
74555 #define TSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
74558 #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
74560 #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
74562 #define TSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
74564 #define TSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
74566 #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
74568 #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
74570 #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
74572 #define TSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
74574 #define TSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
74576 #define TSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
74578 #define TSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
74580 #define TSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
74582 #define TSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
74585 #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
74587 #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
74589 #define TSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
74591 #define TSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
74593 #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
74595 #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
74597 #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
74599 #define TSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
74601 #define TSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
74603 #define TSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
74605 #define TSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
74607 #define TSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
74609 #define TSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
74612 #define TSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
74614 #define TSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR (0x1<<1) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
74616 #define TSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR (0x1<<2) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
74619 #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
74621 #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
74623 #define TSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
74625 #define TSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
74627 #define TSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
74629 #define TSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
74632 #define TSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
74634 #define TSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
74637 #define TSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
74639 #define TSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
74642 #define TSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
74644 #define TSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
74648 #define TSEM_REG_VF_ERROR 0x1700408UL //Access:WR DataWidth:0x1 // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
74649 #define TSEM_REG_PF_ERROR 0x170040cUL //Access:WR DataWidth:0x1 // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
74653 #define TSEM_REG_CLEAR_STALL 0x1700444UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
74658 #define TSEM_REG_ALLOW_LP_SLEEP_THRD 0x1700458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
74665 #define TSEM_REG_FIC_EMPTY_CT_MODE 0x1700620UL //Access:RW DataWidth:0x1 // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
74669 #define TSEM_REG_FULL_FOC_DRA_STRT_EN 0x17006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
74674 #define TSEM_REG_INVLD_PAS_WR_EN 0x1700900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
74678 #define TSEM_REG_ARB_AS_DEF 0x1700a00UL //Access:RW DataWidth:0x3 // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
74692 #define TSEM_REG_ORDER_EMPTY 0x1700d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
74703 #define TSEM_REG_DRA_EMPTY 0x1701100UL //Access:R DataWidth:0x1 // Dra_empty.
74704 #define TSEM_REG_EXT_PAS_EMPTY 0x1701104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
74705 #define TSEM_REG_FIC_EMPTY 0x1701120UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
74706 #define TSEM_REG_SLOW_DBG_EMPTY 0x1701140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
74707 #define TSEM_REG_SLOW_DRA_FIN_EMPTY 0x1701144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
74708 #define TSEM_REG_SLOW_DRA_RD_EMPTY 0x1701148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
74709 #define TSEM_REG_SLOW_DRA_WR_EMPTY 0x170114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
74710 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1701150UL //Access:R DataWidth:0x1 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
74711 #define TSEM_REG_SLOW_EXT_LOAD_EMPTY 0x1701154UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is empty in sem_slow_ls_ext.
74712 #define TSEM_REG_SLOW_RAM_RD_EMPTY 0x1701158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
74713 #define TSEM_REG_SLOW_RAM_WR_EMPTY 0x170115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
74714 #define TSEM_REG_SYNC_DBG_EMPTY 0x1701160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
74715 #define TSEM_REG_THREAD_FIFO_EMPTY 0x1701164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
74716 #define TSEM_REG_ORD_ID_FIFO_EMPTY 0x1701168UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
74717 #define TSEM_REG_EXT_PAS_FULL 0x1701200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
74718 #define TSEM_REG_EXT_STORE_IF_FULL 0x1701204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
74719 #define TSEM_REG_FIC_FULL 0x1701220UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
74720 #define TSEM_REG_PAS_IF_FULL 0x1701240UL //Access:R DataWidth:0x1 // Full from passive buffer asserted toward SDM.
74721 #define TSEM_REG_RAM_IF_FULL 0x1701244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
74722 #define TSEM_REG_SLOW_DBG_ALM_FULL 0x1701248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
74723 #define TSEM_REG_SLOW_DBG_FULL 0x170124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
74724 #define TSEM_REG_SLOW_DRA_FIN_FULL 0x1701250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (never may be active).
74725 #define TSEM_REG_SLOW_DRA_RD_FULL 0x1701254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
74726 #define TSEM_REG_SLOW_DRA_WR_FULL 0x1701258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
74727 #define TSEM_REG_SLOW_EXT_STORE_FULL 0x170125cUL //Access:R DataWidth:0x1 // EXT_STORE FIFO is full in sem_slow_ls_ext.
74728 #define TSEM_REG_SLOW_EXT_LOAD_FULL 0x1701260UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is full in sem_slow_ls_ext.
74729 #define TSEM_REG_SLOW_RAM_RD_FULL 0x1701264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
74730 #define TSEM_REG_SLOW_RAM_WR_ALM_FULL 0x1701268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
74731 #define TSEM_REG_SLOW_RAM_WR_FULL 0x170126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
74732 #define TSEM_REG_SYNC_DBG_FULL 0x1701270UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.
74733 #define TSEM_REG_THREAD_FIFO_FULL 0x1701274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
74734 #define TSEM_REG_ORD_ID_FIFO_FULL 0x1701278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
74736 #define TSEM_REG_THREAD_INTER_CNT_ENABLE 0x1701304UL //Access:RW DataWidth:0x1 // Enable for start count of thread_inter_cnt.
74738 #define TSEM_REG_SLOW_DBG_ACTIVE 0x1701400UL //Access:RW DataWidth:0x1 // Debug mode is active.
74741 #define TSEM_REG_DBG_EACH_CYLE 0x170140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is a change.
74743 #define TSEM_REG_DBG_IF_FULL 0x1701414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
74744 #define TSEM_REG_DBG_MODE0_CFG 0x1701418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
74746 #define TSEM_REG_DBG_MODE1_CFG 0x1701420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
74768 #define MSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN (0x1<<0) // Full input from external IF to LS input enable.
74770 #define MSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN (0x1<<1) // Read data from external LS IF input enable.
74772 #define MSEM_REG_ENABLE_IN_FIC_ENABLE_IN (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
74774 #define MSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
74776 #define MSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN (0x1<<4) // General interface input enable.
74778 #define MSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN (0x1<<5) // External passive write input enable.
74780 #define MSEM_REG_ENABLE_IN_RAM_ENABLE_IN (0x1<<6) // Data input enable to RAM.
74782 #define MSEM_REG_ENABLE_IN_STALL_ENABLE_IN (0x1<<7) // Enable for stall input from all external STORM instances.
74784 #define MSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN (0x1<<8) // Thread ready bus input enable.
74786 #define MSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
74789 #define MSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT (0x1<<0) // Read request output enable from external LS IF.
74791 #define MSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT (0x1<<1) // Write request output enable from external LS IF.
74793 #define MSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
74795 #define MSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT (0x1<<3) // Passive full output enable.
74797 #define MSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT (0x1<<4) // Data output enable to RAM.
74799 #define MSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
74801 #define MSEM_REG_FIC_DISABLE 0x180000cUL //Access:RW DataWidth:0x1 // Disables input messages from all FIC interfaces. May be updated during run_time by the microcode.
74802 #define MSEM_REG_PAS_DISABLE 0x1800010UL //Access:RW DataWidth:0x1 // Disables input messages from the passive buffer May be updated during run_time by the microcode.
74804 #define MSEM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
74806 #define MSEM_REG_INT_STS_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
74808 #define MSEM_REG_INT_STS_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
74810 #define MSEM_REG_INT_STS_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
74812 #define MSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
74814 #define MSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
74816 #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
74818 #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
74820 #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
74822 #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
74824 #define MSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
74826 #define MSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
74828 #define MSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
74830 #define MSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
74832 #define MSEM_REG_INT_STS_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
74834 #define MSEM_REG_INT_STS_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
74836 #define MSEM_REG_INT_STS_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
74838 #define MSEM_REG_INT_STS_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
74840 #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
74842 #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
74844 #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
74846 #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
74848 #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
74850 #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
74852 #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
74854 #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
74856 #define MSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
74858 #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
74860 #define MSEM_REG_INT_STS_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
74862 #define MSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
74864 #define MSEM_REG_INT_STS_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
74866 #define MSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
74869 #define MSEM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.ADDRESS_ERROR .
74871 #define MSEM_REG_INT_MASK_0_FIC_LAST_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_LAST_ERROR .
74873 #define MSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
74875 #define MSEM_REG_INT_MASK_0_FIC_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
74877 #define MSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
74879 #define MSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
74881 #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
74883 #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
74885 #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
74887 #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
74889 #define MSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
74891 #define MSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
74893 #define MSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
74895 #define MSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO (0x1<<13) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
74897 #define MSEM_REG_INT_MASK_0_CAM_OUT_FIFO (0x1<<14) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_OUT_FIFO .
74899 #define MSEM_REG_INT_MASK_0_FIN_FIFO (0x1<<15) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIN_FIFO .
74901 #define MSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
74903 #define MSEM_REG_INT_MASK_0_THREAD_OVERRUN (0x1<<17) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.THREAD_OVERRUN .
74905 #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
74907 #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
74909 #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
74911 #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
74913 #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
74915 #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
74917 #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
74919 #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
74921 #define MSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
74923 #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
74925 #define MSEM_REG_INT_MASK_0_DBG_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
74927 #define MSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO (0x1<<29) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
74929 #define MSEM_REG_INT_MASK_0_VFC_INTERRUPT (0x1<<30) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.VFC_INTERRUPT .
74931 #define MSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
74934 #define MSEM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
74936 #define MSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
74938 #define MSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
74940 #define MSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
74942 #define MSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
74944 #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
74946 #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
74948 #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
74950 #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
74952 #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
74954 #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
74956 #define MSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
74958 #define MSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
74960 #define MSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
74962 #define MSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
74964 #define MSEM_REG_INT_STS_WR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
74966 #define MSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
74968 #define MSEM_REG_INT_STS_WR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
74970 #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
74972 #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
74974 #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
74976 #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
74978 #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
74980 #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
74982 #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
74984 #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
74986 #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
74988 #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
74990 #define MSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
74992 #define MSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
74994 #define MSEM_REG_INT_STS_WR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
74996 #define MSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
74999 #define MSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
75001 #define MSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
75003 #define MSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
75005 #define MSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
75007 #define MSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
75009 #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
75011 #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
75013 #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
75015 #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
75017 #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
75019 #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
75021 #define MSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
75023 #define MSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
75025 #define MSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
75027 #define MSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
75029 #define MSEM_REG_INT_STS_CLR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
75031 #define MSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
75033 #define MSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
75035 #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
75037 #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
75039 #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
75041 #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
75043 #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
75045 #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
75047 #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
75049 #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
75051 #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
75053 #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
75055 #define MSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
75057 #define MSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
75059 #define MSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
75061 #define MSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
75064 #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
75066 #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
75068 #define MSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
75070 #define MSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
75072 #define MSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
75074 #define MSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
75076 #define MSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
75078 #define MSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
75080 #define MSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
75082 #define MSEM_REG_INT_STS_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
75084 #define MSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
75086 #define MSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
75088 #define MSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
75091 #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
75093 #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
75095 #define MSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
75097 #define MSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
75099 #define MSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
75101 #define MSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
75103 #define MSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
75105 #define MSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
75107 #define MSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
75109 #define MSEM_REG_INT_MASK_1_INVLD_FOC_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
75111 #define MSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
75113 #define MSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
75115 #define MSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
75118 #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
75120 #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
75122 #define MSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
75124 #define MSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
75126 #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
75128 #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
75130 #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
75132 #define MSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
75134 #define MSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
75136 #define MSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
75138 #define MSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
75140 #define MSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
75142 #define MSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
75145 #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
75147 #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
75149 #define MSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
75151 #define MSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
75153 #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
75155 #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
75157 #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
75159 #define MSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
75161 #define MSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
75163 #define MSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
75165 #define MSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
75167 #define MSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
75169 #define MSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
75172 #define MSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
75174 #define MSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR (0x1<<1) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
75176 #define MSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR (0x1<<2) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
75179 #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
75181 #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
75183 #define MSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
75185 #define MSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
75187 #define MSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
75189 #define MSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
75192 #define MSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
75194 #define MSEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
75197 #define MSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
75199 #define MSEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
75202 #define MSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_0 in module sem_slow_pas_buf_ram
75204 #define MSEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_ecc_1 in module sem_slow_pas_buf_ram
75208 #define MSEM_REG_VF_ERROR 0x1800408UL //Access:WR DataWidth:0x1 // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
75209 #define MSEM_REG_PF_ERROR 0x180040cUL //Access:WR DataWidth:0x1 // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
75213 #define MSEM_REG_CLEAR_STALL 0x1800444UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
75218 #define MSEM_REG_ALLOW_LP_SLEEP_THRD 0x1800458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
75225 #define MSEM_REG_FIC_EMPTY_CT_MODE 0x1800620UL //Access:RW DataWidth:0x1 // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
75229 #define MSEM_REG_FULL_FOC_DRA_STRT_EN 0x18006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
75234 #define MSEM_REG_INVLD_PAS_WR_EN 0x1800900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
75238 #define MSEM_REG_ARB_AS_DEF 0x1800a00UL //Access:RW DataWidth:0x3 // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
75252 #define MSEM_REG_ORDER_EMPTY 0x1800d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
75263 #define MSEM_REG_DRA_EMPTY 0x1801100UL //Access:R DataWidth:0x1 // Dra_empty.
75264 #define MSEM_REG_EXT_PAS_EMPTY 0x1801104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
75265 #define MSEM_REG_FIC_EMPTY 0x1801120UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
75266 #define MSEM_REG_SLOW_DBG_EMPTY 0x1801140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
75267 #define MSEM_REG_SLOW_DRA_FIN_EMPTY 0x1801144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
75268 #define MSEM_REG_SLOW_DRA_RD_EMPTY 0x1801148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
75269 #define MSEM_REG_SLOW_DRA_WR_EMPTY 0x180114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
75270 #define MSEM_REG_SLOW_EXT_STORE_EMPTY 0x1801150UL //Access:R DataWidth:0x1 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
75271 #define MSEM_REG_SLOW_EXT_LOAD_EMPTY 0x1801154UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is empty in sem_slow_ls_ext.
75272 #define MSEM_REG_SLOW_RAM_RD_EMPTY 0x1801158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
75273 #define MSEM_REG_SLOW_RAM_WR_EMPTY 0x180115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
75274 #define MSEM_REG_SYNC_DBG_EMPTY 0x1801160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
75275 #define MSEM_REG_THREAD_FIFO_EMPTY 0x1801164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
75276 #define MSEM_REG_ORD_ID_FIFO_EMPTY 0x1801168UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
75277 #define MSEM_REG_EXT_PAS_FULL 0x1801200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
75278 #define MSEM_REG_EXT_STORE_IF_FULL 0x1801204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
75279 #define MSEM_REG_FIC_FULL 0x1801220UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
75280 #define MSEM_REG_PAS_IF_FULL 0x1801240UL //Access:R DataWidth:0x1 // Full from passive buffer asserted toward SDM.
75281 #define MSEM_REG_RAM_IF_FULL 0x1801244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
75282 #define MSEM_REG_SLOW_DBG_ALM_FULL 0x1801248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
75283 #define MSEM_REG_SLOW_DBG_FULL 0x180124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
75284 #define MSEM_REG_SLOW_DRA_FIN_FULL 0x1801250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (never may be active).
75285 #define MSEM_REG_SLOW_DRA_RD_FULL 0x1801254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
75286 #define MSEM_REG_SLOW_DRA_WR_FULL 0x1801258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
75287 #define MSEM_REG_SLOW_EXT_STORE_FULL 0x180125cUL //Access:R DataWidth:0x1 // EXT_STORE FIFO is full in sem_slow_ls_ext.
75288 #define MSEM_REG_SLOW_EXT_LOAD_FULL 0x1801260UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is full in sem_slow_ls_ext.
75289 #define MSEM_REG_SLOW_RAM_RD_FULL 0x1801264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
75290 #define MSEM_REG_SLOW_RAM_WR_ALM_FULL 0x1801268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
75291 #define MSEM_REG_SLOW_RAM_WR_FULL 0x180126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
75292 #define MSEM_REG_SYNC_DBG_FULL 0x1801270UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.
75293 #define MSEM_REG_THREAD_FIFO_FULL 0x1801274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
75294 #define MSEM_REG_ORD_ID_FIFO_FULL 0x1801278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
75296 #define MSEM_REG_THREAD_INTER_CNT_ENABLE 0x1801304UL //Access:RW DataWidth:0x1 // Enable for start count of thread_inter_cnt.
75298 #define MSEM_REG_SLOW_DBG_ACTIVE 0x1801400UL //Access:RW DataWidth:0x1 // Debug mode is active.
75301 #define MSEM_REG_DBG_EACH_CYLE 0x180140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is a change.
75303 #define MSEM_REG_DBG_IF_FULL 0x1801414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
75304 #define MSEM_REG_DBG_MODE0_CFG 0x1801418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
75306 #define MSEM_REG_DBG_MODE1_CFG 0x1801420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
75328 #define USEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN (0x1<<0) // Full input from external IF to LS input enable.
75330 #define USEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN (0x1<<1) // Read data from external LS IF input enable.
75332 #define USEM_REG_ENABLE_IN_FIC_ENABLE_IN (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
75334 #define USEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
75336 #define USEM_REG_ENABLE_IN_GENERAL_ENABLE_IN (0x1<<4) // General interface input enable.
75338 #define USEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN (0x1<<5) // External passive write input enable.
75340 #define USEM_REG_ENABLE_IN_RAM_ENABLE_IN (0x1<<6) // Data input enable to RAM.
75342 #define USEM_REG_ENABLE_IN_STALL_ENABLE_IN (0x1<<7) // Enable for stall input from all external STORM instances.
75344 #define USEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN (0x1<<8) // Thread ready bus input enable.
75346 #define USEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
75349 #define USEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT (0x1<<0) // Read request output enable from external LS IF.
75351 #define USEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT (0x1<<1) // Write request output enable from external LS IF.
75353 #define USEM_REG_ENABLE_OUT_FOC_ENABLE_OUT (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
75355 #define USEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT (0x1<<3) // Passive full output enable.
75357 #define USEM_REG_ENABLE_OUT_RAM_ENABLE_OUT (0x1<<4) // Data output enable to RAM.
75359 #define USEM_REG_ENABLE_OUT_STALL_ENABLE_OUT (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
75361 #define USEM_REG_FIC_DISABLE 0x190000cUL //Access:RW DataWidth:0x1 // Disables input messages from all FIC interfaces. May be updated during run_time by the microcode.
75362 #define USEM_REG_PAS_DISABLE 0x1900010UL //Access:RW DataWidth:0x1 // Disables input messages from the passive buffer May be updated during run_time by the microcode.
75364 #define USEM_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
75366 #define USEM_REG_INT_STS_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
75368 #define USEM_REG_INT_STS_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
75370 #define USEM_REG_INT_STS_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
75372 #define USEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
75374 #define USEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
75376 #define USEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
75378 #define USEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
75380 #define USEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
75382 #define USEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
75384 #define USEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
75386 #define USEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
75388 #define USEM_REG_INT_STS_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
75390 #define USEM_REG_INT_STS_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
75392 #define USEM_REG_INT_STS_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
75394 #define USEM_REG_INT_STS_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
75396 #define USEM_REG_INT_STS_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
75398 #define USEM_REG_INT_STS_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
75400 #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
75402 #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
75404 #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
75406 #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
75408 #define USEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
75410 #define USEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
75412 #define USEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
75414 #define USEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
75416 #define USEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
75418 #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
75420 #define USEM_REG_INT_STS_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
75422 #define USEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
75424 #define USEM_REG_INT_STS_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
75426 #define USEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
75429 #define USEM_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.ADDRESS_ERROR .
75431 #define USEM_REG_INT_MASK_0_FIC_LAST_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_LAST_ERROR .
75433 #define USEM_REG_INT_MASK_0_FIC_LENGTH_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
75435 #define USEM_REG_INT_MASK_0_FIC_FIFO_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_FIFO_ERROR .
75437 #define USEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
75439 #define USEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
75441 #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
75443 #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
75445 #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
75447 #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
75449 #define USEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
75451 #define USEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
75453 #define USEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
75455 #define USEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO (0x1<<13) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
75457 #define USEM_REG_INT_MASK_0_CAM_OUT_FIFO (0x1<<14) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_OUT_FIFO .
75459 #define USEM_REG_INT_MASK_0_FIN_FIFO (0x1<<15) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIN_FIFO .
75461 #define USEM_REG_INT_MASK_0_THREAD_FIFO_ERROR (0x1<<16) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
75463 #define USEM_REG_INT_MASK_0_THREAD_OVERRUN (0x1<<17) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.THREAD_OVERRUN .
75465 #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
75467 #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
75469 #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
75471 #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
75473 #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
75475 #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
75477 #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
75479 #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
75481 #define USEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
75483 #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR (0x1<<27) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
75485 #define USEM_REG_INT_MASK_0_DBG_FIFO_ERROR (0x1<<28) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.DBG_FIFO_ERROR .
75487 #define USEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO (0x1<<29) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
75489 #define USEM_REG_INT_MASK_0_VFC_INTERRUPT (0x1<<30) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.VFC_INTERRUPT .
75491 #define USEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
75494 #define USEM_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
75496 #define USEM_REG_INT_STS_WR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
75498 #define USEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
75500 #define USEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
75502 #define USEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
75504 #define USEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
75506 #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
75508 #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
75510 #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
75512 #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
75514 #define USEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
75516 #define USEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
75518 #define USEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
75520 #define USEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
75522 #define USEM_REG_INT_STS_WR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
75524 #define USEM_REG_INT_STS_WR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
75526 #define USEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
75528 #define USEM_REG_INT_STS_WR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
75530 #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
75532 #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
75534 #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
75536 #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
75538 #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
75540 #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
75542 #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
75544 #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
75546 #define USEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
75548 #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
75550 #define USEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
75552 #define USEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
75554 #define USEM_REG_INT_STS_WR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
75556 #define USEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
75559 #define USEM_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
75561 #define USEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
75563 #define USEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
75565 #define USEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR (0x1<<3) // Error in any one of the FIC FIFO is active.
75567 #define USEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR (0x1<<4) // Error in Ext PAS_FIFO is active.
75569 #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
75571 #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
75573 #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
75575 #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
75577 #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
75579 #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
75581 #define USEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR (0x1<<11) // Signals an unknown address in the fast-memory window.
75583 #define USEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
75585 #define USEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
75587 #define USEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO (0x1<<14) // Error in CAM_OUT fifo in cam block.
75589 #define USEM_REG_INT_STS_CLR_0_FIN_FIFO (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
75591 #define USEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
75593 #define USEM_REG_INT_STS_CLR_0_THREAD_OVERRUN (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
75595 #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR (0x1<<18) // Error in external store sync FIFO push logic.
75597 #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR (0x1<<19) // Error in external store sync FIFO pop logic.
75599 #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR (0x1<<20) // Error in external load sync FIFO push logic.
75601 #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR (0x1<<21) // Error in external load sync FIFO pop logic.
75603 #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
75605 #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR (0x1<<23) // Error in LS_SYNC_POP FIFO.
75607 #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR (0x1<<24) // Error in LS_SYNC_POP FIFO.
75609 #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
75611 #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
75613 #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR (0x1<<27) // Error in LS_SYNC_POP FIFO.
75615 #define USEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR (0x1<<28) // Error in slow debug fifo.
75617 #define USEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
75619 #define USEM_REG_INT_STS_CLR_0_VFC_INTERRUPT (0x1<<30) // Error interrupt in VFC block.
75621 #define USEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
75624 #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
75626 #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
75628 #define USEM_REG_INT_STS_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
75630 #define USEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
75632 #define USEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
75634 #define USEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
75636 #define USEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
75638 #define USEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
75640 #define USEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
75642 #define USEM_REG_INT_STS_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
75644 #define USEM_REG_INT_STS_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
75646 #define USEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
75648 #define USEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
75651 #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
75653 #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
75655 #define USEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
75657 #define USEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
75659 #define USEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
75661 #define USEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
75663 #define USEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
75665 #define USEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
75667 #define USEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
75669 #define USEM_REG_INT_MASK_1_INVLD_FOC_ERROR (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.INVLD_FOC_ERROR .
75671 #define USEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
75673 #define USEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
75675 #define USEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
75678 #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
75680 #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
75682 #define USEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
75684 #define USEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
75686 #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
75688 #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
75690 #define USEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
75692 #define USEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
75694 #define USEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
75696 #define USEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
75698 #define USEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
75700 #define USEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
75702 #define USEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
75705 #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN (0x1<<0) // An underflow error was detected in the Storm stack.
75707 #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN (0x1<<1) // An overflow error was detected in the Storm stack.
75709 #define USEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR (0x1<<2) // The Storm detected an illegal runtime value.
75711 #define USEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
75713 #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
75715 #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
75717 #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
75719 #define USEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
75721 #define USEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
75723 #define USEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
75725 #define USEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
75727 #define USEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
75729 #define USEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
75732 #define USEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR (0x1<<0) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
75734 #define USEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR (0x1<<1) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
75736 #define USEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR (0x1<<2) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
75739 #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
75741 #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
75743 #define USEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
75745 #define USEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
75747 #define USEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
75749 #define USEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
75752 #define USEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<0) // Enable ECC for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_buf_ram_usem
75754 #define USEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<1) // Enable ECC for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_buf_ram_usem
75757 #define USEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<0) // Set parity only for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_buf_ram_usem
75759 #define USEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<1) // Set parity only for memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_buf_ram_usem
75762 #define USEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_0 in module sem_slow_pas_buf_ram_usem
75764 #define USEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_ecc_1 in module sem_slow_pas_buf_ram_usem
75768 #define USEM_REG_VF_ERROR 0x1900408UL //Access:WR DataWidth:0x1 // This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.
75769 #define USEM_REG_PF_ERROR 0x190040cUL //Access:WR DataWidth:0x1 // This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.
75773 #define USEM_REG_CLEAR_STALL 0x1900444UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
75778 #define USEM_REG_ALLOW_LP_SLEEP_THRD 0x1900458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.
75785 #define USEM_REG_FIC_EMPTY_CT_MODE 0x1900620UL //Access:RW DataWidth:0x1 // When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.
75789 #define USEM_REG_FULL_FOC_DRA_STRT_EN 0x19006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.
75794 #define USEM_REG_INVLD_PAS_WR_EN 0x1900900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.
75798 #define USEM_REG_ARB_AS_DEF 0x1900a00UL //Access:RW DataWidth:0x3 // Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.
75812 #define USEM_REG_ORDER_EMPTY 0x1900d00UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.
75823 #define USEM_REG_DRA_EMPTY 0x1901100UL //Access:R DataWidth:0x1 // Dra_empty.
75824 #define USEM_REG_EXT_PAS_EMPTY 0x1901104UL //Access:R DataWidth:0x1 // EXT_PAS FIFO empty in sem_slow.
75825 #define USEM_REG_FIC_EMPTY 0x1901120UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO empty in sem_slow_fic.
75826 #define USEM_REG_SLOW_DBG_EMPTY 0x1901140UL //Access:R DataWidth:0x1 // DBG FIFO is empty in sem_slow_ls_dbg.
75827 #define USEM_REG_SLOW_DRA_FIN_EMPTY 0x1901144UL //Access:R DataWidth:0x1 // FIN fifo is empty in sem_slow_dra_sync.
75828 #define USEM_REG_SLOW_DRA_RD_EMPTY 0x1901148UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is empty in sem_slow_dra_sync.
75829 #define USEM_REG_SLOW_DRA_WR_EMPTY 0x190114cUL //Access:R DataWidth:0x1 // DRA_WR push fifo is empty in sem_slow_dra_sync.
75830 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x1901150UL //Access:R DataWidth:0x1 // EXT_STORE FIFO is empty in sem_slow_ls_ext.
75831 #define USEM_REG_SLOW_EXT_LOAD_EMPTY 0x1901154UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is empty in sem_slow_ls_ext.
75832 #define USEM_REG_SLOW_RAM_RD_EMPTY 0x1901158UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.
75833 #define USEM_REG_SLOW_RAM_WR_EMPTY 0x190115cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.
75834 #define USEM_REG_SYNC_DBG_EMPTY 0x1901160UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.
75835 #define USEM_REG_THREAD_FIFO_EMPTY 0x1901164UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is empty in sem_slow_dra_wr.
75836 #define USEM_REG_ORD_ID_FIFO_EMPTY 0x1901168UL //Access:R DataWidth:0x1 // Indicates that the order ID fifo is empty in sem_slow_dra_wr.
75837 #define USEM_REG_EXT_PAS_FULL 0x1901200UL //Access:R DataWidth:0x1 // EXT_PAS FIFO Full in sem_slow.
75838 #define USEM_REG_EXT_STORE_IF_FULL 0x1901204UL //Access:R DataWidth:0x1 // EXT_STORE IF is full in sem_slow_ls_ext.
75839 #define USEM_REG_FIC_FULL 0x1901220UL //Access:R DataWidth:0x1 // Array of registers reflects associated FIC FIFO full in sem_slow_fic.
75840 #define USEM_REG_PAS_IF_FULL 0x1901240UL //Access:R DataWidth:0x1 // Full from passive buffer asserted toward SDM.
75841 #define USEM_REG_RAM_IF_FULL 0x1901244UL //Access:R DataWidth:0x1 // EXT_RAM IF is full in sem_slow_ls_ram.
75842 #define USEM_REG_SLOW_DBG_ALM_FULL 0x1901248UL //Access:R DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.
75843 #define USEM_REG_SLOW_DBG_FULL 0x190124cUL //Access:R DataWidth:0x1 // DBG FIFO is full in sem_slow_ls_dbg.
75844 #define USEM_REG_SLOW_DRA_FIN_FULL 0x1901250UL //Access:R DataWidth:0x1 // FIN fifo is full in sem_slow_dra_sync (never may be active).
75845 #define USEM_REG_SLOW_DRA_RD_FULL 0x1901254UL //Access:R DataWidth:0x1 // DRA_RD pop fifo is full in sem_slow_dra_sync.
75846 #define USEM_REG_SLOW_DRA_WR_FULL 0x1901258UL //Access:R DataWidth:0x1 // DRA_WR push fifo is full in sem_slow_dra_sync.
75847 #define USEM_REG_SLOW_EXT_STORE_FULL 0x190125cUL //Access:R DataWidth:0x1 // EXT_STORE FIFO is full in sem_slow_ls_ext.
75848 #define USEM_REG_SLOW_EXT_LOAD_FULL 0x1901260UL //Access:R DataWidth:0x1 // EXT_LOAD FIFO is full in sem_slow_ls_ext.
75849 #define USEM_REG_SLOW_RAM_RD_FULL 0x1901264UL //Access:R DataWidth:0x1 // EXT_RD_RAM FIFO is full in sem_slow_ls_ext.
75850 #define USEM_REG_SLOW_RAM_WR_ALM_FULL 0x1901268UL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.
75851 #define USEM_REG_SLOW_RAM_WR_FULL 0x190126cUL //Access:R DataWidth:0x1 // EXT_WR_RAM FIFO is full in sem_slow_ls_ext.
75852 #define USEM_REG_SYNC_DBG_FULL 0x1901270UL //Access:R DataWidth:0x1 // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.
75853 #define USEM_REG_THREAD_FIFO_FULL 0x1901274UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
75854 #define USEM_REG_ORD_ID_FIFO_FULL 0x1901278UL //Access:R DataWidth:0x1 // Indicates that the thread fifo is full in sem_slow_dra_wr.
75856 #define USEM_REG_THREAD_INTER_CNT_ENABLE 0x1901304UL //Access:RW DataWidth:0x1 // Enable for start count of thread_inter_cnt.
75858 #define USEM_REG_SLOW_DBG_ACTIVE 0x1901400UL //Access:RW DataWidth:0x1 // Debug mode is active.
75861 #define USEM_REG_DBG_EACH_CYLE 0x190140cUL //Access:RW DataWidth:0x1 // 0=output every cycle; 1= output only when there is a change.
75863 #define USEM_REG_DBG_IF_FULL 0x1901414UL //Access:R DataWidth:0x1 // DBG IF is full in sem_slow_ls_dbg.
75864 #define USEM_REG_DBG_MODE0_CFG 0x1901418UL //Access:RW DataWidth:0x1 // 0=all the message; 1=partial message.
75866 #define USEM_REG_DBG_MODE1_CFG 0x1901420UL //Access:RW DataWidth:0x1 // 0=without the data; 1=with the data.
75900 #define PTLD_REG_TCFC_LOAD_MINI_CACHE_EN 0x19f0034UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
75901 #define PTLD_REG_CCFC_LOAD_MINI_CACHE_EN 0x19f0038UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
75943 #define PTLD_REG_LD_HDR_CLR 0x19f00e0UL //Access:W DataWidth:0x1 // Writing to this register clears hdr registers and enables logging new error details.
75949 #define PTLD_REG_LEN_ERR_LOG_CLR 0x19f00f8UL //Access:W DataWidth:0x1 // Writing to this register clears len err logging registers and enables logging new error details.
75950 #define PTLD_REG_LEN_ERR_LOG_V 0x19f00fcUL //Access:R DataWidth:0x1 // Indicates that the data at the len_err logging registers is valid.
75952 #define PTLD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
75954 #define PTLD_REG_INT_STS_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
75956 #define PTLD_REG_INT_STS_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
75958 #define PTLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
75960 #define PTLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
75962 #define PTLD_REG_INT_STS_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
75965 #define PTLD_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.ADDRESS_ERROR .
75967 #define PTLD_REG_INT_MASK_LD_HDR_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_HDR_ERR .
75969 #define PTLD_REG_INT_MASK_LD_SEG_MSG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_SEG_MSG_ERR .
75971 #define PTLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
75973 #define PTLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
75975 #define PTLD_REG_INT_MASK_LD_LONG_MESSAGE (0x1<<5) // This bit masks, when set, the Interrupt bit: PTLD_REG_INT_STS.LD_LONG_MESSAGE .
75978 #define PTLD_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
75980 #define PTLD_REG_INT_STS_WR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
75982 #define PTLD_REG_INT_STS_WR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
75984 #define PTLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
75986 #define PTLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
75988 #define PTLD_REG_INT_STS_WR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
75991 #define PTLD_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
75993 #define PTLD_REG_INT_STS_CLR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
75995 #define PTLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
75997 #define PTLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
75999 #define PTLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
76001 #define PTLD_REG_INT_STS_CLR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
76012 #define PTLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN (0x1<<0) // Enables L2 message aggregation
76014 #define PTLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK (0x1<<1) // defines that only back-to-back aggregation is allowed
76167 #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0 (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
76169 #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1 (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
76171 #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2 (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
76173 #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3 (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
76184 #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0 (0x1<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
76186 #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1 (0x1<<1) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
76188 #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2 (0x1<<2) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
76190 #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3 (0x1<<3) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
76240 #define YPLD_REG_TCFC_LOAD_MINI_CACHE_EN 0x1a10034UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
76241 #define YPLD_REG_CCFC_LOAD_MINI_CACHE_EN 0x1a10038UL //Access:RW DataWidth:0x1 // Allowes the TID/CID mini cache feature.
76283 #define YPLD_REG_LD_HDR_CLR 0x1a100e0UL //Access:W DataWidth:0x1 // Writing to this register clears hdr registers and enables logging new error details.
76289 #define YPLD_REG_LEN_ERR_LOG_CLR 0x1a100f8UL //Access:W DataWidth:0x1 // Writing to this register clears len err logging registers and enables logging new error details.
76290 #define YPLD_REG_LEN_ERR_LOG_V 0x1a100fcUL //Access:R DataWidth:0x1 // Indicates that the data at the len_err logging registers is valid.
76292 #define YPLD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
76294 #define YPLD_REG_INT_STS_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
76296 #define YPLD_REG_INT_STS_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
76298 #define YPLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
76300 #define YPLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
76302 #define YPLD_REG_INT_STS_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
76305 #define YPLD_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.ADDRESS_ERROR .
76307 #define YPLD_REG_INT_MASK_LD_HDR_ERR (0x1<<1) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_HDR_ERR .
76309 #define YPLD_REG_INT_MASK_LD_SEG_MSG_ERR (0x1<<2) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_SEG_MSG_ERR .
76311 #define YPLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR (0x1<<3) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
76313 #define YPLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR (0x1<<4) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
76315 #define YPLD_REG_INT_MASK_LD_LONG_MESSAGE (0x1<<5) // This bit masks, when set, the Interrupt bit: YPLD_REG_INT_STS.LD_LONG_MESSAGE .
76318 #define YPLD_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
76320 #define YPLD_REG_INT_STS_WR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
76322 #define YPLD_REG_INT_STS_WR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
76324 #define YPLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
76326 #define YPLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
76328 #define YPLD_REG_INT_STS_WR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
76331 #define YPLD_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
76333 #define YPLD_REG_INT_STS_CLR_LD_HDR_ERR (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
76335 #define YPLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
76337 #define YPLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
76339 #define YPLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
76341 #define YPLD_REG_INT_STS_CLR_LD_LONG_MESSAGE (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
76352 #define YPLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN (0x1<<0) // Enables L2 message aggregation
76354 #define YPLD_REG_L2MA_AGGR_CONFIG1_BACK_2_BACK (0x1<<1) // defines that only back-to-back aggregation is allowed
76507 #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0 (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
76509 #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1 (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
76511 #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_2 (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
76513 #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3 (0x1<<3) // indication if to include the flow-ID in the stream-ID for set 3.
76524 #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0 (0x1<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0.
76526 #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1 (0x1<<1) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1.
76528 #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2 (0x1<<2) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 2.
76530 #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3 (0x1<<3) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.