Lines Matching refs:x1
68 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it× â‚¬â„¢s enough that one of them support protection) */
70 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can× â‚¬â„¢t rely on this size × â‚¬â€œ it depends on vlan num) */
78 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
80 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
95 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
159 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */
161 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 /* AreSupport rec_tov timer */
163 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
165 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
189 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 /* SQ deferred (happens when we wait for xfer wqe to complete cleanup/abts */
191 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner vlan flag †for calculating eth header size */
193 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 /* Original vlan configuration. used when we switch from dcb enable to dcb disabled */
224 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 /* Intend to accelerate the protection flows */
226 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection is enough that one of them support protection) */
228 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can’t rely on this size †it depends on vlan num) */
230 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 /* Is size of tx_max_pay_len_prot can be aligned to protection intervals. This means that pure data in each frame is 2k exactly, and protection intervals are no bigger than 2k */
249 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
251 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
253 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
255 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
257 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
259 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
261 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
263 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
266 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
268 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
270 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
272 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
274 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
276 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
278 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
280 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */
334 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
336 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
339 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
341 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
343 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
345 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
347 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
349 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
351 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
353 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
356 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
358 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
360 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
362 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
364 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
366 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
368 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
370 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
373 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
375 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */
377 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
379 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
381 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
383 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
385 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
387 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
390 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
392 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
394 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */
396 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
398 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
400 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
402 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
404 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */
407 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */
409 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
411 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
413 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
415 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
417 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
419 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
421 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
424 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */
426 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
428 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
430 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
432 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
434 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
436 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
438 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
441 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
443 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
445 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
447 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
449 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
451 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
500 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
502 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
504 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
506 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
508 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
510 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
537 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */
539 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */
541 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
543 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
546 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
548 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
550 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
552 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
554 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
556 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
558 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
560 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
563 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
565 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
567 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
569 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
571 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
573 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
575 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
577 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
588 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
590 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
608 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
610 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
612 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
614 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
616 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
618 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
620 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
622 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
625 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
627 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
629 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
631 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
633 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
635 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
637 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
639 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
662 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 /* Does the target support increment sequence counter */
664 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 /* Does the connection support CONF REQ transmission */
688 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
690 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
699 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
701 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
703 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
705 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
707 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
709 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
711 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
713 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
729 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it is enough that one of them support protection) */
731 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss †this is critical since if line mss restrict us we can’t rely on this size †it depends on vlan num) */
876 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
878 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
887 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
889 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
891 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
893 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
895 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
897 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
899 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
901 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
922 #define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
924 #define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
933 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
935 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
937 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
939 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
941 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
943 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
945 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
947 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
961 #define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
963 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
965 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
967 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
969 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
971 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
998 #define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */
1000 #define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */
1002 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1004 #define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */
1007 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1009 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1011 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1013 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1015 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1017 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1019 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1021 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1024 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1026 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1028 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1030 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1032 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1034 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1036 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1038 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1041 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */
1043 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */
1045 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */
1049 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */
1051 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */
1053 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */
1066 #define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1068 #define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1086 #define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1088 #define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1090 #define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1092 #define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1094 #define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1096 #define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1098 #define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1100 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1103 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1105 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1107 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1109 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
1111 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1113 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1115 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1117 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
1120 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */
1122 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */
1128 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */
1130 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */
1149 #define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
1151 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
1153 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
1155 #define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
1157 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
1159 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
1161 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
1163 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
1166 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
1168 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */
1170 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */
1172 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */
1174 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */
1176 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */
1178 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */
1180 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */
1234 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1236 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1239 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1241 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
1243 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
1245 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
1247 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
1249 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
1251 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
1253 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
1256 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
1258 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */
1260 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */
1262 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */
1264 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */
1266 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */
1268 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */
1270 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */
1273 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */
1275 #define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */
1277 #define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */
1279 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */
1281 #define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */
1283 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */
1285 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */
1287 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */
1290 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */
1292 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */
1294 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */
1296 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
1298 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
1300 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
1302 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */
1304 #define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */
1307 #define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */
1309 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */
1311 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */
1313 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */
1315 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */
1317 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */
1319 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */
1321 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */
1324 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */
1326 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */
1328 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */
1330 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */
1332 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */
1334 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */
1336 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */
1338 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */
1341 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */
1343 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */
1345 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */
1347 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */
1349 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */
1351 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */
1375 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */
1377 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */
1379 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */
1383 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */
1385 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */
1387 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */
1404 #define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
1406 #define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
1415 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
1417 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
1419 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
1421 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
1423 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
1425 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
1427 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
1429 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */