Lines Matching refs:w0
59 } while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay); \
562 pcs_cfg.bits.w0.mask = 0; in npi_mac_pcs_link_intr_enable()
576 pcs_cfg.bits.w0.mask = 1; in npi_mac_pcs_link_intr_disable()
590 xpcs_mask1.bits.w0.csr_rx_link_stat = 1; in npi_xmac_xpcs_link_intr_enable()
604 xpcs_mask1.bits.w0.csr_rx_link_stat = 0; in npi_xmac_xpcs_link_intr_disable()
619 mif_cfg.bits.w0.phy_addr = portn; in npi_mac_mif_link_intr_disable()
620 mif_cfg.bits.w0.poll_en = 0; in npi_mac_mif_link_intr_disable()
824 val0 = data->w0; in npi_mac_altaddr_entry()
840 data->w0 = val0 & 0xFFFF; in npi_mac_altaddr_entry()
855 val0 = data->w0; in npi_mac_altaddr_entry()
871 data->w0 = val0 & 0xFFFF; in npi_mac_altaddr_entry()
3097 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_read()
3098 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ in npi_mac_mif_mdio_read()
3099 frame.bits.w0.phyad = portn; /* Port number */ in npi_mac_mif_mdio_read()
3100 frame.bits.w0.regad = device; /* Device number */ in npi_mac_mif_mdio_read()
3101 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_read()
3102 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_read()
3103 frame.bits.w0.data = xcvr_reg; /* register address */ in npi_mac_mif_mdio_read()
3121 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_read()
3122 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ in npi_mac_mif_mdio_read()
3123 frame.bits.w0.phyad = portn; /* Port Number */ in npi_mac_mif_mdio_read()
3124 frame.bits.w0.regad = device; /* Device Number */ in npi_mac_mif_mdio_read()
3125 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_read()
3126 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_read()
3139 *value = frame.bits.w0.data; in npi_mac_mif_mdio_read()
3158 frame.bits.w0.st = 0x1; /* Clause 22 */ in npi_mac_mif_mii_read()
3159 frame.bits.w0.op = 0x2; in npi_mac_mif_mii_read()
3160 frame.bits.w0.phyad = portn; in npi_mac_mif_mii_read()
3161 frame.bits.w0.regad = xcvr_reg; in npi_mac_mif_mii_read()
3162 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mii_read()
3163 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mii_read()
3172 *value = frame.bits.w0.data; in npi_mac_mif_mii_read()
3175 xcvr_reg, frame.bits.w0.data)); in npi_mac_mif_mii_read()
3188 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_write()
3189 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ in npi_mac_mif_mdio_write()
3190 frame.bits.w0.phyad = portn; /* Port Number */ in npi_mac_mif_mdio_write()
3191 frame.bits.w0.regad = device; /* Device Number */ in npi_mac_mif_mdio_write()
3192 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_write()
3193 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_write()
3194 frame.bits.w0.data = xcvr_reg; /* register address */ in npi_mac_mif_mdio_write()
3212 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ in npi_mac_mif_mdio_write()
3213 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ in npi_mac_mif_mdio_write()
3214 frame.bits.w0.phyad = portn; /* Port number */ in npi_mac_mif_mdio_write()
3215 frame.bits.w0.regad = device; /* Device number */ in npi_mac_mif_mdio_write()
3216 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_write()
3217 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_write()
3218 frame.bits.w0.data = value; in npi_mac_mif_mdio_write()
3245 frame.bits.w0.st = 0x1; /* Clause 22 */ in npi_mac_mif_mii_write()
3246 frame.bits.w0.op = 0x1; in npi_mac_mif_mii_write()
3247 frame.bits.w0.phyad = portn; in npi_mac_mif_mii_write()
3248 frame.bits.w0.regad = xcvr_reg; in npi_mac_mif_mii_write()
3249 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mii_write()
3250 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mii_write()
3251 frame.bits.w0.data = value; in npi_mac_mif_mii_write()
3294 if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) && in npi_mac_pcs_mii_read()
3295 (pcs_stat_mc.bits.w0.word_sync != 0)) { in npi_mac_pcs_mii_read()
3296 pcs_stat.bits.w0.link_stat = 1; in npi_mac_pcs_mii_read()
3297 } else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) { in npi_mac_pcs_mii_read()
3298 pcs_stat.bits.w0.link_stat = 0; in npi_mac_pcs_mii_read()
3306 esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; in npi_mac_pcs_mii_read()
3307 esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; in npi_mac_pcs_mii_read()
3314 anar.bits.cap_pause = pcs_anar.bits.w0.pause; in npi_mac_pcs_mii_read()
3315 anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause; in npi_mac_pcs_mii_read()
3321 anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause; in npi_mac_pcs_mii_read()
3322 anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause; in npi_mac_pcs_mii_read()
3329 aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex | in npi_mac_pcs_mii_read()
3330 pcs_anar.bits.w0.half_duplex; in npi_mac_pcs_mii_read()
3337 gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; in npi_mac_pcs_mii_read()
3338 gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; in npi_mac_pcs_mii_read()
3372 pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause; in npi_mac_pcs_mii_write()
3373 pcs_anar.bits.w0.pause = anar.bits.cap_pause; in npi_mac_pcs_mii_write()
3381 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; in npi_mac_pcs_mii_write()
3382 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; in npi_mac_pcs_mii_write()
3416 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ in npi_mac_mif_link_intr_enable()
3417 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */ in npi_mac_mif_link_intr_enable()
3418 mif_cfg.bits.w0.indirect_md = 0; /* Clause 22 */ in npi_mac_mif_link_intr_enable()
3419 mif_cfg.bits.w0.poll_en = 1; in npi_mac_mif_link_intr_enable()
3439 frame.bits.w0.st = 0; /* Clause 45 */ in npi_mac_mif_mdio_link_intr_enable()
3440 frame.bits.w0.op = 0; /* Select address */ in npi_mac_mif_mdio_link_intr_enable()
3441 frame.bits.w0.phyad = portn; /* Port number */ in npi_mac_mif_mdio_link_intr_enable()
3442 frame.bits.w0.regad = device; /* Device number */ in npi_mac_mif_mdio_link_intr_enable()
3443 frame.bits.w0.ta_msb = 1; in npi_mac_mif_mdio_link_intr_enable()
3444 frame.bits.w0.ta_lsb = 0; in npi_mac_mif_mdio_link_intr_enable()
3445 frame.bits.w0.data = xcvr_reg; /* register address */ in npi_mac_mif_mdio_link_intr_enable()
3456 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ in npi_mac_mif_mdio_link_intr_enable()
3457 mif_cfg.bits.w0.reg_addr = device; /* Register address */ in npi_mac_mif_mdio_link_intr_enable()
3458 mif_cfg.bits.w0.indirect_md = 1; /* Clause 45 */ in npi_mac_mif_mdio_link_intr_enable()
3459 mif_cfg.bits.w0.poll_en = 1; in npi_mac_mif_mdio_link_intr_enable()
3475 mif_cfg.bits.w0.indirect_md = on_off; in npi_mac_mif_set_indirect_mode()
3485 mif_cfg.bits.w0.atca_ge = on_off; in npi_mac_mif_set_atca_mode()