Lines Matching refs:dev
42 oce_setup_intr(struct oce_dev *dev) in oce_setup_intr() argument
53 ret = ddi_intr_get_supported_types(dev->dip, &intr_types); in oce_setup_intr()
55 oce_log(dev, CE_WARN, MOD_CONFIG, "%s", in oce_setup_intr()
62 dev->intr_type = DDI_INTR_TYPE_MSIX; in oce_setup_intr()
64 nreqd = dev->rx_rings + 1; in oce_setup_intr()
67 dev->intr_type = DDI_INTR_TYPE_FIXED; in oce_setup_intr()
72 ret = ddi_intr_get_nintrs(dev->dip, dev->intr_type, &nsupported); in oce_setup_intr()
74 oce_log(dev, CE_WARN, MOD_CONFIG, in oce_setup_intr()
80 ret = ddi_intr_get_navail(dev->dip, dev->intr_type, &navail); in oce_setup_intr()
82 oce_log(dev, CE_WARN, MOD_CONFIG, in oce_setup_intr()
98 dev->hsize = nreqd * sizeof (ddi_intr_handle_t); in oce_setup_intr()
99 dev->htable = kmem_zalloc(dev->hsize, KM_NOSLEEP); in oce_setup_intr()
101 if (dev->htable == NULL) in oce_setup_intr()
106 ret = ddi_intr_alloc(dev->dip, dev->htable, dev->intr_type, in oce_setup_intr()
113 dev->num_vectors = nallocd; in oce_setup_intr()
123 ret = ddi_intr_get_pri(dev->htable[0], &dev->intr_pri); in oce_setup_intr()
129 (void) ddi_intr_get_cap(dev->htable[0], &dev->intr_cap); in oce_setup_intr()
132 dev->rx_rings = nallocd - 1; in oce_setup_intr()
134 dev->rx_rings = 1; in oce_setup_intr()
140 (void) oce_teardown_intr(dev); in oce_setup_intr()
141 if ((dev->intr_type == DDI_INTR_TYPE_MSIX) && in oce_setup_intr()
144 oce_log(dev, CE_NOTE, MOD_CONFIG, "%s", in oce_setup_intr()
159 oce_teardown_intr(struct oce_dev *dev) in oce_teardown_intr() argument
164 for (i = 0; i < dev->num_vectors; i++) { in oce_teardown_intr()
165 (void) ddi_intr_free(dev->htable[i]); in oce_teardown_intr()
169 kmem_free(dev->htable, dev->hsize); in oce_teardown_intr()
170 dev->htable = NULL; in oce_teardown_intr()
183 oce_setup_handlers(struct oce_dev *dev) in oce_setup_handlers() argument
187 for (i = 0; i < dev->num_vectors; i++) { in oce_setup_handlers()
188 ret = ddi_intr_add_handler(dev->htable[i], oce_isr, in oce_setup_handlers()
189 (caddr_t)dev->eq[i], NULL); in oce_setup_handlers()
191 oce_log(dev, CE_WARN, MOD_CONFIG, "%s", in oce_setup_handlers()
194 (void) ddi_intr_remove_handler(dev->htable[i]); in oce_setup_handlers()
210 oce_remove_handler(struct oce_dev *dev) in oce_remove_handler() argument
213 for (nvec = 0; nvec < dev->num_vectors; nvec++) { in oce_remove_handler()
214 (void) ddi_intr_remove_handler(dev->htable[nvec]); in oce_remove_handler()
219 oce_chip_ei(struct oce_dev *dev) in oce_chip_ei() argument
223 reg = OCE_CFG_READ32(dev, PCICFG_INTR_CTRL); in oce_chip_ei()
225 OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg); in oce_chip_ei()
236 oce_ei(struct oce_dev *dev) in oce_ei() argument
241 if (dev->intr_cap & DDI_INTR_FLAG_BLOCK) { in oce_ei()
242 (void) ddi_intr_block_enable(dev->htable, dev->num_vectors); in oce_ei()
245 for (i = 0; i < dev->num_vectors; i++) { in oce_ei()
246 ret = ddi_intr_enable(dev->htable[i]); in oce_ei()
249 (void) ddi_intr_disable(dev->htable[i]); in oce_ei()
254 oce_chip_ei(dev); in oce_ei()
258 oce_chip_di(struct oce_dev *dev) in oce_chip_di() argument
262 reg = OCE_CFG_READ32(dev, PCICFG_INTR_CTRL); in oce_chip_di()
264 OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg); in oce_chip_di()
275 oce_di(struct oce_dev *dev) in oce_di() argument
280 oce_chip_di(dev); in oce_di()
281 if (dev->intr_cap & DDI_INTR_FLAG_BLOCK) { in oce_di()
282 (void) ddi_intr_block_disable(dev->htable, dev->num_vectors); in oce_di()
284 for (i = 0; i < dev->num_vectors; i++) { in oce_di()
285 ret = ddi_intr_disable(dev->htable[i]); in oce_di()
287 oce_log(dev, CE_WARN, MOD_CONFIG, in oce_di()
311 struct oce_dev *dev; in oce_isr() local
317 dev = eq->parent; in oce_isr()
327 oce_log(dev, CE_WARN, MOD_ISR, in oce_isr()
334 cq = dev->cq[cq_id]; in oce_isr()
347 oce_arm_eq(dev, eq->eq_id, num_eqe, B_TRUE, B_TRUE); in oce_isr()