Lines Matching refs:x

78 #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)  argument
79 #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV) argument
83 #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT) argument
84 #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT) argument
89 #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL) argument
93 #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE) argument
97 #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE) argument
101 #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY) argument
105 #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO) argument
112 #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR) argument
113 #define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR) argument
117 #define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR) argument
118 #define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR) argument
130 #define V_INTERFACE(x) ((x) << S_INTERFACE) argument
131 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE) argument
134 #define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE) argument
138 #define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE) argument
142 #define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE) argument
147 #define V_MAC_SPEED(x) ((x) << S_MAC_SPEED) argument
148 #define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED) argument
151 #define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE) argument
155 #define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX) argument
159 #define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC) argument
163 #define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE) argument
167 #define V_MAC_RESET(x) ((x) << S_MAC_RESET) argument
171 #define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE) argument
175 #define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE) argument
179 #define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE) argument
183 #define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE) argument
187 #define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE) argument
191 #define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE) argument
195 #define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE) argument
199 #define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE) argument
206 #define V_MAC_IFS2(x) ((x) << S_MAC_IFS2) argument
207 #define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2) argument
211 #define V_MAC_IFS1(x) ((x) << S_MAC_IFS1) argument
212 #define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1) argument
228 #define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD) argument
229 #define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD) argument
233 #define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD) argument
234 #define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD) argument