Lines Matching refs:x1
4 #define ATC_REG_ATC_1_WAY 0x110004UL //ACCESS:RW DataWidth:0x1 Description: If set the ATC will use only one way per set
7 #define ATC_REG_ATC_WAIT_IF_MISS 0x110010UL //ACCESS:RW DataWidth:0x1 Description: WaitIfMiss configuration bit
8 #define ATC_REG_ATC_WAIT_IF_PENDING 0x110014UL //ACCESS:RW DataWidth:0x1 Description: WaitTransPending cofiguration bit
21 #define ATC_REG_ATC_DISABLE_BYPASS 0x110048UL //ACCESS:RW DataWidth:0x1 Description: disables the bypass on the GPA table
22 #define ATC_REG_ATC_ISSUE_4_CYCLES 0x11004cUL //ACCESS:RW DataWidth:0x1 Description: Issue event once in four cycles (instead of 2)
25 #define ATC_REG_ATC_PIGGYBACKED_TREQ_EN 0x110058UL //ACCESS:RW DataWidth:0x1 Description: Piggybacked treq issue enabled
26 #define ATC_REG_ATC_WAIT_RESP 0x11005cUL //ACCESS:RW DataWidth:0x1 Description: Allows the ATC to return Wait response
35 #define ATC_REG_ATC_CHECK_TAGS 0x110080UL //ACCESS:RW DataWidth:0x1 Description: CheckTags configuration bit - when set the available NPH credits is checked before issuing TREQ
38 #define ATC_REG_ATC_DIS_MLKP 0x11008cUL //ACCESS:RW DataWidth:0x1 Description: Disables the main lookup interface
39 #define ATC_REG_ATC_DIS_PLKP 0x110090UL //ACCESS:RW DataWidth:0x1 Description: Disables the pre lookup interface
40 #define ATC_REG_ATC_DIS_IREQ 0x110094UL //ACCESS:RW DataWidth:0x1 Description: Disables the invalidation request interface
41 #define ATC_REG_ATC_DIS_TCPL 0x110098UL //ACCESS:RW DataWidth:0x1 Description: Disables the translation completion interface
42 #define ATC_REG_ATC_DIS_SPAD 0x11009cUL //ACCESS:RW DataWidth:0x1 Description: Disables the spa done interface
43 #define ATC_REG_ATC_DIS_RCPL 0x1100a0UL //ACCESS:RW DataWidth:0x1 Description: Disables the Read Completion interface
44 #define ATC_REG_ATC_DIS_LKPRES 0x1100a4UL //ACCESS:RW DataWidth:0x1 Description: Disables the lookup response interface
45 #define ATC_REG_ATC_DIS_TREQ 0x1100a8UL //ACCESS:RW DataWidth:0x1 Description: Disables the translation request interface
46 #define ATC_REG_ATC_DIS_ICPL 0x1100acUL //ACCESS:RW DataWidth:0x1 Description: Disables the invalidation completion interface
48 #define ATC_REG_ATC_SCRUB_DIS 0x1100b4UL //ACCESS:RW DataWidth:0x1 Description: Disable bit for the scrubbing event of the GPA table
49 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8UL //ACCESS:RW DataWidth:0x1 Description: Initiate the ATC array - reset all the valid bits
50 #define ATC_REG_ATC_INIT_DONE 0x1100bcUL //ACCESS:R DataWidth:0x1 Description: ATC initalization done
58 #define ATC_REG_ATC_STAT_ACTIVE 0x1100dcUL //ACCESS:RW DataWidth:0x1 Description: When this signal is set the statistics count is on
89 #define ATC_REG_ATC_GPA_HASH_EN 0x110158UL //ACCESS:RW DataWidth:0x1 Description: enable the use of a hash function for the GPA table; instead of the lsb bits of the address
90 #define ATC_REG_ATC_GPA_HASH_CRC 0x11015cUL //ACCESS:RW DataWidth:0x1 Description: relevant only if hash_en is set. selects the CRC as hash function for the GPA table; If reset use xor of the FID LS bits with the relevant bits out of the GPA as hash function
96 #define ATC_REG_ATC_TCPL_ERR_LOG_VALID 0x110174UL //ACCESS:R DataWidth:0x1 Description: Indicates valid data at the tcpl error log registers
97 #define ATC_REG_ATC_ARRAY_ACCESS_ENABLE 0x110178UL //ACCESS:RW DataWidth:0x1 Description: Allows GRC access to the GPA and SPA table
98 #define ATC_REG_ATC_DURING_FLI 0x11017cUL //ACCESS:R DataWidth:0x1 Description: Indication that the ATC currently handles FLI
99 #define ATC_REG_ATC_DURING_INV 0x110180UL //ACCESS:R DataWidth:0x1 Description: Indication that the ATC currently handles Any type of invalidation
110 #define ATC_REG_ATC_ALLOW_LOW_REP_HIGH 0x1101acUL //ACCESS:RW DataWidth:0x1 Description: When set low priority lookup can replace high priority entry; iff the set is full with high prio entries
111 #define ATC_REG_ATC_DIS_IREQ_EVENT 0x1101b0UL //ACCESS:RW DataWidth:0x1 Description: When set Ireq event won't be selected by the ATC arbiter
112 #define ATC_REG_ATC_ECO_RESERVED 0x1101b4UL //ACCESS:RW DataWidth:0x1 Description: For future ECOs implementation
127 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
129 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
131 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
133 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
135 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
137 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
140 #define ATC_ATC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
142 #define ATC_ATC_INT_STS_CLR_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
144 #define ATC_ATC_INT_STS_CLR_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
146 #define ATC_ATC_INT_STS_CLR_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
148 #define ATC_ATC_INT_STS_CLR_REG_ATC_TCPL_ERROR (0x1<<4)
150 #define ATC_ATC_INT_STS_CLR_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
153 #define ATC_ATC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
155 #define ATC_ATC_INT_STS_WR_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
157 #define ATC_ATC_INT_STS_WR_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
159 #define ATC_ATC_INT_STS_WR_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
161 #define ATC_ATC_INT_STS_WR_REG_ATC_TCPL_ERROR (0x1<<4)
163 #define ATC_ATC_INT_STS_WR_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
166 #define ATC_ATC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
168 #define ATC_ATC_INT_MASK_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
170 #define ATC_ATC_INT_MASK_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
172 #define ATC_ATC_INT_MASK_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
174 #define ATC_ATC_INT_MASK_REG_ATC_TCPL_ERROR (0x1<<4)
176 #define ATC_ATC_INT_MASK_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
179 #define ATC_ATC_PRTY_STS_REG_PARITY (0x1<<0)
181 #define ATC_ATC_PRTY_STS_REG_GPA_TABLE (0x1<<1)
183 #define ATC_ATC_PRTY_STS_REG_IREQ_FIFO (0x1<<2)
185 #define ATC_ATC_PRTY_STS_REG_SPA_TABLE (0x1<<3)
187 #define ATC_ATC_PRTY_STS_REG_TCPL_FIFO (0x1<<4)
190 #define ATC_ATC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
192 #define ATC_ATC_PRTY_STS_CLR_REG_GPA_TABLE (0x1<<1)
194 #define ATC_ATC_PRTY_STS_CLR_REG_IREQ_FIFO (0x1<<2)
196 #define ATC_ATC_PRTY_STS_CLR_REG_SPA_TABLE (0x1<<3)
198 #define ATC_ATC_PRTY_STS_CLR_REG_TCPL_FIFO (0x1<<4)
201 #define ATC_ATC_PRTY_STS_WR_REG_PARITY (0x1<<0)
203 #define ATC_ATC_PRTY_STS_WR_REG_GPA_TABLE (0x1<<1)
205 #define ATC_ATC_PRTY_STS_WR_REG_IREQ_FIFO (0x1<<2)
207 #define ATC_ATC_PRTY_STS_WR_REG_SPA_TABLE (0x1<<3)
209 #define ATC_ATC_PRTY_STS_WR_REG_TCPL_FIFO (0x1<<4)
212 #define ATC_ATC_PRTY_MASK_REG_PARITY (0x1<<0)
214 #define ATC_ATC_PRTY_MASK_REG_GPA_TABLE (0x1<<1)
216 #define ATC_ATC_PRTY_MASK_REG_IREQ_FIFO (0x1<<2)
218 #define ATC_ATC_PRTY_MASK_REG_SPA_TABLE (0x1<<3)
220 #define ATC_ATC_PRTY_MASK_REG_TCPL_FIFO (0x1<<4)
252 #define BRB1_REG_READ_FREE_BLOCK_ERROR_0 0x60004UL //ACCESS:RC DataWidth:0x1 Description: Read client 0: attempt to read from free block.
253 #define BRB1_REG_READ_FREE_BLOCK_ERROR_10 0x60008UL //ACCESS:RC DataWidth:0x1 Description: Read client 10: attempt to read from free block.
254 #define BRB1_REG_READ_FREE_BLOCK_ERROR_11 0x6000cUL //ACCESS:RC DataWidth:0x1 Description: Read client 11: attempt to read from free block.
255 #define BRB1_REG_READ_FREE_BLOCK_ERROR_12 0x60010UL //ACCESS:RC DataWidth:0x1 Description: Read client 12: attempt to read from free block.
256 #define BRB1_REG_READ_FREE_BLOCK_ERROR_13 0x60014UL //ACCESS:RC DataWidth:0x1 Description: Read client 13: attempt to read from free block.
257 #define BRB1_REG_READ_FREE_BLOCK_ERROR_14 0x60018UL //ACCESS:RC DataWidth:0x1 Description: Read client 14: attempt to read from free block.
258 #define BRB1_REG_READ_FREE_BLOCK_ERROR_2 0x6001cUL //ACCESS:RC DataWidth:0x1 Description: Read client 2: attempt to read from free block.
259 #define BRB1_REG_READ_FREE_BLOCK_ERROR_3 0x60020UL //ACCESS:RC DataWidth:0x1 Description: Read client 3: attempt to read from free block.
260 #define BRB1_REG_READ_FREE_BLOCK_ERROR_4 0x60024UL //ACCESS:RC DataWidth:0x1 Description: Read client 4: attempt to read from free block.
261 #define BRB1_REG_READ_LENGTH_ERROR_0 0x60028UL //ACCESS:RC DataWidth:0x1 Description: Read client 0: attempt to read more data than in packet.
262 #define BRB1_REG_READ_LENGTH_ERROR_10 0x6002cUL //ACCESS:RC DataWidth:0x1 Description: Read client 10: attempt to read more data than in packet.
263 #define BRB1_REG_READ_LENGTH_ERROR_11 0x60030UL //ACCESS:RC DataWidth:0x1 Description: Read client 11: attempt to read more data than in packet.
264 #define BRB1_REG_READ_LENGTH_ERROR_12 0x60034UL //ACCESS:RC DataWidth:0x1 Description: Read client 12: attempt to read more data than in packet.
265 #define BRB1_REG_READ_LENGTH_ERROR_13 0x60038UL //ACCESS:RC DataWidth:0x1 Description: Read client 13: attempt to read more data than in packet.
266 #define BRB1_REG_READ_LENGTH_ERROR_14 0x6003cUL //ACCESS:RC DataWidth:0x1 Description: Read client 14: attempt to read more data than in packet.
267 #define BRB1_REG_READ_LENGTH_ERROR_2 0x60040UL //ACCESS:RC DataWidth:0x1 Description: Read client 2: attempt to read more data than in packet.
268 #define BRB1_REG_READ_LENGTH_ERROR_3 0x60044UL //ACCESS:RC DataWidth:0x1 Description: Read client 3: attempt to read more data than in packet.
269 #define BRB1_REG_READ_LENGTH_ERROR_4 0x60048UL //ACCESS:RC DataWidth:0x1 Description: Read client 4: attempt to read more data than in packet.
306 #define BRB1_REG_SOFT_RESET 0x600dcUL //ACCESS:RW DataWidth:0x1 Description: Reset the design by software.
323 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
325 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
327 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
329 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
331 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
333 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
335 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
337 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
339 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
341 #define BRB1_BRB1_INT_STS_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
343 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_0 (0x1<<10)
345 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_10 (0x1<<11)
347 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_11 (0x1<<12)
349 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_12 (0x1<<13)
351 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_13 (0x1<<14)
353 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_14 (0x1<<15)
355 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_2 (0x1<<16)
357 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_3 (0x1<<17)
359 #define BRB1_BRB1_INT_STS_REG_RD_LEN_ERR_4 (0x1<<18)
362 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
364 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
366 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
368 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
370 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
372 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
374 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
376 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
378 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
380 #define BRB1_BRB1_INT_STS_CLR_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
382 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_0 (0x1<<10)
384 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_10 (0x1<<11)
386 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_11 (0x1<<12)
388 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_12 (0x1<<13)
390 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_13 (0x1<<14)
392 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_14 (0x1<<15)
394 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_2 (0x1<<16)
396 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_3 (0x1<<17)
398 #define BRB1_BRB1_INT_STS_CLR_REG_RD_LEN_ERR_4 (0x1<<18)
401 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
403 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
405 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
407 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
409 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
411 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
413 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
415 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
417 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
419 #define BRB1_BRB1_INT_STS_WR_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
421 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_0 (0x1<<10)
423 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_10 (0x1<<11)
425 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_11 (0x1<<12)
427 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_12 (0x1<<13)
429 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_13 (0x1<<14)
431 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_14 (0x1<<15)
433 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_2 (0x1<<16)
435 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_3 (0x1<<17)
437 #define BRB1_BRB1_INT_STS_WR_REG_RD_LEN_ERR_4 (0x1<<18)
440 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
442 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_0 (0x1<<1)
444 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_10 (0x1<<2)
446 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_11 (0x1<<3)
448 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_12 (0x1<<4)
450 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_13 (0x1<<5)
452 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_14 (0x1<<6)
454 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_2 (0x1<<7)
456 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_3 (0x1<<8)
458 #define BRB1_BRB1_INT_MASK_REG_RD_FREE_BLK_ERR_4 (0x1<<9)
460 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_0 (0x1<<10)
462 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_10 (0x1<<11)
464 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_11 (0x1<<12)
466 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_12 (0x1<<13)
468 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_13 (0x1<<14)
470 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_14 (0x1<<15)
472 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_2 (0x1<<16)
474 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_3 (0x1<<17)
476 #define BRB1_BRB1_INT_MASK_REG_RD_LEN_ERR_4 (0x1<<18)
479 #define BRB1_BRB1_PRTY_STS_REG_PARITY (0x1<<0)
481 #define BRB1_BRB1_PRTY_STS_REG_BRAM_BL (0x1<<1)
483 #define BRB1_BRB1_PRTY_STS_REG_BRAM_BR (0x1<<2)
485 #define BRB1_BRB1_PRTY_STS_REG_LRAM (0x1<<3)
488 #define BRB1_BRB1_PRTY_STS_CLR_REG_PARITY (0x1<<0)
490 #define BRB1_BRB1_PRTY_STS_CLR_REG_BRAM_BL (0x1<<1)
492 #define BRB1_BRB1_PRTY_STS_CLR_REG_BRAM_BR (0x1<<2)
494 #define BRB1_BRB1_PRTY_STS_CLR_REG_LRAM (0x1<<3)
497 #define BRB1_BRB1_PRTY_STS_WR_REG_PARITY (0x1<<0)
499 #define BRB1_BRB1_PRTY_STS_WR_REG_BRAM_BL (0x1<<1)
501 #define BRB1_BRB1_PRTY_STS_WR_REG_BRAM_BR (0x1<<2)
503 #define BRB1_BRB1_PRTY_STS_WR_REG_LRAM (0x1<<3)
506 #define BRB1_BRB1_PRTY_MASK_REG_PARITY (0x1<<0)
508 #define BRB1_BRB1_PRTY_MASK_REG_BRAM_BL (0x1<<1)
510 #define BRB1_BRB1_PRTY_MASK_REG_BRAM_BR (0x1<<2)
512 #define BRB1_BRB1_PRTY_MASK_REG_LRAM (0x1<<3)
580 #define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268UL //ACCESS:RW DataWidth:0x1 Description: Indicates if to use per-class guaranty mode (new mode) or per-MAC guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC mode). 1=per-class guaranty mode (new mode).
581 #define BRB1_REG_EMPTY_BACKWARD_MODE 0x6027cUL //ACCESS:RW DataWidth:0x1 Description: When reset then brb_empty signal will be set according to new E3_B0 formula. When set it will be used an old formula
605 #define CCM_REG_INIT 0xd0000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0. For debug purposes only.
606 #define CCM_REG_CCM_STORM0_IFEN 0xd0004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
607 #define CCM_REG_CCM_STORM1_IFEN 0xd0008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
608 #define CCM_REG_CCM_CQM_IFEN 0xd000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
609 #define CCM_REG_STORM_CCM_IFEN 0xd0010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
610 #define CCM_REG_CQM_CCM_IFEN 0xd0014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
611 #define CCM_REG_CSDM_IFEN 0xd0018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
612 #define CCM_REG_TSEM_IFEN 0xd001cUL //ACCESS:RW DataWidth:0x1 Description: Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
613 #define CCM_REG_XSEM_IFEN 0xd0020UL //ACCESS:RW DataWidth:0x1 Description: Input xsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
614 #define CCM_REG_USEM_IFEN 0xd0024UL //ACCESS:RW DataWidth:0x1 Description: Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
615 #define CCM_REG_PBF_IFEN 0xd0028UL //ACCESS:RW DataWidth:0x1 Description: Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
616 #define CCM_REG_CDU_AG_WR_IFEN 0xd002cUL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
617 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
618 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
619 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
620 #define CCM_REG_CCM_CFC_IFEN 0xd003cUL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
653 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID. Otherwise 0 is inserted.
678 #define CCM_REG_GR_ARB_TYPE 0xd015cUL //ACCESS:RW DataWidth:0x1 Description: Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; ~ccm_registers_gr_ld0_pr.gr_ld0_pr and ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and outputs to STORM: aggregation; load FIC0; load FIC1 and store.
682 #define CCM_REG_STORM_LENGTH_MIS 0xd016cUL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the STORM interface is detected.
683 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the SDM interface is detected.
684 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the tsem interface is detected.
685 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the xsem interface is detected.
686 #define CCM_REG_USEM_LENGTH_MIS 0xd017cUL //ACCESS:RC DataWidth:0x1 Description: Set when message length mismatch (relative to last indication) at the usem interface is detected.
687 #define CCM_REG_PBF_LENGTH_MIS 0xd0180UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the pbf interface is detected.
690 #define CCM_REG_UNLOCK_MISS 0xd018cUL //ACCESS:RC DataWidth:0x1 Description: Error; indicating the LCID to be unlocked from XX protection doesn't exist in LCID CAM.
692 #define CCM_REG_CP_BUF_EMPTY 0xd0194UL //ACCESS:R DataWidth:0x1 Description: Indication of CP buffer is empty.
710 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
712 #define CCM_CCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
714 #define CCM_CCM_INT_STS_REG_STORM_ERR (0x1<<2)
716 #define CCM_CCM_INT_STS_REG_CSDM_ERR (0x1<<3)
718 #define CCM_CCM_INT_STS_REG_TSEM_ERR (0x1<<4)
720 #define CCM_CCM_INT_STS_REG_XSEM_ERR (0x1<<5)
722 #define CCM_CCM_INT_STS_REG_USEM_ERR (0x1<<6)
724 #define CCM_CCM_INT_STS_REG_PBF_ERR (0x1<<7)
726 #define CCM_CCM_INT_STS_REG_CP0_ERR (0x1<<8)
728 #define CCM_CCM_INT_STS_REG_CP1_ERR (0x1<<9)
730 #define CCM_CCM_INT_STS_REG_UM_ERR (0x1<<10)
733 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
735 #define CCM_CCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
737 #define CCM_CCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
739 #define CCM_CCM_INT_STS_CLR_REG_CSDM_ERR (0x1<<3)
741 #define CCM_CCM_INT_STS_CLR_REG_TSEM_ERR (0x1<<4)
743 #define CCM_CCM_INT_STS_CLR_REG_XSEM_ERR (0x1<<5)
745 #define CCM_CCM_INT_STS_CLR_REG_USEM_ERR (0x1<<6)
747 #define CCM_CCM_INT_STS_CLR_REG_PBF_ERR (0x1<<7)
749 #define CCM_CCM_INT_STS_CLR_REG_CP0_ERR (0x1<<8)
751 #define CCM_CCM_INT_STS_CLR_REG_CP1_ERR (0x1<<9)
753 #define CCM_CCM_INT_STS_CLR_REG_UM_ERR (0x1<<10)
756 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
758 #define CCM_CCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
760 #define CCM_CCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
762 #define CCM_CCM_INT_STS_WR_REG_CSDM_ERR (0x1<<3)
764 #define CCM_CCM_INT_STS_WR_REG_TSEM_ERR (0x1<<4)
766 #define CCM_CCM_INT_STS_WR_REG_XSEM_ERR (0x1<<5)
768 #define CCM_CCM_INT_STS_WR_REG_USEM_ERR (0x1<<6)
770 #define CCM_CCM_INT_STS_WR_REG_PBF_ERR (0x1<<7)
772 #define CCM_CCM_INT_STS_WR_REG_CP0_ERR (0x1<<8)
774 #define CCM_CCM_INT_STS_WR_REG_CP1_ERR (0x1<<9)
776 #define CCM_CCM_INT_STS_WR_REG_UM_ERR (0x1<<10)
779 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
781 #define CCM_CCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
783 #define CCM_CCM_INT_MASK_REG_STORM_ERR (0x1<<2)
785 #define CCM_CCM_INT_MASK_REG_CSDM_ERR (0x1<<3)
787 #define CCM_CCM_INT_MASK_REG_TSEM_ERR (0x1<<4)
789 #define CCM_CCM_INT_MASK_REG_XSEM_ERR (0x1<<5)
791 #define CCM_CCM_INT_MASK_REG_USEM_ERR (0x1<<6)
793 #define CCM_CCM_INT_MASK_REG_PBF_ERR (0x1<<7)
795 #define CCM_CCM_INT_MASK_REG_CP0_ERR (0x1<<8)
797 #define CCM_CCM_INT_MASK_REG_CP1_ERR (0x1<<9)
799 #define CCM_CCM_INT_MASK_REG_UM_ERR (0x1<<10)
802 #define CCM_CCM_PRTY_STS_REG_PARITY (0x1<<0)
804 #define CCM_CCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
806 #define CCM_CCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
808 #define CCM_CCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
810 #define CCM_CCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
812 #define CCM_CCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
814 #define CCM_CCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
816 #define CCM_CCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
818 #define CCM_CCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
820 #define CCM_CCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
822 #define CCM_CCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
824 #define CCM_CCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
826 #define CCM_CCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
828 #define CCM_CCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
830 #define CCM_CCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
832 #define CCM_CCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
834 #define CCM_CCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
836 #define CCM_CCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
838 #define CCM_CCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
840 #define CCM_CCM_PRTY_STS_REG_CSDM_PRTY (0x1<<19)
842 #define CCM_CCM_PRTY_STS_REG_TSEM_PRTY (0x1<<20)
844 #define CCM_CCM_PRTY_STS_REG_XSEM_PRTY (0x1<<21)
846 #define CCM_CCM_PRTY_STS_REG_USEM_PRTY (0x1<<22)
848 #define CCM_CCM_PRTY_STS_REG_PBF_PRTY (0x1<<23)
850 #define CCM_CCM_PRTY_STS_REG_CP0_PRTY (0x1<<24)
852 #define CCM_CCM_PRTY_STS_REG_CP1_PRTY (0x1<<25)
854 #define CCM_CCM_PRTY_STS_REG_UM_PRTY (0x1<<26)
857 #define CCM_CCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
859 #define CCM_CCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
861 #define CCM_CCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
863 #define CCM_CCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
865 #define CCM_CCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
867 #define CCM_CCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
869 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
871 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
873 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
875 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
877 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
879 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
881 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
883 #define CCM_CCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
885 #define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
887 #define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
889 #define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
891 #define CCM_CCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
893 #define CCM_CCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
895 #define CCM_CCM_PRTY_STS_CLR_REG_CSDM_PRTY (0x1<<19)
897 #define CCM_CCM_PRTY_STS_CLR_REG_TSEM_PRTY (0x1<<20)
899 #define CCM_CCM_PRTY_STS_CLR_REG_XSEM_PRTY (0x1<<21)
901 #define CCM_CCM_PRTY_STS_CLR_REG_USEM_PRTY (0x1<<22)
903 #define CCM_CCM_PRTY_STS_CLR_REG_PBF_PRTY (0x1<<23)
905 #define CCM_CCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<24)
907 #define CCM_CCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<25)
909 #define CCM_CCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<26)
912 #define CCM_CCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
914 #define CCM_CCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
916 #define CCM_CCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
918 #define CCM_CCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
920 #define CCM_CCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
922 #define CCM_CCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
924 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
926 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
928 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
930 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
932 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
934 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
936 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
938 #define CCM_CCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
940 #define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
942 #define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
944 #define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
946 #define CCM_CCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
948 #define CCM_CCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
950 #define CCM_CCM_PRTY_STS_WR_REG_CSDM_PRTY (0x1<<19)
952 #define CCM_CCM_PRTY_STS_WR_REG_TSEM_PRTY (0x1<<20)
954 #define CCM_CCM_PRTY_STS_WR_REG_XSEM_PRTY (0x1<<21)
956 #define CCM_CCM_PRTY_STS_WR_REG_USEM_PRTY (0x1<<22)
958 #define CCM_CCM_PRTY_STS_WR_REG_PBF_PRTY (0x1<<23)
960 #define CCM_CCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<24)
962 #define CCM_CCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<25)
964 #define CCM_CCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<26)
967 #define CCM_CCM_PRTY_MASK_REG_PARITY (0x1<<0)
969 #define CCM_CCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
971 #define CCM_CCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
973 #define CCM_CCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
975 #define CCM_CCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
977 #define CCM_CCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
979 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
981 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
983 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
985 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
987 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
989 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
991 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
993 #define CCM_CCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
995 #define CCM_CCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
997 #define CCM_CCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
999 #define CCM_CCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
1001 #define CCM_CCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
1003 #define CCM_CCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
1005 #define CCM_CCM_PRTY_MASK_REG_CSDM_PRTY (0x1<<19)
1007 #define CCM_CCM_PRTY_MASK_REG_TSEM_PRTY (0x1<<20)
1009 #define CCM_CCM_PRTY_MASK_REG_XSEM_PRTY (0x1<<21)
1011 #define CCM_CCM_PRTY_MASK_REG_USEM_PRTY (0x1<<22)
1013 #define CCM_CCM_PRTY_MASK_REG_PBF_PRTY (0x1<<23)
1015 #define CCM_CCM_PRTY_MASK_REG_CP0_PRTY (0x1<<24)
1017 #define CCM_CCM_PRTY_MASK_REG_CP1_PRTY (0x1<<25)
1019 #define CCM_CCM_PRTY_MASK_REG_UM_PRTY (0x1<<26)
1027 #define CCM_REG_UM_FIC1_FORCE 0xd0818UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
1147 #define CDU_CDU_CONTROL0_REG_PXP_ACTIVE (0x1<<0)
1149 #define CDU_CDU_CONTROL0_REG_L1TT_SP (0x1<<1)
1151 #define CDU_CDU_CONTROL0_REG_MATT_SP (0x1<<2)
1153 #define CDU_CDU_CONTROL0_REG_DISABLE_DIVIDER (0x1<<3)
1155 #define CDU_CDU_CONTROL0_REG_MASK_ECC (0x1<<4)
1157 #define CDU_CDU_CONTROL0_REG_LDRESP_ADDR_DIS (0x1<<5)
1159 #define CDU_CDU_CONTROL0_REG_DISABLE_INPUTS (0x1<<6)
1161 #define CDU_CDU_CONTROL0_REG_DISABLE_OUTPUTS (0x1<<7)
1163 #define CDU_CDU_CONTROL0_REG_MASK_PCIE (0x1<<8)
1172 #define CDU_CDU_CONTROL1_REG_LDDPRELAX (0x1<<15)
1176 #define CDU_CDU_CONTROL1_REG_WBDPRELAX (0x1<<21)
1181 #define CDU_CDU_DEBUG_REG_MASK_LD_EOP_ERR (0x1<<0)
1183 #define CDU_CDU_DEBUG_REG_DISABLE_MERGE (0x1<<1)
1187 #define CDU_CDU_DEBUG_REG_PXP_INIT_LDCREDIT_SET (0x1<<5)
1191 #define CDU_CDU_DEBUG_REG_PXP_INIT_WBCREDIT_SET (0x1<<9)
1206 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
1208 #define CDU_CDU_INT_STS_REG_EOP_ERROR (0x1<<1)
1210 #define CDU_CDU_INT_STS_REG_LD_L1_NUM_ERROR (0x1<<2)
1212 #define CDU_CDU_INT_STS_REG_WB_L1_NUM_ERROR (0x1<<3)
1214 #define CDU_CDU_INT_STS_REG_BVALID_ERROR (0x1<<4)
1216 #define CDU_CDU_INT_STS_REG_LDOFFSET_ERROR (0x1<<5)
1218 #define CDU_CDU_INT_STS_REG_WBOFFSET_ERROR (0x1<<6)
1221 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
1223 #define CDU_CDU_INT_STS_CLR_REG_EOP_ERROR (0x1<<1)
1225 #define CDU_CDU_INT_STS_CLR_REG_LD_L1_NUM_ERROR (0x1<<2)
1227 #define CDU_CDU_INT_STS_CLR_REG_WB_L1_NUM_ERROR (0x1<<3)
1229 #define CDU_CDU_INT_STS_CLR_REG_BVALID_ERROR (0x1<<4)
1231 #define CDU_CDU_INT_STS_CLR_REG_LDOFFSET_ERROR (0x1<<5)
1233 #define CDU_CDU_INT_STS_CLR_REG_WBOFFSET_ERROR (0x1<<6)
1236 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
1238 #define CDU_CDU_INT_STS_WR_REG_EOP_ERROR (0x1<<1)
1240 #define CDU_CDU_INT_STS_WR_REG_LD_L1_NUM_ERROR (0x1<<2)
1242 #define CDU_CDU_INT_STS_WR_REG_WB_L1_NUM_ERROR (0x1<<3)
1244 #define CDU_CDU_INT_STS_WR_REG_BVALID_ERROR (0x1<<4)
1246 #define CDU_CDU_INT_STS_WR_REG_LDOFFSET_ERROR (0x1<<5)
1248 #define CDU_CDU_INT_STS_WR_REG_WBOFFSET_ERROR (0x1<<6)
1251 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
1253 #define CDU_CDU_INT_MASK_REG_EOP_ERROR (0x1<<1)
1255 #define CDU_CDU_INT_MASK_REG_LD_L1_NUM_ERROR (0x1<<2)
1257 #define CDU_CDU_INT_MASK_REG_WB_L1_NUM_ERROR (0x1<<3)
1259 #define CDU_CDU_INT_MASK_REG_BVALID_ERROR (0x1<<4)
1261 #define CDU_CDU_INT_MASK_REG_LDOFFSET_ERROR (0x1<<5)
1263 #define CDU_CDU_INT_MASK_REG_WBOFFSET_ERROR (0x1<<6)
1266 #define CDU_CDU_PRTY_STS_REG_PARITY (0x1<<0)
1268 #define CDU_CDU_PRTY_STS_REG_CDUWBBUF_PAR_ERR (0x1<<1)
1270 #define CDU_CDU_PRTY_STS_REG_CDULDBUF_PAR_ERR (0x1<<2)
1272 #define CDU_CDU_PRTY_STS_REG_MATT_PAR_ERR (0x1<<3)
1274 #define CDU_CDU_PRTY_STS_REG_L1TT_PAR_ERR (0x1<<4)
1277 #define CDU_CDU_PRTY_STS_CLR_REG_PARITY (0x1<<0)
1279 #define CDU_CDU_PRTY_STS_CLR_REG_CDUWBBUF_PAR_ERR (0x1<<1)
1281 #define CDU_CDU_PRTY_STS_CLR_REG_CDULDBUF_PAR_ERR (0x1<<2)
1283 #define CDU_CDU_PRTY_STS_CLR_REG_MATT_PAR_ERR (0x1<<3)
1285 #define CDU_CDU_PRTY_STS_CLR_REG_L1TT_PAR_ERR (0x1<<4)
1288 #define CDU_CDU_PRTY_STS_WR_REG_PARITY (0x1<<0)
1290 #define CDU_CDU_PRTY_STS_WR_REG_CDUWBBUF_PAR_ERR (0x1<<1)
1292 #define CDU_CDU_PRTY_STS_WR_REG_CDULDBUF_PAR_ERR (0x1<<2)
1294 #define CDU_CDU_PRTY_STS_WR_REG_MATT_PAR_ERR (0x1<<3)
1296 #define CDU_CDU_PRTY_STS_WR_REG_L1TT_PAR_ERR (0x1<<4)
1299 #define CDU_CDU_PRTY_MASK_REG_PARITY (0x1<<0)
1301 #define CDU_CDU_PRTY_MASK_REG_CDUWBBUF_PAR_ERR (0x1<<1)
1303 #define CDU_CDU_PRTY_MASK_REG_CDULDBUF_PAR_ERR (0x1<<2)
1305 #define CDU_CDU_PRTY_MASK_REG_MATT_PAR_ERR (0x1<<3)
1307 #define CDU_CDU_PRTY_MASK_REG_L1TT_PAR_ERR (0x1<<4)
1309 #define CDU_REG_MF_MODE 0x101050UL //ACCESS:RW DataWidth:0x1 Description: when this bit is set the CDU operates in multifunction mode
1340 #define CFC_CONTROL0_REG_STRING_CAM_DISABLE (0x1<<8)
1342 #define CFC_CONTROL0_REG_CID_CAM_DISABLE (0x1<<9)
1344 #define CFC_CONTROL0_REG_NLOE (0x1<<10)
1346 #define CFC_CONTROL0_REG_SCAM_SCRUB_HIT_EN (0x1<<11)
1348 #define CFC_CONTROL0_REG_SCAM_SCRUB_MISS_EN (0x1<<12)
1350 #define CFC_CONTROL0_REG_CCAM_SCRUB_HIT_EN (0x1<<13)
1352 #define CFC_CONTROL0_REG_CCAM_SCRUB_MISS_EN (0x1<<14)
1355 #define CFC_MASK_REQUESTS_REG_MASK_LCREQ (0x1<<0)
1357 #define CFC_MASK_REQUESTS_REG_MASK_SEARCH (0x1<<1)
1359 #define CFC_MASK_REQUESTS_REG_MASK_UPDATE (0x1<<2)
1361 #define CFC_MASK_REQUESTS_REG_MASK_WB (0x1<<3)
1363 #define CFC_MASK_REQUESTS_REG_MASK_INACTIVATE (0x1<<4)
1365 #define CFC_MASK_REQUESTS_REG_MASK_CDULDRESP (0x1<<5)
1367 #define CFC_MASK_REQUESTS_REG_MASK_CDUWBRESP (0x1<<6)
1376 #define CFC_ARBITERS_REG_REG_SP_MARB_RR1 (0x1<<0)
1378 #define CFC_ARBITERS_REG_REG_SP_LCARB (0x1<<1)
1380 #define CFC_ARBITERS_REG_REG_SP_MARB_RR2 (0x1<<2)
1382 #define CFC_ARBITERS_REG_REG_SP_MARB_RR3 (0x1<<3)
1384 #define CFC_ARBITERS_REG_REG_SP_AC_DEC (0x1<<4)
1386 #define CFC_ARBITERS_REG_REG_SP_AC_INC (0x1<<5)
1389 #define CFC_INIT_REG_REG_AC_INIT (0x1<<0)
1393 #define CFC_INIT_REG_REG_LL_INIT (0x1<<9)
1395 #define CFC_INIT_REG_REG_CAM_INIT (0x1<<10)
1398 #define CFC_DEBUG0_REG_DISABLE_INPUTS (0x1<<0)
1400 #define CFC_DEBUG0_REG_DISABLE_OUTPUTS (0x1<<1)
1404 #define CFC_DEBUG0_REG_DELAY_CAM_RESP (0x1<<10)
1421 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
1423 #define CFC_DEBUG1_REG_MY_VAL_AC (0x1<<5)
1427 #define CFC_DEBUG1_REG_TYPE_FROM_REQ1 (0x1<<8)
1429 #define CFC_DEBUG1_REG_TYPE_FROM_REQ2 (0x1<<9)
1431 #define CFC_DEBUG1_REG_SW_RESET (0x1<<10)
1433 #define CFC_DEBUG1_REG_EN_ON_INT_CLR (0x1<<11)
1435 #define CFC_DEBUG1_REG_UPD_CANCEL_DIS (0x1<<12)
1440 #define CFC_INTERFACES_REG_LRESP_CREDIT_SET (0x1<<3)
1444 #define CFC_INTERFACES_REG_PRSRESP_CREDIT_SET (0x1<<7)
1448 #define CFC_INTERFACES_REG_SEARCH_CREDIT_SET (0x1<<11)
1452 #define CFC_INTERFACES_REG_CDULD_CREDIT_SET (0x1<<16)
1456 #define CFC_INTERFACES_REG_CDUWB_CREDIT_SET (0x1<<21)
1460 #define CFC_INTERFACES_REG_LRESP6_CREDIT_SET (0x1<<25)
1465 #define CFC_CID_CAM_CONTROL_REG_CCAM_SEARCH (0x1<<20)
1467 #define CFC_CID_CAM_CONTROL_REG_CAM_125MHZ (0x1<<21)
1472 #define CFC_REG_SCAM_SEARCH 0x10406cUL //ACCESS:RW DataWidth:0x1 Description: when this bit is set writing to the scam will cause a search operation on the written item (written using ~cfc_registers_lcid_string_cam.string_cam interface. the write can be to any address
1474 #define CFC_REG_LL_INIT_DONE 0x104074UL //ACCESS:R DataWidth:0x1 Description: indication the initializing the link list by the hardware was done.
1475 #define CFC_REG_AC_INIT_DONE 0x104078UL //ACCESS:R DataWidth:0x1 Description: indication the initializing the activity counter by the hardware was done.
1476 #define CFC_REG_CAM_INIT_DONE 0x10407cUL //ACCESS:R DataWidth:0x1 Description: indication the initializing the cams by the hardware was done.
1506 #define CFC_REG_CCAM_BIST_EN 0x1040f4UL //ACCESS:RW DataWidth:0x1 Description: CID CAM BIST
1507 #define CFC_REG_SCAM_BIST_EN 0x1040f8UL //ACCESS:RW DataWidth:0x1 Description: STRING CAM BIST
1509 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
1511 #define CFC_CFC_INT_STS_REG_EXE_ERROR (0x1<<1)
1514 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
1516 #define CFC_CFC_INT_STS_CLR_REG_EXE_ERROR (0x1<<1)
1519 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
1521 #define CFC_CFC_INT_STS_WR_REG_EXE_ERROR (0x1<<1)
1524 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
1526 #define CFC_CFC_INT_MASK_REG_EXE_ERROR (0x1<<1)
1529 #define CFC_CFC_PRTY_STS_REG_PARITY (0x1<<0)
1531 #define CFC_CFC_PRTY_STS_REG_LL_PAR_ERR (0x1<<1)
1533 #define CFC_CFC_PRTY_STS_REG_INFORAM_PAR_ERR (0x1<<2)
1535 #define CFC_CFC_PRTY_STS_REG_AC_PAR_ERR (0x1<<3)
1537 #define CFC_CFC_PRTY_STS_REG_CCAM_PAR_ERR (0x1<<4)
1539 #define CFC_CFC_PRTY_STS_REG_SCAM_PAR_ERR (0x1<<5)
1542 #define CFC_CFC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
1544 #define CFC_CFC_PRTY_STS_CLR_REG_LL_PAR_ERR (0x1<<1)
1546 #define CFC_CFC_PRTY_STS_CLR_REG_INFORAM_PAR_ERR (0x1<<2)
1548 #define CFC_CFC_PRTY_STS_CLR_REG_AC_PAR_ERR (0x1<<3)
1550 #define CFC_CFC_PRTY_STS_CLR_REG_CCAM_PAR_ERR (0x1<<4)
1552 #define CFC_CFC_PRTY_STS_CLR_REG_SCAM_PAR_ERR (0x1<<5)
1555 #define CFC_CFC_PRTY_STS_WR_REG_PARITY (0x1<<0)
1557 #define CFC_CFC_PRTY_STS_WR_REG_LL_PAR_ERR (0x1<<1)
1559 #define CFC_CFC_PRTY_STS_WR_REG_INFORAM_PAR_ERR (0x1<<2)
1561 #define CFC_CFC_PRTY_STS_WR_REG_AC_PAR_ERR (0x1<<3)
1563 #define CFC_CFC_PRTY_STS_WR_REG_CCAM_PAR_ERR (0x1<<4)
1565 #define CFC_CFC_PRTY_STS_WR_REG_SCAM_PAR_ERR (0x1<<5)
1568 #define CFC_CFC_PRTY_MASK_REG_PARITY (0x1<<0)
1570 #define CFC_CFC_PRTY_MASK_REG_LL_PAR_ERR (0x1<<1)
1572 #define CFC_CFC_PRTY_MASK_REG_INFORAM_PAR_ERR (0x1<<2)
1574 #define CFC_CFC_PRTY_MASK_REG_AC_PAR_ERR (0x1<<3)
1576 #define CFC_CFC_PRTY_MASK_REG_CCAM_PAR_ERR (0x1<<4)
1578 #define CFC_CFC_PRTY_MASK_REG_SCAM_PAR_ERR (0x1<<5)
1585 #define CFC_REG_DORQ_MASK_VALERR 0x107010UL //ACCESS:RW DataWidth:0x1 Description: Indicates if DORQ Validation Error (CDU Error#2) is masked (independent of cfc_error_mask)
1586 #define CFC_REG_DORQ_MASK_PCIERR 0x107014UL //ACCESS:RW DataWidth:0x1 Description: Indicates if DORQ PCIe Error (CDU Error#1) is masked (independent of cfc_error_mask)
1591 #define CFC_INTERFACES2_REG_LRESP8_CREDIT_SET (0x1<<4)
1595 #define CFC_INTERFACES2_REG_CDULD_CREDIT_SET_E3 (0x1<<10)
1601 #define CFC_REG_WEAK_ENABLE_PF 0x104124UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.
1603 #define CFC_REG_STRONG_ENABLE_PF 0x104128UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf)
1605 #define CFC_REG_SREQ_FULL_STICKY 0x104130UL //ACCESS:RW DataWidth:0x1 Description: The Interface to Searcher Request Queue has reached the maximum value (4)
1607 #define CFC_REG_PRSRESP_FULL_STICKY 0x104134UL //ACCESS:RW DataWidth:0x1 Description: The Interface to Parser Response Queue has reached the maximum value (6)
1609 #define CFC_REG_DISABLE_ROBUSTWB_PF 0x104138UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state
1627 #define CFC_REG_CCAM_BIST_DONE 0x104200UL //ACCESS:R DataWidth:0x1 Description: CID CAM BIST
1629 #define CFC_REG_CCAM_BIST_GO 0x104204UL //ACCESS:R DataWidth:0x1 Description: CID CAM BIST
1647 #define CFC_REG_SCAM_BIST_DONE 0x104228UL //ACCESS:R DataWidth:0x1 Description: STRING CAM BIST
1649 #define CFC_REG_SCAM_BIST_GO 0x10422cUL //ACCESS:R DataWidth:0x1 Description: STRING CAM BIST
1678 #define CSDM_REG_TIMERS_TICK_ENABLE 0xc2004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
1683 #define CSDM_REG_COUNTERS_WRAP 0xc2018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
1723 #define CSDM_REG_AGG_INT_T_0 0xc20b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
1724 #define CSDM_REG_AGG_INT_T_1 0xc20bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
1725 #define CSDM_REG_AGG_INT_T_2 0xc20c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
1726 #define CSDM_REG_AGG_INT_T_3 0xc20c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
1727 #define CSDM_REG_AGG_INT_T_4 0xc20c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
1728 #define CSDM_REG_AGG_INT_T_5 0xc20ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
1729 #define CSDM_REG_AGG_INT_T_6 0xc20d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
1730 #define CSDM_REG_AGG_INT_T_7 0xc20d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
1731 #define CSDM_REG_AGG_INT_T_8 0xc20d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
1732 #define CSDM_REG_AGG_INT_T_9 0xc20dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
1733 #define CSDM_REG_AGG_INT_T_10 0xc20e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
1734 #define CSDM_REG_AGG_INT_T_11 0xc20e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
1735 #define CSDM_REG_AGG_INT_T_12 0xc20e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
1736 #define CSDM_REG_AGG_INT_T_13 0xc20ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
1737 #define CSDM_REG_AGG_INT_T_14 0xc20f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
1738 #define CSDM_REG_AGG_INT_T_15 0xc20f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
1739 #define CSDM_REG_AGG_INT_T_16 0xc20f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
1740 #define CSDM_REG_AGG_INT_T_17 0xc20fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
1741 #define CSDM_REG_AGG_INT_T_18 0xc2100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
1742 #define CSDM_REG_AGG_INT_T_19 0xc2104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
1743 #define CSDM_REG_AGG_INT_T_20 0xc2108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
1744 #define CSDM_REG_AGG_INT_T_21 0xc210cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
1745 #define CSDM_REG_AGG_INT_T_22 0xc2110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
1746 #define CSDM_REG_AGG_INT_T_23 0xc2114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
1747 #define CSDM_REG_AGG_INT_T_24 0xc2118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
1748 #define CSDM_REG_AGG_INT_T_25 0xc211cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
1749 #define CSDM_REG_AGG_INT_T_26 0xc2120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
1750 #define CSDM_REG_AGG_INT_T_27 0xc2124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
1751 #define CSDM_REG_AGG_INT_T_28 0xc2128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
1752 #define CSDM_REG_AGG_INT_T_29 0xc212cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
1753 #define CSDM_REG_AGG_INT_T_30 0xc2130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
1754 #define CSDM_REG_AGG_INT_T_31 0xc2134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
1755 #define CSDM_REG_AGG_INT_FIC_0 0xc2138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
1756 #define CSDM_REG_AGG_INT_FIC_1 0xc213cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
1757 #define CSDM_REG_AGG_INT_FIC_2 0xc2140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
1758 #define CSDM_REG_AGG_INT_FIC_3 0xc2144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
1759 #define CSDM_REG_AGG_INT_FIC_4 0xc2148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
1760 #define CSDM_REG_AGG_INT_FIC_5 0xc214cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
1761 #define CSDM_REG_AGG_INT_FIC_6 0xc2150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
1762 #define CSDM_REG_AGG_INT_FIC_7 0xc2154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
1763 #define CSDM_REG_AGG_INT_FIC_8 0xc2158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
1764 #define CSDM_REG_AGG_INT_FIC_9 0xc215cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
1765 #define CSDM_REG_AGG_INT_FIC_10 0xc2160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
1766 #define CSDM_REG_AGG_INT_FIC_11 0xc2164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
1767 #define CSDM_REG_AGG_INT_FIC_12 0xc2168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
1768 #define CSDM_REG_AGG_INT_FIC_13 0xc216cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
1769 #define CSDM_REG_AGG_INT_FIC_14 0xc2170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
1770 #define CSDM_REG_AGG_INT_FIC_15 0xc2174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
1771 #define CSDM_REG_AGG_INT_FIC_16 0xc2178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
1772 #define CSDM_REG_AGG_INT_FIC_17 0xc217cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
1773 #define CSDM_REG_AGG_INT_FIC_18 0xc2180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
1774 #define CSDM_REG_AGG_INT_FIC_19 0xc2184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
1775 #define CSDM_REG_AGG_INT_FIC_20 0xc2188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
1776 #define CSDM_REG_AGG_INT_FIC_21 0xc218cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
1777 #define CSDM_REG_AGG_INT_FIC_22 0xc2190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
1778 #define CSDM_REG_AGG_INT_FIC_23 0xc2194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
1779 #define CSDM_REG_AGG_INT_FIC_24 0xc2198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
1780 #define CSDM_REG_AGG_INT_FIC_25 0xc219cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
1781 #define CSDM_REG_AGG_INT_FIC_26 0xc21a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
1782 #define CSDM_REG_AGG_INT_FIC_27 0xc21a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
1783 #define CSDM_REG_AGG_INT_FIC_28 0xc21a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
1784 #define CSDM_REG_AGG_INT_FIC_29 0xc21acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
1785 #define CSDM_REG_AGG_INT_FIC_30 0xc21b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
1786 #define CSDM_REG_AGG_INT_FIC_31 0xc21b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
1787 #define CSDM_REG_AGG_INT_MODE_0 0xc21b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1788 #define CSDM_REG_AGG_INT_MODE_1 0xc21bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1789 #define CSDM_REG_AGG_INT_MODE_2 0xc21c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1790 #define CSDM_REG_AGG_INT_MODE_3 0xc21c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1791 #define CSDM_REG_AGG_INT_MODE_4 0xc21c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1792 #define CSDM_REG_AGG_INT_MODE_5 0xc21ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1793 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1794 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1795 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1796 #define CSDM_REG_AGG_INT_MODE_9 0xc21dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1797 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1798 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1799 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1800 #define CSDM_REG_AGG_INT_MODE_13 0xc21ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1801 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1802 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1803 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
1804 #define CSDM_REG_AGG_INT_MODE_17 0xc21fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
1805 #define CSDM_REG_AGG_INT_MODE_18 0xc2200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1806 #define CSDM_REG_AGG_INT_MODE_19 0xc2204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1807 #define CSDM_REG_AGG_INT_MODE_20 0xc2208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1808 #define CSDM_REG_AGG_INT_MODE_21 0xc220cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1809 #define CSDM_REG_AGG_INT_MODE_22 0xc2210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1810 #define CSDM_REG_AGG_INT_MODE_23 0xc2214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1811 #define CSDM_REG_AGG_INT_MODE_24 0xc2218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1812 #define CSDM_REG_AGG_INT_MODE_25 0xc221cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1813 #define CSDM_REG_AGG_INT_MODE_26 0xc2220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1814 #define CSDM_REG_AGG_INT_MODE_27 0xc2224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1815 #define CSDM_REG_AGG_INT_MODE_28 0xc2228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1816 #define CSDM_REG_AGG_INT_MODE_29 0xc222cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1817 #define CSDM_REG_AGG_INT_MODE_30 0xc2230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1818 #define CSDM_REG_AGG_INT_MODE_31 0xc2234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
1820 #define CSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
1822 #define CSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
1824 #define CSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
1826 #define CSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
1828 #define CSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
1830 #define CSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
1832 #define CSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
1834 #define CSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
1836 #define CSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
1838 #define CSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
1840 #define CSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
1842 #define CSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
1844 #define CSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
1846 #define CSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
1848 #define CSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
1850 #define CSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
1852 #define CSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
1854 #define CSDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
1856 #define CSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
1858 #define CSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
1860 #define CSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
1862 #define CSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
1864 #define CSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
1866 #define CSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
1868 #define CSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
1870 #define CSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
1872 #define CSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
1875 #define CSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
1877 #define CSDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
1879 #define CSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
1881 #define CSDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
1883 #define CSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
1885 #define CSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
1887 #define CSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
1890 #define CSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
1892 #define CSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
1894 #define CSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
1896 #define CSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
1898 #define CSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
1900 #define CSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
1902 #define CSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
1904 #define CSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
1906 #define CSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
1908 #define CSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
1910 #define CSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
1912 #define CSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
1914 #define CSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
1916 #define CSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
1918 #define CSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
1920 #define CSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
1922 #define CSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
1924 #define CSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
1926 #define CSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
1928 #define CSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
1930 #define CSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
1932 #define CSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
1934 #define CSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
1936 #define CSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
1938 #define CSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
1940 #define CSDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
1942 #define CSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
1945 #define CSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
1947 #define CSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
1949 #define CSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
1951 #define CSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
1953 #define CSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
1955 #define CSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
1976 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
1978 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
1980 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
1982 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
1984 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
1986 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
1988 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
1990 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
1992 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
1994 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
1996 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
1998 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
2000 #define CSDM_CSDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
2002 #define CSDM_CSDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
2004 #define CSDM_CSDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
2006 #define CSDM_CSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
2008 #define CSDM_CSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
2010 #define CSDM_CSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
2012 #define CSDM_CSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
2014 #define CSDM_CSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
2016 #define CSDM_CSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
2018 #define CSDM_CSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
2020 #define CSDM_CSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
2022 #define CSDM_CSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
2024 #define CSDM_CSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
2026 #define CSDM_CSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
2028 #define CSDM_CSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
2030 #define CSDM_CSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
2032 #define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
2034 #define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
2036 #define CSDM_CSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
2038 #define CSDM_CSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
2041 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
2043 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
2045 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
2047 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
2049 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
2051 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
2053 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
2055 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
2057 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
2059 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
2061 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
2063 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
2065 #define CSDM_CSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
2067 #define CSDM_CSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
2069 #define CSDM_CSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
2071 #define CSDM_CSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
2073 #define CSDM_CSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
2075 #define CSDM_CSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
2077 #define CSDM_CSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
2079 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
2081 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
2083 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
2085 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
2087 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
2089 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
2091 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
2093 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
2095 #define CSDM_CSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
2097 #define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
2099 #define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
2101 #define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
2103 #define CSDM_CSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
2106 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
2108 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
2110 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
2112 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
2114 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
2116 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
2118 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
2120 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
2122 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
2124 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
2126 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
2128 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
2130 #define CSDM_CSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
2132 #define CSDM_CSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
2134 #define CSDM_CSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
2136 #define CSDM_CSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
2138 #define CSDM_CSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
2140 #define CSDM_CSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
2142 #define CSDM_CSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
2144 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
2146 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
2148 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
2150 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
2152 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
2154 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
2156 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
2158 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
2160 #define CSDM_CSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
2162 #define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
2164 #define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
2166 #define CSDM_CSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
2168 #define CSDM_CSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
2171 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2173 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
2175 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
2177 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
2179 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
2181 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
2183 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
2185 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
2187 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
2189 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
2191 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
2193 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
2195 #define CSDM_CSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
2197 #define CSDM_CSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
2199 #define CSDM_CSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
2201 #define CSDM_CSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
2203 #define CSDM_CSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
2205 #define CSDM_CSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
2207 #define CSDM_CSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
2209 #define CSDM_CSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
2211 #define CSDM_CSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
2213 #define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
2215 #define CSDM_CSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
2217 #define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
2219 #define CSDM_CSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
2221 #define CSDM_CSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
2223 #define CSDM_CSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
2225 #define CSDM_CSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
2227 #define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
2229 #define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
2231 #define CSDM_CSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
2233 #define CSDM_CSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
2236 #define CSDM_CSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
2238 #define CSDM_CSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
2240 #define CSDM_CSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
2242 #define CSDM_CSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
2244 #define CSDM_CSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
2246 #define CSDM_CSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
2248 #define CSDM_CSDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
2250 #define CSDM_CSDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
2252 #define CSDM_CSDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
2254 #define CSDM_CSDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
2256 #define CSDM_CSDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
2258 #define CSDM_CSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
2260 #define CSDM_CSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
2262 #define CSDM_CSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
2265 #define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
2267 #define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
2269 #define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
2271 #define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
2273 #define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
2275 #define CSDM_CSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
2277 #define CSDM_CSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
2279 #define CSDM_CSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
2281 #define CSDM_CSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
2283 #define CSDM_CSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
2285 #define CSDM_CSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
2287 #define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
2289 #define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
2291 #define CSDM_CSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
2294 #define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
2296 #define CSDM_CSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
2298 #define CSDM_CSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
2300 #define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
2302 #define CSDM_CSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
2304 #define CSDM_CSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
2306 #define CSDM_CSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
2308 #define CSDM_CSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
2310 #define CSDM_CSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
2312 #define CSDM_CSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
2314 #define CSDM_CSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
2316 #define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
2318 #define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
2320 #define CSDM_CSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
2323 #define CSDM_CSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
2325 #define CSDM_CSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
2327 #define CSDM_CSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
2329 #define CSDM_CSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
2331 #define CSDM_CSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
2333 #define CSDM_CSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
2335 #define CSDM_CSDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
2337 #define CSDM_CSDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
2339 #define CSDM_CSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
2341 #define CSDM_CSDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
2343 #define CSDM_CSDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
2345 #define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
2347 #define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
2349 #define CSDM_CSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
2352 #define CSDM_CSDM_PRTY_STS_REG_PARITY (0x1<<0)
2354 #define CSDM_CSDM_PRTY_STS_REG_TIMERS (0x1<<1)
2356 #define CSDM_CSDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
2358 #define CSDM_CSDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
2360 #define CSDM_CSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
2362 #define CSDM_CSDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
2364 #define CSDM_CSDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
2366 #define CSDM_CSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
2368 #define CSDM_CSDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
2370 #define CSDM_CSDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
2372 #define CSDM_CSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
2375 #define CSDM_CSDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
2377 #define CSDM_CSDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
2379 #define CSDM_CSDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
2381 #define CSDM_CSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
2383 #define CSDM_CSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
2385 #define CSDM_CSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
2387 #define CSDM_CSDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
2389 #define CSDM_CSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
2391 #define CSDM_CSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
2393 #define CSDM_CSDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
2395 #define CSDM_CSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
2398 #define CSDM_CSDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
2400 #define CSDM_CSDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
2402 #define CSDM_CSDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
2404 #define CSDM_CSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
2406 #define CSDM_CSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
2408 #define CSDM_CSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
2410 #define CSDM_CSDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
2412 #define CSDM_CSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
2414 #define CSDM_CSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
2416 #define CSDM_CSDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
2418 #define CSDM_CSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
2421 #define CSDM_CSDM_PRTY_MASK_REG_PARITY (0x1<<0)
2423 #define CSDM_CSDM_PRTY_MASK_REG_TIMERS (0x1<<1)
2425 #define CSDM_CSDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
2427 #define CSDM_CSDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
2429 #define CSDM_CSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
2431 #define CSDM_CSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
2433 #define CSDM_CSDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
2435 #define CSDM_CSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
2437 #define CSDM_CSDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
2439 #define CSDM_CSDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
2441 #define CSDM_CSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
2456 #define CSDM_REG_ASYNC_HOST_EMPTY 0xc2408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
2458 #define CSDM_REG_ASYNC_HOST_FULL 0xc240cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
2460 #define CSDM_REG_CFC_LOAD_PEND_EMPTY 0xc2410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
2462 #define CSDM_REG_CFC_LOAD_PEND_FULL 0xc2414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
2464 #define CSDM_REG_CFC_LOAD_RSP_EMPTY 0xc2418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
2466 #define CSDM_REG_CFC_LOAD_RSP_FULL 0xc241cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
2468 #define CSDM_REG_CM_DELAY_EMPTY 0xc2420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
2470 #define CSDM_REG_CM_DELAY_FULL 0xc2424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
2472 #define CSDM_REG_CM_QUEUE_EMPTY 0xc2428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
2474 #define CSDM_REG_CM_QUEUE_FULL 0xc242cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
2476 #define CSDM_REG_DELAY_FIFO_EMPTY 0xc2430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
2478 #define CSDM_REG_DELAY_FIFO_FULL 0xc2434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
2480 #define CSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0xc2438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
2482 #define CSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0xc243cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
2484 #define CSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0xc2440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
2486 #define CSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0xc2444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
2488 #define CSDM_REG_DST_INT_RAM_IF_FULL 0xc2448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
2490 #define CSDM_REG_DST_INT_RAM_WAIT_EMPTY 0xc244cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
2492 #define CSDM_REG_DST_INT_RAM_WAIT_FULL 0xc2450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
2494 #define CSDM_REG_DST_NONE_PEND_EMPTY 0xc2454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
2496 #define CSDM_REG_DST_NONE_PEND_FULL 0xc2458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
2498 #define CSDM_REG_DST_PAS_BUF_IF_FULL 0xc245cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
2500 #define CSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xc2460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
2502 #define CSDM_REG_DST_PAS_BUF_WAIT_FULL 0xc2464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
2504 #define CSDM_REG_DST_PB_IF_FULL 0xc2468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
2506 #define CSDM_REG_DST_PB_IMMED_EMPTY 0xc246cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
2508 #define CSDM_REG_DST_PB_IMMED_FULL 0xc2470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
2510 #define CSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0xc2474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
2512 #define CSDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0xc2478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
2514 #define CSDM_REG_DST_PXP_CTRL_IF_FULL 0xc247cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
2516 #define CSDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0xc2480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
2518 #define CSDM_REG_DST_PXP_CTRL_IMMED_FULL 0xc2484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
2520 #define CSDM_REG_DST_PXP_CTRL_LINK_EMPTY 0xc2488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
2522 #define CSDM_REG_DST_PXP_CTRL_LINK_FULL 0xc248cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
2524 #define CSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0xc2490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
2526 #define CSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0xc2494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
2528 #define CSDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0xc2498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
2530 #define CSDM_REG_DST_PXP_DP_DST_PEND_FULL 0xc249cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
2532 #define CSDM_REG_DST_PXP_DP_IF_FULL 0xc24a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
2534 #define CSDM_REG_DST_PXP_DP_LINK_EMPTY 0xc24a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
2536 #define CSDM_REG_DST_PXP_DP_LINK_FULL 0xc24a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
2552 #define CSDM_REG_PB_FULL 0xc24c8UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
2554 #define CSDM_REG_PBF_FULL 0xc24ccUL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
2556 #define CSDM_REG_PXP_DELAY_EMPTY 0xc24d0UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
2558 #define CSDM_REG_PXP_DELAY_FULL 0xc24d4UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
2560 #define CSDM_REG_QM_FULL 0xc24d8UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
2572 #define CSDM_REG_RSP_BRB1_CTRL_IF_FULL 0xc24f0UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
2574 #define CSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0xc24f4UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
2576 #define CSDM_REG_RSP_BRB1_CTRL_PEND_FULL 0xc24f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
2578 #define CSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0xc24fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
2580 #define CSDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0xc2500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
2582 #define CSDM_REG_RSP_BRB1_DP_DST_EMPTY 0xc2504UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
2584 #define CSDM_REG_RSP_BRB1_DP_DST_FULL 0xc2508UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
2586 #define CSDM_REG_RSP_BRB1_DP_IF_FULL 0xc250cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
2588 #define CSDM_REG_RSP_BRB1_DP_PEND_EMPTY 0xc2510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
2590 #define CSDM_REG_RSP_BRB1_DP_PEND_FULL 0xc2514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
2592 #define CSDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0xc2518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
2594 #define CSDM_REG_RSP_BRB1_DP_RDATA_FULL 0xc251cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
2596 #define CSDM_REG_RSP_INT_RAM_PEND_EMPTY 0xc2520UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
2598 #define CSDM_REG_RSP_INT_RAM_PEND_FULL 0xc2524UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
2600 #define CSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xc2528UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
2602 #define CSDM_REG_RSP_INT_RAM_RDATA_FULL 0xc252cUL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
2604 #define CSDM_REG_RSP_PB_IF_FULL 0xc2530UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
2606 #define CSDM_REG_RSP_PB_PEND_EMPTY 0xc2534UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
2608 #define CSDM_REG_RSP_PB_PEND_FULL 0xc2538UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
2610 #define CSDM_REG_RSP_PB_RDATA_EMPTY 0xc253cUL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
2612 #define CSDM_REG_RSP_PB_RDATA_FULL 0xc2540UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
2614 #define CSDM_REG_RSP_PXP_CTRL_IF_FULL 0xc2544UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
2616 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
2618 #define CSDM_REG_RSP_PXP_CTRL_RDATA_FULL 0xc254cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
2620 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
2622 #define CSDM_REG_SYNC_PARSER_FULL 0xc2554UL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
2624 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
2626 #define CSDM_REG_SYNC_SYNC_FULL 0xc255cUL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
2628 #define CSDM_REG_TIMERS_ADDR_EMPTY 0xc2560UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
2630 #define CSDM_REG_TIMERS_ADDR_FULL 0xc2564UL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
2632 #define CSDM_REG_TIMERS_PEND_EMPTY 0xc2568UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
2634 #define CSDM_REG_TIMERS_PEND_FULL 0xc256cUL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
2658 #define CSEM_REG_THREAD_INTER_CNT_ENABLE 0x200018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~csem_registers_thread_inter_cnt.thread_inter_cnt
2694 #define CSEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
2696 #define CSEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
2698 #define CSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
2700 #define CSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
2702 #define CSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
2704 #define CSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
2706 #define CSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
2708 #define CSEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
2710 #define CSEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
2712 #define CSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
2714 #define CSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
2716 #define CSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
2718 #define CSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
2720 #define CSEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
2722 #define CSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
2725 #define CSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
2727 #define CSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
2729 #define CSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
2731 #define CSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
2733 #define CSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
2735 #define CSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
2737 #define CSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
2739 #define CSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
2741 #define CSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
2743 #define CSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
2756 #define CSEM_REG_CLEAR_WAITP 0x2000d8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
2758 #define CSEM_REG_SLOW_DBG_ACTIVE 0x2000e0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
2759 #define CSEM_REG_DBG_MSG_SRC 0x2000e4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~csem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
2760 #define CSEM_REG_DBG_MODE0_CFG 0x2000e8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~csem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
2762 #define CSEM_REG_DBG_MODE1_CFG 0x2000f0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~csem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
2763 #define CSEM_REG_DBG_EACH_CYLE 0x2000f4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
2768 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
2770 #define CSEM_CSEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
2772 #define CSEM_CSEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
2774 #define CSEM_CSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
2776 #define CSEM_CSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
2778 #define CSEM_CSEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
2780 #define CSEM_CSEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
2782 #define CSEM_CSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
2784 #define CSEM_CSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
2786 #define CSEM_CSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
2788 #define CSEM_CSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
2790 #define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
2792 #define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
2794 #define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
2796 #define CSEM_CSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
2798 #define CSEM_CSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
2800 #define CSEM_CSEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
2802 #define CSEM_CSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
2804 #define CSEM_CSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
2806 #define CSEM_CSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
2808 #define CSEM_CSEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
2810 #define CSEM_CSEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
2812 #define CSEM_CSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
2814 #define CSEM_CSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
2816 #define CSEM_CSEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
2818 #define CSEM_CSEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
2820 #define CSEM_CSEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
2822 #define CSEM_CSEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
2824 #define CSEM_CSEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
2826 #define CSEM_CSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
2828 #define CSEM_CSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
2830 #define CSEM_CSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
2833 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
2835 #define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
2837 #define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
2839 #define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
2841 #define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
2843 #define CSEM_CSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
2845 #define CSEM_CSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
2847 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
2849 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
2851 #define CSEM_CSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
2853 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
2855 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
2857 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
2859 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
2861 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
2863 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
2865 #define CSEM_CSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
2867 #define CSEM_CSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
2869 #define CSEM_CSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
2871 #define CSEM_CSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
2873 #define CSEM_CSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
2875 #define CSEM_CSEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
2877 #define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
2879 #define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
2881 #define CSEM_CSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
2883 #define CSEM_CSEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
2885 #define CSEM_CSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
2887 #define CSEM_CSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
2889 #define CSEM_CSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
2891 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
2893 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
2895 #define CSEM_CSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
2898 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
2900 #define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
2902 #define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
2904 #define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
2906 #define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
2908 #define CSEM_CSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
2910 #define CSEM_CSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
2912 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
2914 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
2916 #define CSEM_CSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
2918 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
2920 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
2922 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
2924 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
2926 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
2928 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
2930 #define CSEM_CSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
2932 #define CSEM_CSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
2934 #define CSEM_CSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
2936 #define CSEM_CSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
2938 #define CSEM_CSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
2940 #define CSEM_CSEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
2942 #define CSEM_CSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
2944 #define CSEM_CSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
2946 #define CSEM_CSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
2948 #define CSEM_CSEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
2950 #define CSEM_CSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
2952 #define CSEM_CSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
2954 #define CSEM_CSEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
2956 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
2958 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
2960 #define CSEM_CSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
2963 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2965 #define CSEM_CSEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
2967 #define CSEM_CSEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
2969 #define CSEM_CSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
2971 #define CSEM_CSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
2973 #define CSEM_CSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
2975 #define CSEM_CSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
2977 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
2979 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
2981 #define CSEM_CSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
2983 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
2985 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
2987 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
2989 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
2991 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
2993 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
2995 #define CSEM_CSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
2997 #define CSEM_CSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
2999 #define CSEM_CSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
3001 #define CSEM_CSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
3003 #define CSEM_CSEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
3005 #define CSEM_CSEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
3007 #define CSEM_CSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
3009 #define CSEM_CSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
3011 #define CSEM_CSEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
3013 #define CSEM_CSEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
3015 #define CSEM_CSEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
3017 #define CSEM_CSEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
3019 #define CSEM_CSEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
3021 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
3023 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
3025 #define CSEM_CSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
3028 #define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
3030 #define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
3032 #define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
3034 #define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
3036 #define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
3038 #define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
3040 #define CSEM_CSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
3042 #define CSEM_CSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
3044 #define CSEM_CSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
3046 #define CSEM_CSEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
3048 #define CSEM_CSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
3051 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
3053 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
3055 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
3057 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
3059 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
3061 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
3063 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
3065 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
3067 #define CSEM_CSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
3069 #define CSEM_CSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
3071 #define CSEM_CSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
3074 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
3076 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
3078 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
3080 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
3082 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
3084 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
3086 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
3088 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
3090 #define CSEM_CSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
3092 #define CSEM_CSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
3094 #define CSEM_CSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
3097 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
3099 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
3101 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
3103 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
3105 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
3107 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
3109 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
3111 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
3113 #define CSEM_CSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
3115 #define CSEM_CSEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
3117 #define CSEM_CSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
3120 #define CSEM_CSEM_PRTY_STS_0_REG_PARITY (0x1<<0)
3122 #define CSEM_CSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
3124 #define CSEM_CSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
3126 #define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
3128 #define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
3130 #define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
3132 #define CSEM_CSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
3134 #define CSEM_CSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
3136 #define CSEM_CSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
3138 #define CSEM_CSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
3140 #define CSEM_CSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
3142 #define CSEM_CSEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
3144 #define CSEM_CSEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
3146 #define CSEM_CSEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
3148 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
3150 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
3152 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
3154 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
3156 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
3158 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
3160 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
3162 #define CSEM_CSEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
3164 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
3166 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
3168 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
3170 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
3172 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
3174 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
3176 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
3178 #define CSEM_CSEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
3180 #define CSEM_CSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
3182 #define CSEM_CSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
3185 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
3187 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
3189 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
3191 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
3193 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
3195 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
3197 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
3199 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
3201 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
3203 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
3205 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
3207 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
3209 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
3211 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
3213 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
3215 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
3217 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
3219 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
3221 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
3223 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
3225 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
3227 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
3229 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
3231 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
3233 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
3235 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
3237 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
3239 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
3241 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
3243 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
3245 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
3247 #define CSEM_CSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
3250 #define CSEM_CSEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
3252 #define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
3254 #define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
3256 #define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
3258 #define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
3260 #define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
3262 #define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
3264 #define CSEM_CSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
3266 #define CSEM_CSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
3268 #define CSEM_CSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
3270 #define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
3272 #define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
3274 #define CSEM_CSEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
3276 #define CSEM_CSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
3278 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
3280 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
3282 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
3284 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
3286 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
3288 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
3290 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
3292 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
3294 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
3296 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
3298 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
3300 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
3302 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
3304 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
3306 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
3308 #define CSEM_CSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
3310 #define CSEM_CSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
3312 #define CSEM_CSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
3315 #define CSEM_CSEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
3317 #define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
3319 #define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
3321 #define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
3323 #define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
3325 #define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
3327 #define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
3329 #define CSEM_CSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
3331 #define CSEM_CSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
3333 #define CSEM_CSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
3335 #define CSEM_CSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
3337 #define CSEM_CSEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
3339 #define CSEM_CSEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
3341 #define CSEM_CSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
3343 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
3345 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
3347 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
3349 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
3351 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
3353 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
3355 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
3357 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
3359 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
3361 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
3363 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
3365 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
3367 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
3369 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
3371 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
3373 #define CSEM_CSEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
3375 #define CSEM_CSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
3377 #define CSEM_CSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
3380 #define CSEM_CSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
3382 #define CSEM_CSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
3384 #define CSEM_CSEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
3386 #define CSEM_CSEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
3388 #define CSEM_CSEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
3391 #define CSEM_CSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
3393 #define CSEM_CSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
3395 #define CSEM_CSEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
3397 #define CSEM_CSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
3399 #define CSEM_CSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
3402 #define CSEM_CSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
3404 #define CSEM_CSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
3406 #define CSEM_CSEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
3408 #define CSEM_CSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
3410 #define CSEM_CSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
3413 #define CSEM_CSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
3415 #define CSEM_CSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
3417 #define CSEM_CSEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
3419 #define CSEM_CSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
3421 #define CSEM_CSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
3433 #define CSEM_REG_DBG_IF_FULL 0x20020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
3435 #define CSEM_REG_DRA_EMPTY 0x200210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
3437 #define CSEM_REG_EXT_PAS_EMPTY 0x200214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
3439 #define CSEM_REG_EXT_PAS_FULL 0x200218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
3443 #define CSEM_REG_EXT_STORE_IF_FULL 0x200220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
3445 #define CSEM_REG_FIC0_DISABLE 0x200224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
3447 #define CSEM_REG_FIC0_EMPTY 0x200228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
3449 #define CSEM_REG_FIC0_FULL 0x20022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
3453 #define CSEM_REG_FIC1_DISABLE 0x200234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
3455 #define CSEM_REG_FIC1_EMPTY 0x200238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
3457 #define CSEM_REG_FIC1_FULL 0x20023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
3465 #define CSEM_REG_PAS_DISABLE 0x20024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
3467 #define CSEM_REG_PAS_IF_FULL 0x200250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
3469 #define CSEM_REG_RAM0_IF_FULL 0x200254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
3471 #define CSEM_REG_RAM1_IF_FULL 0x200258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
3473 #define CSEM_REG_SET0_THREAD_EMPTY 0x20025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
3475 #define CSEM_REG_SET0_THREAD_FULL 0x200260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
3477 #define CSEM_REG_SET1_THREAD_EMPTY 0x200264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
3479 #define CSEM_REG_SET1_THREAD_FULL 0x200268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
3483 #define CSEM_REG_SLOW_DBG_ALM_EMPTY 0x200270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
3485 #define CSEM_REG_SLOW_DBG_ALM_FULL 0x200274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
3487 #define CSEM_REG_SLOW_DBG_EMPTY 0x200278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
3489 #define CSEM_REG_SLOW_DBG_FULL 0x20027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
3491 #define CSEM_REG_SLOW_DRA_FIN_EMPTY 0x200280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
3493 #define CSEM_REG_SLOW_DRA_FIN_FULL 0x200284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
3495 #define CSEM_REG_SLOW_DRA_INT_EMPTY 0x200288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
3497 #define CSEM_REG_SLOW_DRA_INT_FULL 0x20028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
3499 #define CSEM_REG_SLOW_DRA_RD_EMPTY 0x200290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
3501 #define CSEM_REG_SLOW_DRA_RD_FULL 0x200294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
3503 #define CSEM_REG_SLOW_DRA_WR_EMPTY 0x200298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
3505 #define CSEM_REG_SLOW_DRA_WR_FULL 0x20029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
3507 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
3509 #define CSEM_REG_SLOW_EXT_STORE_FULL 0x2002a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
3511 #define CSEM_REG_SLOW_RAM0_RD_EMPTY 0x2002a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
3513 #define CSEM_REG_SLOW_RAM0_RD_FULL 0x2002acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
3515 #define CSEM_REG_SLOW_RAM0_WR_ALM_FULL 0x2002b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
3517 #define CSEM_REG_SLOW_RAM0_WR_EMPTY 0x2002b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
3519 #define CSEM_REG_SLOW_RAM0_WR_FULL 0x2002b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
3521 #define CSEM_REG_SLOW_RAM1_RD_EMPTY 0x2002bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
3523 #define CSEM_REG_SLOW_RAM1_RD_FULL 0x2002c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
3525 #define CSEM_REG_SLOW_RAM1_WR_ALM_FULL 0x2002c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
3527 #define CSEM_REG_SLOW_RAM1_WR_EMPTY 0x2002c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
3529 #define CSEM_REG_SLOW_RAM1_WR_FULL 0x2002ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
3531 #define CSEM_REG_SYNC_DBG_EMPTY 0x2002d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
3533 #define CSEM_REG_SYNC_DBG_FULL 0x2002d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync
3597 #define DBG_OUTPUT_ENABLE_REG_PCI_REQ_ENABLE (0x1<<0)
3599 #define DBG_OUTPUT_ENABLE_REG_PCI_DATA_ENABLE (0x1<<1)
3601 #define DBG_OUTPUT_ENABLE_REG_NIG_ENABLE (0x1<<2)
3614 #define DBG_REG_FULL_MODE 0xc034UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates whether data will be wrapped (oldest data is thrown) or overflowed-one shot (newest data is thrown) as follows: (a) When ~dbg_registers_debug_target=2/0 (PCI/internal buffer): 1 - wrap; 0 - One Shot; (b) When ~dbg_registers_debug_target=1 (NIG): 1 - constant send; 0 - One Shot;
3624 #define DBG_REG_CPU_DEBUG_FRAME 0xc05cUL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicate the frame signal of the debug data that arrives from the CPU
3625 #define DBG_REG_CPU_TIMEOUT 0xc060UL //ACCESS:RW DataWidth:0x1 Description: debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty
3626 #define DBG_REG_DBG_BLOCK_ON 0xc064UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;
3628 #define DBG_REG_TDM64_ENABLE 0xc06cUL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates tdm working mode as follows: (a) 1 - enables tdm64 mechanism which allows 64 bit of data. In this case the 32 lsb are chosen by the tdm mechanism using slots 0..6 and the 32 msb are taken from the joint HW and are marked as slot number 7; (b) 0 - disables the tdm64 mechanism hence allowing 32 bits of data only; the tdm operation mode allows only the 32 lsb of data. In this case the data is chosen by the tdm mechanism using slots 0..7
3629 #define DBG_REG_IMMEDIATE_ACK 0xc070UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates that an immediate ack should be sent to the CPU upon writing to ~dbg_registers_cpu_debug_data and an interrupt will be sent when a new write can be issued (after the data was actually taken); If 0 then the ack will be delayed until a new write can be issued by the CPU (after the data was actually taken)
3630 #define DBG_REG_NO_GRANT_ON_FULL 0xc074UL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicate whether grant will be issued by the dbg block towards the storms in case the internal buffer is almost full as follows: (a) 1 - no grants will be made to the storms when the internal buffer is almost full. When the buffer will be partialy freed (enough for a complete data chunk) then grant is resumed; (b) 0 - grant is supplied every time the matching storms's slot is chosen disregarding the volume status of the internal buffer.
3632 #define DBG_REG_PCI_LOGIC_ADDR 0xc07cUL //ACCESS:RW DataWidth:0x1 Description: debug only: This bit indicates logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical address;
3633 #define DBG_REG_PATTERN_RECOGNITION_DISABLE 0xc080UL //ACCESS:RW DataWidth:0x1 Description: debug only: For pattern recognition usage: This bit indicates whether the pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;
3634 #define DBG_REG_PATTERN_RECOGNITION_STORAGE_MODE 0xc084UL //ACCESS:RW DataWidth:0x1 Description: debug only: For pattern recognition usage: This bit indicates the trigger behavior of the pattern recognition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially recognized; (b) 0 - start debug data storage when the expected pattern is initially recognized
3635 #define DBG_REG_PATTERN_RECOGNITION_FILTER 0xc088UL //ACCESS:RW DataWidth:0x1 Description: debug only: For pattern recognition usage: This bit indicates whether data is continously stored in the dbg block until/from pattern recognition initial event; or stored only in cycles of a pattern recognition event occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pattern recognition; (b) 0 - enable data storage only in cycles of a pttern recognition event occurence
3637 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3639 #define DBG_DBG_INT_STS_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
3642 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3644 #define DBG_DBG_INT_STS_CLR_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
3647 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3649 #define DBG_DBG_INT_STS_WR_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
3652 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3654 #define DBG_DBG_INT_MASK_REG_CPU_DATA_TAKEN_INTR (0x1<<1)
3656 #define DBG_REG_DBG_PRTY_STS 0xc09cUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
3657 #define DBG_DBG_PRTY_STS_REG_PARITY (0x1<<0)
3659 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
3660 #define DBG_DBG_PRTY_STS_CLR_REG_PARITY (0x1<<0)
3662 #define DBG_REG_DBG_PRTY_STS_WR 0xc0a4UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
3663 #define DBG_DBG_PRTY_STS_WR_REG_PARITY (0x1<<0)
3665 #define DBG_REG_DBG_PRTY_MASK 0xc0a8UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
3666 #define DBG_DBG_PRTY_MASK_REG_PARITY (0x1<<0)
3668 #define DBG_REG_TRIGGER_ENABLE 0xd010UL //ACCESS:RW DataWidth:0x1 Description: (a) 0 - trigger machine is off (all data will bypass the triggering machine) in this mode trigger_event is never asserted. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode & rcrd_on_window_post_trgr_evnt_mode
3669 #define DBG_REG_TRIGGER_INTERLEAVED_ENABLE 0xd014UL //ACCESS:RW DataWidth:0x1 Description: (a) 0 - triggering interleaved messages is disbaled. (b) 1 - triggering interleaved messages is enabled; will be used for triggering on recorded handler messages. NOTE: triggering is possible on one level depth of interleaved messages; i.e. if message B is interleaved within message A then it is ok; However if message C is interleaved within message B and message B is interleaved within message A this scenario is NOT supported
3673 #define DBG_REG_TRIGGER_STATE_VALID_SEL_0 0xd024UL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] (a) 1 - use valid[3] (compared data is data[63:32] in that case); (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: 1. in each state the triggering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) 2. if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
3674 #define DBG_REG_TRIGGER_STATE_VALID_SEL_1 0xd028UL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] (a) 1 - use valid[3] (compared data is data[63:32] in that case); (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: 1. in each state the triggering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) 2. if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
3675 #define DBG_REG_TRIGGER_STATE_VALID_SEL_2 0xd02cUL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] (a) 1 - use valid[3] (compared data is data[63:32] in that case); (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: 1. in each state the triggering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) 2. if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
3676 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_0 0xd030UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
3677 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_1 0xd034UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
3678 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_2 0xd038UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.
3715 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0 0xd0ccUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3716 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_1 0xd0d0UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3717 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_2 0xd0d4UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3718 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_3 0xd0d8UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3719 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_4 0xd0dcUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3720 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_5 0xd0e0UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3721 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_6 0xd0e4UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3722 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_7 0xd0e8UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3723 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_8 0xd0ecUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3724 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_9 0xd0f0UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3725 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_10 0xd0f4UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3726 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_11 0xd0f8UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3727 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_12 0xd0fcUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3728 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_13 0xd100UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3729 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_14 0xd104UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3730 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_15 0xd108UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3731 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_16 0xd10cUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3732 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_17 0xd110UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3733 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_18 0xd114UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3734 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_19 0xd118UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3735 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_20 0xd11cUL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3736 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_21 0xd120UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3737 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_22 0xd124UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3738 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_23 0xd128UL //ACCESS:RW DataWidth:0x1 Description: The frame that need to be compared. The 1 bit vector is determined as follows: (a) frame[0] - if trigger_state_set_cnstr_offseti[0] = 0 OR (b) frame[3] - if trigger_state_set_cnstr_offseti[0] = 1
3763 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0xd18cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3764 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_1 0xd190UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3765 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_2 0xd194UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3766 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_3 0xd198UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3767 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_4 0xd19cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3768 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_5 0xd1a0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3769 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_6 0xd1a4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3770 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_7 0xd1a8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3771 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_8 0xd1acUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3772 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_9 0xd1b0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3773 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_10 0xd1b4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3774 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_11 0xd1b8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3775 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_12 0xd1bcUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3776 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_13 0xd1c0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3777 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_14 0xd1c4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3778 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_15 0xd1c8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3779 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_16 0xd1ccUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3780 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_17 0xd1d0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3781 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_18 0xd1d4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3782 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_19 0xd1d8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3783 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_20 0xd1dcUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3784 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_21 0xd1e0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3785 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_22 0xd1e4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3786 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_23 0xd1e8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal operation (trigger_state_set_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
3955 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0 0xd30cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3956 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_1 0xd310UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3957 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_2 0xd314UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3958 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_3 0xd318UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3959 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_4 0xd31cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3960 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_5 0xd320UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3961 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_6 0xd324UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3962 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_7 0xd328UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3963 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_8 0xd32cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3964 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_9 0xd330UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3965 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_10 0xd334UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3966 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_11 0xd338UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3967 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_12 0xd33cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3968 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_13 0xd340UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3969 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_14 0xd344UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3970 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_15 0xd348UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3971 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_16 0xd34cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3972 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_17 0xd350UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3973 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_18 0xd354UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3974 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_19 0xd358UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3975 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_20 0xd35cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3976 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_21 0xd360UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3977 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_22 0xd364UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
3978 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_23 0xd368UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
4003 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0 0xd3ccUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4004 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_1 0xd3d0UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4005 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_2 0xd3d4UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4006 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_3 0xd3d8UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4007 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_4 0xd3dcUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4008 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_5 0xd3e0UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4009 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_6 0xd3e4UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4010 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_7 0xd3e8UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4011 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_8 0xd3ecUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4012 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_9 0xd3f0UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4013 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_10 0xd3f4UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4014 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_11 0xd3f8UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4015 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_12 0xd3fcUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4016 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_13 0xd400UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4017 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_14 0xd404UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4018 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_15 0xd408UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4019 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_16 0xd40cUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4020 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_17 0xd410UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4021 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_18 0xd414UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4022 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_19 0xd418UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4023 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_20 0xd41cUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4024 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_21 0xd420UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4025 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_22 0xd424UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4026 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_23 0xd428UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (trigger_state_set_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4027 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 0xd42cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use trigger_state_valid_seli to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
4028 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_1 0xd430UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use trigger_state_valid_seli to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
4029 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_2 0xd434UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use trigger_state_valid_seli to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
4055 #define DBG_REG_FILTER_VALID_SEL 0xd49cUL //ACCESS:RW DataWidth:0x1 Description: When working in tdm64 mode there are 2 valid signals as follows: (1) Valid[3] - validates data[63:32] (2) Valid[0] - validates data[31:0] Description: (a) 1 - use valid[3] (compared data is data[63:32] in that case) (b) 0 - use valid[0] (compared data is data[31:0] in that case). NOTE: (1) The filtering machine compares the constraints to single data source only (which means that only data[31:0] / data[63:32] will be compared in each state) (2) if 64 bit framing mode OR tdm32 framing mode then this bit is not relevant; in that case only valid[0] & data[31:0]/data[63:0] are referred.
4060 #define DBG_REG_FILTER_CNSTR_FRAME_0 0xd4b0UL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
4061 #define DBG_REG_FILTER_CNSTR_FRAME_1 0xd4b4UL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
4062 #define DBG_REG_FILTER_CNSTR_FRAME_2 0xd4b8UL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
4063 #define DBG_REG_FILTER_CNSTR_FRAME_3 0xd4bcUL //ACCESS:RW DataWidth:0x1 Description: The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[0] = 0; OR (b) frame[3] - if filter_cnstr_offseti[0] = 1
4068 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_0 0xd4d0UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
4069 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_1 0xd4d4UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
4070 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_2 0xd4d8UL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
4071 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_3 0xd4dcUL //ACCESS:RW DataWidth:0x1 Description: (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; NOTE: The mask is valid only for the equal operation (trigger_cnstr_oprtni=000); i.e. not valid for </<=/>=/>.
4100 #define DBG_REG_FILTER_CNSTR_MUST_0 0xd510UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
4101 #define DBG_REG_FILTER_CNSTR_MUST_1 0xd514UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
4102 #define DBG_REG_FILTER_CNSTR_MUST_2 0xd518UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
4103 #define DBG_REG_FILTER_CNSTR_MUST_3 0xd51cUL //ACCESS:RW DataWidth:0x1 Description: (a) 1: the above data vector & frame must exist as part of the message. (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.
4108 #define DBG_REG_FILTER_CNSTR_CYCLIC_0 0xd530UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4109 #define DBG_REG_FILTER_CNSTR_CYCLIC_1 0xd534UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4110 #define DBG_REG_FILTER_CNSTR_CYCLIC_2 0xd538UL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4111 #define DBG_REG_FILTER_CNSTR_CYCLIC_3 0xd53cUL //ACCESS:RW DataWidth:0x1 Description: refers the comparison which is implemented in case the operation is NOT equal (filter_cnstr_oprtni > 0) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit)
4112 #define DBG_REG_FILTER_MSG_LENGTH_ENABLE 0xd540UL //ACCESS:RW DataWidth:0x1 Description: (a) 1: use filter_msg_length to determine message boundary. (b) 0: use filter_valid_sel to determine which frame (frame[0]/frame[3]) signals message boundary (end of message)
4115 #define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE 0xd54cUL //ACCESS:RW DataWidth:0x1 Description: Recording mode upon trigger event: (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_num_cycles valid cycles upon the event; (b) 1 - disable recording data upon triggering event. NOTE: applicable only if trigger_enable=1
4154 #define DBG_REG_FULL_ON_EXT_BUFFER 0xc108UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the external buffer was filled; Relevant only when ~dbg_registers_full_mode=0 (one shot)
4156 #define DBG_REG_FULL_ON_INT_BUFFER 0xc10cUL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the internal buffer was filled
4162 #define DBG_REG_OVL_ON_EXT_BUFFER 0xc118UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the external buffer was overflowed (newest data was thrown); Relevant only for (a) ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=0 (one shot); or (b) ~dbg_registers_debug_target=1 (NIG) & ~dbg_registers_full_mode=0 (one shot)
4164 #define DBG_REG_OVL_ON_INT_BUFFER 0xc11cUL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates that the internal buffer was overflowed (newest data was thrown); Not relevant if ~dbg_registers_debug_target=0 (internal buffer) & ~dbg_registers_full_mode=1 (wrap);
4168 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates wheter indicates that external buffer was wrapped (oldest data was thrown); Relevant only when ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap);
4170 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128UL //ACCESS:R DataWidth:0x1 Description: debug only: This bit indicates wheter the internal buffer was wrapped (oldest data was thrown) Relevant only when ~dbg_registers_debug_target=0 (internal buffer)
4186 #define DBG_REG_TRIGGER_EVENT 0xd004UL //ACCESS:R DataWidth:0x1 Description: Configured messages sequencing was identified.
4202 #define DMAE_REG_INIT 0x102000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
4203 #define DMAE_REG_PCI_IFEN 0x102004UL //ACCESS:RW DataWidth:0x1 Description: DMAE PCI Interface (Request;Read;Write) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all other signals are treated as usual; if 1 - normal activity.
4204 #define DMAE_REG_GRC_IFEN 0x102008UL //ACCESS:RW DataWidth:0x1 Description: DMAE GRC Interface (Target;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
4205 #define DMAE_REG_RLXD_ORDR 0x10200cUL //ACCESS:RW DataWidth:0x1 Description: Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X relaxed ordering is enabled.
4206 #define DMAE_REG_NO_SNOOP 0x102010UL //ACCESS:RW DataWidth:0x1 Description: 0-PCI type cache snoop protection is required;1-system isn't required to cause processor cache snoop for coherency.
4207 #define DMAE_REG_CRC16I_INIT 0x102014UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16 initial value is all zeroes; if 1 - the CRC-16 initial value is all ones.
4208 #define DMAE_REG_CRC16_BSWAP 0x102018UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16 final calculation result isn't byte swapped; if 1 - the CRC-16 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
4209 #define DMAE_REG_CRC16C_INIT 0x10201cUL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c initial value is all ones.
4210 #define DMAE_REG_CRC16T10_INIT 0x102020UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the CRC-16 T10 initial value is all ones.
4211 #define DMAE_REG_CRC32I_INIT 0x102024UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32 initial value is all zeroes; if 1 - the CRC-32 initial value is all ones.
4212 #define DMAE_REG_CRC32I_BSWAP 0x102028UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
4213 #define DMAE_REG_CRC32C_INIT 0x10202cUL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32c initial value is all zeroes; if 1 - the CRC-32c initial value is all ones.
4214 #define DMAE_REG_CRC32C_BSWAP 0x102030UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the CRC-32c final calculation result isn't byte swapped; if 1 - the CRC-32c final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).
4215 #define DMAE_REG_CHKSUM0_FIX 0x102034UL //ACCESS:RW DataWidth:0x1 Description: If 0 - the final checksum equal 0 won't be changed;if 1 - the final checksum equal 0 will be fixed to all ones.
4221 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
4223 #define DMAE_DMAE_INT_STS_REG_PCI_RD_BUF_ERR (0x1<<1)
4226 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
4228 #define DMAE_DMAE_INT_STS_CLR_REG_PCI_RD_BUF_ERR (0x1<<1)
4231 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
4233 #define DMAE_DMAE_INT_STS_WR_REG_PCI_RD_BUF_ERR (0x1<<1)
4236 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
4238 #define DMAE_DMAE_INT_MASK_REG_PCI_RD_BUF_ERR (0x1<<1)
4241 #define DMAE_DMAE_PRTY_STS_REG_PARITY (0x1<<0)
4243 #define DMAE_DMAE_PRTY_STS_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
4245 #define DMAE_DMAE_PRTY_STS_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
4247 #define DMAE_DMAE_PRTY_STS_REG_CMD_MEM_PRTY_ERR (0x1<<3)
4250 #define DMAE_DMAE_PRTY_STS_CLR_REG_PARITY (0x1<<0)
4252 #define DMAE_DMAE_PRTY_STS_CLR_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
4254 #define DMAE_DMAE_PRTY_STS_CLR_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
4256 #define DMAE_DMAE_PRTY_STS_CLR_REG_CMD_MEM_PRTY_ERR (0x1<<3)
4259 #define DMAE_DMAE_PRTY_STS_WR_REG_PARITY (0x1<<0)
4261 #define DMAE_DMAE_PRTY_STS_WR_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
4263 #define DMAE_DMAE_PRTY_STS_WR_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
4265 #define DMAE_DMAE_PRTY_STS_WR_REG_CMD_MEM_PRTY_ERR (0x1<<3)
4268 #define DMAE_DMAE_PRTY_MASK_REG_PARITY (0x1<<0)
4270 #define DMAE_DMAE_PRTY_MASK_REG_PCI_BUF_LOW_PRTY_ERR (0x1<<1)
4272 #define DMAE_DMAE_PRTY_MASK_REG_PCI_BUF_HIGH_PRTY_ERR (0x1<<2)
4274 #define DMAE_DMAE_PRTY_MASK_REG_CMD_MEM_PRTY_ERR (0x1<<3)
4279 #define DMAE_REG_PCI_ERR_DISCARD_EN 0x102074UL //ACCESS:RW DataWidth:0x1 Description: When set discards 1- or 2-Dword PCI transaction read in case there is PCI error.
4281 #define DMAE_REG_BACKWARD_COMP_EN 0x10207cUL //ACCESS:RW DataWidth:0x1 Description: When set the DMAE will process the commands as in E1.5. 1.The function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 4.Completion function=0; 5.Error handling=0
4308 #define DMAE_REG_GO_C0 0x102080UL //ACCESS:RW DataWidth:0x1 Description: Command 0 go.
4310 #define DMAE_REG_GO_C1 0x102084UL //ACCESS:RW DataWidth:0x1 Description: Command 1 go.
4312 #define DMAE_REG_GO_C10 0x102088UL //ACCESS:RW DataWidth:0x1 Description: Command 10 go.
4314 #define DMAE_REG_GO_C11 0x10208cUL //ACCESS:RW DataWidth:0x1 Description: Command 11 go.
4316 #define DMAE_REG_GO_C12 0x102090UL //ACCESS:RW DataWidth:0x1 Description: Command 12 go.
4318 #define DMAE_REG_GO_C13 0x102094UL //ACCESS:RW DataWidth:0x1 Description: Command 13 go.
4320 #define DMAE_REG_GO_C14 0x102098UL //ACCESS:RW DataWidth:0x1 Description: Command 14 go.
4322 #define DMAE_REG_GO_C15 0x10209cUL //ACCESS:RW DataWidth:0x1 Description: Command 15 go.
4324 #define DMAE_REG_GO_C2 0x1020a0UL //ACCESS:RW DataWidth:0x1 Description: Command 2 go.
4326 #define DMAE_REG_GO_C3 0x1020a4UL //ACCESS:RW DataWidth:0x1 Description: Command 3 go.
4328 #define DMAE_REG_GO_C4 0x1020a8UL //ACCESS:RW DataWidth:0x1 Description: Command 4 go.
4330 #define DMAE_REG_GO_C5 0x1020acUL //ACCESS:RW DataWidth:0x1 Description: Command 5 go.
4332 #define DMAE_REG_GO_C6 0x1020b0UL //ACCESS:RW DataWidth:0x1 Description: Command 6 go.
4334 #define DMAE_REG_GO_C7 0x1020b4UL //ACCESS:RW DataWidth:0x1 Description: Command 7 go.
4336 #define DMAE_REG_GO_C8 0x1020b8UL //ACCESS:RW DataWidth:0x1 Description: Command 8 go.
4338 #define DMAE_REG_GO_C9 0x1020bcUL //ACCESS:RW DataWidth:0x1 Description: Command 9 go.
4350 #define DORQ_REG_INIT 0x170000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
4352 #define DORQ_IF_EN_REG_RQ_IFEN (0x1<<0)
4354 #define DORQ_IF_EN_REG_CF_IFEN (0x1<<1)
4356 #define DORQ_IF_EN_REG_RSP_IFEN (0x1<<2)
4358 #define DORQ_IF_EN_REG_DPM_IFEN (0x1<<3)
4361 #define DORQ_MODE_ACT_REG_NORM_MODE_ACT (0x1<<0)
4363 #define DORQ_MODE_ACT_REG_DPM_MODE_ACT (0x1<<1)
4375 #define DORQ_REG_QM_AEMPTY_EN 0x170034UL //ACCESS:RW DataWidth:0x1 Description: If 0 - QM almost empty is disregarded; if 1 - QM almost empty is taken into consideration.
4396 #define DORQ_REG_DQ_FREEZE 0x170080UL //ACCESS:RW DataWidth:0x1 Description: When set; the DQ will serve the doorbells; already existing in the queue and will block the Response interface.
4397 #define DORQ_REG_AUTO_FREEZE_EN 0x170084UL //ACCESS:RW DataWidth:0x1 Description: When set; the DQ will automatically stop sending CFC load requests when a doorbell discard interrupt is generated. The freeze mode will remain until the auto_freeze_rel register is set.
4398 #define DORQ_REG_AUTO_DISCARD_EN 0x170088UL //ACCESS:RW DataWidth:0x1 Description: If this register is equal to 1 then the DQ will enter auto discard mode when a doorbell discard interrupt is generated. In this mode all incoming doorbells will be dropped even if the FIFO is not full anymore.
4412 #define DORQ_REG_DQ_FULL_ST 0x1700c0UL //ACCESS:R DataWidth:0x1 Description: DQ FIFO full status. Is set; when FIFO filling level is more or equal to full threshold; reset on full clear.
4458 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
4460 #define DORQ_DORQ_INT_STS_REG_DB_DISCARD (0x1<<1)
4462 #define DORQ_DORQ_INT_STS_REG_TYPE_VAL_ERR (0x1<<2)
4464 #define DORQ_DORQ_INT_STS_REG_DB_COLLISION (0x1<<3)
4466 #define DORQ_DORQ_INT_STS_REG_DQ_AFULL (0x1<<4)
4468 #define DORQ_DORQ_INT_STS_REG_VF_TYPE_VAL_ERR (0x1<<5)
4471 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
4473 #define DORQ_DORQ_INT_STS_CLR_REG_DB_DISCARD (0x1<<1)
4475 #define DORQ_DORQ_INT_STS_CLR_REG_TYPE_VAL_ERR (0x1<<2)
4477 #define DORQ_DORQ_INT_STS_CLR_REG_DB_COLLISION (0x1<<3)
4479 #define DORQ_DORQ_INT_STS_CLR_REG_DQ_AFULL (0x1<<4)
4481 #define DORQ_DORQ_INT_STS_CLR_REG_VF_TYPE_VAL_ERR (0x1<<5)
4484 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
4486 #define DORQ_DORQ_INT_STS_WR_REG_DB_DISCARD (0x1<<1)
4488 #define DORQ_DORQ_INT_STS_WR_REG_TYPE_VAL_ERR (0x1<<2)
4490 #define DORQ_DORQ_INT_STS_WR_REG_DB_COLLISION (0x1<<3)
4492 #define DORQ_DORQ_INT_STS_WR_REG_DQ_AFULL (0x1<<4)
4494 #define DORQ_DORQ_INT_STS_WR_REG_VF_TYPE_VAL_ERR (0x1<<5)
4497 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
4499 #define DORQ_DORQ_INT_MASK_REG_DB_DISCARD (0x1<<1)
4501 #define DORQ_DORQ_INT_MASK_REG_TYPE_VAL_ERR (0x1<<2)
4503 #define DORQ_DORQ_INT_MASK_REG_DB_COLLISION (0x1<<3)
4505 #define DORQ_DORQ_INT_MASK_REG_DQ_AFULL (0x1<<4)
4507 #define DORQ_DORQ_INT_MASK_REG_VF_TYPE_VAL_ERR (0x1<<5)
4510 #define DORQ_DORQ_PRTY_STS_REG_PARITY (0x1<<0)
4512 #define DORQ_DORQ_PRTY_STS_REG_DORQ_PRTY (0x1<<1)
4515 #define DORQ_DORQ_PRTY_STS_CLR_REG_PARITY (0x1<<0)
4517 #define DORQ_DORQ_PRTY_STS_CLR_REG_DORQ_PRTY (0x1<<1)
4520 #define DORQ_DORQ_PRTY_STS_WR_REG_PARITY (0x1<<0)
4522 #define DORQ_DORQ_PRTY_STS_WR_REG_DORQ_PRTY (0x1<<1)
4525 #define DORQ_DORQ_PRTY_MASK_REG_PARITY (0x1<<0)
4527 #define DORQ_DORQ_PRTY_MASK_REG_DORQ_PRTY (0x1<<1)
4539 #define DORQ_REG_VF_INDEX_FIX_EN 0x1701e8UL //ACCESS:RW DataWidth:0x1 Description: Chicken bit for VF index fix. If high rf_dorq_func[9:4] maps to VF registers. Otherwise rf_dorq_func[5:0] maps to VF registers.
4604 #define DORQ_REG_AUTO_FREEZE_ST 0x170318UL //ACCESS:R DataWidth:0x1 Description: When high auto freeze is active and doorbells are not being drained from the FIFO. Cleared when auto_freeze_rel is written.
4605 #define DORQ_REG_AUTO_DISCARD_ST 0x17031cUL //ACCESS:R DataWidth:0x1 Description: When high auto discard is active and all doorbells are dropped before going into the FIFO. Cleared when auto_discard_rel is written.
4609 #define DORQ_REG_CM_T_FLAG 0x170344UL //ACCESS:RW DataWidth:0x1 Description: Thread Required bit for error indicating CM messages
4696 #define DORQ_REG_AUTO_DISCARD_REL 0x170200UL //ACCESS:W DataWidth:0x1 Description: Release the discard mode. Write only.
4698 #define DORQ_REG_AUTO_FREEZE_REL 0x170204UL //ACCESS:W DataWidth:0x1 Description: Release the freeze mode set by auto freeze. Write only.
4704 #define DORQ_REG_DQ_FIFO_FULL_CLR 0x170210UL //ACCESS:W DataWidth:0x1 Description: Clears the full interrupt. Functionally write only. The read access is allowed with don't care data.
4710 #define DORQ_REG_PF_DISCARD_STATUS 0x170324UL //ACCESS:R DataWidth:0x1 SPLIT:8 Description: Per-PF register indicating that a doorbell has been dropped for this PF. Cleared when corresponding pf_discard_rel register is written.
4712 #define DORQ_REG_PF_DISCARD_REL 0x170328UL //ACCESS:W DataWidth:0x1 SPLIT:8 Description: When this register is written the corresponding pf_discard_status register is cleared.
4714 #define DORQ_REG_VF_DISCARD_STATUS 0x170330UL //ACCESS:R DataWidth:0x1 SPLIT:64 Description: Per-VF register indicating that a doorbell has been dropped for this VF. Cleared when corresponding vf_discard_rel register is written.
4716 #define DORQ_REG_VF_DISCARD_REL 0x170334UL //ACCESS:W DataWidth:0x1 SPLIT:64 Description: When this register is written the corresponding vf_discard_status register is cleared.
4745 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
4747 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
4749 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
4751 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
4753 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
4755 #define HC_CONFIG_0_REG_NOT_DURING_INT_EN_0 (0x1<<5)
4757 #define HC_CONFIG_0_REG_COALESCE_NOW_EN_0 (0x1<<6)
4759 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
4761 #define HC_CONFIG_0_REG_MSIX_ATTN_EN_0 (0x1<<8)
4765 #define HC_CONFIG_0_REG_STATISTIC_COUNTER_EN_0 (0x1<<11)
4767 #define HC_CONFIG_0_REG_MSI_MSIX_MEMORY_EN_0 (0x1<<12)
4770 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
4772 #define HC_CONFIG_1_REG_SINGLE_ISR_EN_1 (0x1<<1)
4774 #define HC_CONFIG_1_REG_MSI_MSIX_INT_EN_1 (0x1<<2)
4776 #define HC_CONFIG_1_REG_INT_LINE_EN_1 (0x1<<3)
4778 #define HC_CONFIG_1_REG_ATTN_BIT_EN_1 (0x1<<4)
4780 #define HC_CONFIG_1_REG_NOT_DURING_INT_EN_1 (0x1<<5)
4782 #define HC_CONFIG_1_REG_COALESCE_NOW_EN_1 (0x1<<6)
4784 #define HC_CONFIG_1_REG_MSI_ATTN_EN_1 (0x1<<7)
4786 #define HC_CONFIG_1_REG_MSIX_ATTN_EN_1 (0x1<<8)
4790 #define HC_CONFIG_1_REG_STATISTIC_COUNTER_EN_1 (0x1<<11)
4792 #define HC_CONFIG_1_REG_MSI_MSIX_MEMORY_EN_1 (0x1<<12)
4805 #define HC_PCI_CONFIG_0_REG_MSI_RELAX_0 (0x1<<0)
4807 #define HC_PCI_CONFIG_0_REG_MSI_NO_SNOOP_0 (0x1<<1)
4809 #define HC_PCI_CONFIG_0_REG_ATTN_RELAX_0 (0x1<<2)
4811 #define HC_PCI_CONFIG_0_REG_ATTN_NO_SNOOP_0 (0x1<<3)
4814 #define HC_PCI_CONFIG_1_REG_MSI_RELAX_1 (0x1<<0)
4816 #define HC_PCI_CONFIG_1_REG_MSI_NO_SNOOP_1 (0x1<<1)
4818 #define HC_PCI_CONFIG_1_REG_ATTN_RELAX_1 (0x1<<2)
4820 #define HC_PCI_CONFIG_1_REG_ATTN_NO_SNOOP_1 (0x1<<3)
4862 #define HC_REG_INTERRUPT_A 0x108058UL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: read the interrupt b line value; 0 = asserted; 1= deasserted
4863 #define HC_REG_INTERRUPT_B 0x10805cUL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: read the interrupt a line value; 0 = asserted; 1= deasserted
4874 #define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
4876 #define HC_HC_INT_STS_REG_FIFO_ERROR (0x1<<1)
4878 #define HC_HC_INT_STS_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
4880 #define HC_HC_INT_STS_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
4882 #define HC_HC_INT_STS_REG_MAIN_MEMORY (0x1<<4)
4884 #define HC_HC_INT_STS_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
4886 #define HC_HC_INT_STS_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
4889 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
4891 #define HC_HC_INT_STS_CLR_REG_FIFO_ERROR (0x1<<1)
4893 #define HC_HC_INT_STS_CLR_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
4895 #define HC_HC_INT_STS_CLR_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
4897 #define HC_HC_INT_STS_CLR_REG_MAIN_MEMORY (0x1<<4)
4899 #define HC_HC_INT_STS_CLR_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
4901 #define HC_HC_INT_STS_CLR_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
4904 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
4906 #define HC_HC_INT_STS_WR_REG_FIFO_ERROR (0x1<<1)
4908 #define HC_HC_INT_STS_WR_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
4910 #define HC_HC_INT_STS_WR_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
4912 #define HC_HC_INT_STS_WR_REG_MAIN_MEMORY (0x1<<4)
4914 #define HC_HC_INT_STS_WR_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
4916 #define HC_HC_INT_STS_WR_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
4919 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
4921 #define HC_HC_INT_MASK_REG_FIFO_ERROR (0x1<<1)
4923 #define HC_HC_INT_MASK_REG_MME_IS_BIGGER_THEN_5 (0x1<<2)
4925 #define HC_HC_INT_MASK_REG_TMP_STORM_ID_NOT_MATCH (0x1<<3)
4927 #define HC_HC_INT_MASK_REG_MAIN_MEMORY (0x1<<4)
4929 #define HC_HC_INT_MASK_REG_STATISTIC_COUNTER_MEMORY (0x1<<5)
4931 #define HC_HC_INT_MASK_REG_CONS_OR_PROD_IDX_TOO_BIG (0x1<<6)
4934 #define HC_HC_PRTY_STS_REG_PARITY (0x1<<0)
4936 #define HC_HC_PRTY_STS_REG_MAIN_MEMORY (0x1<<1)
4938 #define HC_HC_PRTY_STS_REG_COUNTERS_MEMORY (0x1<<2)
4941 #define HC_HC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
4943 #define HC_HC_PRTY_STS_CLR_REG_MAIN_MEMORY (0x1<<1)
4945 #define HC_HC_PRTY_STS_CLR_REG_COUNTERS_MEMORY (0x1<<2)
4948 #define HC_HC_PRTY_STS_WR_REG_PARITY (0x1<<0)
4950 #define HC_HC_PRTY_STS_WR_REG_MAIN_MEMORY (0x1<<1)
4952 #define HC_HC_PRTY_STS_WR_REG_COUNTERS_MEMORY (0x1<<2)
4955 #define HC_HC_PRTY_MASK_REG_PARITY (0x1<<0)
4957 #define HC_HC_PRTY_MASK_REG_MAIN_MEMORY (0x1<<1)
4959 #define HC_HC_PRTY_MASK_REG_COUNTERS_MEMORY (0x1<<2)
4977 #define HC_REG_DEC_CEILING 0x108130UL //ACCESS:W DataWidth:0x1 SPLIT:4 Description: This command register infuence the MSI configuration state machine. This register is write only and has 4 addresses as follow: 0 = dec port 0; 1 = ceiling port 0; 2 = dec port 1; 3 = ceiling port 1;
4979 #define HC_REG_PBA_COMMAND 0x108140UL //ACCESS:W DataWidth:0x1 SPLIT:4 Description: This register is write only and has 4 addresses as follow: 0 = clear all PBA bits port 0; 1 = clear all pending interrupts request port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts request port1;there is no meaning for the data in this register
5008 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
5010 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
5012 #define IGU_BLOCK_CONFIGURATION_REG_BUS_DWORD_SELECT (0x1<<2)
5014 #define IGU_BLOCK_CONFIGURATION_REG_PORT4MODE_EN (0x1<<3)
5016 #define IGU_BLOCK_CONFIGURATION_REG_TIMER_MASK_EN (0x1<<4)
5023 #define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_RO (0x1<<8)
5025 #define IGU_MESSAGE_FIELDS_REG_MSI_MSIX_NS (0x1<<9)
5027 #define IGU_MESSAGE_FIELDS_REG_MSIX_WRITE_DONE_TYPE (0x1<<10)
5035 #define IGU_MESSAGE_FIELDS_REG_ATTN_RO (0x1<<23)
5037 #define IGU_MESSAGE_FIELDS_REG_ATTN_NS (0x1<<24)
5039 #define IGU_MESSAGE_FIELDS_REG_ATTN_WRITE_DONE_TYPE (0x1<<25)
5052 #define IGU_REG_COMMAND_DEBUG 0x130034UL //ACCESS:RW DataWidth:0x1 Description: Debug only: 0 - FIFO collects eight first error messages; 1 - FIFO collects eight last incoming command.
5053 #define IGU_REG_STATISTIC_EN 0x130038UL //ACCESS:RW DataWidth:0x1 Description: enabling to collect data in the statistic_num_message_sent memory.
5055 #define IGU_REG_TIMER_MASK_ACTIVE 0x130040UL //ACCESS:R DataWidth:0x1 Description: when set the timer mask is active and the IGU does not send interrupts. When clear the timer mask is inactive.
5059 #define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_RESERVED (0x1<<7)
5061 #define IGU_ERROR_HANDLING_FILTER_REG_ERROR_HANDLING_FILTER_EN (0x1<<8)
5084 #define IGU_REG_CAM_BIST_EN 0x130084UL //ACCESS:RW DataWidth:0x1 Description: Debug: for CAM bist uses
5087 #define IGU_IGU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
5089 #define IGU_IGU_INT_STS_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
5091 #define IGU_IGU_INT_STS_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
5093 #define IGU_IGU_INT_STS_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
5095 #define IGU_IGU_INT_STS_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
5097 #define IGU_IGU_INT_STS_REG_MME_BIGGER_THEN_5 (0x1<<5)
5099 #define IGU_IGU_INT_STS_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
5101 #define IGU_IGU_INT_STS_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
5103 #define IGU_IGU_INT_STS_REG_CMD_FID_NOT_MATCH (0x1<<8)
5105 #define IGU_IGU_INT_STS_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
5107 #define IGU_IGU_INT_STS_REG_ATTN_PROD_ACC (0x1<<10)
5110 #define IGU_IGU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
5112 #define IGU_IGU_INT_STS_CLR_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
5114 #define IGU_IGU_INT_STS_CLR_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
5116 #define IGU_IGU_INT_STS_CLR_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
5118 #define IGU_IGU_INT_STS_CLR_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
5120 #define IGU_IGU_INT_STS_CLR_REG_MME_BIGGER_THEN_5 (0x1<<5)
5122 #define IGU_IGU_INT_STS_CLR_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
5124 #define IGU_IGU_INT_STS_CLR_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
5126 #define IGU_IGU_INT_STS_CLR_REG_CMD_FID_NOT_MATCH (0x1<<8)
5128 #define IGU_IGU_INT_STS_CLR_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
5130 #define IGU_IGU_INT_STS_CLR_REG_ATTN_PROD_ACC (0x1<<10)
5133 #define IGU_IGU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
5135 #define IGU_IGU_INT_STS_WR_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
5137 #define IGU_IGU_INT_STS_WR_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
5139 #define IGU_IGU_INT_STS_WR_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
5141 #define IGU_IGU_INT_STS_WR_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
5143 #define IGU_IGU_INT_STS_WR_REG_MME_BIGGER_THEN_5 (0x1<<5)
5145 #define IGU_IGU_INT_STS_WR_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
5147 #define IGU_IGU_INT_STS_WR_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
5149 #define IGU_IGU_INT_STS_WR_REG_CMD_FID_NOT_MATCH (0x1<<8)
5151 #define IGU_IGU_INT_STS_WR_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
5153 #define IGU_IGU_INT_STS_WR_REG_ATTN_PROD_ACC (0x1<<10)
5156 #define IGU_IGU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
5158 #define IGU_IGU_INT_MASK_REG_CTRL_FIFO_ERROR_ERR (0x1<<1)
5160 #define IGU_IGU_INT_MASK_REG_PXP_REQ_LENGTH_TOO_BIG (0x1<<2)
5162 #define IGU_IGU_INT_MASK_REG_HOST_TRIES2ACCESS_PROD_UPD (0x1<<3)
5164 #define IGU_IGU_INT_MASK_REG_VF_TRIES2ACC_ATTN_CMD (0x1<<4)
5166 #define IGU_IGU_INT_MASK_REG_MME_BIGGER_THEN_5 (0x1<<5)
5168 #define IGU_IGU_INT_MASK_REG_SB_INDEX_IS_NOT_VALID (0x1<<6)
5170 #define IGU_IGU_INT_MASK_REG_DURIN_INT_READ_WITH_SIMD_DIS (0x1<<7)
5172 #define IGU_IGU_INT_MASK_REG_CMD_FID_NOT_MATCH (0x1<<8)
5174 #define IGU_IGU_INT_MASK_REG_SEGMENT_ACCESS_INVALID (0x1<<9)
5176 #define IGU_IGU_INT_MASK_REG_ATTN_PROD_ACC (0x1<<10)
5179 #define IGU_IGU_PRTY_STS_REG_PARITY (0x1<<0)
5181 #define IGU_IGU_PRTY_STS_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
5183 #define IGU_IGU_PRTY_STS_REG_CAM_PARITY (0x1<<2)
5185 #define IGU_IGU_PRTY_STS_REG_SB_PARITY (0x1<<3)
5187 #define IGU_IGU_PRTY_STS_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
5189 #define IGU_IGU_PRTY_STS_REG_MASK_LOW_PARITY (0x1<<5)
5191 #define IGU_IGU_PRTY_STS_REG_PBA_LOW_PARITY (0x1<<6)
5193 #define IGU_IGU_PRTY_STS_REG_MSIX_PARITY (0x1<<7)
5195 #define IGU_IGU_PRTY_STS_REG_MSI_PARITY (0x1<<8)
5197 #define IGU_IGU_PRTY_STS_REG_ATTN_ADDR_PARITY (0x1<<9)
5199 #define IGU_IGU_PRTY_STS_REG_STATISTIC_PARITY (0x1<<10)
5202 #define IGU_IGU_PRTY_STS_CLR_REG_PARITY (0x1<<0)
5204 #define IGU_IGU_PRTY_STS_CLR_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
5206 #define IGU_IGU_PRTY_STS_CLR_REG_CAM_PARITY (0x1<<2)
5208 #define IGU_IGU_PRTY_STS_CLR_REG_SB_PARITY (0x1<<3)
5210 #define IGU_IGU_PRTY_STS_CLR_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
5212 #define IGU_IGU_PRTY_STS_CLR_REG_MASK_LOW_PARITY (0x1<<5)
5214 #define IGU_IGU_PRTY_STS_CLR_REG_PBA_LOW_PARITY (0x1<<6)
5216 #define IGU_IGU_PRTY_STS_CLR_REG_MSIX_PARITY (0x1<<7)
5218 #define IGU_IGU_PRTY_STS_CLR_REG_MSI_PARITY (0x1<<8)
5220 #define IGU_IGU_PRTY_STS_CLR_REG_ATTN_ADDR_PARITY (0x1<<9)
5222 #define IGU_IGU_PRTY_STS_CLR_REG_STATISTIC_PARITY (0x1<<10)
5225 #define IGU_IGU_PRTY_STS_WR_REG_PARITY (0x1<<0)
5227 #define IGU_IGU_PRTY_STS_WR_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
5229 #define IGU_IGU_PRTY_STS_WR_REG_CAM_PARITY (0x1<<2)
5231 #define IGU_IGU_PRTY_STS_WR_REG_SB_PARITY (0x1<<3)
5233 #define IGU_IGU_PRTY_STS_WR_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
5235 #define IGU_IGU_PRTY_STS_WR_REG_MASK_LOW_PARITY (0x1<<5)
5237 #define IGU_IGU_PRTY_STS_WR_REG_PBA_LOW_PARITY (0x1<<6)
5239 #define IGU_IGU_PRTY_STS_WR_REG_MSIX_PARITY (0x1<<7)
5241 #define IGU_IGU_PRTY_STS_WR_REG_MSI_PARITY (0x1<<8)
5243 #define IGU_IGU_PRTY_STS_WR_REG_ATTN_ADDR_PARITY (0x1<<9)
5245 #define IGU_IGU_PRTY_STS_WR_REG_STATISTIC_PARITY (0x1<<10)
5248 #define IGU_IGU_PRTY_MASK_REG_PARITY (0x1<<0)
5250 #define IGU_IGU_PRTY_MASK_REG_CTRL_FIFO_ERROR_PARITY (0x1<<1)
5252 #define IGU_IGU_PRTY_MASK_REG_CAM_PARITY (0x1<<2)
5254 #define IGU_IGU_PRTY_MASK_REG_SB_PARITY (0x1<<3)
5256 #define IGU_IGU_PRTY_MASK_REG_SB_BEFORE_INT_LOW_PARITY (0x1<<4)
5258 #define IGU_IGU_PRTY_MASK_REG_MASK_LOW_PARITY (0x1<<5)
5260 #define IGU_IGU_PRTY_MASK_REG_PBA_LOW_PARITY (0x1<<6)
5262 #define IGU_IGU_PRTY_MASK_REG_MSIX_PARITY (0x1<<7)
5264 #define IGU_IGU_PRTY_MASK_REG_MSI_PARITY (0x1<<8)
5266 #define IGU_IGU_PRTY_MASK_REG_ATTN_ADDR_PARITY (0x1<<9)
5268 #define IGU_IGU_PRTY_MASK_REG_STATISTIC_PARITY (0x1<<10)
5294 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130UL //ACCESS:R DataWidth:0x1 Description: data availble for error memory. If this bit is clear do not red from error_handling_memory.
5302 #define IGU_REG_PCI_PF_MSI_EN 0x130140UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF MSI enable status. shadow of PCI config register
5304 #define IGU_REG_PCI_PF_MSIX_EN 0x130144UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF MSIX enable status. shadow of PCI config register
5306 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF MSIX function mask status. shadow of PCI config register. 0 - unmasked; 1 - masked
5308 #define IGU_REG_PCI_VF_MSIX_EN 0x13014cUL //ACCESS:RW DataWidth:0x1 SPLIT:64 Description: VF MSIX enable status. shadow of PCI config register
5310 #define IGU_REG_PCI_VF_MSIX_FUNC_MASK 0x130150UL //ACCESS:RW DataWidth:0x1 SPLIT:64 Description: VF MSIX function mask status shadow of PCI config register. 0 - unmasked; 1 - masked
5364 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 0; this will set/clr bit 94 in the aeu 128 bit vector
5365 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 1; this will set/clr bit 95 in the aeu 128 bit vector
5366 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 2; this will set/clr bit 96 in the aeu 128 bit vector
5367 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 3; this will set/clr bit 97 in the aeu 128 bit vector
5368 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 4; this will set/clr bit 98 in the aeu 128 bit vector
5369 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 5; this will set/clr bit 99 in the aeu 128 bit vector
5370 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 6; this will set/clr bit 100 in the aeu 128 bit vector
5371 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 7; this will set/clr bit 101 in the aeu 128 bit vector
5372 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 8; this will set/clr bit 102 in the aeu 128 bit vector
5373 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 9; this will set/clr bit 103 in the aeu 128 bit vector
5374 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 10; this will set/clr bit 104 in the aeu 128 bit vector
5375 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 11; this will set/clr bit 105 in the aeu 128 bit vector
5376 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 12; this will set/clr bit 106 in the aeu 128 bit vector
5377 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 13; this will set/clr bit 107 in the aeu 128 bit vector
5378 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 14; this will set/clr bit 108 in the aeu 128 bit vector
5379 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 15; this will set/clr bit 109 in the aeu 128 bit vector
5380 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 16; this will set/clr bit 110 in the aeu 128 bit vector
5381 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 17; this will set/clr bit 111 in the aeu 128 bit vector
5382 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 18; this will set/clr bit 112 in the aeu 128 bit vector
5383 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04cUL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 19; this will set/clr bit 113 in the aeu 128 bit vector
5384 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 20; this will set/clr bit 114 in the aeu 128 bit vector
5385 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 21; this will set/clr bit 115 in the aeu 128 bit vector
5386 #define MISC_REG_AEU_EVENT_ENABLE 0xa058UL //ACCESS:RW DataWidth:0x1 Description: Event_enable control; when this bit is clear the event enable toward the MCP is masked.
5514 #define MISC_REG_WAIT_P 0xa25cUL //ACCESS:RW DataWidth:0x1 Description: when set to one stops all storms
5516 #define MISC_EMAC0_REG_EMAC0_SHUTDOWN (0x1<<0)
5518 #define MISC_EMAC0_REG_EMAC0_PARITY_MODE (0x1<<1)
5521 #define MISC_EMAC1_REG_EMAC1_SHUTDOWN (0x1<<0)
5523 #define MISC_EMAC1_REG_EMAC1_PARITY_MODE (0x1<<1)
5525 #define MISC_REG_GRC_TIMEOUT_EN 0xa280UL //ACCESS:RW DataWidth:0x1 Description: Setting this bit enables a timer in the GRC block to timeout any access that does not finish within ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is cleared; this timeout is disabled. If this timeout occurs; the GRC shall assert it attention output.
5527 #define MISC_REG_GRC_DBG_EN 0xa288UL //ACCESS:RW DataWidth:0x1 Description: Debug only: enable the debug mux
5540 #define MISC_RINGOSC_REG_CSEM_RINGOSC_ENABLE (0x1<<0)
5542 #define MISC_RINGOSC_REG_CSEM_RINGOSC_SEL0 (0x1<<1)
5544 #define MISC_RINGOSC_REG_CSEM_RINGOSC_SEL1 (0x1<<2)
5546 #define MISC_RINGOSC_REG_XSEM_RINGOSC_ENABLE (0x1<<3)
5548 #define MISC_RINGOSC_REG_XSEM_RINGOSC_SEL0 (0x1<<4)
5550 #define MISC_RINGOSC_REG_XSEM_RINGOSC_SEL1 (0x1<<5)
5552 #define MISC_RINGOSC_REG_TSEM_RINGOSC_ENABLE (0x1<<6)
5554 #define MISC_RINGOSC_REG_TSEM_RINGOSC_SEL0 (0x1<<7)
5556 #define MISC_RINGOSC_REG_TSEM_RINGOSC_SEL1 (0x1<<8)
5558 #define MISC_RINGOSC_REG_USEM_RINGOSC_ENABLE (0x1<<9)
5560 #define MISC_RINGOSC_REG_USEM_RINGOSC_SEL0 (0x1<<10)
5562 #define MISC_RINGOSC_REG_USEM_RINGOSC_SEL1 (0x1<<11)
5570 #define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_0 (0x1<<3)
5572 #define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_1 (0x1<<4)
5574 #define MISC_OTP_CTRL_REG_0_REG_ENABLE_OTP_2 (0x1<<5)
5578 #define MISC_OTP_CTRL_REG_0_REG_USEPINS (0x1<<8)
5580 #define MISC_OTP_CTRL_REG_0_REG_PROGSEL (0x1<<9)
5582 #define MISC_OTP_CTRL_REG_0_REG_PROGSTART (0x1<<10)
5588 #define MISC_OTP_CTRL_REG_0_REG_PBYP (0x1<<19)
5596 #define MISC_OTP_CTRL_REG_0_REG_SADBYP (0x1<<30)
5598 #define MISC_OTP_CTRL_REG_0_REG_DEBUG (0x1<<31)
5633 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
5635 #define MISC_MISC_INT_STS_REG_RSV_ACCESS_ATTN (0x1<<1)
5637 #define MISC_MISC_INT_STS_REG_TIMEOUT_ATTN (0x1<<2)
5639 #define MISC_MISC_INT_STS_REG_GENERIC_SW (0x1<<3)
5641 #define MISC_MISC_INT_STS_REG_RX_LPI_P0 (0x1<<4)
5643 #define MISC_MISC_INT_STS_REG_RX_LPI_P1 (0x1<<5)
5645 #define MISC_MISC_INT_STS_REG_TX_LPI_REQ_P0 (0x1<<6)
5647 #define MISC_MISC_INT_STS_REG_TX_LPI_REQ_P1 (0x1<<7)
5650 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
5652 #define MISC_MISC_INT_STS_CLR_REG_RSV_ACCESS_ATTN (0x1<<1)
5654 #define MISC_MISC_INT_STS_CLR_REG_TIMEOUT_ATTN (0x1<<2)
5656 #define MISC_MISC_INT_STS_CLR_REG_GENERIC_SW (0x1<<3)
5658 #define MISC_MISC_INT_STS_CLR_REG_RX_LPI_P0 (0x1<<4)
5660 #define MISC_MISC_INT_STS_CLR_REG_RX_LPI_P1 (0x1<<5)
5662 #define MISC_MISC_INT_STS_CLR_REG_TX_LPI_REQ_P0 (0x1<<6)
5664 #define MISC_MISC_INT_STS_CLR_REG_TX_LPI_REQ_P1 (0x1<<7)
5667 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
5669 #define MISC_MISC_INT_STS_WR_REG_RSV_ACCESS_ATTN (0x1<<1)
5671 #define MISC_MISC_INT_STS_WR_REG_TIMEOUT_ATTN (0x1<<2)
5673 #define MISC_MISC_INT_STS_WR_REG_GENERIC_SW (0x1<<3)
5675 #define MISC_MISC_INT_STS_WR_REG_RX_LPI_P0 (0x1<<4)
5677 #define MISC_MISC_INT_STS_WR_REG_RX_LPI_P1 (0x1<<5)
5679 #define MISC_MISC_INT_STS_WR_REG_TX_LPI_REQ_P0 (0x1<<6)
5681 #define MISC_MISC_INT_STS_WR_REG_TX_LPI_REQ_P1 (0x1<<7)
5684 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
5686 #define MISC_MISC_INT_MASK_REG_RSV_ACCESS_ATTN (0x1<<1)
5688 #define MISC_MISC_INT_MASK_REG_TIMEOUT_ATTN (0x1<<2)
5690 #define MISC_MISC_INT_MASK_REG_GENERIC_SW (0x1<<3)
5692 #define MISC_MISC_INT_MASK_REG_RX_LPI_P0 (0x1<<4)
5694 #define MISC_MISC_INT_MASK_REG_RX_LPI_P1 (0x1<<5)
5696 #define MISC_MISC_INT_MASK_REG_TX_LPI_REQ_P0 (0x1<<6)
5698 #define MISC_MISC_INT_MASK_REG_TX_LPI_REQ_P1 (0x1<<7)
5700 #define MISC_REG_MISC_PRTY_STS 0xa38cUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
5701 #define MISC_MISC_PRTY_STS_REG_PARITY (0x1<<0)
5703 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
5704 #define MISC_MISC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
5706 #define MISC_REG_MISC_PRTY_STS_WR 0xa394UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
5707 #define MISC_MISC_PRTY_STS_WR_REG_PARITY (0x1<<0)
5709 #define MISC_REG_MISC_PRTY_MASK 0xa398UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
5710 #define MISC_MISC_PRTY_MASK_REG_PARITY (0x1<<0)
5722 #define MISC_REG_LINK_HOLDOFF_SUCCESS 0xa418UL //ACCESS:R DataWidth:0x1 Description: This bit indicates the PCIE link is successfully being held from starting training. Used in conjunction with ~MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ. Global register.
5723 #define MISC_REG_LINK_IN_L23 0xa41cUL //ACCESS:R DataWidth:0x1 Description: When this bit is 1 it indicates that the link is down and PCIE is prepared for operation off of VAUX. Global register.
5724 #define MISC_REG_PCIE_DIS 0xa420UL //ACCESS:R DataWidth:0x1 Description: This bit reports the current state of the PCIE_DIS pin. If this bit is 1 it means that the LOM design has been strapped to support management only. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode. Global register.
5725 #define MISC_REG_VAUX_PRESENT 0xa428UL //ACCESS:R DataWidth:0x1 Description: 0 - VAUX is not present; 1 - VAUX is present. Global register.
5726 #define MISC_REG_ISOLATION_LOGIC 0xa498UL //ACCESS:R DataWidth:0x1 Description: the isolation between Vaux and Vmain read value. Global register.
5727 #define MISC_REG_LCPLL_MISC_LOCK 0xa49cUL //ACCESS:R DataWidth:0x1 Description: lcpll lock signals. 0-unlocked; 1-locked. Global register.
5728 #define MISC_REG_P0_SERDES_PLL_LOCK 0xa4b0UL //ACCESS:R DataWidth:0x1 Description: serdes port 0 pll lock signals. 0-unlocked; 1-locked
5729 #define MISC_REG_P0_XGXS_PLL_LOCK 0xa4b4UL //ACCESS:R DataWidth:0x1 Description: xgxs port 0 pll lock signals. 0-unlocked; 1-locked
5730 #define MISC_REG_P1_SERDES_PLL_LOCK 0xa4b8UL //ACCESS:R DataWidth:0x1 Description: serdes port 1 pll lock signals. 0-unlocked; 1-locked
5731 #define MISC_REG_P1_XGXS_PLL_LOCK 0xa4bcUL //ACCESS:R DataWidth:0x1 Description: xgxs port 1 pll lock signals. 0-unlocked; 1-locked
5739 #define MISC_REG_PCIE_HOT_RESET 0xa618UL //ACCESS:R DataWidth:0x1 Description: If set indicate that the pcie_rst_b was asserted without perst assertion. Global register.
5741 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
5743 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
5745 #define MISC_AEU_GENERAL_MASK_REG_AEU_SYS_KILL_MASK (0x1<<2)
5782 #define MISC_REG_FUNC_HIDE_PIN 0xa718UL //ACCESS:R DataWidth:0x1 Description: Synchronised value of ifmux_misc_func_hide. Global register.
5783 #define MISC_REG_PORT4MODE_EN 0xa750UL //ACCESS:R DataWidth:0x1 Description: Status of 4 port mode enable input pin.
5784 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754UL //ACCESS:R DataWidth:0x1 Description: Status of 4 port mode port swap input pin.
5785 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758UL //ACCESS:R DataWidth:0x1 Description: Status of two port mode path swap input pin.
5786 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75cUL //ACCESS:R DataWidth:0x1 Description: Status of four port mode path swap input pin.
5794 #define MISC_REG_RX_LPI_P0_STAT 0xa8d4UL //ACCESS:RW DataWidth:0x1 Description: local port 0 SERDES is receiving (Rx) LPI status reference value. If local port 0 SERDES is receiving (Rx) LPI status is different from this value the corresponding interrupt is issued.
5795 #define MISC_REG_RX_LPI_P1_STAT 0xa8d8UL //ACCESS:RW DataWidth:0x1 Description: local port 1 SERDES is receiving (Rx) LPI status reference value. If local port 1 SERDES is receiving (Rx) LPI status is different from this value the corresponding interrupt is issued.
5796 #define MISC_REG_TX_LPI_REQ_P0_STAT 0xa8dcUL //ACCESS:RW DataWidth:0x1 Description: local port 0 SERDES should enter (Tx) LPI mode reference value. If local port 0 SERDES should enter (Tx) LPI mode is different from this value the corresponding interrupt is issued.
5797 #define MISC_REG_TX_LPI_REQ_P1_STAT 0xa8e0UL //ACCESS:RW DataWidth:0x1 Description: local port 1 SERDES should enter (Tx) LPI mode reference value. If local port 1 SERDES should enter (Tx) LPI mode is different from this value the corresponding interrupt is issued.
5799 #define MISC_REG_WC0_PLL_LOCK 0xaa20UL //ACCESS:R DataWidth:0x1 Description: WC0 pll lock signals. 0-unlocked; 1-locked.
5800 #define MISC_REG_WC1_PLL_LOCK 0xaa24UL //ACCESS:R DataWidth:0x1 Description: WC1 pll lock signals. 0-unlocked; 1-locked.
5801 #define MISC_REG_WC2_PLL_LOCK 0xaa28UL //ACCESS:R DataWidth:0x1 Description: WC2 pll lock signals. 0-unlocked; 1-locked.
5804 #define MISC_REG_AEU_PRESET_REF 0xa05cUL //ACCESS:RW DataWidth:0x1 Description: The ref value for PERST signal change detection. Default value is 1 (attention on PERST assertion).
5812 #define MISC_REG_PARITY_MODE 0xa26cUL //ACCESS:RW DataWidth:0x1 Description: debug only : parity mode to MCP. Setting this bit changes the parity checking on the RAMs from even to odd parity. Global register.
5814 #define MISC_REG_NIG_WOL_P0 0xa270UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: when set to one indicates WOL is detected by the MCP FW on port 0. this register is multiply per function.
5816 #define MISC_REG_NIG_WOL_P1 0xa274UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: when set to one indicates WOL is detected by the MCP FW on port 1. this register is multiply per function.
5818 #define MISC_REG_UNCOND_ENTER_PLAY_DEAD 0xa28cUL //ACCESS:RW DataWidth:0x1 Description: Writing to this register result with resetting entire chip via the play dead mechanism. Global register.
5820 #define MISC_REG_COND_ENTER_PLAY_DEAD 0xa290UL //ACCESS:RW DataWidth:0x1 Description: Writing to this register result with resetting entire chip via the play dead mechanism if PERST is asserted. Global register.
5834 #define MISC_REG_LINK_HOLDOFF_REQ 0xa2c4UL //ACCESS:RW DataWidth:0x1 Description: This bit is written to a '1' to request that the PCIE link not begin training yet. Software should set this bit; and then check the ~MISC_REGISTERS_LINK_HOLDOFF_SUCCESS.LINK_HOLDOFF_SUCCESS bit. If ~MISC_REGISTERS_LINK_HOLDOFF_SUCCESS.LINK_HOLDOFF_SUCCESS is set; configure the PCIE link and then clear this bit. If ~MISC_REGISTERS_LINK_HOLDOFF_SUCCESS.LINK_HOLDOFF_SUCCESS is not set; the PCIE link has already begun training so it's too late to do any configuration. Global register.
5838 #define MISC_REG_RINGOSC_TOP_0_ENABLE 0xa330UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
5840 #define MISC_REG_RINGOSC_TOP_0_SEL0 0xa334UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
5842 #define MISC_REG_RINGOSC_TOP_0_SEL1 0xa338UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1 . Global register.
5844 #define MISC_REG_RINGOSC_TOP_1_ENABLE 0xa33cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
5846 #define MISC_REG_RINGOSC_TOP_1_SEL0 0xa340UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
5848 #define MISC_REG_RINGOSC_TOP_1_SEL1 0xa344UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
5850 #define MISC_REG_RINGOSC_TOP_2_ENABLE 0xa348UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
5852 #define MISC_REG_RINGOSC_TOP_2_SEL0 0xa34cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
5854 #define MISC_REG_RINGOSC_TOP_2_SEL1 0xa350UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
5856 #define MISC_REG_RINGOSC_TOP_3_ENABLE 0xa354UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
5858 #define MISC_REG_RINGOSC_TOP_3_SEL0 0xa358UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
5860 #define MISC_REG_RINGOSC_TOP_3_SEL1 0xa35cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
5862 #define MISC_REG_RINGOSC_TOP_4_ENABLE 0xa360UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
5864 #define MISC_REG_RINGOSC_TOP_4_SEL0 0xa364UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
5866 #define MISC_REG_RINGOSC_TOP_4_SEL1 0xa368UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
5868 #define MISC_REG_RINGOSC_TOP_5_ENABLE 0xa36cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control enable. Global register.
5870 #define MISC_REG_RINGOSC_TOP_5_SEL0 0xa370UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 0. Global register.
5872 #define MISC_REG_RINGOSC_TOP_5_SEL1 0xa374UL //ACCESS:RW DataWidth:0x1 Description: Debug only. oscillator control select 1. Global register.
5876 #define MISC_REG_PORT_SWAP_EN 0xa39cUL //ACCESS:RW DataWidth:0x1 Description: If set the port swap feature for the GPIOs is controlled by the port swap IO (or by override register). If clear port swap feature for the GPIOs is disabled. Global register.
5878 #define MISC_REG_SMBIO_ENABLE_GLITCH_FILTER 0xa3a4UL //ACCESS:RW DataWidth:0x1 Description: When set enables the deglitching circuit for the SMBus inputs per I2C requirement. Global register.
5902 #define MISC_REG_IPOR_CMD_REG 0xa414UL //ACCESS:RW DataWidth:0x1 Description: Writing this bit as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is not protection for this request and it may cause any current PCI cycle to lock up. Global register. Reset on hard reset.
5904 #define MISC_REG_UNPREPARED 0xa424UL //ACCESS:RW DataWidth:0x1 Description: Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare;1-unprepare. Global register. Reset on hard reset.
5966 #define MISC_REG_PLL_MAIN_MISC_LOCK 0xa4c8UL //ACCESS:R DataWidth:0x1 Description: main pll lock signals. 0-unlocked; 1-locked. Global register. Reset on POR reset.
5978 #define MISC_REG_PLL_STORM_MISC_LOCK 0xa4e0UL //ACCESS:R DataWidth:0x1 Description: storm pll lock signals. 0-unlocked; 1-locked. Global register.
5980 #define MISC_REG_PWR_ATTN 0xa4e4UL //ACCESS:RW DataWidth:0x1 Description: This bit indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Global register. Reset on hard reset.
6038 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610UL //ACCESS:RW DataWidth:0x1 Description: If set a system kill occurred. Reset on POR reset.
6040 #define MISC_REG_AEU_SYS_KILL_BEHAVIOR 0xa614UL //ACCESS:RW DataWidth:0x1 Description: The System Kill enable: 0 - none; 1 - hard reset. Reset on POR reset.
6060 #define MISC_REG_SWREG_MGMT_PWRDN 0xa724UL //ACCESS:RW DataWidth:0x1 Description: SW Regulator power down. Reset on POR reset.
6070 #define MISC_REG_NIG_DBG_VECTOR 0xa74cUL //ACCESS:RW DataWidth:0x1 Description: NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 - NIG1 debug vector is output to IFMUX.
6074 #define MISC_REG_FOUR_PORT_SHARED_MDIO_EN 0xa778UL //ACCESS:RW DataWidth:0x1 Description: When set this will allow any of the four emacs MDIO masters to initiate MDIO transactions to access XGXS0 or the four external GPHYs. Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. Global register.
6076 #define MISC_REG_SEL_DBG_IFMUX_TEST 0xa77cUL //ACCESS:RW DataWidth:0x1 Description: NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by NIG; If 1 - path1 gmii/mii emac debug outputs are selected by NIG. Drives output misc_cnig_sel_dbg_ifmux_test.
6080 #define MISC_REG_UNPREPARED_FW 0xa788UL //ACCESS:RW DataWidth:0x1 Description: Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare;1-unprepare. Global register. Reset on hard reset.
6082 #define MISC_REG_UNPREPARED_DR 0xa78cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Set by the Driver to remember if one or more of the drivers is/are loaded; 0-prepare;1-unprepare. Reset on hard reset.
6084 #define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_P0 0xa7ccUL //ACCESS:W DataWidth:0x1 Description: MCP (FW) Early EEE LPI Exit. When writing 1 indicates that the MCP (FW) expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz.
6086 #define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_P1 0xa7d0UL //ACCESS:W DataWidth:0x1 Description: MCP (FW) Early EEE LPI Exit. When writing 1 indicates that the MCP (FW) expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz.
6088 #define MISC_REG_CPMU_LP_MCP_EARLY_EXIT_L1 0xa7d4UL //ACCESS:W DataWidth:0x1 Description: MCP (FW) Early L1 Exit. When writing 1 indicates that the MCP (FW) expecting activity in the near future and the SM should begin exiting L1 mode. Clock 25MHz. Global register.
6090 #define MISC_REG_ALT_CLK_SELECT 0xa7d8UL //ACCESS:RW DataWidth:0x1 Description: PCI SERDES alternate clock selector. When 0 - 250MHz. When 1 -25MHz. Global register. Reset on hard reset.
6094 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84cUL //ACCESS:RW DataWidth:0x1 Description: FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 25MHz. Reset on hard reset.
6096 #define MISC_REG_CPMU_LP_FW_ENABLE_P1 0xa850UL //ACCESS:RW DataWidth:0x1 Description: FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 25MHz. Reset on hard reset.
6098 #define MISC_REG_CPMU_LP_FW_ENABLE_L1 0xa854UL //ACCESS:RW DataWidth:0x1 Description: FW L1 Enable. When 1 indicates that L1 mode is enabled by FW. When 0 indicates that the L1 mode is disabled by FW. Clock 25MHz. Global register. Reset on hard reset.
6100 #define MISC_REG_CPMU_LP_DR_ENABLE 0xa858UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Driver EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled by driver. When 0 indicates that the EEE LPI mode is disabled by driver. Clock 25MHz. Reset on hard reset.
6102 #define MISC_REG_CPMU_LP_DR_ENABLE_L1 0xa85cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Driver L1 Enable. When 1 indicates that L1 mode is enabled by driver. When 0 indicates that the L1 mode is disabled by driver. Clock 25MHz. Reset on hard reset.
6104 #define MISC_REG_CPMU_LP_DR_EARLY_EXIT 0xa860UL //ACCESS:W DataWidth:0x1 SPLIT:8 Description: Driver Early EEE LPI Exit. When 1 indicates that the driver expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz. Reset on hard reset.
6106 #define MISC_REG_CPMU_LP_DR_EARLY_EXIT_L1 0xa864UL //ACCESS:W DataWidth:0x1 SPLIT:8 Description: Driver Early L1 Exit. When 1 indicates that the driver expecting activity in the near future and the SM should begin exiting L1 mode. Clock 25MHz. Reset on hard reset.
6108 #define MISC_REG_CPMU_LP_FORCE_REQ_P0 0xa868UL //ACCESS:RW DataWidth:0x1 Description: Force EEE LPI. When 1 indicates to force EEE LPI request to the MACs. When 0 the EEE LPI request is defined based on the normal conditions. Clock 25MHz. Reset on hard reset.
6110 #define MISC_REG_CPMU_LP_FORCE_REQ_P1 0xa86cUL //ACCESS:RW DataWidth:0x1 Description: Force EEE LPI. When 1 indicates to force EEE LPI request to the MACs. When 0 the EEE LPI request is defined based on the normal conditions. Clock 25MHz. Reset on hard reset.
6112 #define MISC_REG_CPMU_LP_FORCE_REQ_L1 0xa870UL //ACCESS:RW DataWidth:0x1 Description: Force L1. When 1 indicates to force L1 request to the MACs. When 0 the L1 request is defined based on the normal conditions. Clock 25MHz. Reset on hard reset.
6162 #define MISC_REG_VTMON_HOLD 0xa8e4UL //ACCESS:RW DataWidth:0x1 Description: Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.
6198 #define MISC_REG_PWRWDOG_E40_ACCU_RUN 0xa934UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog. When 0 all registers and states are of power watchdog accu sub-module are reset. Global register. Reset on POR.
6210 #define MISC_REG_PWRWDOG_E40_DONE 0xa94cUL //ACCESS:R DataWidth:0x1 Description: Power watchdog done. Global register. Reset on POR.
6212 #define MISC_REG_PWRWDOG_E40_PWRDN 0xa950UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog power down. 1 - power down; 0 - power up.Global register. Reset on POR.
6224 #define MISC_REG_UMAC0_LPI_TX_DETECT 0xa968UL //ACCESS:R DataWidth:0x1 Description: UMAC0 transmit LPI (Low Power Indication) state. This per port signal is set to 1; whenever the transmit interface is in LPI (Low Power Indication) state and LPI_IDLES are being sent out on the TX Warpcore interface.
6226 #define MISC_REG_UMAC1_LPI_TX_DETECT 0xa96cUL //ACCESS:R DataWidth:0x1 Description: UMAC1 transmit LPI (Low Power Indication) state. This per port signal is set to 1; whenever the transmit interface is in LPI (Low Power Indication) state and LPI_IDLES are being sent out on the TX Warpcore interface.
6260 #define MISC_REG_MDIO_OVERRIDE 0xa9b8UL //ACCESS:RW DataWidth:0x1 Description: MDIO Override. Enables the values on ~misc_registers_mdio_subscription.mdio_subscription to override the hardware mode defined defaults. Global register. Reset on Hard reset.
6264 #define MISC_REG_WC0_CTRL_EXTREMOTEMDIOST 0xa9c0UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO strap (BRCM mode rarely used); tie to 0. Drives output misc_xgxs0_extremotemdiost. Global register.
6268 #define MISC_REG_WC0_CTRL_MD_ST 0xa9c8UL //ACCESS:RW DataWidth:0x1 Description: MDIO State. This bit defines the LSB of the MDIO state machine in the WarpCore. A logic-1 enables clause 22 and a logic-0 enables clause 45. Drives output misc_xgxs0_md_st. Global register.
6272 #define MISC_REG_WC0_CTRL_PLL_BYPASS 0xa9d0UL //ACCESS:RW DataWidth:0x1 Description: Phase-locked-loop Bypass. Drives output misc_xgxs0_pll_bypass. Global register.
6274 #define MISC_REG_WC0_CTRL_REMOTEMDIOEN 0xa9d4UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO enable. Drives output misc_xgxs0_remotemdioen. Global register.
6276 #define MISC_REG_WC1_CTRL_EXTREMOTEMDIOST 0xa9d8UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO strap (BRCM mode rarely used); tie to 0. Drives output misc_xgxs1_extremotemdiost. Global register.
6280 #define MISC_REG_WC1_CTRL_MD_ST 0xa9e0UL //ACCESS:RW DataWidth:0x1 Description: MDIO State. This bit defines the LSB of the MDIO state machine in the WarpCore. A logic-1 enables clause 22 and a logic-0 enables clause 45. Drives output misc_xgxs1_md_st. Global register.
6284 #define MISC_REG_WC1_CTRL_PLL_BYPASS 0xa9e8UL //ACCESS:RW DataWidth:0x1 Description: Phase-locked-loop Bypass. Drives output misc_xgxs1_pll_bypass. Global register.
6286 #define MISC_REG_WC1_CTRL_REMOTEMDIOEN 0xa9ecUL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO enable. Drives output misc_xgxs1_remotemdioen. Global register.
6288 #define MISC_REG_WC2_CTRL_EXTREMOTEMDIOST 0xa9f0UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO strap (BRCM mode rarely used); tie to 0. Drives output misc_serdes0_extremotemdiost. Global register.
6292 #define MISC_REG_WC2_CTRL_MD_ST 0xa9f8UL //ACCESS:RW DataWidth:0x1 Description: MDIO State. This bit defines the LSB of the MDIO state machine in the WarpCore. A logic-1 enables clause 22 and a logic-0 enables clause 45. Drives output misc_serdes0_md_st. Global register.
6296 #define MISC_REG_WC2_CTRL_PLL_BYPASS 0xaa00UL //ACCESS:RW DataWidth:0x1 Description: Phase-locked-loop Bypass. Drives output misc_serdes0_pll_bypass. Global register.
6298 #define MISC_REG_WC2_CTRL_REMOTEMDIOEN 0xaa04UL //ACCESS:RW DataWidth:0x1 Description: Remote MDIO enable. Drives output misc_serdes0_remotemdioen. Global register.
6324 #define MISC_REG_LCPLL_E40_BYPASS 0xaa44UL //ACCESS:RW DataWidth:0x1 Description: LCPLL Bypass. Drives the 156.25mhz applied to the balls of the LCPLL directly to warpcore. This will allow to continue testing of E3. By doing this we can use the same CML traces from LCPLL to Warpcore. Global register. Reset on POR reset.
6340 #define MISC_REG_LCPLL_E40_FREF_SEL 0xaa64UL //ACCESS:RW DataWidth:0x1 Description: LCPLL 25MHz select. If 1 - selects the 25Mhz clock from the balls or the pins of the LCPLL; if 0 - select 25Mhz from OSC. Global register. Reset on POR reset.
6348 #define MISC_REG_LCPLL_E40_PWRDWN 0xaa74UL //ACCESS:RW DataWidth:0x1 Description: LCPLL power down. Global register. Active High. Reset on POR reset.
6350 #define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78UL //ACCESS:RW DataWidth:0x1 Description: LCPLL VCO reset. Global register. Active Low Reset on POR reset.
6352 #define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7cUL //ACCESS:RW DataWidth:0x1 Description: LCPLL post-divider reset. Global register. Active Low Reset on POR reset.
6356 #define MISC_REG_E1HMF_MODE_P0 0xaa84UL //ACCESS:RW DataWidth:0x1 Description: Multifunction for WOL port0. Reset on hard reset.
6358 #define MISC_REG_E1HMF_MODE_P1 0xaa88UL //ACCESS:RW DataWidth:0x1 Description: Multifunction for WOL port1. Reset on hard reset.
6380 #define MISC_REG_E1HMF_MODE 0xa5f8UL //ACCESS:R DataWidth:0x1 Description: multifunction for WOL. If clr WOL signal of the PXP will be send on bit 0 only. Global register. Reset on hard reset.
6382 #define MISC_REG_PLL_STORM_E65_TEST_EN 0xa638UL //ACCESS:R DataWidth:0x1 Description: Test mode output enable (active HIGH): ;0= testout in High-Z state; 1= testout active. Global register.
6394 #define MISC_REG_PLL_STORM_E65_VCO_RNG 0xa650UL //ACCESS:R DataWidth:0x2 Description: VCO range control register: (bit [1] unused at present); x0: [ 800MHz ; 1600 MHz ]; x1: (1600MHz; 3200 MHz]. Global register.
6402 #define MISC_REG_PLL_MAIN_E65_OTP_TEST_EN 0xa660UL //ACCESS:R DataWidth:0x1 Description: Test mode output enable (active HIGH): ;0= testout in High-Z state; 1= testout active. Global register.
6414 #define MISC_REG_PLL_MAIN_E65_OTP_VCO_RNG 0xa678UL //ACCESS:R DataWidth:0x2 Description: VCO range control register: (bit [1] unused at present); x0: [ 800MHz ; 1600 MHz ]; x1: (1600MHz; 3200 MHz]. Global register.
6422 #define MISC_REG_XGXS0_CTRL_MD_ST 0xa730UL //ACCESS:R DataWidth:0x1 Description: 4-port mode control to XGXS; Hardwired ST bits LSB: 0 - clause 45; 1 - clause 22. Drives output misc_xgxs0_mux_md_st. Global register.
6428 #define MISC_REG_TEMPMON_HOLD 0xa744UL //ACCESS:R DataWidth:0x1 Description: Temperature Monitor hold. 0 - update every 400us; 1 - hold on to the value forever.Global register.
6436 #define MISC_REG_XGXS0_CTRL_REMOTEMDIOEN 0xa768UL //ACCESS:R DataWidth:0x1 Description: 4-port mode control to XGXS; remote PHY in-band MDIO. Drives output misc_xgxs0_mux_remotemdioen. Global register.
6438 #define MISC_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0xa76cUL //ACCESS:R DataWidth:0x1 Description: 4-port mode control to XGXS; remote PHY in-band MDIO. When set causes the remote MDIO arbitration to be performed via pins instead of mdio register bits. Drives output misc_xgxs0_mux_extremotemdiost. Global register.
6440 #define MISC_REG_XGXS0_CTRL_PLL_BYPASS 0xa770UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - PLL bypass
6446 #define MISC_REG_VOLTMON_HOLD 0xa798UL //ACCESS:R DataWidth:0x1 Description: Voltage Monitor hold. 0 - update; 1 - hold on to the value forever.Global register.
6450 #define MISC_REG_VOLTMON_SEL 0xa7a0UL //ACCESS:R DataWidth:0x1 Description: Voltage Monitor select. 1 = choose 3.3V; 0 = choose 1.2V.Global register.
6452 #define MISC_REG_PWRWDOG_PWRDN 0xa7a4UL //ACCESS:R DataWidth:0x1 Description: Power watchdog power down. 1 - power down; 0 - power up.Global register.
6462 #define MISC_REG_PWRWDOG_ACCU_RUN 0xa7b8UL //ACCESS:R DataWidth:0x1 Description: Power watchdog. When 0 all registers and states are of power watchdog accu sub-module are reset. Global register.
6470 #define MISC_REG_PWRWDOG_DONE 0xa7c8UL //ACCESS:R DataWidth:0x1 Description: Power watchdog done. Global register.
6488 #define MISC_REG_PLL_MAIN_E65_TEST_EN 0xa820UL //ACCESS:R DataWidth:0x1 Description: Test mode output enable (active HIGH): ;0= testout in High-Z state; 1= testout active. Global register. Reset on POR reset.
6490 #define MISC_REG_PLL_MAIN_E65_VCO_RNG 0xa824UL //ACCESS:R DataWidth:0x2 Description: VCO range control register: (bit [1] unused at present); x0: [ 800MHz ; 1600 MHz ]; x1: (1600MHz; 3200 MHz]. Global register. Reset on POR reset.
6532 #define MSTAT_REG_MSTAT_INT_STS 0x7f0UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
6533 #define MSTAT_MSTAT_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
6535 #define MSTAT_REG_MSTAT_INT_STS_CLR 0x7f4UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
6536 #define MSTAT_MSTAT_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
6538 #define MSTAT_REG_MSTAT_INT_STS_WR 0x7f8UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
6539 #define MSTAT_MSTAT_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
6541 #define MSTAT_REG_MSTAT_INT_MASK 0x7fcUL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
6542 #define MSTAT_MSTAT_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
6618 #define MSTAT_REG_TX_STAT_GTUFL_HI 0x94UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the TX_STAT_GTUFL statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
6630 #define MSTAT_REG_ETHERSTATSCOLLISIONS_HI 0xacUL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the ETHERSTATSCOLLISIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
6634 #define MSTAT_REG_DOT3STATSSINGLECOLLISIONFRAMES_HI 0xb4UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSSINGLECOLLISIONFRAMES statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
6638 #define MSTAT_REG_DOT3STATSMULTIPLECOLLISIONFRAMES_HI 0xbcUL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSMULTIPLECOLLISIONFRAMES statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
6642 #define MSTAT_REG_DOT3STATSDEFERREDTRANSMISSIONS_HI 0xc4UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSDEFERREDTRANSMISSIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
6646 #define MSTAT_REG_DOT3STATSEXCESSIVECOLLISIONS_HI 0xccUL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSEXCESSIVECOLLISIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
6650 #define MSTAT_REG_DOT3STATSLATECOLLISIONS_HI 0xd4UL //ACCESS:RW DataWidth:0x1 Description: This is the upper half of the DOT3STATSLATECOLLISIONS statistic. Write to this register write bits 0:0. Reads from this register will clear bits 0:0.
6906 #define NIG_REG_TIMER0_WRAP 0x10034UL //ACCESS:RW DataWidth:0x1 Description: If 1- ~nig_registers_timer0_counter.timer0_counter counts from 0 after it gets maximum value = ~nig_registers_timer0_max.timer0_max. In this case interrupt to RBC may be sent some times: each time when counter gets maximum. Other way if 0 - it stops to count for port0
6907 #define NIG_REG_TIMER1_WRAP 0x10038UL //ACCESS:RW DataWidth:0x1 Description: If 1- ~nig_registers_timer1_counter.timer1_counter counts from 0 after it gets maximum value ~nig_registers_timer1_max.timer1_max. In this case interrupt to RBC may be sent some times: each time when counter gets maximum. Other way if 0 - it stops to count for port1
6908 #define NIG_REG_EGRESS_DEBUG_PORT 0x10054UL //ACCESS:RW DataWidth:0x1 Description: Port configuration for packet from debug IF. 1 - debug packet for port 1; other way for port 0
6909 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058UL //ACCESS:RW DataWidth:0x1 Description: MAC configuration for packets of port0. If 1 - all packet outputs to emac for port0; other way to bmac for port0
6910 #define NIG_REG_EGRESS_EMAC1_PORT 0x1005cUL //ACCESS:RW DataWidth:0x1 Description: MAC configuration for packets of port1. If 1 - all packet outputs to emac for port1; other way to bmac for port1. This bit is not used in E2 since port 1 only has EMAC.
6911 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060UL //ACCESS:RW DataWidth:0x1 Description: If 1 - egress drain mode for port0 is active. In this mode all packets from PBFare not forwarded to the MAC and just deleted from FIFO. First packet may be deleted from the middle. And last packet will be always deleted till the end.
6912 #define NIG_REG_EGRESS_DRAIN1_MODE 0x10064UL //ACCESS:RW DataWidth:0x1 Description: If 1 - egress drain mode for port1 is active. In this mode all packets from PBFare not forwarded to the MAC and just deleted from FIFO. First packet may be deleted from the middle. And last packet will be always deleted till the end.
6913 #define NIG_REG_EGRESS_PARITY_ERR_MASK 0x10068UL //ACCESS:RW DataWidth:0x1 Description: if 1 - egress drain mode is enabled when parity error input Is active ti NIG. Otherway always masks parity error.
6914 #define NIG_REG_INGRESS_MNG0_PKT_END 0x1006cUL //ACCESS:RW DataWidth:0x1 Description: When UMP and RBC end to work with RX management packet of port0; RBC has to write to this register. It will cause to increment consumer pointer in RX management FIFO and NIG will pass to work with a next packet.
6915 #define NIG_REG_INGRESS_MNG1_PKT_END 0x10070UL //ACCESS:RW DataWidth:0x1 Description: When UMP and RBC end to work with RX management packet of port1; RBC has to write to this register. It will cause to increment consumer pointer in RX management FIFO and NIG will pass to work with a next packet.
6916 #define NIG_REG_LLH0_T_BIT 0x10074UL //ACCESS:RW DataWidth:0x1 Description: t bit for llh0
6917 #define NIG_REG_LLH1_T_BIT 0x10078UL //ACCESS:RW DataWidth:0x1 Description: t bit for llh1
6923 #define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_VERSION_NOT_4 (0x1<<0)
6925 #define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_VERSION_NOT_6 (0x1<<1)
6927 #define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_HEADER_LESS_5 (0x1<<2)
6929 #define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_HEADER_BIG_5 (0x1<<3)
6931 #define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_UDP_LEN (0x1<<4)
6933 #define NIG_LLH0_ERROR_MASK_REG_LLH0_ERROR_MASK_MAC_ERR (0x1<<5)
6936 #define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_VERSION_NOT_4 (0x1<<0)
6938 #define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_VERSION_NOT_6 (0x1<<1)
6940 #define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_HEADER_LESS_5 (0x1<<2)
6942 #define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_HEADER_BIG_5 (0x1<<3)
6944 #define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_UDP_LEN (0x1<<4)
6946 #define NIG_LLH1_ERROR_MASK_REG_LLH1_ERROR_MASK_MAC_ERR (0x1<<5)
6952 #define NIG_REG_PBF_LB_IN_EN 0x100b4UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX PBF LP IF
6953 #define NIG_REG_PRS_REQ_IN_EN 0x100b8UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX parser request IF
6954 #define NIG_REG_INGRESS_UMP0_IN_EN 0x100bcUL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX UMP port 0 request IF
6955 #define NIG_REG_INGRESS_UMP1_IN_EN 0x100c0UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX UMP port 1 request IF
6956 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX BRB1 pause port 0 IF
6957 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX BRB1 pause port 1 IF
6958 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100ccUL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX PBF user packet from IF0
6959 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX PBF user packet from IF1
6960 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX UMP management packet port0 IF
6961 #define NIG_REG_EGRESS_UMP1_IN_EN 0x100d8UL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX UMP management packet port1 IF
6962 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dcUL //ACCESS:RW DataWidth:0x1 Description: Input enable for TX Debug packet
6963 #define NIG_REG_XCM0_OUT_EN 0x100f0UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX_XCM0 IF
6964 #define NIG_REG_XCM1_OUT_EN 0x100f4UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX_XCM1 IF
6965 #define NIG_REG_BRB0_OUT_EN 0x100f8UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX BRB1 port0 IF
6966 #define NIG_REG_BRB1_OUT_EN 0x100fcUL //ACCESS:RW DataWidth:0x1 Description: output enable for RX BRB1 port1 IF
6967 #define NIG_REG_BRB_LB_OUT_EN 0x10100UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX BRB1 LP IF
6968 #define NIG_REG_PRS_EOP_OUT_EN 0x10104UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX parser descriptor IF
6969 #define NIG_REG_INGRESS_UMP0_OUT_EN 0x10108UL //ACCESS:RW DataWidth:0x1 Description: output enable for RX UMP port 0 response IF
6970 #define NIG_REG_INGRESS_UMP1_OUT_EN 0x1010cUL //ACCESS:RW DataWidth:0x1 Description: output enable for RX UMP port 1 response IF
6971 #define NIG_REG_LLH0_ACPI_UPON_MGMT 0x10128UL //ACCESS:RW DataWidth:0x1 Description: for llh0 : 1 = if match on both WoL & mangement - set power_on; 0 - if match on both WoL & mangement - do not set power_on
6972 #define NIG_REG_LLH1_ACPI_UPON_MGMT 0x1012cUL //ACCESS:RW DataWidth:0x1 Description: for llh1 : 1 = if match on both WoL & mangement - set power_on; 0 - if match on both WoL & mangement - do not set power_on
6974 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
6976 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_MAC_FRAME (0x1<<1)
6978 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_LLFC (0x1<<2)
6981 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
6983 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_MAC_FRAME (0x1<<1)
6985 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_LLFC (0x1<<2)
7005 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4
7006 #define NIG_REG_LLH0_IPV4_IPV6_1 0x1020cUL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_1.llh0_dest_ip_1. 0 - IPv6; 1-IPv4
7007 #define NIG_REG_LLH0_IPV4_IPV6_2 0x10210UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_2.llh0_dest_ip_2. 0 - IPv6; 1-IPv4
7019 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_BRCST (0x1<<0)
7021 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MLCST (0x1<<1)
7023 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UNCST (0x1<<2)
7025 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC0 (0x1<<3)
7027 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC1 (0x1<<4)
7029 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_MAC2 (0x1<<5)
7031 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_ARP (0x1<<6)
7033 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP0 (0x1<<7)
7035 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP1 (0x1<<8)
7037 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_IP2 (0x1<<9)
7039 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_U_SRC (0x1<<10)
7041 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_T_SRC (0x1<<11)
7043 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_RMCP (0x1<<12)
7045 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_DHCP (0x1<<13)
7047 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_U_DST (0x1<<14)
7049 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP0 (0x1<<15)
7051 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP1 (0x1<<16)
7053 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_UDP2 (0x1<<17)
7055 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NTBS_T_DST (0x1<<18)
7057 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP0 (0x1<<19)
7059 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP1 (0x1<<20)
7061 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_TCP2 (0x1<<21)
7063 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID0 (0x1<<22)
7065 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID1 (0x1<<23)
7067 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN_ID2 (0x1<<24)
7069 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_VLAN (0x1<<25)
7071 #define NIG_LLH0_MCP_MASK_REG_LLH0_MCP_MASK_NO_VLAN (0x1<<26)
7074 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_BRCST (0x1<<0)
7076 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MLCST (0x1<<1)
7078 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UNCST (0x1<<2)
7080 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC0 (0x1<<3)
7082 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC1 (0x1<<4)
7084 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_MAC2 (0x1<<5)
7086 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_ARP (0x1<<6)
7088 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP0 (0x1<<7)
7090 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP1 (0x1<<8)
7092 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_IP2 (0x1<<9)
7094 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_U_SRC (0x1<<10)
7096 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_T_SRC (0x1<<11)
7098 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_RMCP (0x1<<12)
7100 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_DHCP (0x1<<13)
7102 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_U_DST (0x1<<14)
7104 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP0 (0x1<<15)
7106 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP1 (0x1<<16)
7108 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_UDP2 (0x1<<17)
7110 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NTBS_T_DST (0x1<<18)
7112 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP0 (0x1<<19)
7114 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP1 (0x1<<20)
7116 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_TCP2 (0x1<<21)
7118 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID0 (0x1<<22)
7120 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID1 (0x1<<23)
7122 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN_ID2 (0x1<<24)
7124 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_VLAN (0x1<<25)
7126 #define NIG_LLH1_MCP_MASK_REG_LLH1_MCP_MASK_NO_VLAN (0x1<<26)
7129 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
7131 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
7133 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
7135 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
7137 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
7139 #define NIG_LLH0_BRB1_DRV_MASK_REG_P0_LLH_BRB1_DRV_MASK_ALLMLCST (0x1<<5)
7142 #define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_BRCST (0x1<<0)
7144 #define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_MLCST (0x1<<1)
7146 #define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_UNCST (0x1<<2)
7148 #define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_VLAN (0x1<<3)
7150 #define NIG_LLH1_BRB1_DRV_MASK_REG_LLH1_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
7152 #define NIG_LLH1_BRB1_DRV_MASK_REG_P1_LLH_BRB1_DRV_MASK_ALLMLCST (0x1<<5)
7155 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC0 (0x1<<0)
7157 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC1 (0x1<<1)
7159 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_MAC2 (0x1<<2)
7161 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_ARP (0x1<<3)
7163 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP0 (0x1<<4)
7165 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP1 (0x1<<5)
7167 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_IP2 (0x1<<6)
7169 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
7171 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
7173 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_RMCP (0x1<<9)
7175 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_DHCP (0x1<<10)
7177 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
7179 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP0 (0x1<<12)
7181 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP1 (0x1<<13)
7183 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_UDP2 (0x1<<14)
7185 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
7187 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP0 (0x1<<16)
7189 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP1 (0x1<<17)
7191 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_TCP2 (0x1<<18)
7193 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID0 (0x1<<19)
7195 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID1 (0x1<<20)
7197 #define NIG_LLH0_BRB1_MCP_MASK_REG_LLH0_BRB1_MCP_MASK_VLAN_ID2 (0x1<<21)
7200 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC0 (0x1<<0)
7202 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC1 (0x1<<1)
7204 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_MAC2 (0x1<<2)
7206 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_ARP (0x1<<3)
7208 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP0 (0x1<<4)
7210 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP1 (0x1<<5)
7212 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_IP2 (0x1<<6)
7214 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
7216 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
7218 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_RMCP (0x1<<9)
7220 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_DHCP (0x1<<10)
7222 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
7224 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP0 (0x1<<12)
7226 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP1 (0x1<<13)
7228 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_UDP2 (0x1<<14)
7230 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
7232 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP0 (0x1<<16)
7234 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP1 (0x1<<17)
7236 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_TCP2 (0x1<<18)
7238 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID0 (0x1<<19)
7240 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID1 (0x1<<20)
7242 #define NIG_LLH1_BRB1_MCP_MASK_REG_LLH1_BRB1_MCP_MASK_VLAN_ID2 (0x1<<21)
7244 #define NIG_REG_LLH0_ACPI_VLAN_STRIP 0x10254UL //ACCESS:RW DataWidth:0x1 Description: Remove VLAN before calculating ACPI pattern. This bit is replaced by llh_acpi_tag_rm in E2.
7245 #define NIG_REG_LLH1_ACPI_VLAN_STRIP 0x10258UL //ACCESS:RW DataWidth:0x1 Description: remove VLAN before calculating ACPI pattern.
7246 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025cUL //ACCESS:RW DataWidth:0x1 Description: send to BRB1 if no match on any of RMP rules.
7265 #define NIG_REG_LLH1_IPV4_IPV6_0 0x102a8UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4
7266 #define NIG_REG_LLH1_IPV4_IPV6_1 0x102acUL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_1.llh0_dest_ip_1. 0 - IPv6; 1-IPv4
7267 #define NIG_REG_LLH1_IPV4_IPV6_2 0x102b0UL //ACCESS:RW DataWidth:0x1 Description: Determine the IP version to look for in ~nig_registers_llh0_dest_ip_2.llh0_dest_ip_2. 0 - IPv6; 1-IPv4
7278 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dcUL //ACCESS:RW DataWidth:0x1 Description: send to BRB1 if no match on any of RMP rules.
7281 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8UL //ACCESS:RW DataWidth:0x1 Description: Port0: If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit ~nig_registers_ led_control_traffic_p0.led_control_traffic_p0 and bit ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0
7282 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P1 0x102fcUL //ACCESS:RW DataWidth:0x1 Description: Port1: If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit ~nig_registers_led_control_traffic_p1.led_control_traffic_p1 and bit ~nig_registers_led_control_blink_traffic_p1.led_control_blink_traffic_p1.
7283 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300UL //ACCESS:RW DataWidth:0x1 Description: Port0: If set along with the led_control_override_trafic_p0 bit; turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also set; the LED will blink with blink rate specified in ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 fields.
7284 #define NIG_REG_LED_CONTROL_TRAFFIC_P1 0x10304UL //ACCESS:RW DataWidth:0x1 Description: Port1: If set along with the ~nig_registers_led_control_override_trafic_p0.led_control_override_trafic_p0 bit; turns on the Traffic LED. If the ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 bit is also set; the LED will blink with blink rate specified in ~nig_registers_led_control_blink_rate_p1.led_control_blink_rate_p1 and ~nig_registers_led_control_blink_rate_ena_p1.led_control_blink_rate_ena_p1 fields.
7285 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308UL //ACCESS:RW DataWidth:0x1 Description: Port0: If set along with the ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED bit; the Traffic LED will blink with the blink rate specified in ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 fields.
7286 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P1 0x1030cUL //ACCESS:RW DataWidth:0x1 Description: Port1: If set along with the ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED bit; the Traffic LED will blink with the blink rate specified in ~nig_registers_led_control_blink_rate_p1.led_control_blink_rate_p1 and ~nig_registers_led_control_blink_rate_ena_p1. led_control_blink_rate_ena_p1 fields.
7289 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318UL //ACCESS:RW DataWidth:0x1 Description: Port0: This bit is set to enable the use of the ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field defined below. If this bit is cleared; then the blink rate will be about 8Hz.
7290 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P1 0x1031cUL //ACCESS:RW DataWidth:0x1 Description: Port1: This bit is set to enable the use of the ~nig_registers_led_control_blink_rate_p1.led_control_blink_rate_p1 field defined below. If this bit is cleared; then the blink rate will be about 8Hz.
7291 #define NIG_REG_LED_10G_P0 0x10320UL //ACCESS:RW DataWidth:0x1 Description: led 10g for port 0
7292 #define NIG_REG_LED_10G_P1 0x10324UL //ACCESS:RW DataWidth:0x1 Description: led 10g for port 1
7294 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
7296 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_COMPLETE (0x1<<1)
7298 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_CFG_CHANGE (0x1<<2)
7300 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_STATUS (0x1<<3)
7302 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_LINK_CHANGE (0x1<<4)
7304 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_ATTN (0x1<<5)
7306 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MAC_CRS (0x1<<6)
7308 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_AUTONEG_COMPLETE (0x1<<7)
7310 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_FIBER_RXACT (0x1<<8)
7312 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
7314 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_MR_PAGE_RX (0x1<<10)
7316 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_AN_COMPLETE (0x1<<11)
7318 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_CL73_MR_PAGE_RX (0x1<<12)
7320 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_RX_SIGDET (0x1<<13)
7322 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_REMOTEMDIOREQ (0x1<<14)
7324 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
7326 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_AUTONEG_COMPLETE (0x1<<16)
7328 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_FIBER_RXACT (0x1<<17)
7332 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MR_PAGE_RX (0x1<<22)
7334 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_AN_COMPLETE (0x1<<23)
7336 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_CL73_MR_PAGE_RX (0x1<<24)
7338 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_RX_SIGDET (0x1<<25)
7340 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_MAC_CRS (0x1<<26)
7343 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_INT (0x1<<0)
7345 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_MI_COMPLETE (0x1<<1)
7347 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_CFG_CHANGE (0x1<<2)
7349 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_STATUS (0x1<<3)
7351 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_LINK_CHANGE (0x1<<4)
7353 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_EMAC1_MISC_ATTN (0x1<<5)
7355 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MAC_CRS (0x1<<6)
7357 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_AUTONEG_COMPLETE (0x1<<7)
7359 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_FIBER_RXACT (0x1<<8)
7361 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_LINK_STATUS (0x1<<9)
7363 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_MR_PAGE_RX (0x1<<10)
7365 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_AN_COMPLETE (0x1<<11)
7367 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_CL73_MR_PAGE_RX (0x1<<12)
7369 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_SERDES1_RX_SIGDET (0x1<<13)
7371 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_REMOTEMDIOREQ (0x1<<14)
7373 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_LINK10G (0x1<<15)
7375 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_AUTONEG_COMPLETE (0x1<<16)
7377 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_FIBER_RXACT (0x1<<17)
7381 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MR_PAGE_RX (0x1<<22)
7383 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_AN_COMPLETE (0x1<<23)
7385 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_CL73_MR_PAGE_RX (0x1<<24)
7387 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_RX_SIGDET (0x1<<25)
7389 #define NIG_STATUS_INTERRUPT_PORT1_REG_STATUS_XGXS1_MAC_CRS (0x1<<26)
7392 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
7394 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_COMPLETE (0x1<<1)
7396 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_CFG_CHANGE (0x1<<2)
7398 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_LINK_STATUS (0x1<<3)
7400 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_LINK_CHANGE (0x1<<4)
7402 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_ATTN (0x1<<5)
7404 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_MAC_CRS (0x1<<6)
7406 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_AUTONEG_COMPLETE (0x1<<7)
7408 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_FIBER_RXACT (0x1<<8)
7410 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
7412 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_MR_PAGE_RX (0x1<<10)
7414 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_CL73_AN_COMPLETE (0x1<<11)
7416 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_CL73_MR_PAGE_RX (0x1<<12)
7418 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_RX_SIGDET (0x1<<13)
7420 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_REMOTEMDIOREQ (0x1<<14)
7422 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
7424 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_AUTONEG_COMPLETE (0x1<<16)
7426 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_FIBER_RXACT (0x1<<17)
7430 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_MR_PAGE_RX (0x1<<22)
7432 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_CL73_AN_COMPLETE (0x1<<23)
7434 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_CL73_MR_PAGE_RX (0x1<<24)
7436 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_RX_SIGDET (0x1<<25)
7438 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_MAC_CRS (0x1<<26)
7441 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_MI_INT (0x1<<0)
7443 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_MI_COMPLETE (0x1<<1)
7445 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_CFG_CHANGE (0x1<<2)
7447 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_LINK_STATUS (0x1<<3)
7449 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_LINK_CHANGE (0x1<<4)
7451 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_EMAC1_MISC_ATTN (0x1<<5)
7453 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_MAC_CRS (0x1<<6)
7455 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_AUTONEG_COMPLETE (0x1<<7)
7457 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_FIBER_RXACT (0x1<<8)
7459 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_LINK_STATUS (0x1<<9)
7461 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_MR_PAGE_RX (0x1<<10)
7463 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_CL73_AN_COMPLETE (0x1<<11)
7465 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_CL73_MR_PAGE_RX (0x1<<12)
7467 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_SERDES1_RX_SIGDET (0x1<<13)
7469 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_REMOTEMDIOREQ (0x1<<14)
7471 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_LINK10G (0x1<<15)
7473 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_AUTONEG_COMPLETE (0x1<<16)
7475 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_FIBER_RXACT (0x1<<17)
7479 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_MR_PAGE_RX (0x1<<22)
7481 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_CL73_AN_COMPLETE (0x1<<23)
7483 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_CL73_MR_PAGE_RX (0x1<<24)
7485 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_RX_SIGDET (0x1<<25)
7487 #define NIG_MASK_INTERRUPT_PORT1_REG_MASK_XGXS1_MAC_CRS (0x1<<26)
7492 #define NIG_REG_PORT_SWAP 0x10394UL //ACCESS:RW DataWidth:0x1 Description: Value of this register will be transmitted to port swap when ~nig_registers_strap_override.strap_override =1
7493 #define NIG_REG_STRAP_OVERRIDE 0x10398UL //ACCESS:RW DataWidth:0x1 Description: port swap mux selection. If this register equal to 0 then port swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then ort swap is equal to ~nig_registers_port_swap.port_swap
7494 #define NIG_REG_SEL_DBG_IFMUX_TEST 0x1039cUL //ACCESS:RW DataWidth:0x1 Description: selection to mux from dbg block for output to ifmux.
7496 #define NIG_REG_SEL_MUX_DBG_VECTOR_NUM 0x103a4UL //ACCESS:RW DataWidth:0x1 Description: If 0 - selection of vector: from port 0; 1 - from port 1
7500 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
7502 #define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
7504 #define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
7506 #define NIG_NIG_INT_STS_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
7508 #define NIG_NIG_INT_STS_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
7510 #define NIG_NIG_INT_STS_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
7512 #define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
7514 #define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
7516 #define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
7518 #define NIG_NIG_INT_STS_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
7520 #define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
7522 #define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
7524 #define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
7526 #define NIG_NIG_INT_STS_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
7528 #define NIG_NIG_INT_STS_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
7530 #define NIG_NIG_INT_STS_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
7532 #define NIG_NIG_INT_STS_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
7534 #define NIG_NIG_INT_STS_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
7536 #define NIG_NIG_INT_STS_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
7538 #define NIG_NIG_INT_STS_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
7540 #define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
7542 #define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
7544 #define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
7546 #define NIG_NIG_INT_STS_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
7548 #define NIG_NIG_INT_STS_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
7550 #define NIG_NIG_INT_STS_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
7552 #define NIG_NIG_INT_STS_0_REG_TIMER0_MAX_INT (0x1<<26)
7554 #define NIG_NIG_INT_STS_0_REG_TIMER1_MAX_INT (0x1<<27)
7556 #define NIG_NIG_INT_STS_0_REG_LLH0_FIFO_ERROR (0x1<<28)
7558 #define NIG_NIG_INT_STS_0_REG_LLH1_FIFO_ERROR (0x1<<29)
7560 #define NIG_NIG_INT_STS_0_REG_LLFC0_POP_ERROR (0x1<<30)
7562 #define NIG_NIG_INT_STS_0_REG_LLFC1_POP_ERROR (0x1<<31)
7565 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
7567 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
7569 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
7571 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
7573 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
7575 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
7577 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
7579 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
7581 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
7583 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
7585 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
7587 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
7589 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
7591 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
7593 #define NIG_NIG_INT_STS_CLR_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
7595 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
7597 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
7599 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
7601 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
7603 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
7605 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
7607 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
7609 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
7611 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
7613 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
7615 #define NIG_NIG_INT_STS_CLR_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
7617 #define NIG_NIG_INT_STS_CLR_0_REG_TIMER0_MAX_INT (0x1<<26)
7619 #define NIG_NIG_INT_STS_CLR_0_REG_TIMER1_MAX_INT (0x1<<27)
7621 #define NIG_NIG_INT_STS_CLR_0_REG_LLH0_FIFO_ERROR (0x1<<28)
7623 #define NIG_NIG_INT_STS_CLR_0_REG_LLH1_FIFO_ERROR (0x1<<29)
7625 #define NIG_NIG_INT_STS_CLR_0_REG_LLFC0_POP_ERROR (0x1<<30)
7627 #define NIG_NIG_INT_STS_CLR_0_REG_LLFC1_POP_ERROR (0x1<<31)
7630 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
7632 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
7634 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
7636 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
7638 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
7640 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
7642 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
7644 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
7646 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
7648 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
7650 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
7652 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
7654 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
7656 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
7658 #define NIG_NIG_INT_STS_WR_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
7660 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
7662 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
7664 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
7666 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
7668 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
7670 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
7672 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
7674 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
7676 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
7678 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
7680 #define NIG_NIG_INT_STS_WR_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
7682 #define NIG_NIG_INT_STS_WR_0_REG_TIMER0_MAX_INT (0x1<<26)
7684 #define NIG_NIG_INT_STS_WR_0_REG_TIMER1_MAX_INT (0x1<<27)
7686 #define NIG_NIG_INT_STS_WR_0_REG_LLH0_FIFO_ERROR (0x1<<28)
7688 #define NIG_NIG_INT_STS_WR_0_REG_LLH1_FIFO_ERROR (0x1<<29)
7690 #define NIG_NIG_INT_STS_WR_0_REG_LLFC0_POP_ERROR (0x1<<30)
7692 #define NIG_NIG_INT_STS_WR_0_REG_LLFC1_POP_ERROR (0x1<<31)
7695 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
7697 #define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_PORT0_ERROR (0x1<<1)
7699 #define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_PORT1_ERROR (0x1<<2)
7701 #define NIG_NIG_INT_MASK_0_REG_INGRESS_EOP_LB_ERROR (0x1<<3)
7703 #define NIG_NIG_INT_MASK_0_REG_INGRESS_RMP0_DSCR_FIFO_ERROR (0x1<<4)
7705 #define NIG_NIG_INT_MASK_0_REG_INGRESS_RMP1_DSCR_FIFO_ERROR (0x1<<5)
7707 #define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC0_ERROR (0x1<<6)
7709 #define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC1_ERROR (0x1<<7)
7711 #define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC0_REGS_ERROR (0x1<<8)
7713 #define NIG_NIG_INT_MASK_0_REG_INGRESS_BMAC1_REGS_ERROR (0x1<<9)
7715 #define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC0_POP_ERROR (0x1<<10)
7717 #define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC1_POP_ERROR (0x1<<11)
7719 #define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC0_PUSH_ERROR (0x1<<12)
7721 #define NIG_NIG_INT_MASK_0_REG_INGRESS_EMAC1_PUSH_ERROR (0x1<<13)
7723 #define NIG_NIG_INT_MASK_0_REG_INGRESS_LB_PBF_DELAY_ERROR (0x1<<14)
7725 #define NIG_NIG_INT_MASK_0_REG_EGRESS_MNG0_FIFO_ERROR (0x1<<15)
7727 #define NIG_NIG_INT_MASK_0_REG_EGRESS_MNG1_FIFO_ERROR (0x1<<16)
7729 #define NIG_NIG_INT_MASK_0_REG_EGRESS_DEBUG_FIFO_ERROR (0x1<<17)
7731 #define NIG_NIG_INT_MASK_0_REG_EGRESS_DELAY0_ERROR (0x1<<18)
7733 #define NIG_NIG_INT_MASK_0_REG_EGRESS_DELAY1_ERROR (0x1<<19)
7735 #define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC0_PUSH_ERROR (0x1<<20)
7737 #define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC1_PUSH_ERROR (0x1<<21)
7739 #define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC0_POP_ERROR (0x1<<22)
7741 #define NIG_NIG_INT_MASK_0_REG_EGRESS_EMAC1_POP_ERROR (0x1<<23)
7743 #define NIG_NIG_INT_MASK_0_REG_EGRESS_BMAC0_ERROR (0x1<<24)
7745 #define NIG_NIG_INT_MASK_0_REG_EGRESS_BMAC1_ERROR (0x1<<25)
7747 #define NIG_NIG_INT_MASK_0_REG_TIMER0_MAX_INT (0x1<<26)
7749 #define NIG_NIG_INT_MASK_0_REG_TIMER1_MAX_INT (0x1<<27)
7751 #define NIG_NIG_INT_MASK_0_REG_LLH0_FIFO_ERROR (0x1<<28)
7753 #define NIG_NIG_INT_MASK_0_REG_LLH1_FIFO_ERROR (0x1<<29)
7755 #define NIG_NIG_INT_MASK_0_REG_LLFC0_POP_ERROR (0x1<<30)
7757 #define NIG_NIG_INT_MASK_0_REG_LLFC1_POP_ERROR (0x1<<31)
7760 #define NIG_NIG_INT_STS_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
7762 #define NIG_NIG_INT_STS_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
7764 #define NIG_NIG_INT_STS_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
7766 #define NIG_NIG_INT_STS_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
7768 #define NIG_NIG_INT_STS_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
7770 #define NIG_NIG_INT_STS_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
7772 #define NIG_NIG_INT_STS_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
7774 #define NIG_NIG_INT_STS_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
7776 #define NIG_NIG_INT_STS_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
7778 #define NIG_NIG_INT_STS_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
7780 #define NIG_NIG_INT_STS_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
7782 #define NIG_NIG_INT_STS_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
7784 #define NIG_NIG_INT_STS_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
7786 #define NIG_NIG_INT_STS_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
7788 #define NIG_NIG_INT_STS_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
7790 #define NIG_NIG_INT_STS_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
7792 #define NIG_NIG_INT_STS_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
7794 #define NIG_NIG_INT_STS_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
7796 #define NIG_NIG_INT_STS_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
7798 #define NIG_NIG_INT_STS_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
7800 #define NIG_NIG_INT_STS_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
7802 #define NIG_NIG_INT_STS_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
7804 #define NIG_NIG_INT_STS_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
7806 #define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
7808 #define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
7810 #define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
7812 #define NIG_NIG_INT_STS_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
7815 #define NIG_NIG_INT_STS_CLR_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
7817 #define NIG_NIG_INT_STS_CLR_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
7819 #define NIG_NIG_INT_STS_CLR_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
7821 #define NIG_NIG_INT_STS_CLR_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
7823 #define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
7825 #define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
7827 #define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
7829 #define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
7831 #define NIG_NIG_INT_STS_CLR_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
7833 #define NIG_NIG_INT_STS_CLR_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
7835 #define NIG_NIG_INT_STS_CLR_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
7837 #define NIG_NIG_INT_STS_CLR_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
7839 #define NIG_NIG_INT_STS_CLR_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
7841 #define NIG_NIG_INT_STS_CLR_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
7843 #define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
7845 #define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
7847 #define NIG_NIG_INT_STS_CLR_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
7849 #define NIG_NIG_INT_STS_CLR_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
7851 #define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
7853 #define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
7855 #define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
7857 #define NIG_NIG_INT_STS_CLR_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
7859 #define NIG_NIG_INT_STS_CLR_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
7861 #define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
7863 #define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
7865 #define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
7867 #define NIG_NIG_INT_STS_CLR_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
7870 #define NIG_NIG_INT_STS_WR_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
7872 #define NIG_NIG_INT_STS_WR_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
7874 #define NIG_NIG_INT_STS_WR_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
7876 #define NIG_NIG_INT_STS_WR_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
7878 #define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
7880 #define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
7882 #define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
7884 #define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
7886 #define NIG_NIG_INT_STS_WR_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
7888 #define NIG_NIG_INT_STS_WR_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
7890 #define NIG_NIG_INT_STS_WR_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
7892 #define NIG_NIG_INT_STS_WR_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
7894 #define NIG_NIG_INT_STS_WR_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
7896 #define NIG_NIG_INT_STS_WR_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
7898 #define NIG_NIG_INT_STS_WR_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
7900 #define NIG_NIG_INT_STS_WR_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
7902 #define NIG_NIG_INT_STS_WR_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
7904 #define NIG_NIG_INT_STS_WR_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
7906 #define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
7908 #define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
7910 #define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
7912 #define NIG_NIG_INT_STS_WR_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
7914 #define NIG_NIG_INT_STS_WR_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
7916 #define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
7918 #define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
7920 #define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
7922 #define NIG_NIG_INT_STS_WR_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
7925 #define NIG_NIG_INT_MASK_1_REG_LLFC0_PUSH_ERROR (0x1<<0)
7927 #define NIG_NIG_INT_MASK_1_REG_LLFC1_PUSH_ERROR (0x1<<1)
7929 #define NIG_NIG_INT_MASK_1_REG_LLH0_MF_ON_AND_NO_OUTER_VLAN (0x1<<2)
7931 #define NIG_NIG_INT_MASK_1_REG_LLH1_MF_ON_AND_NO_OUTER_VLAN (0x1<<3)
7933 #define NIG_NIG_INT_MASK_1_REG_P0_RX_COS0_TIMER_MAX_INT (0x1<<4)
7935 #define NIG_NIG_INT_MASK_1_REG_P0_RX_COS1_TIMER_MAX_INT (0x1<<5)
7937 #define NIG_NIG_INT_MASK_1_REG_P1_RX_COS0_TIMER_MAX_INT (0x1<<6)
7939 #define NIG_NIG_INT_MASK_1_REG_P1_RX_COS1_TIMER_MAX_INT (0x1<<7)
7941 #define NIG_NIG_INT_MASK_1_REG_P0_TX_MNG_HOST_FIFO_ERROR (0x1<<8)
7943 #define NIG_NIG_INT_MASK_1_REG_P1_TX_MNG_HOST_FIFO_ERROR (0x1<<9)
7945 #define NIG_NIG_INT_MASK_1_REG_P0_HBUF_DSCR_FIFO_ERROR (0x1<<10)
7947 #define NIG_NIG_INT_MASK_1_REG_P1_HBUF_DSCR_FIFO_ERROR (0x1<<11)
7949 #define NIG_NIG_INT_MASK_1_REG_P0_TLLH_FIFO_ERROR (0x1<<12)
7951 #define NIG_NIG_INT_MASK_1_REG_P1_TLLH_FIFO_ERROR (0x1<<13)
7953 #define NIG_NIG_INT_MASK_1_REG_P0_RX_MACFIFO_ERROR (0x1<<14)
7955 #define NIG_NIG_INT_MASK_1_REG_P1_RX_MACFIFO_ERROR (0x1<<15)
7957 #define NIG_NIG_INT_MASK_1_REG_P0_TX_MACFIFO_ERROR (0x1<<16)
7959 #define NIG_NIG_INT_MASK_1_REG_P1_TX_MACFIFO_ERROR (0x1<<17)
7961 #define NIG_NIG_INT_MASK_1_REG_P0_RX_COS2_TIMER_MAX_INT (0x1<<18)
7963 #define NIG_NIG_INT_MASK_1_REG_P0_RX_COS3_TIMER_MAX_INT (0x1<<19)
7965 #define NIG_NIG_INT_MASK_1_REG_P0_RX_COS4_TIMER_MAX_INT (0x1<<20)
7967 #define NIG_NIG_INT_MASK_1_REG_P0_RX_COS5_TIMER_MAX_INT (0x1<<21)
7969 #define NIG_NIG_INT_MASK_1_REG_P1_RX_COS2_TIMER_MAX_INT (0x1<<22)
7971 #define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY2_ERROR (0x1<<23)
7973 #define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY3_ERROR (0x1<<24)
7975 #define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY4_ERROR (0x1<<25)
7977 #define NIG_NIG_INT_MASK_1_REG_EGRESS_DELAY5_ERROR (0x1<<26)
7986 #define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_OUTER_VLAN (0x1<<0)
7988 #define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_NO_OUTER_VLAN (0x1<<1)
7990 #define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_OUTER_VLAN_ID (0x1<<2)
7992 #define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_MAC3 (0x1<<3)
7994 #define NIG_LLH0_MCP_MASK_MF_REG_LLH0_MCP_MASK_IPV6_MLCST (0x1<<4)
7996 #define NIG_LLH0_MCP_MASK_MF_REG_P0_LLH_MCP_MASK_PF_OUTER_VLAN (0x1<<5)
7999 #define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_OUTER_VLAN (0x1<<0)
8001 #define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_NO_OUTER_VLAN (0x1<<1)
8003 #define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_OUTER_VLAN_ID (0x1<<2)
8005 #define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_MAC3 (0x1<<3)
8007 #define NIG_LLH1_MCP_MASK_MF_REG_LLH1_MCP_MASK_IPV6_MLCST (0x1<<4)
8009 #define NIG_LLH1_MCP_MASK_MF_REG_P1_LLH_MCP_MASK_PF_OUTER_VLAN (0x1<<5)
8011 #define NIG_REG_LLH_MF_MODE 0x16024UL //ACCESS:RW DataWidth:0x1 Description: When this bit is set; the LLH will classify the packet before sending it to the BRB or calculating WoL on it. This bit is applicable to both ports 0 and 1 for E2. This bit only controls port 0 in E3.
8021 #define NIG_LLH0_BRB1_DRV_MASK_MF_REG_LLH0_BRB1_DRV_MASK_OUTER_VLAN (0x1<<0)
8023 #define NIG_LLH0_BRB1_DRV_MASK_MF_REG_LLH0_BRB1_DRV_MASK_NO_OUTER_VLAN (0x1<<1)
8025 #define NIG_LLH0_BRB1_DRV_MASK_MF_REG_P0_LLH_BRB1_DRV_MASK_PF_OUTER_VLAN (0x1<<2)
8028 #define NIG_LLH1_BRB1_DRV_MASK_MF_REG_LLH1_BRB1_DRV_MASK_OUTER_VLAN (0x1<<0)
8030 #define NIG_LLH1_BRB1_DRV_MASK_MF_REG_LLH1_BRB1_DRV_MASK_NO_OUTER_VLAN (0x1<<1)
8032 #define NIG_LLH1_BRB1_DRV_MASK_MF_REG_P1_LLH_BRB1_DRV_MASK_PF_OUTER_VLAN (0x1<<2)
8035 #define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_MAC3 (0x1<<0)
8037 #define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_OUTER_VLAN_ID (0x1<<1)
8039 #define NIG_LLH0_BRB1_MCP_MASK_MF_REG_LLH0_BRB1_MCP_MASK_IPV6_MLCST (0x1<<2)
8042 #define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_MAC3 (0x1<<0)
8044 #define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_OUTER_VLAN_ID (0x1<<1)
8046 #define NIG_LLH1_BRB1_MCP_MASK_MF_REG_LLH1_BRB1_MCP_MASK_IPV6_MLCST (0x1<<2)
8058 #define NIG_REG_LLH0_MNG_OUTER_VLAN_STRIP 0x16088UL //ACCESS:RW DataWidth:0x1 Description: Remove outer VLAN before sending the packet to the RMP. This configuration is ORed with llh_mng_tag_rm - the new E2 tag removal configuration.
8059 #define NIG_REG_LLH1_MNG_OUTER_VLAN_STRIP 0x1608cUL //ACCESS:RW DataWidth:0x1 Description: remove outer VLAN before sending the packet to the RMP.
8064 #define NIG_REG_PPP_ENABLE_0 0x160b0UL //ACCESS:RW DataWidth:0x1 Description: PPP enable for port0. This register may get 1 only when ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the same port
8065 #define NIG_REG_PPP_ENABLE_1 0x160b4UL //ACCESS:RW DataWidth:0x1 Description: PPP enable for port1. This register may get 1 only when ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the same port
8066 #define NIG_REG_PAUSE_ENABLE_0 0x160c0UL //ACCESS:RW DataWidth:0x1 Description: Pause enable for port0. This register may get 1 only when ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same port
8067 #define NIG_REG_PAUSE_ENABLE_1 0x160c4UL //ACCESS:RW DataWidth:0x1 Description: Pause enable for port1. This register may get 1 only when ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same port
8068 #define NIG_REG_LLFC_OUT_EN_0 0x160c8UL //ACCESS:RW DataWidth:0x1 Description: Output enable of message to LLFC BMAC IF for port0
8069 #define NIG_REG_LLFC_OUT_EN_1 0x160ccUL //ACCESS:RW DataWidth:0x1 Description: Output enable of message to LLFC BMAC IF for port1
8072 #define NIG_REG_LLH_E1HOV_MODE 0x160d8UL //ACCESS:RW DataWidth:0x1 Description: When this bit is set; the LLH will expect all packets to be with outer VLAN. This is not applicable to E2.
8073 #define NIG_REG_PPP_OUT_EN 0x16204UL //ACCESS:RW DataWidth:0x1 Description: Output enable of message to PXP IF
8074 #define NIG_REG_LLFC_ENABLE_0 0x16208UL //ACCESS:RW DataWidth:0x1 Description: SAFC enable for port0. This register may get 1 only when ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same port
8075 #define NIG_REG_LLFC_ENABLE_1 0x1620cUL //ACCESS:RW DataWidth:0x1 Description: SAFC enable for port1. This register may get 1 only when ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same port
8098 #define NIG_REG_P0_RX_COS0_TIMER_WRAP 0x18060UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 0 timer to start over when it reaches the configured maximum time.
8099 #define NIG_REG_P0_RX_COS1_TIMER_WRAP 0x18064UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 1 timer to start over when it reaches the configured maximum time.
8103 #define NIG_REG_P0_HWLLFC_RX_ENABLE 0x18074UL //ACCESS:RW DataWidth:0x1 Description: HW LLFC receive enable bit. Set this bit to enable the HW LLFC/SAFC functionality in the NIG in the RX path. The NIG block determines the XOFF/XON state of each class according to the BigMAC output SAFC signals and the mapping configuration. If a class is in XOFF state then stop the corresponding PBF queue. Other HW flow control modes such as PAUSE and PFC should be disabled when this bit is set.
8104 #define NIG_REG_P0_HWPFC_ENABLE 0x18078UL //ACCESS:RW DataWidth:0x1 Description: HW PFC enable bit. Set this bit to enable the PFC functionality in the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be disabled when this bit is set.
8107 #define NIG_REG_P0_ETHERTYPE0_FOR_XCM_MASK 0x18084UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype0_for_xcm to be forwarded to XCM.
8108 #define NIG_REG_P0_ETHERTYPE1_FOR_XCM_MASK 0x18088UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype1_for_xcm to be forwarded to XCM.
8115 #define NIG_REG_P0_FRAME_CRACKER_SOFT_RST 0x180c0UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
8138 #define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_MAC4 (0x1<<0)
8140 #define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_MAC5 (0x1<<1)
8142 #define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
8144 #define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
8146 #define NIG_P0_LLH_MCP_MASK_A_REG_P0_LLH_MCP_MASK_A_ALLMLCST (0x1<<4)
8149 #define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ARP (0x1<<0)
8151 #define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ICMPV4 (0x1<<1)
8153 #define NIG_P0_LLH_MCP_MASK_B_REG_P0_LLH_MCP_MASK_B_ICMPV6 (0x1<<2)
8155 #define NIG_REG_P0_LLH_MCP_MASK_C_LLDP 0x18140UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching llh_lldp_type to be forwarded to MCP.
8157 #define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_MAC4 (0x1<<0)
8159 #define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_MAC5 (0x1<<1)
8161 #define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
8163 #define NIG_P0_LLH_BRB1_MCP_MASK_A_REG_P0_LLH_BRB1_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
8166 #define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_OUTER_VLAN (0x1<<0)
8168 #define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_NO_OUTER_VLAN (0x1<<1)
8170 #define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_OUTER_VLAN_ID (0x1<<2)
8172 #define NIG_P0_LLH_MCP_OVMASK_B_REG_P0_LLH_MCP_OVMASK_B_PF_OUTER_VLAN (0x1<<3)
8175 #define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_OUTER_VLAN (0x1<<0)
8177 #define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_NO_OUTER_VLAN (0x1<<1)
8179 #define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_OUTER_VLAN_ID (0x1<<2)
8181 #define NIG_P0_LLH_MCP_OVMASK_C_REG_P0_LLH_MCP_OVMASK_C_PF_OUTER_VLAN (0x1<<3)
8184 #define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_MCF (0x1<<0)
8186 #define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_BCN (0x1<<1)
8188 #define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_ETHERTYPE0 (0x1<<2)
8190 #define NIG_P0_XCM_TYPE_VALID_REG_P0_XCM_TYPE_VALID_ETHERTYPE1 (0x1<<3)
8193 #define NIG_REG_EGRESS_DEBUG_PATH 0x18170UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to select the path for sending debug traffic. 0 selects the current path. 1 selects the other path.
8211 #define NIG_REG_P1_RX_COS0_TIMER_WRAP 0x181b8UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 0 timer to start over when it reaches the configured maximum time.
8212 #define NIG_REG_P1_RX_COS1_TIMER_WRAP 0x181bcUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 1 timer to start over when it reaches the configured maximum time.
8216 #define NIG_REG_P1_HWLLFC_RX_ENABLE 0x181ccUL //ACCESS:RW DataWidth:0x1 Description: HW LLFC receive enable bit. Set this bit to enable the HW LLFC/SAFC functionality in the NIG in the RX path. The NIG block determines the XOFF/XON state of each class according to the BigMAC output SAFC signals and the mapping configuration. If a class is in XOFF state then stop the corresponding PBF queue. Other HW flow control modes such as PAUSE and PFC should be disabled when this bit is set.
8217 #define NIG_REG_P1_HWPFC_ENABLE 0x181d0UL //ACCESS:RW DataWidth:0x1 Description: HW PFC enable bit. Set this bit to enable the PFC functionality in the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be disabled when this bit is set.
8220 #define NIG_REG_P1_ETHERTYPE0_FOR_XCM_MASK 0x181dcUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype0_for_xcm to be forwarded to XCM.
8221 #define NIG_REG_P1_ETHERTYPE1_FOR_XCM_MASK 0x181e0UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching ethertype1_for_xcm to be forwarded to XCM.
8233 #define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_MAC4 (0x1<<0)
8235 #define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_MAC5 (0x1<<1)
8237 #define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
8239 #define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
8241 #define NIG_P1_LLH_MCP_MASK_A_REG_P1_LLH_MCP_MASK_A_ALLMLCST (0x1<<4)
8244 #define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ARP (0x1<<0)
8246 #define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ICMPV4 (0x1<<1)
8248 #define NIG_P1_LLH_MCP_MASK_B_REG_P1_LLH_MCP_MASK_B_ICMPV6 (0x1<<2)
8250 #define NIG_REG_P1_LLH_MCP_MASK_C_LLDP 0x18214UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with Ethertype matching llh_lldp_type to be forwarded to MCP.
8252 #define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_MAC4 (0x1<<0)
8254 #define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_MAC5 (0x1<<1)
8256 #define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_ETHERTYPE0 (0x1<<2)
8258 #define NIG_P1_LLH_BRB1_MCP_MASK_A_REG_P1_LLH_BRB1_MCP_MASK_A_ETHERTYPE1 (0x1<<3)
8261 #define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_OUTER_VLAN (0x1<<0)
8263 #define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_NO_OUTER_VLAN (0x1<<1)
8265 #define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_OUTER_VLAN_ID (0x1<<2)
8267 #define NIG_P1_LLH_MCP_OVMASK_B_REG_P1_LLH_MCP_OVMASK_B_PF_OUTER_VLAN (0x1<<3)
8270 #define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_OUTER_VLAN (0x1<<0)
8272 #define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_NO_OUTER_VLAN (0x1<<1)
8274 #define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_OUTER_VLAN_ID (0x1<<2)
8276 #define NIG_P1_LLH_MCP_OVMASK_C_REG_P1_LLH_MCP_OVMASK_C_PF_OUTER_VLAN (0x1<<3)
8278 #define NIG_REG_P1_FRAME_CRACKER_SOFT_RST 0x18224UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
8295 #define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_MCF (0x1<<0)
8297 #define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_BCN (0x1<<1)
8299 #define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_ETHERTYPE0 (0x1<<2)
8301 #define NIG_P1_XCM_TYPE_VALID_REG_P1_XCM_TYPE_VALID_ETHERTYPE1 (0x1<<3)
8305 #define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_XCM_ERROR_MASK (0x1<<0)
8307 #define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_MCP_ERROR_MASK (0x1<<1)
8309 #define NIG_P0_LLH_GLOBAL_ERROR_MASK_REG_P0_LLH_BRB1_ERROR_MASK (0x1<<2)
8313 #define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_XCM_ERROR_MASK (0x1<<0)
8315 #define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_MCP_ERROR_MASK (0x1<<1)
8317 #define NIG_P1_LLH_GLOBAL_ERROR_MASK_REG_P1_LLH_BRB1_ERROR_MASK (0x1<<2)
8323 #define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_PORT_ID_TAG (0x1<<16)
8327 #define NIG_P0_TX_MNG_HOST_CTRL_REG_P0_TX_MNG_HOST_OUTER_VLAN_HEADER_INSERT (0x1<<19)
8335 #define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_PORT_ID_TAG (0x1<<16)
8339 #define NIG_P1_TX_MNG_HOST_CTRL_REG_P1_TX_MNG_HOST_OUTER_VLAN_HEADER_INSERT (0x1<<19)
8343 #define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4UL //ACCESS:RW DataWidth:0x1 Description: MCP-to-host path enable. Set this bit to enable the routing of MCP packets to BRB LB interface to forward the packet to the host. All packets from MCP are forwarded to the network when this bit is cleared - regardless of the configured destination in tx_mng_destination register. When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter for BRB LB interface is bypassed and PBF LB traffic is always selected to send to BRB LB.
8344 #define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8UL //ACCESS:RW DataWidth:0x1 Description: MCP-to-host path enable. Set this bit to enable the routing of MCP packets to BRB LB interface to forward the packet to the host. All packets from MCP are forwarded to the network when this bit is cleared - regardless of the configured destination in tx_mng_destination register.
8345 #define NIG_REG_P0_TX_HOST_MNG_ENABLE 0x1835cUL //ACCESS:RW DataWidth:0x1 Description: Host-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface toward MCP when the criteria for the MCP filters are met. All packets from PBF are forwarded to the network when this bit is cleared.
8347 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_BRCST (0x1<<0)
8349 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MLCST (0x1<<1)
8351 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UNCST (0x1<<2)
8353 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC0 (0x1<<3)
8355 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC1 (0x1<<4)
8357 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC2 (0x1<<5)
8359 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_ARP (0x1<<6)
8361 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP0 (0x1<<7)
8363 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP1 (0x1<<8)
8365 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IP2 (0x1<<9)
8367 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_U_SRC (0x1<<10)
8369 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_T_SRC (0x1<<11)
8371 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_RMCP (0x1<<12)
8373 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_DHCP (0x1<<13)
8375 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_U_DST (0x1<<14)
8377 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP0 (0x1<<15)
8379 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP1 (0x1<<16)
8381 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_UDP2 (0x1<<17)
8383 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NTBS_T_DST (0x1<<18)
8385 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP0 (0x1<<19)
8387 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP1 (0x1<<20)
8389 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_TCP2 (0x1<<21)
8391 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID0 (0x1<<22)
8393 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID1 (0x1<<23)
8395 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN_ID2 (0x1<<24)
8397 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_VLAN (0x1<<25)
8399 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_NO_VLAN (0x1<<26)
8401 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_MAC3 (0x1<<27)
8403 #define NIG_P0_TLLH_MCP_MASK_REG_P0_TLLH_MCP_MASK_IPV6_MLCST (0x1<<28)
8406 #define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_MAC4 (0x1<<0)
8408 #define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_MAC5 (0x1<<1)
8410 #define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ETHERTYPE0 (0x1<<2)
8412 #define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ETHERTYPE1 (0x1<<3)
8414 #define NIG_P0_TLLH_MCP_MASK_EXT_REG_P0_TLLH_MCP_MASK_EXT_ALLMLCST (0x1<<4)
8417 #define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_BRCST (0x1<<0)
8419 #define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_MLCST (0x1<<1)
8421 #define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_UNCST (0x1<<2)
8423 #define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_VLAN (0x1<<3)
8425 #define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_NO_VLAN (0x1<<4)
8427 #define NIG_P0_TLLH_NTWK_DRV_MASK_REG_P0_TLLH_NTWK_DRV_MASK_ALLMLCST (0x1<<5)
8430 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC0 (0x1<<0)
8432 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC1 (0x1<<1)
8434 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC2 (0x1<<2)
8436 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ARP (0x1<<3)
8438 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP0 (0x1<<4)
8440 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP1 (0x1<<5)
8442 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IP2 (0x1<<6)
8444 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
8446 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
8448 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_RMCP (0x1<<9)
8450 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_DHCP (0x1<<10)
8452 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
8454 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP0 (0x1<<12)
8456 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP1 (0x1<<13)
8458 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_UDP2 (0x1<<14)
8460 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
8462 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP0 (0x1<<16)
8464 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP1 (0x1<<17)
8466 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_TCP2 (0x1<<18)
8468 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID0 (0x1<<19)
8470 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID1 (0x1<<20)
8472 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_VLAN_ID2 (0x1<<21)
8474 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC3 (0x1<<22)
8476 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_IPV6_MLCST (0x1<<23)
8478 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC4 (0x1<<24)
8480 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_MAC5 (0x1<<25)
8482 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ETHERTYPE0 (0x1<<26)
8484 #define NIG_P0_TLLH_NTWK_MCP_MASK_REG_P0_TLLH_NTWK_MCP_MASK_ETHERTYPE1 (0x1<<27)
8487 #define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_BRCST (0x1<<0)
8489 #define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_MLCST (0x1<<1)
8491 #define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_UNCST (0x1<<2)
8493 #define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_VLAN (0x1<<3)
8495 #define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_NO_VLAN (0x1<<4)
8497 #define NIG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P0_TLLH_NTWK_DONT_FWD_DRV_MASK_ALLMLCST (0x1<<5)
8500 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC0 (0x1<<0)
8502 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC1 (0x1<<1)
8504 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC2 (0x1<<2)
8506 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ARP (0x1<<3)
8508 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP0 (0x1<<4)
8510 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP1 (0x1<<5)
8512 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IP2 (0x1<<6)
8514 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
8516 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
8518 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_RMCP (0x1<<9)
8520 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_DHCP (0x1<<10)
8522 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
8524 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP0 (0x1<<12)
8526 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP1 (0x1<<13)
8528 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP2 (0x1<<14)
8530 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
8532 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP0 (0x1<<16)
8534 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP1 (0x1<<17)
8536 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP2 (0x1<<18)
8538 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID0 (0x1<<19)
8540 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID1 (0x1<<20)
8542 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID2 (0x1<<21)
8544 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC3 (0x1<<22)
8546 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_IPV6_MLCST (0x1<<23)
8548 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC4 (0x1<<24)
8550 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC5 (0x1<<25)
8552 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE0 (0x1<<26)
8554 #define NIG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P0_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE1 (0x1<<27)
8557 #define NIG_P0_TLLH_GLOBAL_ERROR_MASK_REG_P0_TLLH_MCP_ERROR_MASK (0x1<<0)
8559 #define NIG_P0_TLLH_GLOBAL_ERROR_MASK_REG_P0_TLLH_NTWK_ERROR_MASK (0x1<<1)
8561 #define NIG_REG_P0_HBUF_MEM_RBC_ACCESS 0x1837cUL //ACCESS:RW DataWidth:0x1 Description: Debug only. This bit is for selecting the RX management memory for register read/write access through ingress_mng*_fifo register space. Set to 1 to select the Host-to-BMC buffer (HBUF). Set to 0 to select the MCP RX buffer:w.
8564 #define NIG_REG_P0_TLLH_FRAME_CRACKER_SOFT_RST 0x18388UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
8565 #define NIG_REG_P1_TX_HOST_MNG_ENABLE 0x1838cUL //ACCESS:RW DataWidth:0x1 Description: Host-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface toward MCP when the criteria for the MCP filters are met. All packets from PBF are forwarded to the network when this bit is cleared.
8567 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_BRCST (0x1<<0)
8569 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MLCST (0x1<<1)
8571 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UNCST (0x1<<2)
8573 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC0 (0x1<<3)
8575 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC1 (0x1<<4)
8577 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC2 (0x1<<5)
8579 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_ARP (0x1<<6)
8581 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP0 (0x1<<7)
8583 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP1 (0x1<<8)
8585 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IP2 (0x1<<9)
8587 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_U_SRC (0x1<<10)
8589 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_T_SRC (0x1<<11)
8591 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_RMCP (0x1<<12)
8593 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_DHCP (0x1<<13)
8595 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_U_DST (0x1<<14)
8597 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP0 (0x1<<15)
8599 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP1 (0x1<<16)
8601 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_UDP2 (0x1<<17)
8603 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NTBS_T_DST (0x1<<18)
8605 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP0 (0x1<<19)
8607 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP1 (0x1<<20)
8609 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_TCP2 (0x1<<21)
8611 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID0 (0x1<<22)
8613 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID1 (0x1<<23)
8615 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN_ID2 (0x1<<24)
8617 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_VLAN (0x1<<25)
8619 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_NO_VLAN (0x1<<26)
8621 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_MAC3 (0x1<<27)
8623 #define NIG_P1_TLLH_MCP_MASK_REG_P1_TLLH_MCP_MASK_IPV6_MLCST (0x1<<28)
8626 #define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_MAC4 (0x1<<0)
8628 #define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_MAC5 (0x1<<1)
8630 #define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ETHERTYPE0 (0x1<<2)
8632 #define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ETHERTYPE1 (0x1<<3)
8634 #define NIG_P1_TLLH_MCP_MASK_EXT_REG_P1_TLLH_MCP_MASK_EXT_ALLMLCST (0x1<<4)
8637 #define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_BRCST (0x1<<0)
8639 #define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_MLCST (0x1<<1)
8641 #define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_UNCST (0x1<<2)
8643 #define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_VLAN (0x1<<3)
8645 #define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_NO_VLAN (0x1<<4)
8647 #define NIG_P1_TLLH_NTWK_DRV_MASK_REG_P1_TLLH_NTWK_DRV_MASK_ALLMLCST (0x1<<5)
8650 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC0 (0x1<<0)
8652 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC1 (0x1<<1)
8654 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC2 (0x1<<2)
8656 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ARP (0x1<<3)
8658 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP0 (0x1<<4)
8660 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP1 (0x1<<5)
8662 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IP2 (0x1<<6)
8664 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
8666 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
8668 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_RMCP (0x1<<9)
8670 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_DHCP (0x1<<10)
8672 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
8674 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP0 (0x1<<12)
8676 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP1 (0x1<<13)
8678 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_UDP2 (0x1<<14)
8680 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
8682 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP0 (0x1<<16)
8684 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP1 (0x1<<17)
8686 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_TCP2 (0x1<<18)
8688 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID0 (0x1<<19)
8690 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID1 (0x1<<20)
8692 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_VLAN_ID2 (0x1<<21)
8694 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC3 (0x1<<22)
8696 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_IPV6_MLCST (0x1<<23)
8698 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC4 (0x1<<24)
8700 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_MAC5 (0x1<<25)
8702 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ETHERTYPE0 (0x1<<26)
8704 #define NIG_P1_TLLH_NTWK_MCP_MASK_REG_P1_TLLH_NTWK_MCP_MASK_ETHERTYPE1 (0x1<<27)
8707 #define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_BRCST (0x1<<0)
8709 #define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_MLCST (0x1<<1)
8711 #define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_UNCST (0x1<<2)
8713 #define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_VLAN (0x1<<3)
8715 #define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_NO_VLAN (0x1<<4)
8717 #define NIG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_REG_P1_TLLH_NTWK_DONT_FWD_DRV_MASK_ALLMLCST (0x1<<5)
8720 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC0 (0x1<<0)
8722 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC1 (0x1<<1)
8724 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC2 (0x1<<2)
8726 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ARP (0x1<<3)
8728 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP0 (0x1<<4)
8730 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP1 (0x1<<5)
8732 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IP2 (0x1<<6)
8734 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_SRC (0x1<<7)
8736 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_SRC (0x1<<8)
8738 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_RMCP (0x1<<9)
8740 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_DHCP (0x1<<10)
8742 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_UDP_DST (0x1<<11)
8744 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP0 (0x1<<12)
8746 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP1 (0x1<<13)
8748 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_UDP2 (0x1<<14)
8750 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_NTBIOS_TCP_DST (0x1<<15)
8752 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP0 (0x1<<16)
8754 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP1 (0x1<<17)
8756 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_TCP2 (0x1<<18)
8758 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID0 (0x1<<19)
8760 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID1 (0x1<<20)
8762 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_VLAN_ID2 (0x1<<21)
8764 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC3 (0x1<<22)
8766 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_IPV6_MLCST (0x1<<23)
8768 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC4 (0x1<<24)
8770 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_MAC5 (0x1<<25)
8772 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE0 (0x1<<26)
8774 #define NIG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_REG_P1_TLLH_NTWK_DONT_FWD_MCP_MASK_ETHERTYPE1 (0x1<<27)
8777 #define NIG_P1_TLLH_GLOBAL_ERROR_MASK_REG_P1_TLLH_MCP_ERROR_MASK (0x1<<0)
8779 #define NIG_P1_TLLH_GLOBAL_ERROR_MASK_REG_P1_TLLH_NTWK_ERROR_MASK (0x1<<1)
8781 #define NIG_REG_P1_HBUF_MEM_RBC_ACCESS 0x183acUL //ACCESS:RW DataWidth:0x1 Description: Debug only. This bit is for selecting the RX management memory for register read/write access through ingress_mng*_fifo register space. Set to 1 to select the Host-to-BMC buffer (HBUF). Set to 0 to select the MCP RX buffer:w.
8784 #define NIG_REG_P1_TLLH_FRAME_CRACKER_SOFT_RST 0x183b8UL //ACCESS:RW DataWidth:0x1 Description: Soft reset bit for frame cracker - not expected to be used.
8786 #define NIG_NIG_PRTY_STS_0_REG_PARITY (0x1<<0)
8788 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
8790 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
8792 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
8794 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
8796 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
8798 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
8800 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
8802 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
8804 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
8806 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
8808 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
8810 #define NIG_NIG_PRTY_STS_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
8812 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
8814 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
8816 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
8818 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
8820 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
8822 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
8824 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
8826 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
8828 #define NIG_NIG_PRTY_STS_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
8830 #define NIG_NIG_PRTY_STS_0_REG_LLH0_FIFO_PARITY (0x1<<22)
8832 #define NIG_NIG_PRTY_STS_0_REG_LLH1_FIFO_PARITY (0x1<<23)
8834 #define NIG_NIG_PRTY_STS_0_REG_LLH0_ACPI_PARITY (0x1<<24)
8836 #define NIG_NIG_PRTY_STS_0_REG_LLH1_ACPI_PARITY (0x1<<25)
8838 #define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
8840 #define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
8842 #define NIG_NIG_PRTY_STS_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
8844 #define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
8846 #define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
8848 #define NIG_NIG_PRTY_STS_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
8851 #define NIG_NIG_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
8853 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
8855 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
8857 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
8859 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
8861 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
8863 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
8865 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
8867 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
8869 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
8871 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
8873 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
8875 #define NIG_NIG_PRTY_STS_CLR_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
8877 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
8879 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
8881 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
8883 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
8885 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
8887 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
8889 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
8891 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
8893 #define NIG_NIG_PRTY_STS_CLR_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
8895 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FIFO_PARITY (0x1<<22)
8897 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FIFO_PARITY (0x1<<23)
8899 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_ACPI_PARITY (0x1<<24)
8901 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_ACPI_PARITY (0x1<<25)
8903 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
8905 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
8907 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
8909 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
8911 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
8913 #define NIG_NIG_PRTY_STS_CLR_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
8916 #define NIG_NIG_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
8918 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
8920 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
8922 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
8924 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
8926 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
8928 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
8930 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
8932 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
8934 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
8936 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
8938 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
8940 #define NIG_NIG_PRTY_STS_WR_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
8942 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
8944 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
8946 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
8948 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
8950 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
8952 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
8954 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
8956 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
8958 #define NIG_NIG_PRTY_STS_WR_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
8960 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FIFO_PARITY (0x1<<22)
8962 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FIFO_PARITY (0x1<<23)
8964 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_ACPI_PARITY (0x1<<24)
8966 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_ACPI_PARITY (0x1<<25)
8968 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
8970 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
8972 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
8974 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
8976 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
8978 #define NIG_NIG_PRTY_STS_WR_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
8981 #define NIG_NIG_PRTY_MASK_0_REG_PARITY (0x1<<0)
8983 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP0_PARITY (0x1<<1)
8985 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP1_PARITY (0x1<<2)
8987 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EOP_LB_PARITY (0x1<<3)
8989 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG0_PARITY0 (0x1<<4)
8991 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG1_PARITY0 (0x1<<5)
8993 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG0_PARITY1 (0x1<<6)
8995 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_MNG1_PARITY1 (0x1<<7)
8997 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_BMAC0_PARITY (0x1<<8)
8999 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_BMAC1_PARITY (0x1<<9)
9001 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EMAC0_RDDATA_PARITY (0x1<<10)
9003 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_EMAC1_RDDATA_PARITY (0x1<<11)
9005 #define NIG_NIG_PRTY_MASK_0_REG_INGRESS_LB_PBF_DELAY_PARITY (0x1<<12)
9007 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_MNG0_FIFO_PARITY (0x1<<13)
9009 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_MNG1_FIFO_PARITY (0x1<<14)
9011 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DEBUG_FIFO_PARITY (0x1<<15)
9013 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DELAY0_PARITY (0x1<<16)
9015 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_DELAY1_PARITY (0x1<<17)
9017 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_BMAC0_PARITY (0x1<<18)
9019 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_BMAC1_PARITY (0x1<<19)
9021 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_EMAC0_RDDATA_PARITY (0x1<<20)
9023 #define NIG_NIG_PRTY_MASK_0_REG_EGRESS_EMAC1_RDDATA_PARITY (0x1<<21)
9025 #define NIG_NIG_PRTY_MASK_0_REG_LLH0_FIFO_PARITY (0x1<<22)
9027 #define NIG_NIG_PRTY_MASK_0_REG_LLH1_FIFO_PARITY (0x1<<23)
9029 #define NIG_NIG_PRTY_MASK_0_REG_LLH0_ACPI_PARITY (0x1<<24)
9031 #define NIG_NIG_PRTY_MASK_0_REG_LLH1_ACPI_PARITY (0x1<<25)
9033 #define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC1_ACPI_RF_PARITY_ERR (0x1<<26)
9035 #define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC2_ACPI_RF_PARITY_ERR (0x1<<27)
9037 #define NIG_NIG_PRTY_MASK_0_REG_LLH0_FUNC3_ACPI_RF_PARITY_ERR (0x1<<28)
9039 #define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC1_ACPI_RF_PARITY_ERR (0x1<<29)
9041 #define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC2_ACPI_RF_PARITY_ERR (0x1<<30)
9043 #define NIG_NIG_PRTY_MASK_0_REG_LLH1_FUNC3_ACPI_RF_PARITY_ERR (0x1<<31)
9046 #define NIG_NIG_PRTY_STS_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
9048 #define NIG_NIG_PRTY_STS_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
9050 #define NIG_NIG_PRTY_STS_1_REG_P0_HBUF_PARITY0 (0x1<<2)
9052 #define NIG_NIG_PRTY_STS_1_REG_P0_HBUF_PARITY1 (0x1<<3)
9054 #define NIG_NIG_PRTY_STS_1_REG_P1_HBUF_PARITY0 (0x1<<4)
9056 #define NIG_NIG_PRTY_STS_1_REG_P1_HBUF_PARITY1 (0x1<<5)
9058 #define NIG_NIG_PRTY_STS_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
9060 #define NIG_NIG_PRTY_STS_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
9062 #define NIG_NIG_PRTY_STS_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
9064 #define NIG_NIG_PRTY_STS_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
9066 #define NIG_NIG_PRTY_STS_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
9068 #define NIG_NIG_PRTY_STS_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
9070 #define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
9072 #define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
9074 #define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
9076 #define NIG_NIG_PRTY_STS_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
9079 #define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
9081 #define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
9083 #define NIG_NIG_PRTY_STS_CLR_1_REG_P0_HBUF_PARITY0 (0x1<<2)
9085 #define NIG_NIG_PRTY_STS_CLR_1_REG_P0_HBUF_PARITY1 (0x1<<3)
9087 #define NIG_NIG_PRTY_STS_CLR_1_REG_P1_HBUF_PARITY0 (0x1<<4)
9089 #define NIG_NIG_PRTY_STS_CLR_1_REG_P1_HBUF_PARITY1 (0x1<<5)
9091 #define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
9093 #define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
9095 #define NIG_NIG_PRTY_STS_CLR_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
9097 #define NIG_NIG_PRTY_STS_CLR_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
9099 #define NIG_NIG_PRTY_STS_CLR_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
9101 #define NIG_NIG_PRTY_STS_CLR_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
9103 #define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
9105 #define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
9107 #define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
9109 #define NIG_NIG_PRTY_STS_CLR_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
9112 #define NIG_NIG_PRTY_STS_WR_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
9114 #define NIG_NIG_PRTY_STS_WR_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
9116 #define NIG_NIG_PRTY_STS_WR_1_REG_P0_HBUF_PARITY0 (0x1<<2)
9118 #define NIG_NIG_PRTY_STS_WR_1_REG_P0_HBUF_PARITY1 (0x1<<3)
9120 #define NIG_NIG_PRTY_STS_WR_1_REG_P1_HBUF_PARITY0 (0x1<<4)
9122 #define NIG_NIG_PRTY_STS_WR_1_REG_P1_HBUF_PARITY1 (0x1<<5)
9124 #define NIG_NIG_PRTY_STS_WR_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
9126 #define NIG_NIG_PRTY_STS_WR_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
9128 #define NIG_NIG_PRTY_STS_WR_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
9130 #define NIG_NIG_PRTY_STS_WR_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
9132 #define NIG_NIG_PRTY_STS_WR_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
9134 #define NIG_NIG_PRTY_STS_WR_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
9136 #define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
9138 #define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
9140 #define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
9142 #define NIG_NIG_PRTY_STS_WR_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
9145 #define NIG_NIG_PRTY_MASK_1_REG_P0_TX_MNG_HOST_FIFO_PARITY (0x1<<0)
9147 #define NIG_NIG_PRTY_MASK_1_REG_P1_TX_MNG_HOST_FIFO_PARITY (0x1<<1)
9149 #define NIG_NIG_PRTY_MASK_1_REG_P0_HBUF_PARITY0 (0x1<<2)
9151 #define NIG_NIG_PRTY_MASK_1_REG_P0_HBUF_PARITY1 (0x1<<3)
9153 #define NIG_NIG_PRTY_MASK_1_REG_P1_HBUF_PARITY0 (0x1<<4)
9155 #define NIG_NIG_PRTY_MASK_1_REG_P1_HBUF_PARITY1 (0x1<<5)
9157 #define NIG_NIG_PRTY_MASK_1_REG_P0_TLLH_FIFO_PARITY (0x1<<6)
9159 #define NIG_NIG_PRTY_MASK_1_REG_P1_TLLH_FIFO_PARITY (0x1<<7)
9161 #define NIG_NIG_PRTY_MASK_1_REG_P0_RX_MACFIFO_PARITY (0x1<<8)
9163 #define NIG_NIG_PRTY_MASK_1_REG_P1_RX_MACFIFO_PARITY (0x1<<9)
9165 #define NIG_NIG_PRTY_MASK_1_REG_P0_TX_MACFIFO_PARITY (0x1<<10)
9167 #define NIG_NIG_PRTY_MASK_1_REG_P1_TX_MACFIFO_PARITY (0x1<<11)
9169 #define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY2_PARITY (0x1<<12)
9171 #define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY3_PARITY (0x1<<13)
9173 #define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY4_PARITY (0x1<<14)
9175 #define NIG_NIG_PRTY_MASK_1_REG_EGRESS_DELAY5_PARITY (0x1<<15)
9177 #define NIG_REG_P0_ACPI_MF_GLOBAL_EN 0x18500UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable ACPI pattern matching in multi-function mode even when the per-function outer VLAN matching fails.
9178 #define NIG_REG_P0_LLH_CLS_TYPE_IVLAN 0x18504UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on Inner VLAN instead of the default Outer VLAN.
9179 #define NIG_REG_P0_LLH_CLS_TYPE_PERFUNC_EN 0x18508UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the use of separate classification type configuration for each function. Set to 0 to use registers p*_llh_cls_type_ivlan and llh*_cls_type as the global classification type registers. Set to 1 to use the p*_llh_cls_type_func* registers as the classification type registers - one register for each function.
9184 #define NIG_REG_P1_ACPI_MF_GLOBAL_EN 0x1851cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable ACPI pattern matching in multi-function mode even when the per-function outer VLAN matching fails.
9185 #define NIG_REG_P1_LLH_CLS_TYPE_IVLAN 0x18520UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on Inner VLAN instead of the default Outer VLAN.
9186 #define NIG_REG_P1_LLH_CLS_TYPE_PERFUNC_EN 0x18524UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the use separate classification type configuration for each function. Set to 0 to use registers p*_llh_cls_type_ivlan and llh*_cls_type as the global classification type registers. Set to 1 to use the p*_llh_cls_type_func* registers as the classification type registers - one register for each function.
9191 #define NIG_REG_BRB_LB_CLS_FAIL_SEL 0x18538UL //ACCESS:RW DataWidth:0x1 Description: This bit selects the value for the BRB LB 'classification failed' signal. Clear this bit to select the hard-wired zero value. Set this bit to take the value from bit 11 of the sideband_info[15:0] signal.
9192 #define NIG_REG_P0_LED_20G 0x185a8UL //ACCESS:RW DataWidth:0x1 Description: This bit controls the 20G LED output to CNIG.
9193 #define NIG_REG_P0_MAC_IN_EN 0x185acUL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX MAC interface.
9194 #define NIG_REG_P0_MAC_OUT_EN 0x185b0UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX MAC interface
9195 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX PAUSE signal to the MAC.
9198 #define NIG_REG_P1_MAC_IN_EN 0x185c0UL //ACCESS:RW DataWidth:0x1 Description: Input enable for RX MAC interface.
9199 #define NIG_REG_P1_MAC_OUT_EN 0x185c4UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX MAC interface
9200 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8UL //ACCESS:RW DataWidth:0x1 Description: Output enable for TX PAUSE signal to the MAC.
9204 #define NIG_REG_P0_TXUMP_W_HIGIG 0x18600UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to 1 when HiGig mode is enabled (p*_higig_hdr_size > 0). Clear this bit to 0 when HiGig mode is disabled (p*_higig_hdr_size == 0).
9206 #define NIG_REG_P1_TXUMP_W_HIGIG 0x18608UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to 1 when HiGig mode is enabled (p*_higig_hdr_size > 0). Clear this bit to 0 when HiGig mode is disabled (p*_higig_hdr_size == 0).
9207 #define NIG_REG_LLH1_MF_MODE 0x18614UL //ACCESS:RW DataWidth:0x1 Description: When this bit is set; the LLH will classify the packet before sending it to the BRB or calculating WoL on it. This bit controls port 1 only. The legacy llh_multi_function_mode bit controls port 0.
9224 #define NIG_REG_P0_RX_COS2_TIMER_WRAP 0x186c0UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 2 timer to start over when it reaches the configured maximum time.
9225 #define NIG_REG_P0_RX_COS3_TIMER_WRAP 0x186c4UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 3 timer to start over when it reaches the configured maximum time.
9226 #define NIG_REG_P0_RX_COS4_TIMER_WRAP 0x186c8UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 4 timer to start over when it reaches the configured maximum time.
9227 #define NIG_REG_P0_RX_COS5_TIMER_WRAP 0x186ccUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 5 timer to start over when it reaches the configured maximum time.
9239 #define NIG_REG_P1_RX_COS2_TIMER_WRAP 0x186fcUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable the RX COS 2 timer to start over when it reaches the configured maximum time.
9242 #define NIG_REG_P0_LLH_CLS_TYPE_VNTAG 0x18708UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on VNTAG. Note that classifications based on VLAN and MAC addresses are disabled when VNTAG classification is enabled.
9243 #define NIG_REG_P1_LLH_CLS_TYPE_VNTAG 0x1870cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable VNIC classification based on VNTAG. Note that classifications based on VLAN and MAC addresses are disabled when VNTAG classification is enabled.
9246 #define NIG_REG_P0_LLH_MCP_MASK_C_DST_VIF0 0x18718UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif0 to be forwarded to MCP.
9247 #define NIG_REG_P0_LLH_MCP_MASK_C_DST_VIF1 0x1871cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif1 to be forwarded to MCP.
9250 #define NIG_REG_P1_LLH_MCP_MASK_C_DST_VIF0 0x18728UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif0 to be forwarded to MCP.
9251 #define NIG_REG_P1_LLH_MCP_MASK_C_DST_VIF1 0x1872cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to enable packets with VNTAG matching p*_llh_dst_vif1 to be forwarded to MCP.
9256 #define NIG_REG_P0_LLH_PTP_TO_MCP 0x187a8UL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to MCP.
9257 #define NIG_REG_P0_LLH_PTP_TO_HOST 0x187acUL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to the host.
9262 #define NIG_REG_P1_LLH_PTP_TO_MCP 0x187d0UL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to MCP.
9263 #define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4UL //ACCESS:RW DataWidth:0x1 Description: Set to 1 to enable PTP packets to be forwarded to the host.
9280 #define NIG_REG_P0_PTP_SW_TXTSEN 0x18a48UL //ACCESS:RW DataWidth:0x1 Description: Enable for SW-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indicated through PBF interface for host traffic or through the p*_tx_mng_timestamp_pkt bit for TX management packet. Note that the p*_ptp_en[3] bit has to be set to enable TimeSync on TX side for this mode to work. NIG will extract and capture the sequence ID if one of the version bits is enabled.
9281 #define NIG_REG_P0_TX_MNG_TIMESTAMP_PKT 0x18a4cUL //ACCESS:RW DataWidth:0x1 Description: Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.
9282 #define NIG_REG_P1_PTP_SW_TXTSEN 0x18a50UL //ACCESS:RW DataWidth:0x1 Description: Enable for SW-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indicated through PBF interface for host traffic or through the p*_tx_mng_timestamp_pkt bit for TX management packet. Note that the p*_ptp_en[3] bit has to be set to enable TimeSync on TX side for this mode to work. NIG will extract and capture the sequence ID if one of the version bits is enabled.
9283 #define NIG_REG_P1_TX_MNG_TIMESTAMP_PKT 0x18a54UL //ACCESS:RW DataWidth:0x1 Description: Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.
9284 #define NIG_REG_P0_RX_FC_STATUS_CLEAR 0x18a58UL //ACCESS:RW DataWidth:0x1 Description: Set this bit to clear the current flow control (PFC and LLFC) latched status.
9285 #define NIG_REG_P1_RX_FC_STATUS_CLEAR 0x18a5cUL //ACCESS:RW DataWidth:0x1 Description: Set this bit to clear the current flow control (PFC and LLFC) latched status.
9286 #define NIG_REG_LLH0_ACPI_ENABLE 0x10138UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: When this bit is set ACPI packet recognition will be enabled. This bit must not be enabled until after after all other acpi registers were configured.
9320 #define NIG_REG_LLH1_ACPI_ENABLE 0x1017cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: When this bit is set ACPI packet recognition will be enabled. This bit must not be enabled until after after all other acpi registers were configured.
9354 #define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in DEBUG_FIFO in NIG_TX_DBG
9356 #define NIG_REG_EGRESS_DEBUG_FIFO_FULL 0x1041cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in DEBUG_FIFO in NIG_TX_DBG
9358 #define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT0
9360 #define NIG_REG_EGRESS_DELAY0_FULL 0x10424UL //ACCESS:R DataWidth:0x1 Description: FIFO full in DELAY_PBF_FIFO in NIG_RX_PORT0
9362 #define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT1
9364 #define NIG_REG_EGRESS_DELAY1_FULL 0x1042cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in DELAY_PBF_FIFO in NIG_RX_PORT1
9370 #define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in MNG_FIFO in NIG_TX_PORT0
9372 #define NIG_REG_EGRESS_MNG0_FIFO_FULL 0x10464UL //ACCESS:R DataWidth:0x1 Description: FIFO full in MNG_FIFO in NIG_TX_PORT0
9380 #define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in MNG_FIFO in NIG_TX_PORT1
9382 #define NIG_REG_EGRESS_MNG1_FIFO_FULL 0x10478UL //ACCESS:R DataWidth:0x1 Description: FIFO full in MNG_FIFO in NIG_TX_PORT1
9386 #define NIG_REG_EMAC0_STATUS_MISC_ATTN 0x10480UL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that 1 of the attentions occurred. (enabled inside the ~emac_reg_emac_attention_ena.emac_attention_ena fields).
9388 #define NIG_REG_EMAC0_STATUS_MISC_CFG_CHANGE 0x10484UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This register is not applicable.
9390 #define NIG_REG_EMAC0_STATUS_MISC_LINK_CHANGE 0x10488UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set on each change of the link.
9392 #define NIG_REG_EMAC0_STATUS_MISC_LINK_STATUS 0x1048cUL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that the physical interface is linked (when all is configured correctly).
9394 #define NIG_REG_EMAC0_STATUS_MISC_MI_COMPLETE 0x10490UL //ACCESS:R DataWidth:0x1 Description: status from emac0 This bit is set each time the Management Interface transaction has completed.
9396 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set when MDINT from either the EXT_MDINT pin or from the Copper PHY is driven low. This condition must be cleared in the attached PHY device that is driving the MINT pin.
9398 #define NIG_REG_EMAC1_STATUS_MISC_ATTN 0x10498UL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that 1 of the attentions occurred. (enabled inside the ~emac_reg_emac_attention_ena.emac_attention_ena fields).
9400 #define NIG_REG_EMAC1_STATUS_MISC_CFG_CHANGE 0x1049cUL //ACCESS:R DataWidth:0x1 Description: status from emac0. This register is not applicable.
9402 #define NIG_REG_EMAC1_STATUS_MISC_LINK_CHANGE 0x104a0UL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set on each change of the link.
9404 #define NIG_REG_EMAC1_STATUS_MISC_LINK_STATUS 0x104a4UL //ACCESS:R DataWidth:0x1 Description: status from emac0. A value of 1 indicates that the physical interface is linked (when all is configured correctly).
9406 #define NIG_REG_EMAC1_STATUS_MISC_MI_COMPLETE 0x104a8UL //ACCESS:R DataWidth:0x1 Description: status from emac0 This bit is set each time the Management Interface transaction has completed.
9408 #define NIG_REG_EMAC1_STATUS_MISC_MI_INT 0x104acUL //ACCESS:R DataWidth:0x1 Description: status from emac0. This bit is set when MDINT from either the EXT_MDINT pin or from the Copper PHY is driven low. This condition must be cleared in the attached PHY device that is driving the MINT pin.
9410 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP
9414 #define NIG_REG_INGRESS_EOP_LB_FULL 0x104e8UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EOP descriptor FIFO of LP in NIG_RX_EOP
9416 #define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ecUL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EOP descriptor FIFO of port 0 in NIG_RX_EOP
9420 #define NIG_REG_INGRESS_EOP_PORT0_FULL 0x104f4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EOP descriptor FIFO of port 0 in NIG_RX_EOP
9422 #define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EOP descriptor FIFO of port 1 in NIG_RX_EOP
9426 #define NIG_REG_INGRESS_EOP_PORT1_FULL 0x10500UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EOP descriptor FIFO of port 1 in NIG_RX_EOP
9428 #define NIG_REG_INGRESS_LB_PBF_DELAY_ALM_FULL 0x10504UL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in PBF_DELAY_lb_FIFO in NIG_RX_lb
9430 #define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in PBF_DELAY_lb_FIFO in NIG_RX_lb
9432 #define NIG_REG_INGRESS_LB_PBF_DELAY_FULL 0x1050cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in PBF_DELAY_lb_FIFO in NIG_RX_lb
9450 #define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in dscr_fifo in NIG_RX_RMP block
9452 #define NIG_REG_INGRESS_RMP0_DSCR_FULL 0x10534UL //ACCESS:R DataWidth:0x1 Description: FIFO full in dscr_fifo in NIG_RX_RMP block
9454 #define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in dscr_fifo in NIG_RX_RMP block
9456 #define NIG_REG_INGRESS_RMP1_DSCR_FULL 0x1053cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in dscr_fifo in NIG_RX_RMP block
9458 #define NIG_REG_LED_STATUS_ACTIVE_P0 0x10540UL //ACCESS:R DataWidth:0x1 Description: status of led active for port0
9460 #define NIG_REG_LED_STATUS_ACTIVE_P1 0x10544UL //ACCESS:R DataWidth:0x1 Description: status of led active for port1
9462 #define NIG_REG_LLH0_FIFO_EMPTY 0x10548UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLH port0
9464 #define NIG_REG_LLH0_FIFO_FULL 0x1054cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLH port0
9470 #define NIG_REG_LLH1_FIFO_EMPTY 0x10558UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLH port1
9472 #define NIG_REG_LLH1_FIFO_FULL 0x1055cUL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLH port1
9478 #define NIG_REG_SERDES0_STATUS_AUTONEG_COMPLETE 0x10568UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of CL37 AN complete.
9480 #define NIG_REG_SERDES0_STATUS_CL73_AN_COMPLETE 0x1056cUL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of CL73 AN complete
9482 #define NIG_REG_SERDES0_STATUS_CL73_MR_PAGE_RX 0x10570UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of received CL73 AN page.
9484 #define NIG_REG_SERDES0_STATUS_FIBER_RXACT 0x10574UL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
9486 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of link status
9488 #define NIG_REG_SERDES0_STATUS_MAC_COL 0x1057cUL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
9490 #define NIG_REG_SERDES0_STATUS_MAC_CRS 0x10580UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC carrier sense event.
9492 #define NIG_REG_SERDES0_STATUS_MR_PAGE_RX 0x10584UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of received CL37 AN page.
9494 #define NIG_REG_SERDES0_STATUS_RX_SIGDET 0x10588UL //ACCESS:R DataWidth:0x1 Description: status from serdes0 that inputs to interrupt logic of Rx signal detected on its pins.
9496 #define NIG_REG_SERDES0_STATUS_SPEED_10 0x1058cUL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 10M
9498 #define NIG_REG_SERDES0_STATUS_SPEED_100 0x10590UL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 100M
9500 #define NIG_REG_SERDES0_STATUS_SPEED_1000 0x10594UL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 1G
9502 #define NIG_REG_SERDES0_STATUS_SPEED_1000_KX 0x10598UL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 1G-KX
9504 #define NIG_REG_SERDES0_STATUS_SPEED_2500 0x1059cUL //ACCESS:R DataWidth:0x1 Description: When set SERDES0 link speed is 2.5G
9506 #define NIG_REG_SERDES0_STATUS_TXPLL_LOCK 0x105a0UL //ACCESS:R DataWidth:0x1 Description: when set SERDES0 TX PLL is locked.
9508 #define NIG_REG_SERDES1_STATUS_AUTONEG_COMPLETE 0x105a4UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of CL37 AN complete.
9510 #define NIG_REG_SERDES1_STATUS_CL73_AN_COMPLETE 0x105a8UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of CL73 AN complete.
9512 #define NIG_REG_SERDES1_STATUS_CL73_MR_PAGE_RX 0x105acUL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of received CL73 AN page.
9514 #define NIG_REG_SERDES1_STATUS_FIBER_RXACT 0x105b0UL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
9516 #define NIG_REG_SERDES1_STATUS_LINK_STATUS 0x105b4UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of link status
9518 #define NIG_REG_SERDES1_STATUS_MAC_COL 0x105b8UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
9520 #define NIG_REG_SERDES1_STATUS_MAC_CRS 0x105bcUL //ACCESS:R DataWidth:0x1 Description: Indication of MAC carrier sense event.
9522 #define NIG_REG_SERDES1_STATUS_MR_PAGE_RX 0x105c0UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of received CL37 AN page.
9524 #define NIG_REG_SERDES1_STATUS_RX_SIGDET 0x105c4UL //ACCESS:R DataWidth:0x1 Description: status from serdes1 that inputs to interrupt logic of Rx signal detected on its pins.
9526 #define NIG_REG_SERDES1_STATUS_SPEED_10 0x105c8UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 10M
9528 #define NIG_REG_SERDES1_STATUS_SPEED_100 0x105ccUL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 100M
9530 #define NIG_REG_SERDES1_STATUS_SPEED_1000 0x105d0UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 1G
9532 #define NIG_REG_SERDES1_STATUS_SPEED_1000_KX 0x105d4UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 1G-KX
9534 #define NIG_REG_SERDES1_STATUS_SPEED_2500 0x105d8UL //ACCESS:R DataWidth:0x1 Description: When set SERDES1 link speed is 2.5G
9536 #define NIG_REG_SERDES1_STATUS_TXPLL_LOCK 0x105dcUL //ACCESS:R DataWidth:0x1 Description: when set SERDES1 TX PLL is locked.
9538 #define NIG_REG_SLOW_LLFC0_WR_EMPTY 0x105e0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLFC0 push block
9540 #define NIG_REG_SLOW_LLFC0_WR_FULL 0x105e4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLFC0 push block
9542 #define NIG_REG_SLOW_LLFC1_WR_EMPTY 0x105e8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in LLFC1 push block
9544 #define NIG_REG_SLOW_LLFC1_WR_FULL 0x105ecUL //ACCESS:R DataWidth:0x1 Description: FIFO full in LLFC1 push block
9610 #define NIG_REG_XGXS0_STATUS_AUTONEG_COMPLETE 0x10670UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of CL37 AN complete.
9612 #define NIG_REG_XGXS0_STATUS_CL73_AN_COMPLETE 0x10674UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of CL73 AN complete
9614 #define NIG_REG_XGXS0_STATUS_CL73_MR_PAGE_RX 0x10678UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of received CL73 AN page.
9616 #define NIG_REG_XGXS0_STATUS_FIBER_RXACT 0x1067cUL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
9618 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of link10g.
9622 #define NIG_REG_XGXS0_STATUS_MAC_COL 0x10688UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
9624 #define NIG_REG_XGXS0_STATUS_MAC_CRS 0x1068cUL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of mac crs
9626 #define NIG_REG_XGXS0_STATUS_MR_PAGE_RX 0x10690UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of received CL37 AN page.
9628 #define NIG_REG_XGXS0_STATUS_REMOTEMDIOREQ 0x10694UL //ACCESS:R DataWidth:0x1 Description: status from xgxs port 0 of remote mdio request
9630 #define NIG_REG_XGXS0_STATUS_RX_SIGDET 0x10698UL //ACCESS:R DataWidth:0x1 Description: status from xgxs0 that inputs to interrupt logic of Rx signal detected on its pins.
9632 #define NIG_REG_XGXS0_STATUS_SPEED_10 0x1069cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10M
9634 #define NIG_REG_XGXS0_STATUS_SPEED_100 0x106a0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 100M
9636 #define NIG_REG_XGXS0_STATUS_SPEED_1000 0x106a4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 1G
9638 #define NIG_REG_XGXS0_STATUS_SPEED_10000 0x106a8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10GHiG
9640 #define NIG_REG_XGXS0_STATUS_SPEED_10000_CX4 0x106acUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10G-CX4
9642 #define NIG_REG_XGXS0_STATUS_SPEED_10000_KR 0x106b0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10G-KR
9644 #define NIG_REG_XGXS0_STATUS_SPEED_10000_KX4 0x106b4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 10G-KX4
9646 #define NIG_REG_XGXS0_STATUS_SPEED_1000_KX 0x106b8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 1G-KX
9648 #define NIG_REG_XGXS0_STATUS_SPEED_12000 0x106bcUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 12G
9650 #define NIG_REG_XGXS0_STATUS_SPEED_12500 0x106c0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 12.5GHiG
9652 #define NIG_REG_XGXS0_STATUS_SPEED_13000 0x106c4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 13G
9654 #define NIG_REG_XGXS0_STATUS_SPEED_15000 0x106c8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 15G
9656 #define NIG_REG_XGXS0_STATUS_SPEED_16000 0x106ccUL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 16G
9658 #define NIG_REG_XGXS0_STATUS_SPEED_2500 0x106d0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS0 link speed is 2.5G
9660 #define NIG_REG_XGXS0_STATUS_TXPLL_LOCK 0x106d4UL //ACCESS:R DataWidth:0x1 Description: when set; XGXS0 TX PLL is locked.
9662 #define NIG_REG_XGXS1_STATUS_AUTONEG_COMPLETE 0x106d8UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of CL37 AN complete.
9664 #define NIG_REG_XGXS1_STATUS_CL73_AN_COMPLETE 0x106dcUL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of CL73 AN complete
9666 #define NIG_REG_XGXS1_STATUS_CL73_MR_PAGE_RX 0x106e0UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of received CL73 AN page.
9668 #define NIG_REG_XGXS1_STATUS_FIBER_RXACT 0x106e4UL //ACCESS:R DataWidth:0x1 Description: Detection of Fiber RX activity.
9670 #define NIG_REG_XGXS1_STATUS_LINK10G 0x106e8UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of link10g
9674 #define NIG_REG_XGXS1_STATUS_MAC_COL 0x106f0UL //ACCESS:R DataWidth:0x1 Description: Indication of MAC collision. Valid upon half duplex link.
9676 #define NIG_REG_XGXS1_STATUS_MAC_CRS 0x106f4UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of mac crs
9678 #define NIG_REG_XGXS1_STATUS_MR_PAGE_RX 0x106f8UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of received CL37 AN page.
9680 #define NIG_REG_XGXS1_STATUS_REMOTEMDIOREQ 0x106fcUL //ACCESS:R DataWidth:0x1 Description: status from xgxs port 1 of remote mdio request
9682 #define NIG_REG_XGXS1_STATUS_RX_SIGDET 0x10700UL //ACCESS:R DataWidth:0x1 Description: status from xgxs1 that inputs to interrupt logic of Rx signal detected on its pins.
9684 #define NIG_REG_XGXS1_STATUS_SPEED_10 0x10704UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10M
9686 #define NIG_REG_XGXS1_STATUS_SPEED_100 0x10708UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 100M
9688 #define NIG_REG_XGXS1_STATUS_SPEED_1000 0x1070cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 1G
9690 #define NIG_REG_XGXS1_STATUS_SPEED_10000 0x10710UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10GHiG
9692 #define NIG_REG_XGXS1_STATUS_SPEED_10000_CX4 0x10714UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10G-CX4
9694 #define NIG_REG_XGXS1_STATUS_SPEED_10000_KR 0x10718UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10G-KR
9696 #define NIG_REG_XGXS1_STATUS_SPEED_10000_KX4 0x1071cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 10G-KX4
9698 #define NIG_REG_XGXS1_STATUS_SPEED_1000_KX 0x10720UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 1G-KX
9700 #define NIG_REG_XGXS1_STATUS_SPEED_12000 0x10724UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 12G
9702 #define NIG_REG_XGXS1_STATUS_SPEED_12500 0x10728UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 12.5GHiG
9704 #define NIG_REG_XGXS1_STATUS_SPEED_13000 0x1072cUL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 13G
9706 #define NIG_REG_XGXS1_STATUS_SPEED_15000 0x10730UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 15G
9708 #define NIG_REG_XGXS1_STATUS_SPEED_16000 0x10734UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 16G
9710 #define NIG_REG_XGXS1_STATUS_SPEED_2500 0x10738UL //ACCESS:R DataWidth:0x1 Description: When set XGXS1 link speed is 2.5G
9712 #define NIG_REG_XGXS1_STATUS_TXPLL_LOCK 0x1073cUL //ACCESS:R DataWidth:0x1 Description: when set XGXS0 TX PLL is locked.
9746 #define NIG_REG_LLH0_FUNC_EN 0x160fcUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: VLAN ID enabler. This is the per-function enabler for VNIC classification based on VLAN.
9750 #define NIG_REG_LLH1_FUNC_EN 0x16104UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: VLAN ID enabler. This is the per-function enabler for VNIC classification based on VLAN.
9754 #define NIG_REG_PAUSE_STATUS_BRB1_0 0x16114UL //ACCESS:R DataWidth:0x1 Description: pause status for BRB1 input per port
9756 #define NIG_REG_PAUSE_STATUS_BRB1_1 0x16118UL //ACCESS:R DataWidth:0x1 Description: pause status for BRB1 input per port
9758 #define NIG_REG_PAUSE_STATUS_TSDM_0 0x1611cUL //ACCESS:R DataWidth:0x1 Description: pause status for TSDM input per port
9760 #define NIG_REG_PAUSE_STATUS_TSDM_1 0x16120UL //ACCESS:R DataWidth:0x1 Description: pause status for TSDM input per port
9762 #define NIG_REG_PAUSE_STATUS_USDM_0 0x16124UL //ACCESS:R DataWidth:0x1 Description: pause status for USDM input per port
9764 #define NIG_REG_PAUSE_STATUS_USDM_1 0x16128UL //ACCESS:R DataWidth:0x1 Description: pause status for USDM input per port
9766 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be matched with the VLAN ID for function identification.
9768 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be matched with the VLAN ID for function identification.
9818 #define NIG_REG_P0_TX_MNG_HOST_FIFO_FULL 0x182a4UL //ACCESS:R DataWidth:0x1 Description: FIFO full status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
9820 #define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
9826 #define NIG_REG_P1_TX_MNG_HOST_FIFO_FULL 0x182b4UL //ACCESS:R DataWidth:0x1 Description: FIFO full status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
9828 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty status of the MCP TX FIFO used for storing MCP packets forwarded to the host.
9848 #define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308UL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is empty.
9850 #define NIG_REG_P0_TLLH_FIFO_FULL 0x1830cUL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is full.
9852 #define NIG_REG_P0_TLLH_RSLT_BUF_FULL 0x18310UL //ACCESS:R DataWidth:0x1 Description: TLLH local parsing result buffer is full.
9854 #define NIG_REG_P0_HBUF_DSCR_FULL 0x18314UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is full.
9856 #define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is empty.
9872 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338UL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is empty.
9874 #define NIG_REG_P1_TLLH_FIFO_FULL 0x1833cUL //ACCESS:R DataWidth:0x1 Description: TLLH FIFO is full.
9876 #define NIG_REG_P1_TLLH_RSLT_BUF_FULL 0x18340UL //ACCESS:R DataWidth:0x1 Description: TLLH local parsing result buffer is full.
9878 #define NIG_REG_P1_HBUF_DSCR_FULL 0x18344UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is full.
9880 #define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348UL //ACCESS:R DataWidth:0x1 Description: Indication that HBUF descriptor FIFO is empty.
9890 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be used for VNIC classification. These are the enable bits for addresses 8-15 of the 16 MAC addresses of each function.
9892 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for MAC addresses to be used for VNIC classification. These are the enable bits for addresses 8-15 of the 16 MAC addresses of each function.
9898 #define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570UL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is empty.
9900 #define NIG_REG_P0_RX_MACFIFO_FULL 0x18574UL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is full.
9902 #define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is empty.
9904 #define NIG_REG_P0_TX_MACFIFO_FULL 0x1857cUL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is full.
9906 #define NIG_REG_P0_TX_MACFIFO_ALM_FULL 0x18580UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is almost full.
9910 #define NIG_REG_P0_PAUSE_STATUS_TO_MAC 0x18588UL //ACCESS:R DataWidth:0x1 Description: Current value of PAUSE signal sent to MAC.
9912 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858cUL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is empty.
9914 #define NIG_REG_P1_RX_MACFIFO_FULL 0x18590UL //ACCESS:R DataWidth:0x1 Description: RX FIFO for receiving data from MAC is full.
9916 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is empty.
9918 #define NIG_REG_P1_TX_MACFIFO_FULL 0x18598UL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is full.
9920 #define NIG_REG_P1_TX_MACFIFO_ALM_FULL 0x1859cUL //ACCESS:R DataWidth:0x1 Description: TX FIFO for transmitting data to MAC is almost full.
9924 #define NIG_REG_P1_PAUSE_STATUS_TO_MAC 0x185a4UL //ACCESS:R DataWidth:0x1 Description: Current value of PAUSE signal sent to MAC.
9926 #define NIG_REG_XGXS0_SPEED_10000_LR_SR 0x185d4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-LR/SR.
9928 #define NIG_REG_XGXS0_SPEED_10000_XFI 0x185d8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-XFI.
9930 #define NIG_REG_XGXS0_SPEED_20000_CX4 0x185dcUL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G-CX4.
9932 #define NIG_REG_XGXS0_SPEED_20000 0x185e0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G.
9934 #define NIG_REG_XGXS0_FIBER_TXACT 0x185e4UL //ACCESS:R DataWidth:0x1 Description: Indicate TX traffic activity for the link.
9936 #define NIG_REG_XGXS1_SPEED_10000_LR_SR 0x185e8UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-LR/SR.
9938 #define NIG_REG_XGXS1_SPEED_10000_XFI 0x185ecUL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 10G-XFI.
9940 #define NIG_REG_XGXS1_SPEED_20000_CX4 0x185f0UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G-CX4.
9942 #define NIG_REG_XGXS1_SPEED_20000 0x185f4UL //ACCESS:R DataWidth:0x1 Description: When set XGXS link speed is 20G.
9944 #define NIG_REG_XGXS1_FIBER_TXACT 0x185f8UL //ACCESS:R DataWidth:0x1 Description: Indicate TX traffic activity for the link.
9946 #define NIG_REG_XGXS0_LINK10G_DXGXS1 0x1860cUL //ACCESS:R DataWidth:0x1 Description: A '1' indicates that the second DXGXS has acquired link.
9948 #define NIG_REG_XGXS1_LINK10G_DXGXS1 0x18610UL //ACCESS:R DataWidth:0x1 Description: A '1' indicates that the second DXGXS has acquired link.
9960 #define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862cUL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
9962 #define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
9964 #define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
9966 #define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO empty flag.
9968 #define NIG_REG_EGRESS_DELAY2_FULL 0x1863cUL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
9970 #define NIG_REG_EGRESS_DELAY3_FULL 0x18640UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
9972 #define NIG_REG_EGRESS_DELAY4_FULL 0x18644UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
9974 #define NIG_REG_EGRESS_DELAY5_FULL 0x18648UL //ACCESS:R DataWidth:0x1 Description: PBF FIFO full flag.
10042 #define NIG_REG_P0_LLH_FUNC_DST_VIF0_EN 0x18a08UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
10044 #define NIG_REG_P0_LLH_FUNC_DST_VIF1_EN 0x18a0cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
10046 #define NIG_REG_P1_LLH_FUNC_DST_VIF0_EN 0x18a10UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
10048 #define NIG_REG_P1_LLH_FUNC_DST_VIF1_EN 0x18a14UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable for the destination virtual interface value to be used for VNTAG classification.
10064 #define NIG_REG_P0_LLH_FUNC_VLAN_ID1_EN 0x18a7cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
10066 #define NIG_REG_P0_LLH_FUNC_VLAN_ID2_EN 0x18a80UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
10068 #define NIG_REG_P0_LLH_FUNC_VLAN_ID3_EN 0x18a84UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
10070 #define NIG_REG_P0_LLH_FUNC_VLAN_ID0_NOVLAN 0x18a88UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10072 #define NIG_REG_P0_LLH_FUNC_VLAN_ID1_NOVLAN 0x18a8cUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10074 #define NIG_REG_P0_LLH_FUNC_VLAN_ID2_NOVLAN 0x18a90UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10076 #define NIG_REG_P0_LLH_FUNC_VLAN_ID3_NOVLAN 0x18a94UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10084 #define NIG_REG_P1_LLH_FUNC_VLAN_ID1_EN 0x18aa4UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
10086 #define NIG_REG_P1_LLH_FUNC_VLAN_ID2_EN 0x18aa8UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
10088 #define NIG_REG_P1_LLH_FUNC_VLAN_ID3_EN 0x18aacUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function outer VLAN ID filter enable. Set this bit to 1 to enable the filter. VLAN ID 0 is enabled when llh0/1_func_en is set.
10090 #define NIG_REG_P1_LLH_FUNC_VLAN_ID0_NOVLAN 0x18ab0UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10092 #define NIG_REG_P1_LLH_FUNC_VLAN_ID1_NOVLAN 0x18ab4UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10094 #define NIG_REG_P1_LLH_FUNC_VLAN_ID2_NOVLAN 0x18ab8UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10096 #define NIG_REG_P1_LLH_FUNC_VLAN_ID3_NOVLAN 0x18abcUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Per-function no-VLAN select bit. Set this bit to 1 to select the no-outer-VLAN-present filter. Set this bit to 0 to select the perfect-match-of-outer-VLAN-ID filter.
10100 #define NIG_REG_NIG_EMAC0_EN 0x1003cUL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to EMAC0. When set enables the EMAC0 block.
10102 #define NIG_REG_NIG_EMAC1_EN 0x10040UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to EMAC1. When set enables the EMAC1 block.
10104 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0 to strip the CRC from the ingress packets.
10106 #define NIG_REG_NIG_INGRESS_EMAC1_NO_CRC 0x10048UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC1. When set indicates to the EMAC1 to strip the CRC from the ingress packets.
10108 #define NIG_REG_NIG_EGRESS_EMAC0_NO_CRC 0x1004cUL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0 not to append CRC to the egress packets.
10110 #define NIG_REG_NIG_EGRESS_EMAC1_NO_CRC 0x10050UL //ACCESS:R DataWidth:0x1 Description: Output signal from NIG to TX_EMAC1. When set indicates to the EMAC1 not to append CRC to the egress packets.
10112 #define NIG_REG_EMAC0_IN_EN 0x100a4UL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_EMAC0 IF
10114 #define NIG_REG_EMAC1_IN_EN 0x100a8UL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_EMAC1 IF
10116 #define NIG_REG_BMAC0_IN_EN 0x100acUL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_BMAC0 IF
10118 #define NIG_REG_BMAC1_IN_EN 0x100b0UL //ACCESS:R DataWidth:0x1 Description: Input enable for RX_BMAC1 IF
10120 #define NIG_REG_BMAC0_OUT_EN 0x100e0UL //ACCESS:R DataWidth:0x1 Description: output enable for TX_BMAC0 IF
10122 #define NIG_REG_BMAC1_OUT_EN 0x100e4UL //ACCESS:R DataWidth:0x1 Description: output enable for TX_BMAC1 IF
10124 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8UL //ACCESS:R DataWidth:0x1 Description: output enable for RX_BMAC0_REGS IF
10126 #define NIG_REG_BMAC1_REGS_OUT_EN 0x100ecUL //ACCESS:R DataWidth:0x1 Description: output enable for RX_BMAC1_REGS IF
10128 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110UL //ACCESS:R DataWidth:0x1 Description: output enable for TX BMAC pause port 0 IF
10130 #define NIG_REG_BMAC1_PAUSE_OUT_EN 0x10114UL //ACCESS:R DataWidth:0x1 Description: output enable for TX BMAC pause port 1 IF
10132 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118UL //ACCESS:R DataWidth:0x1 Description: output enable for TX EMAC pause port 0 IF
10134 #define NIG_REG_EMAC1_PAUSE_OUT_EN 0x1011cUL //ACCESS:R DataWidth:0x1 Description: output enable for TX EMAC pause port 1 IF
10136 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120UL //ACCESS:R DataWidth:0x1 Description: Output enable to EMAC0
10138 #define NIG_REG_EGRESS_EMAC1_OUT_EN 0x10124UL //ACCESS:R DataWidth:0x1 Description: Output enable to EMAC1
10140 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0UL //ACCESS:R DataWidth:0x1 Description: selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS
10142 #define NIG_REG_XGXS_SERDES1_MODE_SEL 0x102e4UL //ACCESS:R DataWidth:0x1 Description: selection for port1 for NIG_MUX block : 0 = SerDes; 1 = XGXS
10148 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338UL //ACCESS:R DataWidth:0x1 Description: control to xgxs; 0 - clause 45; 1 - clause 22
10154 #define NIG_REG_XGXS0_CTRL_REMOTEMDIOEN 0x10344UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
10156 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
10158 #define NIG_REG_XGXS0_CTRL_PLL_BYPASS 0x1034cUL //ACCESS:R DataWidth:0x1 Description: control to xgxs - PLL bypass
10160 #define NIG_REG_XGXS1_CTRL_MD_ST 0x10350UL //ACCESS:R DataWidth:0x1 Description: control to xgxs; 0 - clause 45; 1 - clause 22
10166 #define NIG_REG_XGXS1_CTRL_REMOTEMDIOEN 0x1035cUL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
10168 #define NIG_REG_XGXS1_CTRL_EXTREMOTEMDIOST 0x10360UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - remote PHY in-band MDIO
10170 #define NIG_REG_XGXS1_CTRL_PLL_BYPASS 0x10364UL //ACCESS:R DataWidth:0x1 Description: control to xgxs - PLL bypass
10172 #define NIG_REG_SERDES0_CTRL_PLL_BYPASS 0x10368UL //ACCESS:R DataWidth:0x1 Description: control to serdes - PLL bypass
10174 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036cUL //ACCESS:R DataWidth:0x1 Description: control to serdes; 0 - clause 45; 1 - clause 22
10180 #define NIG_REG_SERDES1_CTRL_PLL_BYPASS 0x10378UL //ACCESS:R DataWidth:0x1 Description: control to serdes - PLL bypass
10182 #define NIG_REG_SERDES1_CTRL_MD_ST 0x1037cUL //ACCESS:R DataWidth:0x1 Description: control to serdes; 0 - clause 45; 1 - clause 22
10196 #define NIG_REG_EGRESS_BMAC0_ALM_FULL 0x10400UL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in BMAC_FIFO in NIG_TX_PORT0
10198 #define NIG_REG_EGRESS_BMAC0_EMPTY 0x10404UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_TX_PORT0
10200 #define NIG_REG_EGRESS_BMAC0_FULL 0x10408UL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_TX_PORT0
10202 #define NIG_REG_EGRESS_BMAC1_ALM_FULL 0x1040cUL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in BMAC_FIFO in NIG_TX_PORT1
10204 #define NIG_REG_EGRESS_BMAC1_EMPTY 0x10410UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_TX_PORT1
10206 #define NIG_REG_EGRESS_BMAC1_FULL 0x10414UL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_TX_PORT1
10208 #define NIG_REG_EGRESS_EMAC0_POP_EMPTY 0x10430UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_TX_EMAC0
10210 #define NIG_REG_EGRESS_EMAC0_POP_FULL 0x10434UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_TX_EMAC0
10212 #define NIG_REG_EGRESS_EMAC0_PUSH_ALM_FULL 0x10438UL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in emac_FIFO in NIG_TX_PORT0
10214 #define NIG_REG_EGRESS_EMAC0_PUSH_EMPTY 0x1043cUL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_TX_PORT0
10216 #define NIG_REG_EGRESS_EMAC0_PUSH_FULL 0x10440UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_TX_PORT0
10218 #define NIG_REG_EGRESS_EMAC1_POP_EMPTY 0x10444UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_TX_EMAC1
10220 #define NIG_REG_EGRESS_EMAC1_POP_FULL 0x10448UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_TX_EMAC1
10222 #define NIG_REG_EGRESS_EMAC1_PUSH_ALM_FULL 0x1044cUL //ACCESS:R DataWidth:0x1 Description: FIFO almost full in emac_FIFO in NIG_TX_PORT1
10224 #define NIG_REG_EGRESS_EMAC1_PUSH_EMPTY 0x10450UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_TX_PORT1
10226 #define NIG_REG_EGRESS_EMAC1_PUSH_FULL 0x10454UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_TX_PORT1
10228 #define NIG_REG_INGRESS_BMAC0_EMPTY 0x104b0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_RX_PORT0
10230 #define NIG_REG_INGRESS_BMAC0_FULL 0x104b4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_RX_PORT0
10232 #define NIG_REG_INGRESS_BMAC1_EMPTY 0x104b8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in BMAC_FIFO in NIG_RX_PORT1
10234 #define NIG_REG_INGRESS_BMAC1_FULL 0x104bcUL //ACCESS:R DataWidth:0x1 Description: FIFO full in BMAC_FIFO in NIG_RX_PORT1
10236 #define NIG_REG_INGRESS_EMAC0_POP_EMPTY 0x104c0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_RX_PORT0
10238 #define NIG_REG_INGRESS_EMAC0_POP_FULL 0x104c4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_RX_PORT0
10240 #define NIG_REG_INGRESS_EMAC0_PUSH_EMPTY 0x104c8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_RX_EMAC0
10242 #define NIG_REG_INGRESS_EMAC0_PUSH_FULL 0x104ccUL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_RX_EMAC0
10244 #define NIG_REG_INGRESS_EMAC1_POP_EMPTY 0x104d0UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_POP_FIFO in NIG_RX_PORT1
10246 #define NIG_REG_INGRESS_EMAC1_POP_FULL 0x104d4UL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_POP_FIFO in NIG_RX_PORT1
10248 #define NIG_REG_INGRESS_EMAC1_PUSH_EMPTY 0x104d8UL //ACCESS:R DataWidth:0x1 Description: FIFO empty in EMAC_PUSH_FIFO in NIG_RX_EMAC1
10250 #define NIG_REG_INGRESS_EMAC1_PUSH_FULL 0x104dcUL //ACCESS:R DataWidth:0x1 Description: FIFO full in EMAC_PUSH_FIFO in NIG_RX_EMAC1
10278 #define NIG_REG_EGRESS_OUTER_VLAN_HEADER_INSERT_0 0x16098UL //ACCESS:R DataWidth:0x1 Description: Enable for insert outer vlan header ~egress_outer_vlan_header.egress_outer_vlan_header for port0
10280 #define NIG_REG_EGRESS_OUTER_VLAN_HEADER_INSERT_1 0x1609cUL //ACCESS:R DataWidth:0x1 Description: Enable for insert outer vlan header ~egress_outer_vlan_header.egress_outer_vlan_header for port1
10286 #define NIG_REG_PAUSE_STATUS_BMAC_0 0x1610cUL //ACCESS:R DataWidth:0x1 Description: pause status for BMAC output port
10288 #define NIG_REG_PAUSE_STATUS_BMAC_1 0x16110UL //ACCESS:R DataWidth:0x1 Description: pause status for BMAC output port
10298 #define NIG_REG_PORT4MODE_EN 0x18274UL //ACCESS:R DataWidth:0x1 Description: Set this bit to indicate that this path is used for 4-port mode. Clear this bit to select 2-port mode. This bit is used to decide how th route the two traffic flows from PBF to ports 0 and 1 of this path. In 2-port mode - both flows goes to port 0. In 4-port mode - IF0 flow goes to port 0; IF1 flow goes to port 1.
10342 #define NIG_TSGEN_REG_NIG_TSGEN_INT_STS 0xc0UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
10343 #define NIG_TSGEN_NIG_TSGEN_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
10345 #define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_CLR 0xc4UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
10346 #define NIG_TSGEN_NIG_TSGEN_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
10348 #define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_WR 0xc8UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
10349 #define NIG_TSGEN_NIG_TSGEN_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
10351 #define NIG_TSGEN_REG_NIG_TSGEN_INT_MASK 0xccUL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
10352 #define NIG_TSGEN_NIG_TSGEN_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
10394 #define PBF_REG_INIT 0x140000UL //ACCESS:RW DataWidth:0x1 Description: Init bit. When set the initial credits are copied to the credit registers (except the port credits). Should be set and then reset after the configuration of the block has ended.
10395 #define PBF_REG_CRC_BYTE_REVERSE 0x140028UL //ACCESS:RW DataWidth:0x1 Description: If set the CRC result will be byte reversed before inserting to the packet.
10396 #define PBF_REG_DBG_CMP_SEND_MAX 0x14002cUL //ACCESS:RW DataWidth:0x1 Description: If set then SendMax check for debug will be enabled.
10397 #define PBF_REG_MAC_IF0_ENABLE 0x140030UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 0.
10398 #define PBF_REG_MAC_IF1_ENABLE 0x140034UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 1.
10399 #define PBF_REG_MAC_IF2_ENABLE 0x140038UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 2.
10400 #define PBF_REG_MAC_IF3_ENABLE 0x14003cUL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 3.
10401 #define PBF_REG_MAC_LB_ENABLE 0x140040UL //ACCESS:RW DataWidth:0x1 Description: Enable for the loopback interface.
10403 #define PBF_IF_ENABLE_REG_REG_XSDM_IF_ENABLE (0x1<<0)
10405 #define PBF_IF_ENABLE_REG_REG_PB_REQ_IF_ENABLE (0x1<<1)
10407 #define PBF_IF_ENABLE_REG_REG_DATA_FROM_PB_IF_ENABLE (0x1<<2)
10409 #define PBF_IF_ENABLE_REG_REG_DATA2PB_IF_ENABLE (0x1<<3)
10411 #define PBF_IF_ENABLE_REG_REG_CCM_IF_ENABLE (0x1<<4)
10413 #define PBF_IF_ENABLE_REG_REG_XCM_IF_ENABLE (0x1<<5)
10415 #define PBF_IF_ENABLE_REG_REG_TCM_IF_ENABLE (0x1<<6)
10417 #define PBF_IF_ENABLE_REG_REG_CFC_IF_ENABLE (0x1<<7)
10419 #define PBF_IF_ENABLE_REG_REG_TM_IF_ENABLE (0x1<<8)
10421 #define PBF_IF_ENABLE_REG_REG_XQM_CMD_CREDIT_IF_ENABLE (0x1<<9)
10423 #define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF0_ENABLE (0x1<<10)
10425 #define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF1_ENABLE (0x1<<11)
10427 #define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF2_ENABLE (0x1<<12)
10429 #define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF3_ENABLE (0x1<<13)
10431 #define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF4_ENABLE (0x1<<14)
10433 #define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_IF5_ENABLE (0x1<<15)
10435 #define PBF_IF_ENABLE_REG_REG_XQM_BYTE_CRD_LB_ENABLE (0x1<<16)
10437 #define PBF_IF_ENABLE_REG_REG_PCI_REQ_IF_ENABLE (0x1<<17)
10439 #define PBF_IF_ENABLE_REG_REG_PCI_DATA_IF_ENABLE (0x1<<18)
10441 #define PBF_IF_ENABLE_REG_REG_PCI_INTER_WR_IF_ENABLE (0x1<<19)
10444 #define PBF_SOFT_RESET_REG_PB_OUT_FIFO_INIT (0x1<<0)
10446 #define PBF_SOFT_RESET_REG_HA_CMD_Q_INIT (0x1<<1)
10448 #define PBF_SOFT_RESET_REG_SDM_IN_Q_INIT (0x1<<2)
10450 #define PBF_SOFT_RESET_REG_HEADER_BUFFER_INIT (0x1<<3)
10452 #define PBF_SOFT_RESET_REG_CRACKER_INFO_FIFO_INIT (0x1<<4)
10501 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
10503 #define PBF_PBF_INT_STS_REG_SEQ_CHECK_ERROR (0x1<<1)
10505 #define PBF_PBF_INT_STS_REG_SDM_IN_Q_ERROR (0x1<<2)
10507 #define PBF_PBF_INT_STS_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
10509 #define PBF_PBF_INT_STS_REG_HA_CMD_Q_ERROR (0x1<<4)
10511 #define PBF_PBF_INT_STS_REG_HEADER_BUFFER_ERROR (0x1<<5)
10513 #define PBF_PBF_INT_STS_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
10516 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
10518 #define PBF_PBF_INT_STS_CLR_REG_SEQ_CHECK_ERROR (0x1<<1)
10520 #define PBF_PBF_INT_STS_CLR_REG_SDM_IN_Q_ERROR (0x1<<2)
10522 #define PBF_PBF_INT_STS_CLR_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
10524 #define PBF_PBF_INT_STS_CLR_REG_HA_CMD_Q_ERROR (0x1<<4)
10526 #define PBF_PBF_INT_STS_CLR_REG_HEADER_BUFFER_ERROR (0x1<<5)
10528 #define PBF_PBF_INT_STS_CLR_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
10531 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
10533 #define PBF_PBF_INT_STS_WR_REG_SEQ_CHECK_ERROR (0x1<<1)
10535 #define PBF_PBF_INT_STS_WR_REG_SDM_IN_Q_ERROR (0x1<<2)
10537 #define PBF_PBF_INT_STS_WR_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
10539 #define PBF_PBF_INT_STS_WR_REG_HA_CMD_Q_ERROR (0x1<<4)
10541 #define PBF_PBF_INT_STS_WR_REG_HEADER_BUFFER_ERROR (0x1<<5)
10543 #define PBF_PBF_INT_STS_WR_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
10546 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
10548 #define PBF_PBF_INT_MASK_REG_SEQ_CHECK_ERROR (0x1<<1)
10550 #define PBF_PBF_INT_MASK_REG_SDM_IN_Q_ERROR (0x1<<2)
10552 #define PBF_PBF_INT_MASK_REG_MCU_DATA_FIFO_ERROR (0x1<<3)
10554 #define PBF_PBF_INT_MASK_REG_HA_CMD_Q_ERROR (0x1<<4)
10556 #define PBF_PBF_INT_MASK_REG_HEADER_BUFFER_ERROR (0x1<<5)
10558 #define PBF_PBF_INT_MASK_REG_CRACKER_INFO_FIFO_ERROR (0x1<<6)
10561 #define PBF_PBF_PRTY_STS_REG_PARITY (0x1<<0)
10563 #define PBF_PBF_PRTY_STS_REG_TQ_EVEN (0x1<<1)
10565 #define PBF_PBF_PRTY_STS_REG_TQ_ODD (0x1<<2)
10567 #define PBF_PBF_PRTY_STS_REG_PBUF_A_EVEN (0x1<<3)
10569 #define PBF_PBF_PRTY_STS_REG_PBUF_A_ODD (0x1<<4)
10571 #define PBF_PBF_PRTY_STS_REG_PBUF_B_EVEN (0x1<<5)
10573 #define PBF_PBF_PRTY_STS_REG_PBUF_B_ODD (0x1<<6)
10575 #define PBF_PBF_PRTY_STS_REG_PBUF_C_EVEN (0x1<<7)
10577 #define PBF_PBF_PRTY_STS_REG_PBUF_C_ODD (0x1<<8)
10579 #define PBF_PBF_PRTY_STS_REG_SMG_IN_Q (0x1<<9)
10581 #define PBF_PBF_PRTY_STS_REG_SMG_CMD_Q (0x1<<10)
10583 #define PBF_PBF_PRTY_STS_REG_SMG_CURR_CMD (0x1<<11)
10585 #define PBF_PBF_PRTY_STS_REG_PB_OUT_Q (0x1<<12)
10587 #define PBF_PBF_PRTY_STS_REG_HA_CMD_Q (0x1<<13)
10589 #define PBF_PBF_PRTY_STS_REG_HD_HDRS_MEM (0x1<<14)
10591 #define PBF_PBF_PRTY_STS_REG_HD_CMD_Q (0x1<<15)
10593 #define PBF_PBF_PRTY_STS_REG_SDM_IN_Q (0x1<<16)
10595 #define PBF_PBF_PRTY_STS_REG_HM_CMD_Q (0x1<<17)
10597 #define PBF_PBF_PRTY_STS_REG_HEADER_BUFFER (0x1<<18)
10599 #define PBF_PBF_PRTY_STS_REG_CRACKER_INFO_FIFO (0x1<<19)
10601 #define PBF_PBF_PRTY_STS_REG_PBUF_D_EVEN (0x1<<20)
10603 #define PBF_PBF_PRTY_STS_REG_PBUF_D_ODD (0x1<<21)
10605 #define PBF_PBF_PRTY_STS_REG_PBUF_E_EVEN (0x1<<22)
10607 #define PBF_PBF_PRTY_STS_REG_PBUF_E_ODD (0x1<<23)
10609 #define PBF_PBF_PRTY_STS_REG_PBUF_F_EVEN (0x1<<24)
10611 #define PBF_PBF_PRTY_STS_REG_PBUF_F_ODD (0x1<<25)
10613 #define PBF_PBF_PRTY_STS_REG_PBUF_G_EVEN (0x1<<26)
10615 #define PBF_PBF_PRTY_STS_REG_PBUF_G_ODD (0x1<<27)
10618 #define PBF_PBF_PRTY_STS_CLR_REG_PARITY (0x1<<0)
10620 #define PBF_PBF_PRTY_STS_CLR_REG_TQ_EVEN (0x1<<1)
10622 #define PBF_PBF_PRTY_STS_CLR_REG_TQ_ODD (0x1<<2)
10624 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_A_EVEN (0x1<<3)
10626 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_A_ODD (0x1<<4)
10628 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_B_EVEN (0x1<<5)
10630 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_B_ODD (0x1<<6)
10632 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_C_EVEN (0x1<<7)
10634 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_C_ODD (0x1<<8)
10636 #define PBF_PBF_PRTY_STS_CLR_REG_SMG_IN_Q (0x1<<9)
10638 #define PBF_PBF_PRTY_STS_CLR_REG_SMG_CMD_Q (0x1<<10)
10640 #define PBF_PBF_PRTY_STS_CLR_REG_SMG_CURR_CMD (0x1<<11)
10642 #define PBF_PBF_PRTY_STS_CLR_REG_PB_OUT_Q (0x1<<12)
10644 #define PBF_PBF_PRTY_STS_CLR_REG_HA_CMD_Q (0x1<<13)
10646 #define PBF_PBF_PRTY_STS_CLR_REG_HD_HDRS_MEM (0x1<<14)
10648 #define PBF_PBF_PRTY_STS_CLR_REG_HD_CMD_Q (0x1<<15)
10650 #define PBF_PBF_PRTY_STS_CLR_REG_SDM_IN_Q (0x1<<16)
10652 #define PBF_PBF_PRTY_STS_CLR_REG_HM_CMD_Q (0x1<<17)
10654 #define PBF_PBF_PRTY_STS_CLR_REG_HEADER_BUFFER (0x1<<18)
10656 #define PBF_PBF_PRTY_STS_CLR_REG_CRACKER_INFO_FIFO (0x1<<19)
10658 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_D_EVEN (0x1<<20)
10660 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_D_ODD (0x1<<21)
10662 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_E_EVEN (0x1<<22)
10664 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_E_ODD (0x1<<23)
10666 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_F_EVEN (0x1<<24)
10668 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_F_ODD (0x1<<25)
10670 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_G_EVEN (0x1<<26)
10672 #define PBF_PBF_PRTY_STS_CLR_REG_PBUF_G_ODD (0x1<<27)
10675 #define PBF_PBF_PRTY_STS_WR_REG_PARITY (0x1<<0)
10677 #define PBF_PBF_PRTY_STS_WR_REG_TQ_EVEN (0x1<<1)
10679 #define PBF_PBF_PRTY_STS_WR_REG_TQ_ODD (0x1<<2)
10681 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_A_EVEN (0x1<<3)
10683 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_A_ODD (0x1<<4)
10685 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_B_EVEN (0x1<<5)
10687 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_B_ODD (0x1<<6)
10689 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_C_EVEN (0x1<<7)
10691 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_C_ODD (0x1<<8)
10693 #define PBF_PBF_PRTY_STS_WR_REG_SMG_IN_Q (0x1<<9)
10695 #define PBF_PBF_PRTY_STS_WR_REG_SMG_CMD_Q (0x1<<10)
10697 #define PBF_PBF_PRTY_STS_WR_REG_SMG_CURR_CMD (0x1<<11)
10699 #define PBF_PBF_PRTY_STS_WR_REG_PB_OUT_Q (0x1<<12)
10701 #define PBF_PBF_PRTY_STS_WR_REG_HA_CMD_Q (0x1<<13)
10703 #define PBF_PBF_PRTY_STS_WR_REG_HD_HDRS_MEM (0x1<<14)
10705 #define PBF_PBF_PRTY_STS_WR_REG_HD_CMD_Q (0x1<<15)
10707 #define PBF_PBF_PRTY_STS_WR_REG_SDM_IN_Q (0x1<<16)
10709 #define PBF_PBF_PRTY_STS_WR_REG_HM_CMD_Q (0x1<<17)
10711 #define PBF_PBF_PRTY_STS_WR_REG_HEADER_BUFFER (0x1<<18)
10713 #define PBF_PBF_PRTY_STS_WR_REG_CRACKER_INFO_FIFO (0x1<<19)
10715 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_D_EVEN (0x1<<20)
10717 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_D_ODD (0x1<<21)
10719 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_E_EVEN (0x1<<22)
10721 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_E_ODD (0x1<<23)
10723 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_F_EVEN (0x1<<24)
10725 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_F_ODD (0x1<<25)
10727 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_G_EVEN (0x1<<26)
10729 #define PBF_PBF_PRTY_STS_WR_REG_PBUF_G_ODD (0x1<<27)
10732 #define PBF_PBF_PRTY_MASK_REG_PARITY (0x1<<0)
10734 #define PBF_PBF_PRTY_MASK_REG_TQ_EVEN (0x1<<1)
10736 #define PBF_PBF_PRTY_MASK_REG_TQ_ODD (0x1<<2)
10738 #define PBF_PBF_PRTY_MASK_REG_PBUF_A_EVEN (0x1<<3)
10740 #define PBF_PBF_PRTY_MASK_REG_PBUF_A_ODD (0x1<<4)
10742 #define PBF_PBF_PRTY_MASK_REG_PBUF_B_EVEN (0x1<<5)
10744 #define PBF_PBF_PRTY_MASK_REG_PBUF_B_ODD (0x1<<6)
10746 #define PBF_PBF_PRTY_MASK_REG_PBUF_C_EVEN (0x1<<7)
10748 #define PBF_PBF_PRTY_MASK_REG_PBUF_C_ODD (0x1<<8)
10750 #define PBF_PBF_PRTY_MASK_REG_SMG_IN_Q (0x1<<9)
10752 #define PBF_PBF_PRTY_MASK_REG_SMG_CMD_Q (0x1<<10)
10754 #define PBF_PBF_PRTY_MASK_REG_SMG_CURR_CMD (0x1<<11)
10756 #define PBF_PBF_PRTY_MASK_REG_PB_OUT_Q (0x1<<12)
10758 #define PBF_PBF_PRTY_MASK_REG_HA_CMD_Q (0x1<<13)
10760 #define PBF_PBF_PRTY_MASK_REG_HD_HDRS_MEM (0x1<<14)
10762 #define PBF_PBF_PRTY_MASK_REG_HD_CMD_Q (0x1<<15)
10764 #define PBF_PBF_PRTY_MASK_REG_SDM_IN_Q (0x1<<16)
10766 #define PBF_PBF_PRTY_MASK_REG_HM_CMD_Q (0x1<<17)
10768 #define PBF_PBF_PRTY_MASK_REG_HEADER_BUFFER (0x1<<18)
10770 #define PBF_PBF_PRTY_MASK_REG_CRACKER_INFO_FIFO (0x1<<19)
10772 #define PBF_PBF_PRTY_MASK_REG_PBUF_D_EVEN (0x1<<20)
10774 #define PBF_PBF_PRTY_MASK_REG_PBUF_D_ODD (0x1<<21)
10776 #define PBF_PBF_PRTY_MASK_REG_PBUF_E_EVEN (0x1<<22)
10778 #define PBF_PBF_PRTY_MASK_REG_PBUF_E_ODD (0x1<<23)
10780 #define PBF_PBF_PRTY_MASK_REG_PBUF_F_EVEN (0x1<<24)
10782 #define PBF_PBF_PRTY_MASK_REG_PBUF_F_ODD (0x1<<25)
10784 #define PBF_PBF_PRTY_MASK_REG_PBUF_G_EVEN (0x1<<26)
10786 #define PBF_PBF_PRTY_MASK_REG_PBUF_G_ODD (0x1<<27)
10791 #define PBF_REG_E15_FW_COMPAT_MODE 0x15c024UL //ACCESS:RW DataWidth:0x1 Description: E1.5 FW backward compatibility mode. If set then backward compatible to E1.5.
10796 #define PBF_REG_LIMIT_OUTSTANDING_READ_DATA 0x15c038UL //ACCESS:RW DataWidth:0x1 Description: If set enables limitting the outstanding read data from the PCI.
10799 #define PBF_REG_WRR_BURST_MODE 0x15c048UL //ACCESS:RW DataWidth:0x1 Description: If set; in the command queue arbiter; the WRR arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness.
10836 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_BAD_IPV_ERR (0x1<<0)
10838 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_BAD_IP_HDR_LEN_ERR (0x1<<1)
10840 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_PRS_PKT_TOO_SMALL_ERR (0x1<<2)
10842 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_TCP_HDR_PTR_INV_ERR (0x1<<3)
10844 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_UNKNOWN_OVER_IPV4_ERR (0x1<<4)
10846 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_UNKNOWN_OVER_ETH_ERR (0x1<<5)
10848 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_OVERIP_HM_4NON_1ST_FRAG_ERR (0x1<<6)
10850 #define PBF_NO_ERR_ON_PRS_ERR_REG_NO_ERR_ON_TCP_UDP_CHK_PTR_BEYOND_PKT_ERR (0x1<<7)
10853 #define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_BAD_IPV_ERR (0x1<<0)
10855 #define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_BAD_IP_HDR_LEN_ERR (0x1<<1)
10857 #define PBF_PRS_ERRORS_MASK_REG_MASK_PRS_PKT_TOO_SMALL_ERR (0x1<<2)
10859 #define PBF_PRS_ERRORS_MASK_REG_MASK_TCP_HDR_PTR_INV_ERR (0x1<<3)
10861 #define PBF_PRS_ERRORS_MASK_REG_MASK_UNKNOWN_OVER_IPV4_ERR (0x1<<4)
10863 #define PBF_PRS_ERRORS_MASK_REG_MASK_UNKNOWN_OVER_ETH_ERR (0x1<<5)
10865 #define PBF_PRS_ERRORS_MASK_REG_MASK_OVERIP_HM_4NON_1ST_FRAG_ERR (0x1<<6)
10867 #define PBF_PRS_ERRORS_MASK_REG_MASK_TCP_UDP_CHK_PTR_BEYOND_PKT_ERR (0x1<<7)
10869 #define PBF_REG_DROP_PKT_UPON_ERR 0x15c100UL //ACCESS:RW DataWidth:0x1 Description: if set; packets with error will be dropped; otherwise transmitted with error to the NIG (FCS).
10870 #define PBF_REG_NO_PAD_IN_PKT 0x15c104UL //ACCESS:RW DataWidth:0x1 Description: if set; there is no expected L2 padding in the packet.
10889 #define PBF_REG_INIT_Q0 0x15c160UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 0. When set the initial credit of queue 0 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
10890 #define PBF_REG_INIT_Q1 0x15c164UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 1. When set the initial credit of queue 1 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
10891 #define PBF_REG_INIT_Q2 0x15c168UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 2. When set the initial credit of queue 2 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
10892 #define PBF_REG_INIT_Q3 0x15c16cUL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 3. When set the initial credit of queue 3 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
10893 #define PBF_REG_INIT_Q4 0x15c170UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 4. When set the initial credit of queue 4 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
10894 #define PBF_REG_INIT_Q5 0x15c174UL //ACCESS:RW DataWidth:0x1 Description: Init bit for queue 5. When set the initial credit of queue 5 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
10895 #define PBF_REG_INIT_LB_Q 0x15c178UL //ACCESS:RW DataWidth:0x1 Description: Init bit for LB queue. When set the initial credit of the LB queue is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
10896 #define PBF_REG_PAUSE_ENABLE_Q0 0x15c17cUL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 0.
10897 #define PBF_REG_PAUSE_ENABLE_Q1 0x15c180UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 1.
10898 #define PBF_REG_PAUSE_ENABLE_Q2 0x15c184UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 2.
10899 #define PBF_REG_PAUSE_ENABLE_Q3 0x15c188UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 3.
10900 #define PBF_REG_PAUSE_ENABLE_Q4 0x15c18cUL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 4.
10901 #define PBF_REG_PAUSE_ENABLE_Q5 0x15c190UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 5.
10902 #define PBF_REG_PAUSE_ENABLE_LB_Q 0x15c194UL //ACCESS:RW DataWidth:0x1 Description: Indication that pause is enabled for queue 6.
10903 #define PBF_REG_MAC_IF4_ENABLE 0x15c198UL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 4.
10904 #define PBF_REG_MAC_IF5_ENABLE 0x15c19cUL //ACCESS:RW DataWidth:0x1 Description: Enable for mac interface 5.
10905 #define PBF_REG_DISABLE_WR2TQ_Q0 0x15c1a0UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 0.
10906 #define PBF_REG_DISABLE_WR2TQ_Q1 0x15c1a4UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 1.
10907 #define PBF_REG_DISABLE_WR2TQ_Q2 0x15c1a8UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 2.
10908 #define PBF_REG_DISABLE_WR2TQ_Q3 0x15c1acUL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 3.
10909 #define PBF_REG_DISABLE_WR2TQ_Q4 0x15c1b0UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 4.
10910 #define PBF_REG_DISABLE_WR2TQ_Q5 0x15c1b4UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to queue 5.
10911 #define PBF_REG_DISABLE_WR2TQ_LB_Q 0x15c1b8UL //ACCESS:RW DataWidth:0x1 Description: Disable the STORM writing to the LB queue.
10912 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bcUL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
10913 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
10914 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
10915 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
10916 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1ccUL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
10917 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
10918 #define PBF_REG_DISABLE_NEW_TASK_PROC_LB_Q 0x15c1d4UL //ACCESS:RW DataWidth:0x1 Description: Disable processing further tasks from port 0 (after ending the current task in process).
10965 #define PBF_REG_ETS_ARB_RR_BURST_MODE_P0 0x15c290UL //ACCESS:RW DataWidth:0x1 Description: For port 0: If set; the round robin arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
10966 #define PBF_REG_ETS_ARB_RR_BURST_MODE_P1 0x15c294UL //ACCESS:RW DataWidth:0x1 Description: For port 1: If set; the round robin arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
10967 #define PBF_REG_ETS_ARB_SPWAS_BURST_MODE_P0 0x15c298UL //ACCESS:RW DataWidth:0x1 Description: For port 0: If set; the round robin arbiter within the strict priority w/ anti-starvation arbiter; will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
10968 #define PBF_REG_ETS_ARB_SPWAS_BURST_MODE_P1 0x15c29cUL //ACCESS:RW DataWidth:0x1 Description: For port 1: If set; the round robin arbiter within the strict priority w/ anti-starvation arbiter; will stay on the winning input; instead of moving to the next one. This allows burstiness. This mode should be carefully used; since in certain arbitration configurations it can cause starvation.
11038 #define PBF_REG_DISABLE_PF 0x1402e8UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Disable a PF from transmitting.
11040 #define PBF_REG_DISABLE_VF 0x1402ecUL //ACCESS:RW DataWidth:0x1 SPLIT:64 Description: Disable a VF from transmitting.
11186 #define PBF_REG_INIT_P0 0x140004UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Init bit for port 0. When set the initial credit of port 0 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
11188 #define PBF_REG_INIT_P1 0x140008UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Init bit for port 1. When set the initial credit of port 1 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
11190 #define PBF_REG_INIT_P4 0x14000cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Init bit for port 4. When set the initial credit of port 4 is copied to the credit register. Should be set and then reset after the configuration of the port has ended.
11192 #define PBF_REG_PORT_MODE 0x140010UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - 0 - the device is in 2 port mode; 1 - 4 port mode.
11194 #define PBF_REG_P0_PAUSE_ENABLE 0x140014UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 0.
11196 #define PBF_REG_P1_PAUSE_ENABLE 0x140018UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 1.
11198 #define PBF_REG_P2_PAUSE_ENABLE 0x14001cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 2.
11200 #define PBF_REG_P3_PAUSE_ENABLE 0x140020UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 3.
11202 #define PBF_REG_P4_PAUSE_ENABLE 0x140024UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indication that pause is enabled for port 4.
11204 #define PBF_REG_DISABLE_WR2TQ_P0 0x140048UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 0 for the write interface of the STORM to that port task Q.
11206 #define PBF_REG_DISABLE_WR2TQ_P1 0x14004cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 1 for the write interface of the STORM to that port task Q.
11208 #define PBF_REG_DISABLE_WR2TQ_P2 0x140050UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 2 for the write interface of the STORM to that port task Q.
11210 #define PBF_REG_DISABLE_WR2TQ_P3 0x140054UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 3 for the write interface of the STORM to that port task Q.
11212 #define PBF_REG_DISABLE_WR2TQ_P4 0x140058UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable bit per port 4 for the write interface of the STORM to that port task Q.
11214 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 0 (after ending the current task in process).
11216 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 1 (after ending the current task in process).
11218 #define PBF_REG_DISABLE_NEW_TASK_PROC_P2 0x140064UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 2 (after ending the current task in process).
11220 #define PBF_REG_DISABLE_NEW_TASK_PROC_P3 0x140068UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 3 (after ending the current task in process).
11222 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Disable processing further tasks from port 4 (after ending the current task in process).
11378 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04cUL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indicates which COS is conncted to the highest priority in the command arbiter.
11380 #define PBF_REG_ETS_ENABLED 0x15c050UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - Indicates that ETS is performed between the COSes in the command arbiter. If reset strict priority w/ anti-starvation will be performed w/o WFQ.
11392 #define PBF_REG_ETS_BURST_MODE 0x15c068UL //ACCESS:R DataWidth:0x1 Description: Removed for E3 B0 - If set; in the command queue arbiter; the round robin arbiters pointer will stay on the winning input; instead of moving to the next one. This allows burstiness. This bit can be set only when ETS is enabled.
11425 #define PB_CONTROL_REG_BYTE_ORDER_SWITCH (0x1<<0)
11427 #define PB_CONTROL_REG_DB_IGNORE_ERROR (0x1<<1)
11429 #define PB_CONTROL_REG_DONT_PASS_ERROR (0x1<<2)
11431 #define PB_CONTROL_REG_EOP_CHECK_DISABLE (0x1<<3)
11433 #define PB_CONTROL_REG_CRC_COMPARE_DISABLE (0x1<<4)
11435 #define PB_CONTROL_REG_EN_INPUTS (0x1<<5)
11437 #define PB_CONTROL_REG_DISABLE_PB (0x1<<6)
11441 #define PB_CONTROL_REG_RELAX_TH (0x1<<11)
11454 #define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
11456 #define PB_PB_INT_STS_REG_EOP_ERROR (0x1<<1)
11459 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
11461 #define PB_PB_INT_STS_CLR_REG_EOP_ERROR (0x1<<1)
11464 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
11466 #define PB_PB_INT_STS_WR_REG_EOP_ERROR (0x1<<1)
11469 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
11471 #define PB_PB_INT_MASK_REG_EOP_ERROR (0x1<<1)
11474 #define PB_PB_PRTY_STS_REG_PARITY (0x1<<0)
11476 #define PB_PB_PRTY_STS_REG_DB (0x1<<1)
11478 #define PB_PB_PRTY_STS_REG_TQ (0x1<<2)
11480 #define PB_PB_PRTY_STS_REG_L1 (0x1<<3)
11483 #define PB_PB_PRTY_STS_CLR_REG_PARITY (0x1<<0)
11485 #define PB_PB_PRTY_STS_CLR_REG_DB (0x1<<1)
11487 #define PB_PB_PRTY_STS_CLR_REG_TQ (0x1<<2)
11489 #define PB_PB_PRTY_STS_CLR_REG_L1 (0x1<<3)
11492 #define PB_PB_PRTY_STS_WR_REG_PARITY (0x1<<0)
11494 #define PB_PB_PRTY_STS_WR_REG_DB (0x1<<1)
11496 #define PB_PB_PRTY_STS_WR_REG_TQ (0x1<<2)
11498 #define PB_PB_PRTY_STS_WR_REG_L1 (0x1<<3)
11501 #define PB_PB_PRTY_MASK_REG_PARITY (0x1<<0)
11503 #define PB_PB_PRTY_MASK_REG_DB (0x1<<1)
11505 #define PB_PB_PRTY_MASK_REG_TQ (0x1<<2)
11507 #define PB_PB_PRTY_MASK_REG_L1 (0x1<<3)
11527 #define PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_FLR_REQUEST (0x1<<0)
11529 #define PGLUE_B_DISABLE_FLR_SRIOV_DISABLED_REG_DISABLE_SRIOV_DISABLED_REQUEST (0x1<<1)
11544 #define PGLUE_B_REG_DISABLE_ATS_EN_CLEARING 0x9064UL //ACCESS:RW DataWidth:0x1 Description: Debug only: PGLUE automatically clears ATC enable for a function if a TCPL arrived for that function with Unsupported Request error. Setting this register to 1 disables this automatic clearing.
11563 #define PGLUE_B_TX_ERR_E15_MODE_REG_TX_ERR_E15_MODE_PF (0x1<<0)
11565 #define PGLUE_B_TX_ERR_E15_MODE_REG_TX_ERR_E15_MODE_VF (0x1<<1)
11615 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170UL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 - enable.
11616 #define PGLUE_B_REG_TSDM_INB_INT_A_VF_ENABLE 0x9174UL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for TSDM. 0 - disable; 1 - enable.
11617 #define PGLUE_B_REG_TSDM_INB_INT_B_VF_ENABLE 0x9178UL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for TSDM. 0 - disable; 1 - enable.
11618 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917cUL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 - enable.
11619 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180UL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 - enable.
11620 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184UL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 - enable.
11621 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188UL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 - enable.
11622 #define PGLUE_B_REG_XSDM_INB_INT_A_VF_ENABLE 0x918cUL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for XSDM. 0 - disable; 1 - enable.
11623 #define PGLUE_B_REG_XSDM_INB_INT_B_VF_ENABLE 0x9190UL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for XSDM. 0 - disable; 1 - enable.
11624 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194UL //ACCESS:RW DataWidth:0x1 Description: Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 - enable.
11625 #define PGLUE_B_REG_CSDM_INB_INT_A_VF_ENABLE 0x9198UL //ACCESS:RW DataWidth:0x1 Description: Type A VF enable inbound interrupt table for CSDM. 0 - disable; 1 - enable.
11626 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919cUL //ACCESS:RW DataWidth:0x1 Description: Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 - enable.
11627 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0UL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
11628 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4UL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
11629 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8UL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
11630 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91acUL //ACCESS:RW DataWidth:0x1 Description: 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B.
11666 #define PGLUE_B_REG_IDO_ENABLE_MASTER_RW2 0x923cUL //ACCESS:RW DataWidth:0x1 Description: bit 0 - when set indicates that IDO bit towards PGLUE should be set for Translation Requests
11667 #define PGLUE_B_REG_IDO_ENABLE_TARGET_CPL 0x9240UL //ACCESS:RW DataWidth:0x1 Description: bit 0 - when set indicates that IDO bit towards PGLUE should be set for Target Completions
11669 #define PGLUE_B_REG_IGU_BYPASS_ON_ERR 0x9248UL //ACCESS:RW DataWidth:0x1 Description: 1 - Do not discard IGU master transactions for PF when the corresponding was_error bit is set.
11670 #define PGLUE_B_REG_ALLOW_MSIX_ACCESS_IN_BAR0 0x9250UL //ACCESS:RW DataWidth:0x1 Description: 0 - Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value is configured; BAR2 size for PFs and VFs should be configured to 8KB to allow ONLY MSIX table and PBA access. 1 - All IGU space in BAR 0 is accessible; including the first 8KB. When this value is configured; BAR2 size for PFs can be configured to 64KB and for VFs to 16KB to allow all IGU space to be accessed in BAR2 as well.
11672 #define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_HIGHER_BW_WAW (0x1<<0)
11674 #define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_TWO_PENDING_REQUESTS (0x1<<1)
11676 #define PGLUE_B_DISABLE_HIGHER_BW_REG_DISABLE_TWO_PENDING_WR_REQUESTS (0x1<<2)
11678 #define PGLUE_B_REG_DISABLE_RAM1_BAR_ACCESS 0x9258UL //ACCESS:RW DataWidth:0x1 Description: 0 - RAM1 PF BAR accesses are enabled. 1 - RAM1 PF BAR accesses are disabled.
11695 #define PGLUE_B_DBGBUS_PATH_SELECT_REG_DBGBUS_PATH_SELECT_E0 (0x1<<0)
11697 #define PGLUE_B_DBGBUS_PATH_SELECT_REG_DBGBUS_PATH_SELECT_E1 (0x1<<1)
11707 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
11709 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
11711 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
11713 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
11715 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
11717 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
11719 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
11721 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
11723 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
11725 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
11727 #define PGLUE_B_PGLUE_B_INT_STS_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
11730 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
11732 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
11734 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_WAS_ERROR_ATTN (0x1<<2)
11736 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
11738 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
11740 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
11742 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_ERROR_ATTN (0x1<<6)
11744 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
11746 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
11748 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
11750 #define PGLUE_B_PGLUE_B_INT_STS_CLR_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
11753 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
11755 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
11757 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_WAS_ERROR_ATTN (0x1<<2)
11759 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
11761 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
11763 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
11765 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_ERROR_ATTN (0x1<<6)
11767 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
11769 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
11771 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
11773 #define PGLUE_B_PGLUE_B_INT_STS_WR_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
11776 #define PGLUE_B_PGLUE_B_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
11778 #define PGLUE_B_PGLUE_B_INT_MASK_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
11780 #define PGLUE_B_PGLUE_B_INT_MASK_REG_WAS_ERROR_ATTN (0x1<<2)
11782 #define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
11784 #define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
11786 #define PGLUE_B_PGLUE_B_INT_MASK_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
11788 #define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_ERROR_ATTN (0x1<<6)
11790 #define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
11792 #define PGLUE_B_PGLUE_B_INT_MASK_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
11794 #define PGLUE_B_PGLUE_B_INT_MASK_REG_TCPL_TRANSLATION_SIZE_DIFFERENT (0x1<<9)
11796 #define PGLUE_B_PGLUE_B_INT_MASK_REG_PCIE_RX_L0S_TIMEOUT (0x1<<10)
11799 #define PGLUE_B_PGLUE_B_PRTY_STS_REG_PARITY (0x1<<0)
11801 #define PGLUE_B_PGLUE_B_PRTY_STS_REG_TAG_DB (0x1<<1)
11804 #define PGLUE_B_PGLUE_B_PRTY_STS_CLR_REG_PARITY (0x1<<0)
11806 #define PGLUE_B_PGLUE_B_PRTY_STS_CLR_REG_TAG_DB (0x1<<1)
11809 #define PGLUE_B_PGLUE_B_PRTY_STS_WR_REG_PARITY (0x1<<0)
11811 #define PGLUE_B_PGLUE_B_PRTY_STS_WR_REG_TAG_DB (0x1<<1)
11814 #define PGLUE_B_PGLUE_B_PRTY_MASK_REG_PARITY (0x1<<0)
11816 #define PGLUE_B_PGLUE_B_PRTY_MASK_REG_TAG_DB (0x1<<1)
11818 #define PGLUE_B_REG_DISABLE_TCPL_TRANSLATION_SIZE_CHECK 0x9484UL //ACCESS:RW DataWidth:0x1 Description: Debug only: 0 - Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation Size field smaller than the Function programmed STU value; clear the ATS_en shadow bit and send UR to the ATC. 1 - Disable the fix for CQ45220.
11861 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for master transactions.
11863 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for target read transactions.
11865 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: Internal FID_enable configuration per-PF for target write transactions.
11867 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438UL //ACCESS:RW DataWidth:0x1 SPLIT:128 Description: Internal FID_enable configuration per-VF for master and target transactions.
11905 #define PGLUE_B_REG_PORT4MODE_EN 0x924cUL //ACCESS:R DataWidth:0x1 Description: 0 - Work in two ports mode (one port per engine). 1 - Work in 4 port mode (2 ports per engine). This affects PFID translation. This register is removed for E3; where this information is received as an input from MISC block.
11982 #define PRS_A_PRSU_12_REG_TCP_SEARCH_IP_SRC (0x1<<0)
11984 #define PRS_A_PRSU_12_REG_TCP_SEARCH_IP_DST (0x1<<1)
11986 #define PRS_A_PRSU_12_REG_TCP_SEARCH_TCP_SRC (0x1<<2)
11988 #define PRS_A_PRSU_12_REG_TCP_SEARCH_TCP_DST (0x1<<3)
11997 #define PRS_A_PRSU_20_REG_HASH_TCP_IPV4_PORT_0 (0x1<<0)
11999 #define PRS_A_PRSU_20_REG_HASH_TCP_IPV4_PORT_1 (0x1<<1)
12001 #define PRS_A_PRSU_20_REG_HASH_TCP_IPV6_PORT_0 (0x1<<2)
12003 #define PRS_A_PRSU_20_REG_HASH_TCP_IPV6_PORT_1 (0x1<<3)
12005 #define PRS_REG_SOFT_RST 0x4013cUL //ACCESS:RW DataWidth:0x1 Description: Soft reset - reset all FSM
12024 #define PRS_REG_PRS_INT_STS 0x40188UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
12025 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
12027 #define PRS_REG_PRS_INT_STS_CLR 0x4018cUL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
12028 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
12030 #define PRS_REG_PRS_INT_STS_WR 0x40190UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
12031 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
12033 #define PRS_REG_PRS_INT_MASK 0x40194UL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
12034 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
12037 #define PRS_PRS_PRTY_STS_REG_PARITY (0x1<<0)
12039 #define PRS_PRS_PRTY_STS_REG_IFIFO (0x1<<1)
12041 #define PRS_PRS_PRTY_STS_REG_CACU (0x1<<2)
12043 #define PRS_PRS_PRTY_STS_REG_CFCR (0x1<<3)
12045 #define PRS_PRS_PRTY_STS_REG_CFCQ (0x1<<4)
12047 #define PRS_PRS_PRTY_STS_REG_CFCF (0x1<<5)
12049 #define PRS_PRS_PRTY_STS_REG_SRCF (0x1<<6)
12051 #define PRS_PRS_PRTY_STS_REG_PRSF (0x1<<7)
12054 #define PRS_PRS_PRTY_STS_CLR_REG_PARITY (0x1<<0)
12056 #define PRS_PRS_PRTY_STS_CLR_REG_IFIFO (0x1<<1)
12058 #define PRS_PRS_PRTY_STS_CLR_REG_CACU (0x1<<2)
12060 #define PRS_PRS_PRTY_STS_CLR_REG_CFCR (0x1<<3)
12062 #define PRS_PRS_PRTY_STS_CLR_REG_CFCQ (0x1<<4)
12064 #define PRS_PRS_PRTY_STS_CLR_REG_CFCF (0x1<<5)
12066 #define PRS_PRS_PRTY_STS_CLR_REG_SRCF (0x1<<6)
12068 #define PRS_PRS_PRTY_STS_CLR_REG_PRSF (0x1<<7)
12071 #define PRS_PRS_PRTY_STS_WR_REG_PARITY (0x1<<0)
12073 #define PRS_PRS_PRTY_STS_WR_REG_IFIFO (0x1<<1)
12075 #define PRS_PRS_PRTY_STS_WR_REG_CACU (0x1<<2)
12077 #define PRS_PRS_PRTY_STS_WR_REG_CFCR (0x1<<3)
12079 #define PRS_PRS_PRTY_STS_WR_REG_CFCQ (0x1<<4)
12081 #define PRS_PRS_PRTY_STS_WR_REG_CFCF (0x1<<5)
12083 #define PRS_PRS_PRTY_STS_WR_REG_SRCF (0x1<<6)
12085 #define PRS_PRS_PRTY_STS_WR_REG_PRSF (0x1<<7)
12088 #define PRS_PRS_PRTY_MASK_REG_PARITY (0x1<<0)
12090 #define PRS_PRS_PRTY_MASK_REG_IFIFO (0x1<<1)
12092 #define PRS_PRS_PRTY_MASK_REG_CACU (0x1<<2)
12094 #define PRS_PRS_PRTY_MASK_REG_CFCR (0x1<<3)
12096 #define PRS_PRS_PRTY_MASK_REG_CFCQ (0x1<<4)
12098 #define PRS_PRS_PRTY_MASK_REG_CFCF (0x1<<5)
12100 #define PRS_PRS_PRTY_MASK_REG_SRCF (0x1<<6)
12102 #define PRS_PRS_PRTY_MASK_REG_PRSF (0x1<<7)
12112 #define PRS_REG_E1HOV_MODE 0x401c8UL //ACCESS:RW DataWidth:0x1 Description: Indicates if in outer vlan mode. 0=non-outer-vlan mode; 1=outer vlan mode.
12113 #define PRS_REG_HASH_5TH_TUPLE 0x401ccUL //ACCESS:RW DataWidth:0x1 Description: Indicates if to include the protocol field in the hash request. 0=do not include; 1=include
12116 #define PRS_REG_TCP_SEARCH_VLAN 0x401d8UL //ACCESS:RW DataWidth:0x1 Description: Indicates whether to include inner VLAN (if present) in the TCP search. If not present, a value of 0 will be sent in its place.
12145 #define PRS_REG_TCP_SEARCH_OVLAN 0x402b0UL //ACCESS:RW DataWidth:0x1 Description: Indicates whether to include outer VLAN (if present) in the TCP search. If not present, a value of 1 will be sent in its place.
12146 #define PRS_REG_NIC_MODE 0x40138UL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: If set indicates not to send messages to CFC on received packets - one bit per PF
12349 #define PXP2_REG_RQ_IGNORE_BLK 0x12016cUL //ACCESS:RW DataWidth:0x1 Description: if '1'; requester will ignore the reader blk_per_client indication
12353 #define PXP2_PSWRQ_QM_PCI_ATTR_REG_RQ_QM_RELAXED (0x1<<0)
12355 #define PXP2_PSWRQ_QM_PCI_ATTR_REG_RQ_QM_NOSNOOP (0x1<<1)
12358 #define PXP2_PSWRQ_TM_PCI_ATTR_REG_RQ_TM_RELAXED (0x1<<0)
12360 #define PXP2_PSWRQ_TM_PCI_ATTR_REG_RQ_TM_NOSNOOP (0x1<<1)
12363 #define PXP2_PSWRQ_SRC_PCI_ATTR_REG_RQ_SRC_RELAXED (0x1<<0)
12365 #define PXP2_PSWRQ_SRC_PCI_ATTR_REG_RQ_SRC_NOSNOOP (0x1<<1)
12368 #define PXP2_PSWRQ_CDU_PCI_ATTR_REG_RQ_CDU_RELAXED (0x1<<0)
12370 #define PXP2_PSWRQ_CDU_PCI_ATTR_REG_RQ_CDU_NOSNOOP (0x1<<1)
12373 #define PXP2_PSWRQ_DBG_PCI_ATTR_REG_RQ_DBG_RELAXED (0x1<<0)
12375 #define PXP2_PSWRQ_DBG_PCI_ATTR_REG_RQ_DBG_NOSNOOP (0x1<<1)
12378 #define PXP2_PSWRQ_HC_PCI_ATTR_REG_RQ_HC_RELAXED (0x1<<0)
12380 #define PXP2_PSWRQ_HC_PCI_ATTR_REG_RQ_HC_NOSNOOP (0x1<<1)
12383 #define PXP2_PSWRQ_DMAE_PCI_ATTR_REG_RQ_DMAE_RELAXED (0x1<<0)
12385 #define PXP2_PSWRQ_DMAE_PCI_ATTR_REG_RQ_DMAE_NOSNOOP (0x1<<1)
12394 #define PXP2_REG_RQ_RBC_DONE 0x1201b0UL //ACCESS:RW DataWidth:0x1 Description: 1' indicates that the RBC has finished configuring the PSWRQ
12395 #define PXP2_REG_RQ_CFG_DONE 0x1201b4UL //ACCESS:R DataWidth:0x1 Description: 1' indicates that the requester has finished its internal configuration
12626 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330UL //ACCESS:RW DataWidth:0x1 Description: When '1'; requests will enter input buffers but wont get out towards the glue
12641 #define PXP2_REG_RD_START_INIT 0x12036cUL //ACCESS:RW DataWidth:0x1 Description: Signals the PSWRD block to start initializing internal memories
12642 #define PXP2_REG_RD_INIT_DONE 0x120370UL //ACCESS:R DataWidth:0x1 Description: PSWRD internal memories initialization is done
12643 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374UL //ACCESS:RW DataWidth:0x1 Description: When '1'; inputs to the PSWRD block are ignored
12674 #define PXP2_REG_RD_PBF_IN_SEPARATE_VQ 0x1203f0UL //ACCESS:RW DataWidth:0x1 Description: 1' indicates that the PBF has a separate VQ and uses VQ4. '0' indicates it shares VQ9 with SDM clients. This field should be consistent with ~pbf_registers_pci_voq_id.pci_voq_id
12685 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041cUL //ACCESS:R DataWidth:0x1 Description: Debug only: Indication if delivery ports are idle
12686 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420UL //ACCESS:R DataWidth:0x1 Description: Debug only: Indication if delivery ports are idle
12687 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12688 #define PXP2_REG_RD_ALMOST_FULL_1 0x120428UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12689 #define PXP2_REG_RD_ALMOST_FULL_2 0x12042cUL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12690 #define PXP2_REG_RD_ALMOST_FULL_3 0x120430UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12691 #define PXP2_REG_RD_ALMOST_FULL_4 0x120434UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12692 #define PXP2_REG_RD_ALMOST_FULL_5 0x120438UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12693 #define PXP2_REG_RD_ALMOST_FULL_6 0x12043cUL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12694 #define PXP2_REG_RD_ALMOST_FULL_7 0x120440UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12695 #define PXP2_REG_RD_ALMOST_FULL_8 0x120444UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12696 #define PXP2_REG_RD_ALMOST_FULL_9 0x120448UL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12697 #define PXP2_REG_RD_ALMOST_FULL_10 0x12044cUL //ACCESS:R DataWidth:0x1 Description: Debug only: The 'almost full' indication from each fifo (gives indication about backpressure)
12707 #define PXP2_REG_HST_DISABLE_INPUTS_PCI 0x120474UL //ACCESS:RW DataWidth:0x1 Description: Debug only: When '1'; inputs to the PSWHST block in clk_pci domain are ignored
12717 #define PXP2_PGL_CONTROL0_REG_PGL_DISABLE_INPUTS (0x1<<7)
12762 #define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_TSDM (0x1<<10)
12764 #define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_USDM (0x1<<11)
12766 #define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_XSDM (0x1<<12)
12768 #define PXP2_PGL_CONTROL1_REG_PGL_EN_INT_CSDM (0x1<<13)
12773 #define PXP2_PGL_DEBUG_REG_PGL_TXR_RELAX (0x1<<0)
12775 #define PXP2_PGL_DEBUG_REG_PGL_TXW_RELAX (0x1<<1)
12777 #define PXP2_PGL_DEBUG_REG_PGL_DISABLE (0x1<<2)
12790 #define PXP2_PGL_CORE_DEBUG_REG_PGL_1US_DISABLE (0x1<<0)
12796 #define PXP2_PGL_CORE_DEBUG_REG_PGL_PARITY_MODE (0x1<<9)
12798 #define PXP2_PGL_CORE_DEBUG_REG_PGL_TXARB_SP (0x1<<10)
12801 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564UL //ACCESS:R DataWidth:0x1 Description: this bit indicates that a write request was blocked because of bus_master_en was deasserted
12802 #define PXP2_REG_PGL_READ_BLOCKED 0x120568UL //ACCESS:R DataWidth:0x1 Description: this bit indicates that a read request was blocked because of bus_master_en was deasserted
12804 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
12806 #define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
12808 #define PXP2_PXP2_INT_STS_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
12810 #define PXP2_PXP2_INT_STS_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
12812 #define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
12814 #define PXP2_PXP2_INT_STS_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
12816 #define PXP2_PXP2_INT_STS_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
12818 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
12820 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
12822 #define PXP2_PXP2_INT_STS_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
12824 #define PXP2_PXP2_INT_STS_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
12826 #define PXP2_PXP2_INT_STS_0_REG_RD_PUSH_ERROR (0x1<<11)
12828 #define PXP2_PXP2_INT_STS_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
12830 #define PXP2_PXP2_INT_STS_0_REG_RD_COMPLETION_ERR (0x1<<13)
12832 #define PXP2_PXP2_INT_STS_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
12834 #define PXP2_PXP2_INT_STS_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
12836 #define PXP2_PXP2_INT_STS_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
12838 #define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_ERR (0x1<<17)
12840 #define PXP2_PXP2_INT_STS_0_REG_PGL_TXW_OF (0x1<<18)
12842 #define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_AFT (0x1<<19)
12844 #define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_OF (0x1<<20)
12846 #define PXP2_PXP2_INT_STS_0_REG_PGL_CPL_ECRC (0x1<<21)
12848 #define PXP2_PXP2_INT_STS_0_REG_PGL_PCIE_ATTN (0x1<<22)
12850 #define PXP2_PXP2_INT_STS_0_REG_PGL_READ_BLOCKED (0x1<<23)
12852 #define PXP2_PXP2_INT_STS_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
12854 #define PXP2_PXP2_INT_STS_0_REG_WR_TM_UNDERFLOW (0x1<<25)
12856 #define PXP2_PXP2_INT_STS_0_REG_WR_QM_UNDERFLOW (0x1<<26)
12858 #define PXP2_PXP2_INT_STS_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
12860 #define PXP2_PXP2_INT_STS_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
12862 #define PXP2_PXP2_INT_STS_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
12864 #define PXP2_PXP2_INT_STS_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
12866 #define PXP2_PXP2_INT_STS_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
12869 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
12871 #define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
12873 #define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
12875 #define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
12877 #define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
12879 #define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
12881 #define PXP2_PXP2_INT_STS_CLR_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
12883 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
12885 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
12887 #define PXP2_PXP2_INT_STS_CLR_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
12889 #define PXP2_PXP2_INT_STS_CLR_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
12891 #define PXP2_PXP2_INT_STS_CLR_0_REG_RD_PUSH_ERROR (0x1<<11)
12893 #define PXP2_PXP2_INT_STS_CLR_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
12895 #define PXP2_PXP2_INT_STS_CLR_0_REG_RD_COMPLETION_ERR (0x1<<13)
12897 #define PXP2_PXP2_INT_STS_CLR_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
12899 #define PXP2_PXP2_INT_STS_CLR_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
12901 #define PXP2_PXP2_INT_STS_CLR_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
12903 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_ERR (0x1<<17)
12905 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_TXW_OF (0x1<<18)
12907 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_AFT (0x1<<19)
12909 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_OF (0x1<<20)
12911 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_CPL_ECRC (0x1<<21)
12913 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_PCIE_ATTN (0x1<<22)
12915 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_READ_BLOCKED (0x1<<23)
12917 #define PXP2_PXP2_INT_STS_CLR_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
12919 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_TM_UNDERFLOW (0x1<<25)
12921 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_QM_UNDERFLOW (0x1<<26)
12923 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
12925 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
12927 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
12929 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
12931 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
12934 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
12936 #define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
12938 #define PXP2_PXP2_INT_STS_WR_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
12940 #define PXP2_PXP2_INT_STS_WR_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
12942 #define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
12944 #define PXP2_PXP2_INT_STS_WR_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
12946 #define PXP2_PXP2_INT_STS_WR_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
12948 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
12950 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
12952 #define PXP2_PXP2_INT_STS_WR_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
12954 #define PXP2_PXP2_INT_STS_WR_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
12956 #define PXP2_PXP2_INT_STS_WR_0_REG_RD_PUSH_ERROR (0x1<<11)
12958 #define PXP2_PXP2_INT_STS_WR_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
12960 #define PXP2_PXP2_INT_STS_WR_0_REG_RD_COMPLETION_ERR (0x1<<13)
12962 #define PXP2_PXP2_INT_STS_WR_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
12964 #define PXP2_PXP2_INT_STS_WR_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
12966 #define PXP2_PXP2_INT_STS_WR_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
12968 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_ERR (0x1<<17)
12970 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_TXW_OF (0x1<<18)
12972 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_AFT (0x1<<19)
12974 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_OF (0x1<<20)
12976 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_CPL_ECRC (0x1<<21)
12978 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_PCIE_ATTN (0x1<<22)
12980 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_READ_BLOCKED (0x1<<23)
12982 #define PXP2_PXP2_INT_STS_WR_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
12984 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_TM_UNDERFLOW (0x1<<25)
12986 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_QM_UNDERFLOW (0x1<<26)
12988 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
12990 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
12992 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
12994 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
12996 #define PXP2_PXP2_INT_STS_WR_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
12999 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
13001 #define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_FIFO_OVERFLOW (0x1<<1)
13003 #define PXP2_PXP2_INT_MASK_0_REG_RQ_WDFIFO_OVERFLOW (0x1<<2)
13005 #define PXP2_PXP2_INT_MASK_0_REG_RQ_PHYADDR_FIFO_OF (0x1<<3)
13007 #define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_VIOLATION_1 (0x1<<4)
13009 #define PXP2_PXP2_INT_MASK_0_REG_RQ_L2P_VIOLATION_2 (0x1<<5)
13011 #define PXP2_PXP2_INT_MASK_0_REG_RQ_FREE_LIST_EMPTY (0x1<<6)
13013 #define PXP2_PXP2_INT_MASK_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
13015 #define PXP2_PXP2_INT_MASK_0_REG_WR_PGLUE_UNDERFLOW (0x1<<8)
13017 #define PXP2_PXP2_INT_MASK_0_REG_RD_SR_FIFO_ERROR (0x1<<9)
13019 #define PXP2_PXP2_INT_MASK_0_REG_RD_BLK_FIFO_ERROR (0x1<<10)
13021 #define PXP2_PXP2_INT_MASK_0_REG_RD_PUSH_ERROR (0x1<<11)
13023 #define PXP2_PXP2_INT_MASK_0_REG_RD_PUSH_PBF_ERROR (0x1<<12)
13025 #define PXP2_PXP2_INT_MASK_0_REG_RD_COMPLETION_ERR (0x1<<13)
13027 #define PXP2_PXP2_INT_MASK_0_REG_HST_HEADER_FIFO_ERR (0x1<<14)
13029 #define PXP2_PXP2_INT_MASK_0_REG_HST_DATA_FIFO_ERR (0x1<<15)
13031 #define PXP2_PXP2_INT_MASK_0_REG_HST_CPL_FIFO_ERR (0x1<<16)
13033 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_ERR (0x1<<17)
13035 #define PXP2_PXP2_INT_MASK_0_REG_PGL_TXW_OF (0x1<<18)
13037 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
13039 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
13041 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_ECRC (0x1<<21)
13043 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
13045 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
13047 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
13049 #define PXP2_PXP2_INT_MASK_0_REG_WR_TM_UNDERFLOW (0x1<<25)
13051 #define PXP2_PXP2_INT_MASK_0_REG_WR_QM_UNDERFLOW (0x1<<26)
13053 #define PXP2_PXP2_INT_MASK_0_REG_WR_SRC_UNDERFLOW (0x1<<27)
13055 #define PXP2_PXP2_INT_MASK_0_REG_WR_USDM_UNDERFLOW (0x1<<28)
13057 #define PXP2_PXP2_INT_MASK_0_REG_WR_TSDM_UNDERFLOW (0x1<<29)
13059 #define PXP2_PXP2_INT_MASK_0_REG_WR_CSDM_UNDERFLOW (0x1<<30)
13061 #define PXP2_PXP2_INT_MASK_0_REG_WR_XSDM_UNDERFLOW (0x1<<31)
13064 #define PXP2_PXP2_PRTY_STS_0_REG_PARITY (0x1<<0)
13066 #define PXP2_PXP2_PRTY_STS_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
13068 #define PXP2_PXP2_PRTY_STS_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
13070 #define PXP2_PXP2_PRTY_STS_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
13072 #define PXP2_PXP2_PRTY_STS_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
13074 #define PXP2_PXP2_PRTY_STS_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
13076 #define PXP2_PXP2_PRTY_STS_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
13078 #define PXP2_PXP2_PRTY_STS_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
13080 #define PXP2_PXP2_PRTY_STS_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
13082 #define PXP2_PXP2_PRTY_STS_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
13084 #define PXP2_PXP2_PRTY_STS_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
13086 #define PXP2_PXP2_PRTY_STS_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
13088 #define PXP2_PXP2_PRTY_STS_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
13090 #define PXP2_PXP2_PRTY_STS_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
13092 #define PXP2_PXP2_PRTY_STS_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
13094 #define PXP2_PXP2_PRTY_STS_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
13096 #define PXP2_PXP2_PRTY_STS_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
13098 #define PXP2_PXP2_PRTY_STS_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
13100 #define PXP2_PXP2_PRTY_STS_0_REG_RD_VQ_HEAD (0x1<<18)
13102 #define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_COMPLETION (0x1<<19)
13104 #define PXP2_PXP2_PRTY_STS_0_REG_RD_COMP_CTX (0x1<<20)
13106 #define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_DELIVERY1 (0x1<<21)
13108 #define PXP2_PXP2_PRTY_STS_0_REG_RD_SR_DELIVERY2 (0x1<<22)
13110 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
13112 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
13114 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
13116 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
13118 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
13120 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
13122 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
13124 #define PXP2_PXP2_PRTY_STS_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
13126 #define PXP2_PXP2_PRTY_STS_0_REG_RD_FIRST_BLK (0x1<<31)
13129 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
13131 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
13133 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
13135 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
13137 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
13139 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
13141 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
13143 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
13145 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
13147 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
13149 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
13151 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
13153 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
13155 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
13157 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
13159 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
13161 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
13163 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
13165 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_VQ_HEAD (0x1<<18)
13167 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_COMPLETION (0x1<<19)
13169 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_COMP_CTX (0x1<<20)
13171 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_DELIVERY1 (0x1<<21)
13173 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_SR_DELIVERY2 (0x1<<22)
13175 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
13177 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
13179 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
13181 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
13183 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
13185 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
13187 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
13189 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
13191 #define PXP2_PXP2_PRTY_STS_CLR_0_REG_RD_FIRST_BLK (0x1<<31)
13194 #define PXP2_PXP2_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
13196 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
13198 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
13200 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
13202 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
13204 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
13206 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
13208 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
13210 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
13212 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
13214 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
13216 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
13218 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
13220 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
13222 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
13224 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
13226 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
13228 #define PXP2_PXP2_PRTY_STS_WR_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
13230 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_VQ_HEAD (0x1<<18)
13232 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_COMPLETION (0x1<<19)
13234 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_COMP_CTX (0x1<<20)
13236 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_DELIVERY1 (0x1<<21)
13238 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_SR_DELIVERY2 (0x1<<22)
13240 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
13242 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
13244 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
13246 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
13248 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
13250 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
13252 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
13254 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
13256 #define PXP2_PXP2_PRTY_STS_WR_0_REG_RD_FIRST_BLK (0x1<<31)
13259 #define PXP2_PXP2_PRTY_MASK_0_REG_PARITY (0x1<<0)
13261 #define PXP2_PXP2_PRTY_MASK_0_REG_RQ_CXR_PARITY_ERR (0x1<<1)
13263 #define PXP2_PXP2_PRTY_MASK_0_REG_RQ_HOQ_PARITY_ERR (0x1<<2)
13265 #define PXP2_PXP2_PRTY_MASK_0_REG_RQ_UFIFO_PARITY_ERR (0x1<<3)
13267 #define PXP2_PXP2_PRTY_MASK_0_REG_RQ_ONCHIP_PARITY_ERR (0x1<<4)
13269 #define PXP2_PXP2_PRTY_MASK_0_REG_RQ_OFFCHIP_PARITY_ERR (0x1<<5)
13271 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_SRC_FIFO_PRTY (0x1<<6)
13273 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_QM_FIFO_PRTY (0x1<<7)
13275 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_TM_FIFO_PRTY (0x1<<8)
13277 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_USDM_FIFO_PRTY (0x1<<9)
13279 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_USDMDP_FIFO_PRTY (0x1<<10)
13281 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_XSDM_FIFO_PRTY (0x1<<11)
13283 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_TSDM_FIFO_PRTY (0x1<<12)
13285 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_CSDM_FIFO_PRTY (0x1<<13)
13287 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_CDUWR_FIFO_PRTY (0x1<<14)
13289 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_DMAE_FIFO_PRTY (0x1<<15)
13291 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_DBG_FIFO_PRTY (0x1<<16)
13293 #define PXP2_PXP2_PRTY_MASK_0_REG_WR_HC_FIFO_PRTY (0x1<<17)
13295 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_VQ_HEAD (0x1<<18)
13297 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_COMPLETION (0x1<<19)
13299 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_COMP_CTX (0x1<<20)
13301 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_DELIVERY1 (0x1<<21)
13303 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_SR_DELIVERY2 (0x1<<22)
13305 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER1 (0x1<<23)
13307 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER2 (0x1<<24)
13309 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER3 (0x1<<25)
13311 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER4 (0x1<<26)
13313 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER5 (0x1<<27)
13315 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER6 (0x1<<28)
13317 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER7 (0x1<<29)
13319 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_TETRIS_BUFFER8 (0x1<<30)
13321 #define PXP2_PXP2_PRTY_MASK_0_REG_RD_FIRST_BLK (0x1<<31)
13324 #define PXP2_PXP2_PRTY_STS_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
13326 #define PXP2_PXP2_PRTY_STS_1_REG_RD_SR_FREE_LIST (0x1<<1)
13328 #define PXP2_PXP2_PRTY_STS_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
13330 #define PXP2_PXP2_PRTY_STS_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
13332 #define PXP2_PXP2_PRTY_STS_1_REG_PGL_CPL (0x1<<4)
13334 #define PXP2_PXP2_PRTY_STS_1_REG_PGL_TXW (0x1<<5)
13336 #define PXP2_PXP2_PRTY_STS_1_REG_PGL_REPLAY (0x1<<6)
13338 #define PXP2_PXP2_PRTY_STS_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
13340 #define PXP2_PXP2_PRTY_STS_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
13342 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
13344 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
13346 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
13348 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
13350 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
13352 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
13354 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
13356 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
13358 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
13360 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
13362 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
13364 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
13366 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
13368 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
13370 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
13372 #define PXP2_PXP2_PRTY_STS_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
13375 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
13377 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_SR_FREE_LIST (0x1<<1)
13379 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
13381 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
13383 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_CPL (0x1<<4)
13385 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_TXW (0x1<<5)
13387 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_PGL_REPLAY (0x1<<6)
13389 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
13391 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
13393 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
13395 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
13397 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
13399 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
13401 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
13403 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
13405 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
13407 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
13409 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
13411 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
13413 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
13415 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
13417 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
13419 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
13421 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
13423 #define PXP2_PXP2_PRTY_STS_CLR_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
13426 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
13428 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_SR_FREE_LIST (0x1<<1)
13430 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
13432 #define PXP2_PXP2_PRTY_STS_WR_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
13434 #define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_CPL (0x1<<4)
13436 #define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_TXW (0x1<<5)
13438 #define PXP2_PXP2_PRTY_STS_WR_1_REG_PGL_REPLAY (0x1<<6)
13440 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
13442 #define PXP2_PXP2_PRTY_STS_WR_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
13444 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
13446 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
13448 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
13450 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
13452 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
13454 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
13456 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
13458 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
13460 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
13462 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
13464 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
13466 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
13468 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
13470 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
13472 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
13474 #define PXP2_PXP2_PRTY_STS_WR_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
13477 #define PXP2_PXP2_PRTY_MASK_1_REG_RD_NEXT_BLK_PTRS (0x1<<0)
13479 #define PXP2_PXP2_PRTY_MASK_1_REG_RD_SR_FREE_LIST (0x1<<1)
13481 #define PXP2_PXP2_PRTY_MASK_1_REG_RD_BLOCK_FREE_LIST (0x1<<2)
13483 #define PXP2_PXP2_PRTY_MASK_1_REG_HST_CPL_SYNC_FIFO (0x1<<3)
13485 #define PXP2_PXP2_PRTY_MASK_1_REG_PGL_CPL (0x1<<4)
13487 #define PXP2_PXP2_PRTY_MASK_1_REG_PGL_TXW (0x1<<5)
13489 #define PXP2_PXP2_PRTY_MASK_1_REG_PGL_REPLAY (0x1<<6)
13491 #define PXP2_PXP2_PRTY_MASK_1_REG_RD_ATC_ENTRY_ID (0x1<<7)
13493 #define PXP2_PXP2_PRTY_MASK_1_REG_HST_IREQ_SYNC_FIFO (0x1<<8)
13495 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TREQ_FIFO_PARITY_ERR (0x1<<9)
13497 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_ICPL_FIFO_PARITY_ERR (0x1<<10)
13499 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_PBF_REQ_PARITY_ERR (0x1<<11)
13501 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_QM_REQ_PARITY_ERR (0x1<<12)
13503 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TM_REQ_PARITY_ERR (0x1<<13)
13505 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_SRC_REQ_PARITY_ERR (0x1<<14)
13507 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_USDM_REQ_PARITY_ERR (0x1<<15)
13509 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_USDMDP_REQ_PARITY_ERR (0x1<<16)
13511 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_TSDM_REQ_PARITY_ERR (0x1<<17)
13513 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CSDM_REQ_PARITY_ERR (0x1<<18)
13515 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CDUWR_REQ_PARITY_ERR (0x1<<19)
13517 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_CDURD_REQ_PARITY_ERR (0x1<<20)
13519 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_DMAE_REQ_PARITY_ERR (0x1<<21)
13521 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_XSDM_REQ_PARITY_ERR (0x1<<22)
13523 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_HC_REQ_PARITY_ERR (0x1<<23)
13525 #define PXP2_PXP2_PRTY_MASK_1_REG_RQ_DBG_REQ_PARITY_ERR (0x1<<24)
13527 #define PXP2_REG_RD_INIT_MEMS_WITH_ZERO 0x12059cUL //ACCESS:RW DataWidth:0x1 Description: Debug only: '1' indicates that the following memories should be initialized with zeros or NULL values after 'start_init': tetris buffer; completion context memory; vq head memory; SR memory for delivery; first block pointers memory. This is a fix done in E1.5 to fix a parity error bug on these memories. '0' indicates not to initialize these memories; so 'start_init' will behave as in E1A0.
13533 #define PXP2_PGL_TAGS_LIMIT_REG_PGL_MAX_TAGS_DISABLE (0x1<<6)
13535 #define PXP2_REG_RQ_L2P_MODE 0x1205acUL //ACCESS:RW DataWidth:0x1 Description: will determine how the logical address is calculated; 0: as in E1; 1:with new algorithm
13537 #define PXP2_REG_RQ_ILT_MODE 0x1205b4UL //ACCESS:RW DataWidth:0x1 Description: when '0' ILT logic will work as in A0; otherwise B0; for back compatibility needs; Note that different registers are used per mode
13557 #define PXP2_REG_WR_TH_MODE_USDMDP 0x120604UL //ACCESS:RW DataWidth:0x1 Description: For USDMDP - 0 - B0 mode (E1.5-65nm) - asserts has_payload when MPS bytes are in the buffer and no outstanding sub-request grants or EOP arrived; 1 - enhanced mode (E1.5-90nm) - assert has_payload when (~pxp2.wr_usdmdp_th x 32) bytes are in the buffer or EOP arrived.
13559 #define PXP2_PXP2_INT_STS_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
13561 #define PXP2_PXP2_INT_STS_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
13563 #define PXP2_PXP2_INT_STS_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
13565 #define PXP2_PXP2_INT_STS_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
13567 #define PXP2_PXP2_INT_STS_1_REG_WR_HC_UNDERFLOW (0x1<<4)
13569 #define PXP2_PXP2_INT_STS_1_REG_RQ_ELT_ADDR (0x1<<5)
13571 #define PXP2_PXP2_INT_STS_1_REG_RQ_L2P_VF_ERR (0x1<<6)
13573 #define PXP2_PXP2_INT_STS_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
13575 #define PXP2_PXP2_INT_STS_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
13577 #define PXP2_PXP2_INT_STS_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
13579 #define PXP2_PXP2_INT_STS_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
13581 #define PXP2_PXP2_INT_STS_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
13583 #define PXP2_PXP2_INT_STS_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
13585 #define PXP2_PXP2_INT_STS_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
13587 #define PXP2_PXP2_INT_STS_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
13589 #define PXP2_PXP2_INT_STS_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
13591 #define PXP2_PXP2_INT_STS_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
13594 #define PXP2_PXP2_INT_STS_CLR_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
13596 #define PXP2_PXP2_INT_STS_CLR_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
13598 #define PXP2_PXP2_INT_STS_CLR_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
13600 #define PXP2_PXP2_INT_STS_CLR_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
13602 #define PXP2_PXP2_INT_STS_CLR_1_REG_WR_HC_UNDERFLOW (0x1<<4)
13604 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ELT_ADDR (0x1<<5)
13606 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_L2P_VF_ERR (0x1<<6)
13608 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
13610 #define PXP2_PXP2_INT_STS_CLR_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
13612 #define PXP2_PXP2_INT_STS_CLR_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
13614 #define PXP2_PXP2_INT_STS_CLR_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
13616 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
13618 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
13620 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
13622 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
13624 #define PXP2_PXP2_INT_STS_CLR_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
13626 #define PXP2_PXP2_INT_STS_CLR_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
13629 #define PXP2_PXP2_INT_STS_WR_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
13631 #define PXP2_PXP2_INT_STS_WR_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
13633 #define PXP2_PXP2_INT_STS_WR_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
13635 #define PXP2_PXP2_INT_STS_WR_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
13637 #define PXP2_PXP2_INT_STS_WR_1_REG_WR_HC_UNDERFLOW (0x1<<4)
13639 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ELT_ADDR (0x1<<5)
13641 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_L2P_VF_ERR (0x1<<6)
13643 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
13645 #define PXP2_PXP2_INT_STS_WR_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
13647 #define PXP2_PXP2_INT_STS_WR_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
13649 #define PXP2_PXP2_INT_STS_WR_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
13651 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
13653 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
13655 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
13657 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
13659 #define PXP2_PXP2_INT_STS_WR_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
13661 #define PXP2_PXP2_INT_STS_WR_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
13664 #define PXP2_PXP2_INT_MASK_1_REG_WR_USDMDP_UNDERFLOW (0x1<<0)
13666 #define PXP2_PXP2_INT_MASK_1_REG_WR_CDU_UNDERFLOW (0x1<<1)
13668 #define PXP2_PXP2_INT_MASK_1_REG_WR_DBG_UNDERFLOW (0x1<<2)
13670 #define PXP2_PXP2_INT_MASK_1_REG_WR_DMAE_UNDERFLOW (0x1<<3)
13672 #define PXP2_PXP2_INT_MASK_1_REG_WR_HC_UNDERFLOW (0x1<<4)
13674 #define PXP2_PXP2_INT_MASK_1_REG_RQ_ELT_ADDR (0x1<<5)
13676 #define PXP2_PXP2_INT_MASK_1_REG_RQ_L2P_VF_ERR (0x1<<6)
13678 #define PXP2_PXP2_INT_MASK_1_REG_RQ_CORE_WDONE_OVERFLOW (0x1<<7)
13680 #define PXP2_PXP2_INT_MASK_1_REG_HST_IREQ_FIFO_ERR (0x1<<8)
13682 #define PXP2_PXP2_INT_MASK_1_REG_RD_SR_CNT_UNDERFLOW (0x1<<9)
13684 #define PXP2_PXP2_INT_MASK_1_REG_RD_BLK_CNT_UNDERFLOW (0x1<<10)
13686 #define PXP2_PXP2_INT_MASK_1_REG_RQ_TREQ_FIFO_UNDERFLOW (0x1<<11)
13688 #define PXP2_PXP2_INT_MASK_1_REG_RQ_TREQ_FIFO_OVERFLOW (0x1<<12)
13690 #define PXP2_PXP2_INT_MASK_1_REG_RQ_ICPL_FIFO_UNDERFLOW (0x1<<13)
13692 #define PXP2_PXP2_INT_MASK_1_REG_RQ_ICPL_FIFO_OVERFLOW (0x1<<14)
13694 #define PXP2_PXP2_INT_MASK_1_REG_RQ_BACK2BACK_ATC_RESPONSE (0x1<<15)
13696 #define PXP2_PXP2_INT_MASK_1_REG_WR_PGLUE_LSR_ERROR (0x1<<16)
13699 #define PXP2_REG_RQ_ELT_DISABLE 0x12066cUL //ACCESS:RW DataWidth:0x1 Description: If 1 ILT failiue will not result in ELT access; An interrupt will be asserted
13700 #define PXP2_REG_WR_REV_MODE 0x120670UL //ACCESS:RW DataWidth:0x1 Description: For non-USDMDP clients. 0 - working in A0 mode - assert has_payload only when EOP arrived;1 - working in B0 mode - assert has_payload according to pxp2.wr_th_usdmdp or to EOP arrived.
13709 #define PXP2_REG_RQ_LOW_FREE_BYP 0x120694UL //ACCESS:RW DataWidth:0x1 Description: when 1;there cannot be more than 3 pswrq_garb_gnt for reads within 8 cycles; this can prevent the low free blocks bug
13781 #define PXP2_RD_CONF11_REG_RD_OVERRIDE_DATA_WHEN_ERROR (0x1<<16)
13783 #define PXP2_RD_CONF11_REG_RD_OVERRIDE_LAST_CYCLE_ONLY (0x1<<17)
13804 #define PXP2_REG_RQ_ATC_GLOBAL_ENABLE 0x1207c4UL //ACCESS:RW DataWidth:0x1 Description: Global ATC enable bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be the same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
13806 #define PXP2_REG_RD_ATC_GLOBAL_ENABLE 0x1207ccUL //ACCESS:RW DataWidth:0x1 Description: Global ATC enable bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated. The value of this register must be the same as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.
13811 #define PXP2_REG_RQ_ASSERT_IF_ILT_FAIL 0x120918UL //ACCESS:RW DataWidth:0x1 Description: when set - assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail due to overflow on vah_plus_1st signal (Cont00041628). If reset - interrupt will not assert
13813 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930UL //ACCESS:RW DataWidth:0x1 Description: when set the new alignment method (E2) will be applied; when reset the original alignment method (E1 E1H) will be applied
13815 #define PXP2_REG_RQ_HOQ_RAM_RD_EN 0x120938UL //ACCESS:RW DataWidth:0x1 Description: FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is disabled (i.e. rq_hoq_ram_rd_req will not have any affect)
13816 #define PXP2_REG_RD_CONTINUE_SERVING_PBF 0x12095cUL //ACCESS:RW DataWidth:0x1 Description: This register defines the delivery port behavior when finishing delivering a request to the PBF and the data for the next request is already in the Tetris buffer. 0 - The delivery port continues delivering the next PBF request only if the second delivery port is idle. This is the behavior in E1 E1H and E2. 1 - The delivery port always continues delivering the next PBF request. This is more efficient since about 11 arbitration cycles are not wasted.
13844 #define PXP2_REG_RQ_SR_CNT_WINDOW_MODE 0x1209a4UL //ACCESS:RW DataWidth:0x1 Description: Counting window mode. 0 - manual window: counting is manually being initiated & stopped by the user through GRC. 1 - configured window: counting occurs according to configured window size.
13846 #define PXP2_REG_RQ_SR_CNT_START_MODE 0x1209b8UL //ACCESS:RW DataWidth:0x1 Description: Determines the trigger for start counting (for both SR counters & global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start counting upon first PBF/USDM-DP SR that is sent to the PGLUE.
13847 #define PXP2_REG_RQ_SR_CNT_ENABLE 0x1209bcUL //ACCESS:RW DataWidth:0x1 Description: Enables the SR counting mechanism.
13897 #define PXP2_REG_RD_CPL_ERR_DETAILS_CLR 0x1207d0UL //ACCESS:W DataWidth:0x1 Description: Writing to this register clears rd_cpl_err_details and rd_cpl_err_details2 and enables logging new error details
14047 #define PXP2_REG_RQ_HOQ_RAM_RD_STATUS 0x120940UL //ACCESS:R DataWidth:0x1 Description: FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed)
14087 #define PXP2_REG_RQ_SR_CNT_MANUAL_CMD 0x1209b0UL //ACCESS:W DataWidth:0x1 Description: Write Only register. The manual window command sent by the user. Valid when working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start counting.
14089 #define PXP2_REG_RQ_SR_CNT_RST 0x1209b4UL //ACCESS:W DataWidth:0x1 Description: Write Only register. RBC write command to this reg (any value) will reset the SR counters & the global window counter. In addition it'll move the Sr_cnt_status to idle state.
14141 #define PXP_REG_HST_DISABLE_INPUTS 0x103000UL //ACCESS:RW DataWidth:0x1 Description: debug only: When '1'; inputs to the PSWHST block in clk domain are ignored
14142 #define PXP_REG_HST_ARB_IS_IDLE 0x103004UL //ACCESS:R DataWidth:0x1 Description: debug only: Indication if PSWHST arbiter is idle
14168 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
14170 #define PXP_PXP_INT_STS_0_REG_RD_POP_ERROR (0x1<<1)
14172 #define PXP_PXP_INT_STS_0_REG_RD_POP_PBF_ERROR (0x1<<2)
14174 #define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
14176 #define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
14178 #define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
14180 #define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
14182 #define PXP_PXP_INT_STS_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
14184 #define PXP_PXP_INT_STS_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
14186 #define PXP_PXP_INT_STS_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
14188 #define PXP_PXP_INT_STS_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
14190 #define PXP_PXP_INT_STS_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
14192 #define PXP_PXP_INT_STS_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
14194 #define PXP_PXP_INT_STS_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
14196 #define PXP_PXP_INT_STS_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
14198 #define PXP_PXP_INT_STS_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
14200 #define PXP_PXP_INT_STS_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
14202 #define PXP_PXP_INT_STS_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
14204 #define PXP_PXP_INT_STS_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
14206 #define PXP_PXP_INT_STS_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
14208 #define PXP_PXP_INT_STS_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
14210 #define PXP_PXP_INT_STS_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
14212 #define PXP_PXP_INT_STS_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
14214 #define PXP_PXP_INT_STS_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
14216 #define PXP_PXP_INT_STS_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
14218 #define PXP_PXP_INT_STS_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
14220 #define PXP_PXP_INT_STS_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
14222 #define PXP_PXP_INT_STS_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
14224 #define PXP_PXP_INT_STS_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
14226 #define PXP_PXP_INT_STS_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
14228 #define PXP_PXP_INT_STS_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
14230 #define PXP_PXP_INT_STS_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
14233 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
14235 #define PXP_PXP_INT_STS_CLR_0_REG_RD_POP_ERROR (0x1<<1)
14237 #define PXP_PXP_INT_STS_CLR_0_REG_RD_POP_PBF_ERROR (0x1<<2)
14239 #define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
14241 #define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
14243 #define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
14245 #define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
14247 #define PXP_PXP_INT_STS_CLR_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
14249 #define PXP_PXP_INT_STS_CLR_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
14251 #define PXP_PXP_INT_STS_CLR_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
14253 #define PXP_PXP_INT_STS_CLR_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
14255 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
14257 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
14259 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
14261 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
14263 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
14265 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
14267 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
14269 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
14271 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
14273 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
14275 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
14277 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
14279 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
14281 #define PXP_PXP_INT_STS_CLR_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
14283 #define PXP_PXP_INT_STS_CLR_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
14285 #define PXP_PXP_INT_STS_CLR_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
14287 #define PXP_PXP_INT_STS_CLR_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
14289 #define PXP_PXP_INT_STS_CLR_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
14291 #define PXP_PXP_INT_STS_CLR_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
14293 #define PXP_PXP_INT_STS_CLR_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
14295 #define PXP_PXP_INT_STS_CLR_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
14298 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
14300 #define PXP_PXP_INT_STS_WR_0_REG_RD_POP_ERROR (0x1<<1)
14302 #define PXP_PXP_INT_STS_WR_0_REG_RD_POP_PBF_ERROR (0x1<<2)
14304 #define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
14306 #define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
14308 #define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
14310 #define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
14312 #define PXP_PXP_INT_STS_WR_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
14314 #define PXP_PXP_INT_STS_WR_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
14316 #define PXP_PXP_INT_STS_WR_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
14318 #define PXP_PXP_INT_STS_WR_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
14320 #define PXP_PXP_INT_STS_WR_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
14322 #define PXP_PXP_INT_STS_WR_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
14324 #define PXP_PXP_INT_STS_WR_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
14326 #define PXP_PXP_INT_STS_WR_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
14328 #define PXP_PXP_INT_STS_WR_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
14330 #define PXP_PXP_INT_STS_WR_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
14332 #define PXP_PXP_INT_STS_WR_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
14334 #define PXP_PXP_INT_STS_WR_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
14336 #define PXP_PXP_INT_STS_WR_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
14338 #define PXP_PXP_INT_STS_WR_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
14340 #define PXP_PXP_INT_STS_WR_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
14342 #define PXP_PXP_INT_STS_WR_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
14344 #define PXP_PXP_INT_STS_WR_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
14346 #define PXP_PXP_INT_STS_WR_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
14348 #define PXP_PXP_INT_STS_WR_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
14350 #define PXP_PXP_INT_STS_WR_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
14352 #define PXP_PXP_INT_STS_WR_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
14354 #define PXP_PXP_INT_STS_WR_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
14356 #define PXP_PXP_INT_STS_WR_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
14358 #define PXP_PXP_INT_STS_WR_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
14360 #define PXP_PXP_INT_STS_WR_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
14363 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
14365 #define PXP_PXP_INT_MASK_0_REG_RD_POP_ERROR (0x1<<1)
14367 #define PXP_PXP_INT_MASK_0_REG_RD_POP_PBF_ERROR (0x1<<2)
14369 #define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO1_ERR (0x1<<3)
14371 #define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO2_ERR (0x1<<4)
14373 #define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO3_ERR (0x1<<5)
14375 #define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO4_ERR (0x1<<6)
14377 #define PXP_PXP_INT_MASK_0_REG_HST_SRC_FIFO5_ERR (0x1<<7)
14379 #define PXP_PXP_INT_MASK_0_REG_HST_HDR_SYNC_FIFO_ERR (0x1<<8)
14381 #define PXP_PXP_INT_MASK_0_REG_HST_DATA_SYNC_FIFO_ERR (0x1<<9)
14383 #define PXP_PXP_INT_MASK_0_REG_HST_CPL_SYNC_FIFO_ERR (0x1<<10)
14385 #define PXP_PXP_INT_MASK_0_REG_RQ_PBF_FIFO_OVERFLOW (0x1<<11)
14387 #define PXP_PXP_INT_MASK_0_REG_RQ_SRC_FIFO_OVERFLOW (0x1<<12)
14389 #define PXP_PXP_INT_MASK_0_REG_RQ_QM_FIFO_OVERFLOW (0x1<<13)
14391 #define PXP_PXP_INT_MASK_0_REG_RQ_TM_FIFO_OVERFLOW (0x1<<14)
14393 #define PXP_PXP_INT_MASK_0_REG_RQ_USDM_FIFO_OVERFLOW (0x1<<15)
14395 #define PXP_PXP_INT_MASK_0_REG_RQ_USDMDP_FIFO_OVERFLOW (0x1<<16)
14397 #define PXP_PXP_INT_MASK_0_REG_RQ_XSDM_FIFO_OVERFLOW (0x1<<17)
14399 #define PXP_PXP_INT_MASK_0_REG_RQ_TSDM_FIFO_OVERFLOW (0x1<<18)
14401 #define PXP_PXP_INT_MASK_0_REG_RQ_CSDM_FIFO_OVERFLOW (0x1<<19)
14403 #define PXP_PXP_INT_MASK_0_REG_RQ_CDUWR_FIFO_OVERFLOW (0x1<<20)
14405 #define PXP_PXP_INT_MASK_0_REG_RQ_CDURD_FIFO_OVERFLOW (0x1<<21)
14407 #define PXP_PXP_INT_MASK_0_REG_RQ_DMAE_FIFO_OVERFLOW (0x1<<22)
14409 #define PXP_PXP_INT_MASK_0_REG_RQ_HC_FIFO_OVERFLOW (0x1<<23)
14411 #define PXP_PXP_INT_MASK_0_REG_RQ_DBG_FIFO_OVERFLOW (0x1<<24)
14413 #define PXP_PXP_INT_MASK_0_REG_WR_SRC_FIFO_OVERFLOW (0x1<<25)
14415 #define PXP_PXP_INT_MASK_0_REG_WR_QM_FIFO_OVERFLOW (0x1<<26)
14417 #define PXP_PXP_INT_MASK_0_REG_WR_TM_FIFO_OVERFLOW (0x1<<27)
14419 #define PXP_PXP_INT_MASK_0_REG_WR_USDM_FIFO_OVERFLOW (0x1<<28)
14421 #define PXP_PXP_INT_MASK_0_REG_WR_USDMDP_FIFO_OVERFLOW (0x1<<29)
14423 #define PXP_PXP_INT_MASK_0_REG_WR_XSDM_FIFO_OVERFLOW (0x1<<30)
14425 #define PXP_PXP_INT_MASK_0_REG_WR_TSDM_FIFO_OVERFLOW (0x1<<31)
14428 #define PXP_PXP_INT_STS_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
14430 #define PXP_PXP_INT_STS_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
14432 #define PXP_PXP_INT_STS_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
14434 #define PXP_PXP_INT_STS_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
14436 #define PXP_PXP_INT_STS_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
14438 #define PXP_PXP_INT_STS_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
14440 #define PXP_PXP_INT_STS_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
14442 #define PXP_PXP_INT_STS_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
14445 #define PXP_PXP_INT_STS_CLR_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
14447 #define PXP_PXP_INT_STS_CLR_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
14449 #define PXP_PXP_INT_STS_CLR_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
14451 #define PXP_PXP_INT_STS_CLR_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
14453 #define PXP_PXP_INT_STS_CLR_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
14455 #define PXP_PXP_INT_STS_CLR_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
14457 #define PXP_PXP_INT_STS_CLR_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
14459 #define PXP_PXP_INT_STS_CLR_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
14462 #define PXP_PXP_INT_STS_WR_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
14464 #define PXP_PXP_INT_STS_WR_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
14466 #define PXP_PXP_INT_STS_WR_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
14468 #define PXP_PXP_INT_STS_WR_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
14470 #define PXP_PXP_INT_STS_WR_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
14472 #define PXP_PXP_INT_STS_WR_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
14474 #define PXP_PXP_INT_STS_WR_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
14476 #define PXP_PXP_INT_STS_WR_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
14479 #define PXP_PXP_INT_MASK_1_REG_WR_CSDM_FIFO_OVERFLOW (0x1<<0)
14481 #define PXP_PXP_INT_MASK_1_REG_WR_CDUWR_FIFO_OVERFLOW (0x1<<1)
14483 #define PXP_PXP_INT_MASK_1_REG_WR_DBG_FIFO_OVERFLOW (0x1<<2)
14485 #define PXP_PXP_INT_MASK_1_REG_WR_DMAE_FIFO_OVERFLOW (0x1<<3)
14487 #define PXP_PXP_INT_MASK_1_REG_WR_HC_FIFO_OVERFLOW (0x1<<4)
14489 #define PXP_PXP_INT_MASK_1_REG_HST_VF_DISABLED_ACCESS (0x1<<5)
14491 #define PXP_PXP_INT_MASK_1_REG_HST_INCORRECT_ACCESS (0x1<<6)
14493 #define PXP_PXP_INT_MASK_1_REG_HST_PERMISSION_VIOLATION (0x1<<7)
14496 #define PXP_PXP_PRTY_STS_REG_PARITY (0x1<<0)
14498 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO0 (0x1<<1)
14500 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO1 (0x1<<2)
14502 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO2 (0x1<<3)
14504 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO3 (0x1<<4)
14506 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO4 (0x1<<5)
14508 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO5 (0x1<<6)
14510 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO6 (0x1<<7)
14512 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO7 (0x1<<8)
14514 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO8 (0x1<<9)
14516 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO9 (0x1<<10)
14518 #define PXP_PXP_PRTY_STS_REG_RD_SYNC_FIFO10 (0x1<<11)
14520 #define PXP_PXP_PRTY_STS_REG_HST_HDR_SYNC_FIFO (0x1<<12)
14522 #define PXP_PXP_PRTY_STS_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
14524 #define PXP_PXP_PRTY_STS_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
14526 #define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO1 (0x1<<15)
14528 #define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO2 (0x1<<16)
14530 #define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO3 (0x1<<17)
14532 #define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO4 (0x1<<18)
14534 #define PXP_PXP_PRTY_STS_REG_HST_SRC_FIFO5 (0x1<<19)
14536 #define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM1 (0x1<<20)
14538 #define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM2 (0x1<<21)
14540 #define PXP_PXP_PRTY_STS_REG_HST_INBND_INT_MEM3 (0x1<<22)
14542 #define PXP_PXP_PRTY_STS_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
14544 #define PXP_PXP_PRTY_STS_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
14546 #define PXP_PXP_PRTY_STS_REG_DBGSYN_FIFO (0x1<<25)
14548 #define PXP_PXP_PRTY_STS_REG_PERM_TABLE (0x1<<26)
14551 #define PXP_PXP_PRTY_STS_CLR_REG_PARITY (0x1<<0)
14553 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO0 (0x1<<1)
14555 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO1 (0x1<<2)
14557 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO2 (0x1<<3)
14559 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO3 (0x1<<4)
14561 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO4 (0x1<<5)
14563 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO5 (0x1<<6)
14565 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO6 (0x1<<7)
14567 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO7 (0x1<<8)
14569 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO8 (0x1<<9)
14571 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO9 (0x1<<10)
14573 #define PXP_PXP_PRTY_STS_CLR_REG_RD_SYNC_FIFO10 (0x1<<11)
14575 #define PXP_PXP_PRTY_STS_CLR_REG_HST_HDR_SYNC_FIFO (0x1<<12)
14577 #define PXP_PXP_PRTY_STS_CLR_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
14579 #define PXP_PXP_PRTY_STS_CLR_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
14581 #define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO1 (0x1<<15)
14583 #define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO2 (0x1<<16)
14585 #define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO3 (0x1<<17)
14587 #define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO4 (0x1<<18)
14589 #define PXP_PXP_PRTY_STS_CLR_REG_HST_SRC_FIFO5 (0x1<<19)
14591 #define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM1 (0x1<<20)
14593 #define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM2 (0x1<<21)
14595 #define PXP_PXP_PRTY_STS_CLR_REG_HST_INBND_INT_MEM3 (0x1<<22)
14597 #define PXP_PXP_PRTY_STS_CLR_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
14599 #define PXP_PXP_PRTY_STS_CLR_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
14601 #define PXP_PXP_PRTY_STS_CLR_REG_DBGSYN_FIFO (0x1<<25)
14603 #define PXP_PXP_PRTY_STS_CLR_REG_PERM_TABLE (0x1<<26)
14606 #define PXP_PXP_PRTY_STS_WR_REG_PARITY (0x1<<0)
14608 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO0 (0x1<<1)
14610 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO1 (0x1<<2)
14612 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO2 (0x1<<3)
14614 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO3 (0x1<<4)
14616 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO4 (0x1<<5)
14618 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO5 (0x1<<6)
14620 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO6 (0x1<<7)
14622 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO7 (0x1<<8)
14624 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO8 (0x1<<9)
14626 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO9 (0x1<<10)
14628 #define PXP_PXP_PRTY_STS_WR_REG_RD_SYNC_FIFO10 (0x1<<11)
14630 #define PXP_PXP_PRTY_STS_WR_REG_HST_HDR_SYNC_FIFO (0x1<<12)
14632 #define PXP_PXP_PRTY_STS_WR_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
14634 #define PXP_PXP_PRTY_STS_WR_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
14636 #define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO1 (0x1<<15)
14638 #define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO2 (0x1<<16)
14640 #define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO3 (0x1<<17)
14642 #define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO4 (0x1<<18)
14644 #define PXP_PXP_PRTY_STS_WR_REG_HST_SRC_FIFO5 (0x1<<19)
14646 #define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM1 (0x1<<20)
14648 #define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM2 (0x1<<21)
14650 #define PXP_PXP_PRTY_STS_WR_REG_HST_INBND_INT_MEM3 (0x1<<22)
14652 #define PXP_PXP_PRTY_STS_WR_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
14654 #define PXP_PXP_PRTY_STS_WR_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
14656 #define PXP_PXP_PRTY_STS_WR_REG_DBGSYN_FIFO (0x1<<25)
14658 #define PXP_PXP_PRTY_STS_WR_REG_PERM_TABLE (0x1<<26)
14661 #define PXP_PXP_PRTY_MASK_REG_PARITY (0x1<<0)
14663 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO0 (0x1<<1)
14665 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO1 (0x1<<2)
14667 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO2 (0x1<<3)
14669 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO3 (0x1<<4)
14671 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO4 (0x1<<5)
14673 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO5 (0x1<<6)
14675 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO6 (0x1<<7)
14677 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO7 (0x1<<8)
14679 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO8 (0x1<<9)
14681 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO9 (0x1<<10)
14683 #define PXP_PXP_PRTY_MASK_REG_RD_SYNC_FIFO10 (0x1<<11)
14685 #define PXP_PXP_PRTY_MASK_REG_HST_HDR_SYNC_FIFO (0x1<<12)
14687 #define PXP_PXP_PRTY_MASK_REG_HST_DATA_SYNC_FIFO1 (0x1<<13)
14689 #define PXP_PXP_PRTY_MASK_REG_HST_DATA_SYNC_FIFO2 (0x1<<14)
14691 #define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO1 (0x1<<15)
14693 #define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO2 (0x1<<16)
14695 #define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO3 (0x1<<17)
14697 #define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO4 (0x1<<18)
14699 #define PXP_PXP_PRTY_MASK_REG_HST_SRC_FIFO5 (0x1<<19)
14701 #define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM1 (0x1<<20)
14703 #define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM2 (0x1<<21)
14705 #define PXP_PXP_PRTY_MASK_REG_HST_INBND_INT_MEM3 (0x1<<22)
14707 #define PXP_PXP_PRTY_MASK_REG_RQ_WDONE_FIFO_PRTY (0x1<<23)
14709 #define PXP_PXP_PRTY_MASK_REG_RQ_PHY_FIFO_PRTY (0x1<<24)
14711 #define PXP_PXP_PRTY_MASK_REG_DBGSYN_FIFO (0x1<<25)
14713 #define PXP_PXP_PRTY_MASK_REG_PERM_TABLE (0x1<<26)
14715 #define PXP_REG_HST_HOST_STRICT_PRIORITY 0x103098UL //ACCESS:RW DataWidth:0x1 Description: When 1; host requests have strict priority on internal write requests; as in A0. When 0; arbiter alternately chooses host requests and internal write requests.
14717 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0UL //ACCESS:R DataWidth:0x1 Description: debug only: '1' means this PSWHST is discarding doorbells. This bit should update accoring to 'hst_discard_doorbells' register when the state machine is idle
14725 #define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bcUL //ACCESS:R DataWidth:0x1 Description: 1 - An error request is logged and wasn't handled yet. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
14729 #define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030ccUL //ACCESS:R DataWidth:0x1 Description: 1 - An incorrect access is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
14731 #define PXP_REG_HST_ZONE_PERM_TABLE_INIT 0x1030d8UL //ACCESS:RW DataWidth:0x1 Description: Start the Init sequence for the zone permission table
14732 #define PXP_REG_HST_ZONE_PERM_TABLE_INIT_DONE 0x1030dcUL //ACCESS:RC DataWidth:0x1 Description: Done indication for the permission table's init sequence
14733 #define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0UL //ACCESS:R DataWidth:0x1 Description: 1- permission violation data is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1)
14735 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4UL //ACCESS:RW DataWidth:0x1 Description: When 1; doorbells are discarded and not passed to doorbell queue block. Should be used for close the gates.
14737 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8UL //ACCESS:RW DataWidth:0x1 Description: When 1; new internal writes arriving to the block are discarded. Should be used for close the gates.
14751 #define PXP_REG_HST_PORT4MODE_EN 0x1030b4UL //ACCESS:R DataWidth:0x1 Description: 4 Port mode enable bit
14758 #define QM_REG_XQM_WRC_EN 0x168004UL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 1
14760 #define QM_REG_UQM_WRC_EN 0x16800cUL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 2
14762 #define QM_REG_TQM_WRC_EN 0x168014UL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 3
14764 #define QM_REG_CQM_WRC_EN 0x16801cUL //ACCESS:RW DataWidth:0x1 Description: Enable the write client 4
14780 #define QM_REG_OVFERROR 0x16805cUL //ACCESS:RC DataWidth:0x1 Description: A flag to indicate that overflow error occurred in one of the queues.
15005 #define QM_REG_SOFT_RESET 0x168428UL //ACCESS:RW DataWidth:0x1 Description: Initialization bit command
15010 #define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
15012 #define QM_QM_INT_STS_REG_OVF_ERR (0x1<<1)
15014 #define QM_QM_INT_STS_REG_PF_USG_CNT_0_ERR (0x1<<2)
15016 #define QM_QM_INT_STS_REG_PF_USG_CNT_1_ERR (0x1<<3)
15018 #define QM_QM_INT_STS_REG_PF_USG_CNT_2_ERR (0x1<<4)
15020 #define QM_QM_INT_STS_REG_PF_USG_CNT_3_ERR (0x1<<5)
15022 #define QM_QM_INT_STS_REG_PF_USG_CNT_4_ERR (0x1<<6)
15024 #define QM_QM_INT_STS_REG_PF_USG_CNT_5_ERR (0x1<<7)
15026 #define QM_QM_INT_STS_REG_PF_USG_CNT_6_ERR (0x1<<8)
15028 #define QM_QM_INT_STS_REG_PF_USG_CNT_7_ERR (0x1<<9)
15030 #define QM_QM_INT_STS_REG_VOQ_CRD_INC_ERR (0x1<<10)
15032 #define QM_QM_INT_STS_REG_VOQ_CRD_DEC_ERR (0x1<<11)
15034 #define QM_QM_INT_STS_REG_BYTE_CRD_INC_ERR (0x1<<12)
15036 #define QM_QM_INT_STS_REG_BYTE_CRD_DEC_ERR (0x1<<13)
15039 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
15041 #define QM_QM_INT_STS_CLR_REG_OVF_ERR (0x1<<1)
15043 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_0_ERR (0x1<<2)
15045 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_1_ERR (0x1<<3)
15047 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_2_ERR (0x1<<4)
15049 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_3_ERR (0x1<<5)
15051 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_4_ERR (0x1<<6)
15053 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_5_ERR (0x1<<7)
15055 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_6_ERR (0x1<<8)
15057 #define QM_QM_INT_STS_CLR_REG_PF_USG_CNT_7_ERR (0x1<<9)
15059 #define QM_QM_INT_STS_CLR_REG_VOQ_CRD_INC_ERR (0x1<<10)
15061 #define QM_QM_INT_STS_CLR_REG_VOQ_CRD_DEC_ERR (0x1<<11)
15063 #define QM_QM_INT_STS_CLR_REG_BYTE_CRD_INC_ERR (0x1<<12)
15065 #define QM_QM_INT_STS_CLR_REG_BYTE_CRD_DEC_ERR (0x1<<13)
15068 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
15070 #define QM_QM_INT_STS_WR_REG_OVF_ERR (0x1<<1)
15072 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_0_ERR (0x1<<2)
15074 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_1_ERR (0x1<<3)
15076 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_2_ERR (0x1<<4)
15078 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_3_ERR (0x1<<5)
15080 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_4_ERR (0x1<<6)
15082 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_5_ERR (0x1<<7)
15084 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_6_ERR (0x1<<8)
15086 #define QM_QM_INT_STS_WR_REG_PF_USG_CNT_7_ERR (0x1<<9)
15088 #define QM_QM_INT_STS_WR_REG_VOQ_CRD_INC_ERR (0x1<<10)
15090 #define QM_QM_INT_STS_WR_REG_VOQ_CRD_DEC_ERR (0x1<<11)
15092 #define QM_QM_INT_STS_WR_REG_BYTE_CRD_INC_ERR (0x1<<12)
15094 #define QM_QM_INT_STS_WR_REG_BYTE_CRD_DEC_ERR (0x1<<13)
15097 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
15099 #define QM_QM_INT_MASK_REG_OVF_ERR (0x1<<1)
15101 #define QM_QM_INT_MASK_REG_PF_USG_CNT_0_ERR (0x1<<2)
15103 #define QM_QM_INT_MASK_REG_PF_USG_CNT_1_ERR (0x1<<3)
15105 #define QM_QM_INT_MASK_REG_PF_USG_CNT_2_ERR (0x1<<4)
15107 #define QM_QM_INT_MASK_REG_PF_USG_CNT_3_ERR (0x1<<5)
15109 #define QM_QM_INT_MASK_REG_PF_USG_CNT_4_ERR (0x1<<6)
15111 #define QM_QM_INT_MASK_REG_PF_USG_CNT_5_ERR (0x1<<7)
15113 #define QM_QM_INT_MASK_REG_PF_USG_CNT_6_ERR (0x1<<8)
15115 #define QM_QM_INT_MASK_REG_PF_USG_CNT_7_ERR (0x1<<9)
15117 #define QM_QM_INT_MASK_REG_VOQ_CRD_INC_ERR (0x1<<10)
15119 #define QM_QM_INT_MASK_REG_VOQ_CRD_DEC_ERR (0x1<<11)
15121 #define QM_QM_INT_MASK_REG_BYTE_CRD_INC_ERR (0x1<<12)
15123 #define QM_QM_INT_MASK_REG_BYTE_CRD_DEC_ERR (0x1<<13)
15126 #define QM_QM_PRTY_STS_REG_PARITY (0x1<<0)
15128 #define QM_QM_PRTY_STS_REG_XCM_WRC_FIFO (0x1<<1)
15130 #define QM_QM_PRTY_STS_REG_UCM_WRC_FIFO (0x1<<2)
15132 #define QM_QM_PRTY_STS_REG_TCM_WRC_FIFO (0x1<<3)
15134 #define QM_QM_PRTY_STS_REG_CCM_WRC_FIFO (0x1<<4)
15136 #define QM_QM_PRTY_STS_REG_BIGRAMHIGH (0x1<<5)
15138 #define QM_QM_PRTY_STS_REG_BIGRAMLOW (0x1<<6)
15140 #define QM_QM_PRTY_STS_REG_BASE_ADDRESS (0x1<<7)
15142 #define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
15144 #define QM_QM_PRTY_STS_REG_BIGRAMHIGH_EXT_A (0x1<<9)
15146 #define QM_QM_PRTY_STS_REG_BIGRAMLOW_EXT_A (0x1<<10)
15148 #define QM_QM_PRTY_STS_REG_BASE_ADDRESS_EXT_A (0x1<<11)
15151 #define QM_QM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
15153 #define QM_QM_PRTY_STS_CLR_REG_XCM_WRC_FIFO (0x1<<1)
15155 #define QM_QM_PRTY_STS_CLR_REG_UCM_WRC_FIFO (0x1<<2)
15157 #define QM_QM_PRTY_STS_CLR_REG_TCM_WRC_FIFO (0x1<<3)
15159 #define QM_QM_PRTY_STS_CLR_REG_CCM_WRC_FIFO (0x1<<4)
15161 #define QM_QM_PRTY_STS_CLR_REG_BIGRAMHIGH (0x1<<5)
15163 #define QM_QM_PRTY_STS_CLR_REG_BIGRAMLOW (0x1<<6)
15165 #define QM_QM_PRTY_STS_CLR_REG_BASE_ADDRESS (0x1<<7)
15167 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
15169 #define QM_QM_PRTY_STS_CLR_REG_BIGRAMHIGH_EXT_A (0x1<<9)
15171 #define QM_QM_PRTY_STS_CLR_REG_BIGRAMLOW_EXT_A (0x1<<10)
15173 #define QM_QM_PRTY_STS_CLR_REG_BASE_ADDRESS_EXT_A (0x1<<11)
15176 #define QM_QM_PRTY_STS_WR_REG_PARITY (0x1<<0)
15178 #define QM_QM_PRTY_STS_WR_REG_XCM_WRC_FIFO (0x1<<1)
15180 #define QM_QM_PRTY_STS_WR_REG_UCM_WRC_FIFO (0x1<<2)
15182 #define QM_QM_PRTY_STS_WR_REG_TCM_WRC_FIFO (0x1<<3)
15184 #define QM_QM_PRTY_STS_WR_REG_CCM_WRC_FIFO (0x1<<4)
15186 #define QM_QM_PRTY_STS_WR_REG_BIGRAMHIGH (0x1<<5)
15188 #define QM_QM_PRTY_STS_WR_REG_BIGRAMLOW (0x1<<6)
15190 #define QM_QM_PRTY_STS_WR_REG_BASE_ADDRESS (0x1<<7)
15192 #define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
15194 #define QM_QM_PRTY_STS_WR_REG_BIGRAMHIGH_EXT_A (0x1<<9)
15196 #define QM_QM_PRTY_STS_WR_REG_BIGRAMLOW_EXT_A (0x1<<10)
15198 #define QM_QM_PRTY_STS_WR_REG_BASE_ADDRESS_EXT_A (0x1<<11)
15201 #define QM_QM_PRTY_MASK_REG_PARITY (0x1<<0)
15203 #define QM_QM_PRTY_MASK_REG_XCM_WRC_FIFO (0x1<<1)
15205 #define QM_QM_PRTY_MASK_REG_UCM_WRC_FIFO (0x1<<2)
15207 #define QM_QM_PRTY_MASK_REG_TCM_WRC_FIFO (0x1<<3)
15209 #define QM_QM_PRTY_MASK_REG_CCM_WRC_FIFO (0x1<<4)
15211 #define QM_QM_PRTY_MASK_REG_BIGRAMHIGH (0x1<<5)
15213 #define QM_QM_PRTY_MASK_REG_BIGRAMLOW (0x1<<6)
15215 #define QM_QM_PRTY_MASK_REG_BASE_ADDRESS (0x1<<7)
15217 #define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
15219 #define QM_QM_PRTY_MASK_REG_BIGRAMHIGH_EXT_A (0x1<<9)
15221 #define QM_QM_PRTY_MASK_REG_BIGRAMLOW_EXT_A (0x1<<10)
15223 #define QM_QM_PRTY_MASK_REG_BASE_ADDRESS_EXT_A (0x1<<11)
15237 #define QM_REG_PCI_RD_ERR_EN 0x16e788UL //ACCESS:RW DataWidth:0x1 Description: enable pci rd error usage. When set pci rd error indication coming from the pci will set the bank with error (within pci_rd_err reg). When reset pci_rd_reg will be always 0 (i.e. not affected by the error coming from the pci).
15239 #define QM_REG_PQ_MODE 0x16e794UL //ACCESS:RW DataWidth:0x1 Description: This register affects the way the QM looks on the interfaces that involve physical queue logic (push; pop; xsdm command; xcm bypass) and takes care of the required physical queue mapping logic. the QM will map IPQN[4:0] = EPQN[4:0]. In addition when set the QM will map IPQN[5]=EPQN[6]. when reset IPQN[5]=EPQN[5].
15315 #define QM_REG_PF_EN 0x16e70cUL //ACCESS:RW DataWidth:0x1 SPLIT:8 Description: PF enable vector. Bit per PF. If set the PF is enabled
15347 #define QM_REG_VOQPORT_0 0x1682a0UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15349 #define QM_REG_VOQPORT_1 0x1682a4UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15351 #define QM_REG_VOQPORT_2 0x1682a8UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15353 #define QM_REG_VOQPORT_3 0x1682acUL //ACCESS:R DataWidth:0x1 Description: NOT USED
15355 #define QM_REG_VOQPORT_4 0x1682b0UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15357 #define QM_REG_VOQPORT_5 0x1682b4UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15359 #define QM_REG_VOQPORT_6 0x1682b8UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15361 #define QM_REG_VOQPORT_7 0x1682bcUL //ACCESS:R DataWidth:0x1 Description: NOT USED
15363 #define QM_REG_VOQPORT_8 0x1682c0UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15365 #define QM_REG_VOQPORT_9 0x1682c4UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15367 #define QM_REG_VOQPORT_10 0x1682c8UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15369 #define QM_REG_VOQPORT_11 0x1682ccUL //ACCESS:R DataWidth:0x1 Description: NOT USED
15415 #define QM_REG_BIGRAMSELUPPERQUEUES 0x16e400UL //ACCESS:R DataWidth:0x1 Description: NOT USED
15802 #define SEM_FAST_FILTER_ENABLE_REG_FILTER_CID_USE_RCRD (0x1<<2)
15804 #define SEM_FAST_FILTER_ENABLE_REG_FILTER_CID_EN (0x1<<3)
15806 #define SEM_FAST_FILTER_ENABLE_REG_FILTER_EVNT_ID_EN (0x1<<4)
15808 #define SEM_FAST_FILTER_ENABLE_REG_FILTER_DRA_SRC (0x1<<5)
15810 #define SEM_FAST_FILTER_ENABLE_REG_FILTER_DRA_SRC_EN (0x1<<6)
15822 #define SEM_FAST_REG_PWRWDOG_E40_PWRDN 0x19080UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog power down. 1 - power down; 0 - power up.Global register. Reset on POR.
15827 #define SEM_FAST_REG_PWRWDOG_E40_ACCU_RUN 0x19094UL //ACCESS:RW DataWidth:0x1 Description: Power watchdog. When 0 all registers and states are of power watchdog accu sub-module are reset. Global register. Reset on POR.
15831 #define SEM_FAST_REG_PWRWDOG_E40_DONE 0x190a4UL //ACCESS:R DataWidth:0x1 Description: Power watchdog done. Global register. Reset on POR.
15832 #define SEM_FAST_REG_SEM_FAST_PRTY_MASK 0x1ffe0UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
15833 #define SEM_FAST_SEM_FAST_PRTY_MASK_REG_PARITY (0x1<<0)
15835 #define SEM_FAST_REG_SEM_FAST_PRTY_STS_WR 0x1ffe4UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
15836 #define SEM_FAST_SEM_FAST_PRTY_STS_WR_REG_PARITY (0x1<<0)
15838 #define SEM_FAST_REG_SEM_FAST_PRTY_STS_CLR 0x1ffe8UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
15839 #define SEM_FAST_SEM_FAST_PRTY_STS_CLR_REG_PARITY (0x1<<0)
15841 #define SEM_FAST_REG_SEM_FAST_PRTY_STS 0x1ffecUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
15842 #define SEM_FAST_SEM_FAST_PRTY_STS_REG_PARITY (0x1<<0)
15844 #define SEM_FAST_REG_SEM_FAST_INT_MASK 0x1fff0UL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
15845 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
15847 #define SEM_FAST_REG_SEM_FAST_INT_STS_WR 0x1fff4UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
15848 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
15850 #define SEM_FAST_REG_SEM_FAST_INT_STS_CLR 0x1fff8UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
15851 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
15853 #define SEM_FAST_REG_SEM_FAST_INT_STS 0x1fffcUL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
15854 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
15876 #define SEM_FAST_REG_CAM_MODE 0x11440UL //ACCESS:RW DataWidth:0x1 Description: Cam mode - 0: cam width =52 bit; 1=cam width=80 bit
15878 #define SEM_FAST_REG_CAM_PRTY_EN 0x11480UL //ACCESS:RW DataWidth:0x1 Description: Cam parity enable - 0: cam read mechanism for parity check is disabled; 1- enabled
15886 #define SEM_FAST_REG_ACTIVE_REG_SET 0x12000UL //ACCESS:R DataWidth:0x1 Description: active register set of STORM. If 1 then passive register set 0 is active; other way passive register set 1 is active.
15972 #define SEM_FAST_REG_ERROR_RST 0x18800UL //ACCESS:W DataWidth:0x1 Description: reset to error interrupt
15974 #define SEM_FAST_REG_PARITY_RST 0x18840UL //ACCESS:W DataWidth:0x1 Description: reset to parity interrupt
15976 #define SEM_FAST_REG_RAM0_EXT_DISABLE 0x18880UL //ACCESS:RW DataWidth:0x1 Description: disable for SDM write to int_ram0
15978 #define SEM_FAST_REG_RAM1_EXT_DISABLE 0x188c0UL //ACCESS:RW DataWidth:0x1 Description: disable for SDM write to int_ram1
15992 #define SEM_FAST_REG_WAITP 0x18a80UL //ACCESS:RW DataWidth:0x1 Description: waitp to STORM(b0=1-set; b0=0-reset)
15994 #define SEM_FAST_REG_DEBUG_ACTIVE 0x18ac0UL //ACCESS:RW DataWidth:0x1 Description: debug active register. If set then output to debug FIFO is open
15998 #define SEM_FAST_REG_INT_WAITP_DISABLE 0x18b40UL //ACCESS:RW DataWidth:0x1 Description: disable waitp by STORM to itself. If this register equal to 1then STORE from microcode to address 0x6015 is disabled.
16000 #define SEM_FAST_REG_EXT_WAITP_DISABLE 0x18b80UL //ACCESS:RW DataWidth:0x1 Description: disable waitp from other 3 STORM
16002 #define SEM_FAST_REG_BREAKPOINT_WAITP_DISABLE 0x18bc0UL //ACCESS:RW DataWidth:0x1 Description: disable waitp by address is equal to the PcBreakpoint
16004 #define SEM_FAST_REG_DBG_WAITP_DISABLE 0x18c00UL //ACCESS:RW DataWidth:0x1 Description: disable waitp by full debug fifo for debug mode 0
16010 #define SEM_FAST_REG_CAM_BIST_EN 0x18cc0UL //ACCESS:RW DataWidth:0x1 Description: Bist enable bit for Cam
16014 #define SEM_FAST_REG_CAM_BIST_DONE 0x18d00UL //ACCESS:R DataWidth:0x1 Description: Bist done bit from CAM
16016 #define SEM_FAST_REG_CAM_BIST_GO 0x18d40UL //ACCESS:R DataWidth:0x1 Description: Bist go bit from CAM
16239 #define SRC_REG_ALLOWSHORTCUT 0x40494UL //ACCESS:RW DataWidth:0x1 Description: If set; same search shortcut is allowed.
16241 #define SRC_REG_SOFT_RST 0x4049cUL //ACCESS:RW DataWidth:0x1 Description: Reset internal state machines.
16246 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
16248 #define SRC_SRC_INT_STS_REG_MMURQ_FIFO_ERR (0x1<<1)
16250 #define SRC_SRC_INT_STS_REG_WR_FIFO_ERR (0x1<<2)
16253 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
16255 #define SRC_SRC_INT_STS_CLR_REG_MMURQ_FIFO_ERR (0x1<<1)
16257 #define SRC_SRC_INT_STS_CLR_REG_WR_FIFO_ERR (0x1<<2)
16260 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
16262 #define SRC_SRC_INT_STS_WR_REG_MMURQ_FIFO_ERR (0x1<<1)
16264 #define SRC_SRC_INT_STS_WR_REG_WR_FIFO_ERR (0x1<<2)
16267 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
16269 #define SRC_SRC_INT_MASK_REG_MMURQ_FIFO_ERR (0x1<<1)
16271 #define SRC_SRC_INT_MASK_REG_WR_FIFO_ERR (0x1<<2)
16274 #define SRC_SRC_PRTY_STS_REG_PARITY (0x1<<0)
16276 #define SRC_SRC_PRTY_STS_REG_MEM_RQ (0x1<<1)
16278 #define SRC_SRC_PRTY_STS_REG_WDATA (0x1<<2)
16281 #define SRC_SRC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
16283 #define SRC_SRC_PRTY_STS_CLR_REG_MEM_RQ (0x1<<1)
16285 #define SRC_SRC_PRTY_STS_CLR_REG_WDATA (0x1<<2)
16288 #define SRC_SRC_PRTY_STS_WR_REG_PARITY (0x1<<0)
16290 #define SRC_SRC_PRTY_STS_WR_REG_MEM_RQ (0x1<<1)
16292 #define SRC_SRC_PRTY_STS_WR_REG_WDATA (0x1<<2)
16295 #define SRC_SRC_PRTY_MASK_REG_PARITY (0x1<<0)
16297 #define SRC_SRC_PRTY_MASK_REG_MEM_RQ (0x1<<1)
16299 #define SRC_SRC_PRTY_MASK_REG_WDATA (0x1<<2)
16301 #define SRC_REG_E1HMF_ENABLE 0x404ccUL //ACCESS:RW DataWidth:0x1 Description: If clr the searcher is compatible to E1 A0 - support only two ports. If set the searcher support 8 functions.
16309 #define SRC_REG_VLAN_HASH_ENABLE 0x40564UL //ACCESS:RW DataWidth:0x1 Description: Enable for VLAN in Hash Address
16310 #define SRC_REG_ALLOWEMPTYSHORTCUT 0x40610UL //ACCESS:RW DataWidth:0x1 Description: If set; search return no match on empty shortcut is allowed.
16311 #define SRC_REG_VLAN_MATCH_DISABLE 0x40614UL //ACCESS:RW DataWidth:0x1 Description: Disable VLAN and VLAN Promiscuous Mode (vpf) matching logic
16354 #define TCM_REG_INIT 0x50000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
16355 #define TCM_REG_TCM_STORM0_IFEN 0x50004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
16356 #define TCM_REG_TCM_STORM1_IFEN 0x50008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
16357 #define TCM_REG_TCM_TQM_IFEN 0x5000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
16358 #define TCM_REG_STORM_TCM_IFEN 0x50010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16359 #define TCM_REG_TQM_TCM_IFEN 0x50014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16360 #define TCM_REG_TSDM_IFEN 0x50018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16361 #define TCM_REG_TM_TCM_IFEN 0x5001cUL //ACCESS:RW DataWidth:0x1 Description: Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16362 #define TCM_REG_PRS_IFEN 0x50020UL //ACCESS:RW DataWidth:0x1 Description: Input prs Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16363 #define TCM_REG_PBF_IFEN 0x50024UL //ACCESS:RW DataWidth:0x1 Description: Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16364 #define TCM_REG_USEM_IFEN 0x50028UL //ACCESS:RW DataWidth:0x1 Description: Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16365 #define TCM_REG_CSEM_IFEN 0x5002cUL //ACCESS:RW DataWidth:0x1 Description: Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16366 #define TCM_REG_CDU_AG_WR_IFEN 0x50030UL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
16367 #define TCM_REG_CDU_AG_RD_IFEN 0x50034UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16368 #define TCM_REG_CDU_SM_WR_IFEN 0x50038UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
16369 #define TCM_REG_CDU_SM_RD_IFEN 0x5003cUL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16370 #define TCM_REG_TCM_CFC_IFEN 0x50040UL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
16407 #define TCM_REG_TCM_TQM_USE_Q 0x500d4UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID.
16415 #define TCM_REG_GR_ARB_TYPE 0x50114UL //ACCESS:RW DataWidth:0x1 Description: Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; ~tcm_registers_gr_ld0_pr.gr_ld0_pr and ~tcm_registers_gr_ld1_pr.gr_ld1_pr.
16434 #define TCM_REG_STORM_LENGTH_MIS 0x50160UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the STORM interface.
16435 #define TCM_REG_TSDM_LENGTH_MIS 0x50164UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the SDM interface.
16436 #define TCM_REG_PRS_LENGTH_MIS 0x50168UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#6 interface.
16437 #define TCM_REG_PBF_LENGTH_MIS 0x5016cUL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#7 interface.
16438 #define TCM_REG_USEM_LENGTH_MIS 0x50170UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#8 interface.
16439 #define TCM_REG_CSEM_LENGTH_MIS 0x50174UL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the In#9 interface.
16442 #define TCM_REG_UNLOCK_MISS 0x50180UL //ACCESS:RC DataWidth:0x1 Description: Set when an error; indicating the LCID to be unlocked doesn't exist in LCID CAM; happens. Is reset on read.
16444 #define TCM_REG_CP_BUF_EMPTY 0x50188UL //ACCESS:R DataWidth:0x1 Description: CP buffer is empty status.
16463 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
16465 #define TCM_TCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
16467 #define TCM_TCM_INT_STS_REG_STORM_ERR (0x1<<2)
16469 #define TCM_TCM_INT_STS_REG_TSDM_ERR (0x1<<3)
16471 #define TCM_TCM_INT_STS_REG_PRS_ERR (0x1<<4)
16473 #define TCM_TCM_INT_STS_REG_PBF_ERR (0x1<<5)
16475 #define TCM_TCM_INT_STS_REG_USEM_ERR (0x1<<6)
16477 #define TCM_TCM_INT_STS_REG_CSEM_ERR (0x1<<7)
16479 #define TCM_TCM_INT_STS_REG_CP0_ERR (0x1<<8)
16481 #define TCM_TCM_INT_STS_REG_CP1_ERR (0x1<<9)
16483 #define TCM_TCM_INT_STS_REG_UM_ERR (0x1<<10)
16486 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
16488 #define TCM_TCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
16490 #define TCM_TCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
16492 #define TCM_TCM_INT_STS_CLR_REG_TSDM_ERR (0x1<<3)
16494 #define TCM_TCM_INT_STS_CLR_REG_PRS_ERR (0x1<<4)
16496 #define TCM_TCM_INT_STS_CLR_REG_PBF_ERR (0x1<<5)
16498 #define TCM_TCM_INT_STS_CLR_REG_USEM_ERR (0x1<<6)
16500 #define TCM_TCM_INT_STS_CLR_REG_CSEM_ERR (0x1<<7)
16502 #define TCM_TCM_INT_STS_CLR_REG_CP0_ERR (0x1<<8)
16504 #define TCM_TCM_INT_STS_CLR_REG_CP1_ERR (0x1<<9)
16506 #define TCM_TCM_INT_STS_CLR_REG_UM_ERR (0x1<<10)
16509 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
16511 #define TCM_TCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
16513 #define TCM_TCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
16515 #define TCM_TCM_INT_STS_WR_REG_TSDM_ERR (0x1<<3)
16517 #define TCM_TCM_INT_STS_WR_REG_PRS_ERR (0x1<<4)
16519 #define TCM_TCM_INT_STS_WR_REG_PBF_ERR (0x1<<5)
16521 #define TCM_TCM_INT_STS_WR_REG_USEM_ERR (0x1<<6)
16523 #define TCM_TCM_INT_STS_WR_REG_CSEM_ERR (0x1<<7)
16525 #define TCM_TCM_INT_STS_WR_REG_CP0_ERR (0x1<<8)
16527 #define TCM_TCM_INT_STS_WR_REG_CP1_ERR (0x1<<9)
16529 #define TCM_TCM_INT_STS_WR_REG_UM_ERR (0x1<<10)
16532 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
16534 #define TCM_TCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
16536 #define TCM_TCM_INT_MASK_REG_STORM_ERR (0x1<<2)
16538 #define TCM_TCM_INT_MASK_REG_TSDM_ERR (0x1<<3)
16540 #define TCM_TCM_INT_MASK_REG_PRS_ERR (0x1<<4)
16542 #define TCM_TCM_INT_MASK_REG_PBF_ERR (0x1<<5)
16544 #define TCM_TCM_INT_MASK_REG_USEM_ERR (0x1<<6)
16546 #define TCM_TCM_INT_MASK_REG_CSEM_ERR (0x1<<7)
16548 #define TCM_TCM_INT_MASK_REG_CP0_ERR (0x1<<8)
16550 #define TCM_TCM_INT_MASK_REG_CP1_ERR (0x1<<9)
16552 #define TCM_TCM_INT_MASK_REG_UM_ERR (0x1<<10)
16555 #define TCM_TCM_PRTY_STS_REG_PARITY (0x1<<0)
16557 #define TCM_TCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
16559 #define TCM_TCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
16561 #define TCM_TCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
16563 #define TCM_TCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
16565 #define TCM_TCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
16567 #define TCM_TCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
16569 #define TCM_TCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
16571 #define TCM_TCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
16573 #define TCM_TCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
16575 #define TCM_TCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
16577 #define TCM_TCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
16579 #define TCM_TCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
16581 #define TCM_TCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
16583 #define TCM_TCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
16585 #define TCM_TCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
16587 #define TCM_TCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
16589 #define TCM_TCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
16591 #define TCM_TCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
16593 #define TCM_TCM_PRTY_STS_REG_TSDM_PRTY (0x1<<19)
16595 #define TCM_TCM_PRTY_STS_REG_PRS_PRTY (0x1<<20)
16597 #define TCM_TCM_PRTY_STS_REG_PBF_PRTY (0x1<<21)
16599 #define TCM_TCM_PRTY_STS_REG_USEM_PRTY (0x1<<22)
16601 #define TCM_TCM_PRTY_STS_REG_CSEM_PRTY (0x1<<23)
16603 #define TCM_TCM_PRTY_STS_REG_CP0_PRTY (0x1<<24)
16605 #define TCM_TCM_PRTY_STS_REG_CP1_PRTY (0x1<<25)
16607 #define TCM_TCM_PRTY_STS_REG_UM_PRTY (0x1<<26)
16610 #define TCM_TCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
16612 #define TCM_TCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
16614 #define TCM_TCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
16616 #define TCM_TCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
16618 #define TCM_TCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
16620 #define TCM_TCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
16622 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
16624 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
16626 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
16628 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
16630 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
16632 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
16634 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
16636 #define TCM_TCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
16638 #define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
16640 #define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
16642 #define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
16644 #define TCM_TCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
16646 #define TCM_TCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
16648 #define TCM_TCM_PRTY_STS_CLR_REG_TSDM_PRTY (0x1<<19)
16650 #define TCM_TCM_PRTY_STS_CLR_REG_PRS_PRTY (0x1<<20)
16652 #define TCM_TCM_PRTY_STS_CLR_REG_PBF_PRTY (0x1<<21)
16654 #define TCM_TCM_PRTY_STS_CLR_REG_USEM_PRTY (0x1<<22)
16656 #define TCM_TCM_PRTY_STS_CLR_REG_CSEM_PRTY (0x1<<23)
16658 #define TCM_TCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<24)
16660 #define TCM_TCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<25)
16662 #define TCM_TCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<26)
16665 #define TCM_TCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
16667 #define TCM_TCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
16669 #define TCM_TCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
16671 #define TCM_TCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
16673 #define TCM_TCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
16675 #define TCM_TCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
16677 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
16679 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
16681 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
16683 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
16685 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
16687 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
16689 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
16691 #define TCM_TCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
16693 #define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
16695 #define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
16697 #define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
16699 #define TCM_TCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
16701 #define TCM_TCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
16703 #define TCM_TCM_PRTY_STS_WR_REG_TSDM_PRTY (0x1<<19)
16705 #define TCM_TCM_PRTY_STS_WR_REG_PRS_PRTY (0x1<<20)
16707 #define TCM_TCM_PRTY_STS_WR_REG_PBF_PRTY (0x1<<21)
16709 #define TCM_TCM_PRTY_STS_WR_REG_USEM_PRTY (0x1<<22)
16711 #define TCM_TCM_PRTY_STS_WR_REG_CSEM_PRTY (0x1<<23)
16713 #define TCM_TCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<24)
16715 #define TCM_TCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<25)
16717 #define TCM_TCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<26)
16720 #define TCM_TCM_PRTY_MASK_REG_PARITY (0x1<<0)
16722 #define TCM_TCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
16724 #define TCM_TCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
16726 #define TCM_TCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
16728 #define TCM_TCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
16730 #define TCM_TCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
16732 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
16734 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
16736 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
16738 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
16740 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
16742 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
16744 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
16746 #define TCM_TCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
16748 #define TCM_TCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
16750 #define TCM_TCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
16752 #define TCM_TCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
16754 #define TCM_TCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
16756 #define TCM_TCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
16758 #define TCM_TCM_PRTY_MASK_REG_TSDM_PRTY (0x1<<19)
16760 #define TCM_TCM_PRTY_MASK_REG_PRS_PRTY (0x1<<20)
16762 #define TCM_TCM_PRTY_MASK_REG_PBF_PRTY (0x1<<21)
16764 #define TCM_TCM_PRTY_MASK_REG_USEM_PRTY (0x1<<22)
16766 #define TCM_TCM_PRTY_MASK_REG_CSEM_PRTY (0x1<<23)
16768 #define TCM_TCM_PRTY_MASK_REG_CP0_PRTY (0x1<<24)
16770 #define TCM_TCM_PRTY_MASK_REG_CP1_PRTY (0x1<<25)
16772 #define TCM_TCM_PRTY_MASK_REG_UM_PRTY (0x1<<26)
16780 #define TCM_REG_L1ST_PAGE_MODE 0x50318UL //ACCESS:RW DataWidth:0x1 Description: L1 Storm context page mode enable. If 0 - the whole context of 256 LCIDs is visible. Possible only in legacy mode; looking only into the old per-LCID addresses and not seeing the new per-LCID addresses. If 1- page mode; when looking into all per-LCID addresses is possible but for only one page of the whole context.
16784 #define TCM_REG_UM_FIC1_FORCE 0x50330UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
16855 #define TM_REG_EN_TIMERS 0x164000UL //ACCESS:RW DataWidth:0x1 Description: Enable for Timers state machines.
16856 #define TM_REG_TIMER_SOFT_RST 0x164004UL //ACCESS:RW DataWidth:0x1 Description: Timer software reset - active high.
16857 #define TM_REG_EN_CL0_INPUT 0x164008UL //ACCESS:RW DataWidth:0x1 Description: Enable client0 input.
16858 #define TM_REG_EN_CL1_INPUT 0x16400cUL //ACCESS:RW DataWidth:0x1 Description: Enable client1 input.
16859 #define TM_REG_EN_CL2_INPUT 0x164010UL //ACCESS:RW DataWidth:0x1 Description: Enable client2 input.
16861 #define TM_REG_CLIN_ARB_TYPE 0x164020UL //ACCESS:RW DataWidth:0x1 Description: Clin arbiter type 0=roundrobbin 1=priority.
16875 #define TM_REG_PCI_NS_FLAG 0x164058UL //ACCESS:RW DataWidth:0x1 Description: NS flag for pci requests.
16876 #define TM_REG_PCI_RO_FLAG 0x16405cUL //ACCESS:RW DataWidth:0x1 Description: RO flag for pci requests.
16890 #define TM_REG_SET_ERR_FLAG 0x164094UL //ACCESS:RC DataWidth:0x1 Description: Set error flag from cmd handler.
16891 #define TM_REG_CLEAR_ERR_FLAG 0x164098UL //ACCESS:RC DataWidth:0x1 Description: Clear error flag from cmd handler.
16892 #define TM_REG_STOPALL_ERR_FLAG 0x16409cUL //ACCESS:RC DataWidth:0x1 Description: Stopall error flag from cmd handler.
16905 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8UL //ACCESS:RW DataWidth:0x1 Description: Enable real time counter.
16911 #define TM_REG_TM_INT_STS 0x1640f0UL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
16912 #define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
16914 #define TM_REG_TM_INT_STS_CLR 0x1640f4UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
16915 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
16917 #define TM_REG_TM_INT_STS_WR 0x1640f8UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
16918 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
16920 #define TM_REG_TM_INT_MASK 0x1640fcUL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
16921 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
16924 #define TM_TM_PRTY_STS_REG_PARITY (0x1<<0)
16926 #define TM_TM_PRTY_STS_REG_TM_L1_0_PARITY (0x1<<1)
16928 #define TM_TM_PRTY_STS_REG_TM_L1_1_PARITY (0x1<<2)
16930 #define TM_TM_PRTY_STS_REG_TU_BANK0_PARITY (0x1<<3)
16932 #define TM_TM_PRTY_STS_REG_TU_BANK1_PARITY (0x1<<4)
16934 #define TM_TM_PRTY_STS_REG_TU_SETCLR0_PARITY (0x1<<5)
16936 #define TM_TM_PRTY_STS_REG_TU_SETCLR1_PARITY (0x1<<6)
16939 #define TM_TM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
16941 #define TM_TM_PRTY_STS_CLR_REG_TM_L1_0_PARITY (0x1<<1)
16943 #define TM_TM_PRTY_STS_CLR_REG_TM_L1_1_PARITY (0x1<<2)
16945 #define TM_TM_PRTY_STS_CLR_REG_TU_BANK0_PARITY (0x1<<3)
16947 #define TM_TM_PRTY_STS_CLR_REG_TU_BANK1_PARITY (0x1<<4)
16949 #define TM_TM_PRTY_STS_CLR_REG_TU_SETCLR0_PARITY (0x1<<5)
16951 #define TM_TM_PRTY_STS_CLR_REG_TU_SETCLR1_PARITY (0x1<<6)
16954 #define TM_TM_PRTY_STS_WR_REG_PARITY (0x1<<0)
16956 #define TM_TM_PRTY_STS_WR_REG_TM_L1_0_PARITY (0x1<<1)
16958 #define TM_TM_PRTY_STS_WR_REG_TM_L1_1_PARITY (0x1<<2)
16960 #define TM_TM_PRTY_STS_WR_REG_TU_BANK0_PARITY (0x1<<3)
16962 #define TM_TM_PRTY_STS_WR_REG_TU_BANK1_PARITY (0x1<<4)
16964 #define TM_TM_PRTY_STS_WR_REG_TU_SETCLR0_PARITY (0x1<<5)
16966 #define TM_TM_PRTY_STS_WR_REG_TU_SETCLR1_PARITY (0x1<<6)
16969 #define TM_TM_PRTY_MASK_REG_PARITY (0x1<<0)
16971 #define TM_TM_PRTY_MASK_REG_TM_L1_0_PARITY (0x1<<1)
16973 #define TM_TM_PRTY_MASK_REG_TM_L1_1_PARITY (0x1<<2)
16975 #define TM_TM_PRTY_MASK_REG_TU_BANK0_PARITY (0x1<<3)
16977 #define TM_TM_PRTY_MASK_REG_TU_BANK1_PARITY (0x1<<4)
16979 #define TM_TM_PRTY_MASK_REG_TU_SETCLR0_PARITY (0x1<<5)
16981 #define TM_TM_PRTY_MASK_REG_TU_SETCLR1_PARITY (0x1<<6)
16983 #define TM_REG_EN_PHY0_ADDR_CACHE 0x164110UL //ACCESS:RW DataWidth:0x1 Description: Enable physical addres caching Port0.
16984 #define TM_REG_EN_PHY1_ADDR_CACHE 0x164114UL //ACCESS:RW DataWidth:0x1 Description: Enable physical addres caching Port1.
16997 #define TM_REG_AC_UPD_CHANGE_DIS 0x164150UL //ACCESS:RW DataWidth:0x1 Description: Disables ac updt change; ac updt change prevents cmd handler from pre-incr ac for expiration msg clients & incr ac as part of client out cfc load request
16998 #define TM_REG_EN_LINEAR0_TIMER 0x164014UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable Linear Engine Port0; function 0.
17000 #define TM_REG_EN_LINEAR1_TIMER 0x164018UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: Enable Linear Engine Port1; function 0.
17002 #define TM_REG_LIN0_SCAN_ON 0x1640d0UL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: Scan-on sig from lin engine 0. Active during bank-rd; scan; bank-wr; expr cfc load.
17004 #define TM_REG_LIN1_SCAN_ON 0x1640d4UL //ACCESS:R DataWidth:0x1 SPLIT:4 Description: Scan-on sig from lin engine 1. Active during bank-rd; scan; bank-wr; expr cfc load.
17028 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248UL //ACCESS:RW DataWidth:0x1 Description: Linear0 physical address valid.
17032 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258UL //ACCESS:RW DataWidth:0x1 Description: Linear1 physical address valid.
17055 #define TSDM_REG_TIMERS_TICK_ENABLE 0x42004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
17060 #define TSDM_REG_COUNTERS_WRAP 0x42018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
17100 #define TSDM_REG_AGG_INT_T_0 0x420b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
17101 #define TSDM_REG_AGG_INT_T_1 0x420bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
17102 #define TSDM_REG_AGG_INT_T_2 0x420c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
17103 #define TSDM_REG_AGG_INT_T_3 0x420c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
17104 #define TSDM_REG_AGG_INT_T_4 0x420c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
17105 #define TSDM_REG_AGG_INT_T_5 0x420ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
17106 #define TSDM_REG_AGG_INT_T_6 0x420d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
17107 #define TSDM_REG_AGG_INT_T_7 0x420d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
17108 #define TSDM_REG_AGG_INT_T_8 0x420d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
17109 #define TSDM_REG_AGG_INT_T_9 0x420dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
17110 #define TSDM_REG_AGG_INT_T_10 0x420e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
17111 #define TSDM_REG_AGG_INT_T_11 0x420e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
17112 #define TSDM_REG_AGG_INT_T_12 0x420e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
17113 #define TSDM_REG_AGG_INT_T_13 0x420ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
17114 #define TSDM_REG_AGG_INT_T_14 0x420f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
17115 #define TSDM_REG_AGG_INT_T_15 0x420f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
17116 #define TSDM_REG_AGG_INT_T_16 0x420f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
17117 #define TSDM_REG_AGG_INT_T_17 0x420fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
17118 #define TSDM_REG_AGG_INT_T_18 0x42100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
17119 #define TSDM_REG_AGG_INT_T_19 0x42104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
17120 #define TSDM_REG_AGG_INT_T_20 0x42108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
17121 #define TSDM_REG_AGG_INT_T_21 0x4210cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
17122 #define TSDM_REG_AGG_INT_T_22 0x42110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
17123 #define TSDM_REG_AGG_INT_T_23 0x42114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
17124 #define TSDM_REG_AGG_INT_T_24 0x42118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
17125 #define TSDM_REG_AGG_INT_T_25 0x4211cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
17126 #define TSDM_REG_AGG_INT_T_26 0x42120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
17127 #define TSDM_REG_AGG_INT_T_27 0x42124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
17128 #define TSDM_REG_AGG_INT_T_28 0x42128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
17129 #define TSDM_REG_AGG_INT_T_29 0x4212cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
17130 #define TSDM_REG_AGG_INT_T_30 0x42130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
17131 #define TSDM_REG_AGG_INT_T_31 0x42134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
17132 #define TSDM_REG_AGG_INT_FIC_0 0x42138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
17133 #define TSDM_REG_AGG_INT_FIC_1 0x4213cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
17134 #define TSDM_REG_AGG_INT_FIC_2 0x42140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
17135 #define TSDM_REG_AGG_INT_FIC_3 0x42144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
17136 #define TSDM_REG_AGG_INT_FIC_4 0x42148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
17137 #define TSDM_REG_AGG_INT_FIC_5 0x4214cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
17138 #define TSDM_REG_AGG_INT_FIC_6 0x42150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
17139 #define TSDM_REG_AGG_INT_FIC_7 0x42154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
17140 #define TSDM_REG_AGG_INT_FIC_8 0x42158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
17141 #define TSDM_REG_AGG_INT_FIC_9 0x4215cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
17142 #define TSDM_REG_AGG_INT_FIC_10 0x42160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
17143 #define TSDM_REG_AGG_INT_FIC_11 0x42164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
17144 #define TSDM_REG_AGG_INT_FIC_12 0x42168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
17145 #define TSDM_REG_AGG_INT_FIC_13 0x4216cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
17146 #define TSDM_REG_AGG_INT_FIC_14 0x42170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
17147 #define TSDM_REG_AGG_INT_FIC_15 0x42174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
17148 #define TSDM_REG_AGG_INT_FIC_16 0x42178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
17149 #define TSDM_REG_AGG_INT_FIC_17 0x4217cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
17150 #define TSDM_REG_AGG_INT_FIC_18 0x42180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
17151 #define TSDM_REG_AGG_INT_FIC_19 0x42184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
17152 #define TSDM_REG_AGG_INT_FIC_20 0x42188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
17153 #define TSDM_REG_AGG_INT_FIC_21 0x4218cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
17154 #define TSDM_REG_AGG_INT_FIC_22 0x42190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
17155 #define TSDM_REG_AGG_INT_FIC_23 0x42194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
17156 #define TSDM_REG_AGG_INT_FIC_24 0x42198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
17157 #define TSDM_REG_AGG_INT_FIC_25 0x4219cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
17158 #define TSDM_REG_AGG_INT_FIC_26 0x421a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
17159 #define TSDM_REG_AGG_INT_FIC_27 0x421a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
17160 #define TSDM_REG_AGG_INT_FIC_28 0x421a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
17161 #define TSDM_REG_AGG_INT_FIC_29 0x421acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
17162 #define TSDM_REG_AGG_INT_FIC_30 0x421b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
17163 #define TSDM_REG_AGG_INT_FIC_31 0x421b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
17164 #define TSDM_REG_AGG_INT_MODE_0 0x421b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17165 #define TSDM_REG_AGG_INT_MODE_1 0x421bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17166 #define TSDM_REG_AGG_INT_MODE_2 0x421c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17167 #define TSDM_REG_AGG_INT_MODE_3 0x421c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17168 #define TSDM_REG_AGG_INT_MODE_4 0x421c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17169 #define TSDM_REG_AGG_INT_MODE_5 0x421ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17170 #define TSDM_REG_AGG_INT_MODE_6 0x421d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17171 #define TSDM_REG_AGG_INT_MODE_7 0x421d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17172 #define TSDM_REG_AGG_INT_MODE_8 0x421d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17173 #define TSDM_REG_AGG_INT_MODE_9 0x421dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17174 #define TSDM_REG_AGG_INT_MODE_10 0x421e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17175 #define TSDM_REG_AGG_INT_MODE_11 0x421e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17176 #define TSDM_REG_AGG_INT_MODE_12 0x421e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17177 #define TSDM_REG_AGG_INT_MODE_13 0x421ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17178 #define TSDM_REG_AGG_INT_MODE_14 0x421f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17179 #define TSDM_REG_AGG_INT_MODE_15 0x421f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17180 #define TSDM_REG_AGG_INT_MODE_16 0x421f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
17181 #define TSDM_REG_AGG_INT_MODE_17 0x421fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
17182 #define TSDM_REG_AGG_INT_MODE_18 0x42200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17183 #define TSDM_REG_AGG_INT_MODE_19 0x42204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17184 #define TSDM_REG_AGG_INT_MODE_20 0x42208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17185 #define TSDM_REG_AGG_INT_MODE_21 0x4220cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17186 #define TSDM_REG_AGG_INT_MODE_22 0x42210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17187 #define TSDM_REG_AGG_INT_MODE_23 0x42214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17188 #define TSDM_REG_AGG_INT_MODE_24 0x42218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17189 #define TSDM_REG_AGG_INT_MODE_25 0x4221cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17190 #define TSDM_REG_AGG_INT_MODE_26 0x42220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17191 #define TSDM_REG_AGG_INT_MODE_27 0x42224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17192 #define TSDM_REG_AGG_INT_MODE_28 0x42228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17193 #define TSDM_REG_AGG_INT_MODE_29 0x4222cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17194 #define TSDM_REG_AGG_INT_MODE_30 0x42230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17195 #define TSDM_REG_AGG_INT_MODE_31 0x42234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
17197 #define TSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
17199 #define TSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
17201 #define TSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
17203 #define TSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
17205 #define TSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
17207 #define TSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
17209 #define TSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
17211 #define TSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
17213 #define TSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
17215 #define TSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
17217 #define TSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
17219 #define TSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
17221 #define TSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
17223 #define TSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
17225 #define TSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
17227 #define TSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
17229 #define TSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
17231 #define TSDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
17233 #define TSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
17235 #define TSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
17237 #define TSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
17239 #define TSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
17241 #define TSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
17243 #define TSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
17245 #define TSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
17247 #define TSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
17249 #define TSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
17252 #define TSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
17254 #define TSDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
17256 #define TSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
17258 #define TSDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
17260 #define TSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
17262 #define TSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
17264 #define TSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
17267 #define TSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
17269 #define TSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
17271 #define TSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
17273 #define TSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
17275 #define TSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
17277 #define TSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
17279 #define TSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
17281 #define TSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
17283 #define TSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
17285 #define TSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
17287 #define TSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
17289 #define TSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
17291 #define TSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
17293 #define TSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
17295 #define TSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
17297 #define TSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
17299 #define TSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
17301 #define TSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
17303 #define TSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
17305 #define TSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
17307 #define TSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
17309 #define TSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
17311 #define TSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
17313 #define TSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
17315 #define TSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
17317 #define TSDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
17319 #define TSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
17322 #define TSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
17324 #define TSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
17326 #define TSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
17328 #define TSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
17330 #define TSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
17332 #define TSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
17353 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
17355 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
17357 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
17359 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
17361 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
17363 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
17365 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
17367 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
17369 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
17371 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
17373 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
17375 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
17377 #define TSDM_TSDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
17379 #define TSDM_TSDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
17381 #define TSDM_TSDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
17383 #define TSDM_TSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
17385 #define TSDM_TSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
17387 #define TSDM_TSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
17389 #define TSDM_TSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
17391 #define TSDM_TSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
17393 #define TSDM_TSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
17395 #define TSDM_TSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
17397 #define TSDM_TSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
17399 #define TSDM_TSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
17401 #define TSDM_TSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
17403 #define TSDM_TSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
17405 #define TSDM_TSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
17407 #define TSDM_TSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
17409 #define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
17411 #define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
17413 #define TSDM_TSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
17415 #define TSDM_TSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
17418 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
17420 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
17422 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
17424 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
17426 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
17428 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
17430 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
17432 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
17434 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
17436 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
17438 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
17440 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
17442 #define TSDM_TSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
17444 #define TSDM_TSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
17446 #define TSDM_TSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
17448 #define TSDM_TSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
17450 #define TSDM_TSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
17452 #define TSDM_TSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
17454 #define TSDM_TSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
17456 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
17458 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
17460 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
17462 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
17464 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
17466 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
17468 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
17470 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
17472 #define TSDM_TSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
17474 #define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
17476 #define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
17478 #define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
17480 #define TSDM_TSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
17483 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
17485 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
17487 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
17489 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
17491 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
17493 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
17495 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
17497 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
17499 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
17501 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
17503 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
17505 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
17507 #define TSDM_TSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
17509 #define TSDM_TSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
17511 #define TSDM_TSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
17513 #define TSDM_TSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
17515 #define TSDM_TSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
17517 #define TSDM_TSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
17519 #define TSDM_TSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
17521 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
17523 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
17525 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
17527 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
17529 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
17531 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
17533 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
17535 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
17537 #define TSDM_TSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
17539 #define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
17541 #define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
17543 #define TSDM_TSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
17545 #define TSDM_TSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
17548 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
17550 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
17552 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
17554 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
17556 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
17558 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
17560 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
17562 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
17564 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
17566 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
17568 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
17570 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
17572 #define TSDM_TSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
17574 #define TSDM_TSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
17576 #define TSDM_TSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
17578 #define TSDM_TSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
17580 #define TSDM_TSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
17582 #define TSDM_TSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
17584 #define TSDM_TSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
17586 #define TSDM_TSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
17588 #define TSDM_TSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
17590 #define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
17592 #define TSDM_TSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
17594 #define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
17596 #define TSDM_TSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
17598 #define TSDM_TSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
17600 #define TSDM_TSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
17602 #define TSDM_TSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
17604 #define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
17606 #define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
17608 #define TSDM_TSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
17610 #define TSDM_TSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
17613 #define TSDM_TSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
17615 #define TSDM_TSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
17617 #define TSDM_TSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
17619 #define TSDM_TSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
17621 #define TSDM_TSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
17623 #define TSDM_TSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
17625 #define TSDM_TSDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
17627 #define TSDM_TSDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
17629 #define TSDM_TSDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
17631 #define TSDM_TSDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
17633 #define TSDM_TSDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
17635 #define TSDM_TSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
17637 #define TSDM_TSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
17639 #define TSDM_TSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
17642 #define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
17644 #define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
17646 #define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
17648 #define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
17650 #define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
17652 #define TSDM_TSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
17654 #define TSDM_TSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
17656 #define TSDM_TSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
17658 #define TSDM_TSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
17660 #define TSDM_TSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
17662 #define TSDM_TSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
17664 #define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
17666 #define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
17668 #define TSDM_TSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
17671 #define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
17673 #define TSDM_TSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
17675 #define TSDM_TSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
17677 #define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
17679 #define TSDM_TSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
17681 #define TSDM_TSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
17683 #define TSDM_TSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
17685 #define TSDM_TSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
17687 #define TSDM_TSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
17689 #define TSDM_TSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
17691 #define TSDM_TSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
17693 #define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
17695 #define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
17697 #define TSDM_TSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
17700 #define TSDM_TSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
17702 #define TSDM_TSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
17704 #define TSDM_TSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
17706 #define TSDM_TSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
17708 #define TSDM_TSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
17710 #define TSDM_TSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
17712 #define TSDM_TSDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
17714 #define TSDM_TSDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
17716 #define TSDM_TSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
17718 #define TSDM_TSDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
17720 #define TSDM_TSDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
17722 #define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
17724 #define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
17726 #define TSDM_TSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
17729 #define TSDM_TSDM_PRTY_STS_REG_PARITY (0x1<<0)
17731 #define TSDM_TSDM_PRTY_STS_REG_TIMERS (0x1<<1)
17733 #define TSDM_TSDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
17735 #define TSDM_TSDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
17737 #define TSDM_TSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
17739 #define TSDM_TSDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
17741 #define TSDM_TSDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
17743 #define TSDM_TSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
17745 #define TSDM_TSDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
17747 #define TSDM_TSDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
17749 #define TSDM_TSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
17752 #define TSDM_TSDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
17754 #define TSDM_TSDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
17756 #define TSDM_TSDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
17758 #define TSDM_TSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
17760 #define TSDM_TSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
17762 #define TSDM_TSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
17764 #define TSDM_TSDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
17766 #define TSDM_TSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
17768 #define TSDM_TSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
17770 #define TSDM_TSDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
17772 #define TSDM_TSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
17775 #define TSDM_TSDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
17777 #define TSDM_TSDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
17779 #define TSDM_TSDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
17781 #define TSDM_TSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
17783 #define TSDM_TSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
17785 #define TSDM_TSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
17787 #define TSDM_TSDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
17789 #define TSDM_TSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
17791 #define TSDM_TSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
17793 #define TSDM_TSDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
17795 #define TSDM_TSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
17798 #define TSDM_TSDM_PRTY_MASK_REG_PARITY (0x1<<0)
17800 #define TSDM_TSDM_PRTY_MASK_REG_TIMERS (0x1<<1)
17802 #define TSDM_TSDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
17804 #define TSDM_TSDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
17806 #define TSDM_TSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
17808 #define TSDM_TSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
17810 #define TSDM_TSDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
17812 #define TSDM_TSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
17814 #define TSDM_TSDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
17816 #define TSDM_TSDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
17818 #define TSDM_TSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
17839 #define TSDM_REG_ASYNC_HOST_EMPTY 0x42408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
17841 #define TSDM_REG_ASYNC_HOST_FULL 0x4240cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
17843 #define TSDM_REG_CFC_LOAD_PEND_EMPTY 0x42410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
17845 #define TSDM_REG_CFC_LOAD_PEND_FULL 0x42414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
17847 #define TSDM_REG_CFC_LOAD_RSP_EMPTY 0x42418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
17849 #define TSDM_REG_CFC_LOAD_RSP_FULL 0x4241cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
17851 #define TSDM_REG_CM_DELAY_EMPTY 0x42420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
17853 #define TSDM_REG_CM_DELAY_FULL 0x42424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
17855 #define TSDM_REG_CM_QUEUE_EMPTY 0x42428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
17857 #define TSDM_REG_CM_QUEUE_FULL 0x4242cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
17859 #define TSDM_REG_DELAY_FIFO_EMPTY 0x42430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
17861 #define TSDM_REG_DELAY_FIFO_FULL 0x42434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
17863 #define TSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0x42438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
17865 #define TSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0x4243cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
17867 #define TSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0x42440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
17869 #define TSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0x42444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
17871 #define TSDM_REG_DST_INT_RAM_IF_FULL 0x42448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
17873 #define TSDM_REG_DST_INT_RAM_WAIT_EMPTY 0x4244cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
17875 #define TSDM_REG_DST_INT_RAM_WAIT_FULL 0x42450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
17877 #define TSDM_REG_DST_NONE_PEND_EMPTY 0x42454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
17879 #define TSDM_REG_DST_NONE_PEND_FULL 0x42458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
17881 #define TSDM_REG_DST_PAS_BUF_IF_FULL 0x4245cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
17883 #define TSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0x42460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
17885 #define TSDM_REG_DST_PAS_BUF_WAIT_FULL 0x42464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
17887 #define TSDM_REG_DST_PB_IF_FULL 0x42468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
17889 #define TSDM_REG_DST_PB_IMMED_EMPTY 0x4246cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
17891 #define TSDM_REG_DST_PB_IMMED_FULL 0x42470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
17893 #define TSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0x42474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
17895 #define TSDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0x42478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
17897 #define TSDM_REG_DST_PXP_CTRL_IF_FULL 0x4247cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
17899 #define TSDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0x42480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
17901 #define TSDM_REG_DST_PXP_CTRL_IMMED_FULL 0x42484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
17903 #define TSDM_REG_DST_PXP_CTRL_LINK_EMPTY 0x42488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
17905 #define TSDM_REG_DST_PXP_CTRL_LINK_FULL 0x4248cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
17907 #define TSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0x42490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
17909 #define TSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0x42494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
17911 #define TSDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0x42498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
17913 #define TSDM_REG_DST_PXP_DP_DST_PEND_FULL 0x4249cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
17915 #define TSDM_REG_DST_PXP_DP_IF_FULL 0x424a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
17917 #define TSDM_REG_DST_PXP_DP_LINK_EMPTY 0x424a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
17919 #define TSDM_REG_DST_PXP_DP_LINK_FULL 0x424a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
17935 #define TSDM_REG_PB_FULL 0x424c8UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
17937 #define TSDM_REG_PBF_FULL 0x424ccUL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
17939 #define TSDM_REG_PXP_DELAY_EMPTY 0x424d0UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
17941 #define TSDM_REG_PXP_DELAY_FULL 0x424d4UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
17943 #define TSDM_REG_QM_FULL 0x424d8UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
17955 #define TSDM_REG_RSP_BRB1_CTRL_IF_FULL 0x424f0UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
17957 #define TSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0x424f4UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
17959 #define TSDM_REG_RSP_BRB1_CTRL_PEND_FULL 0x424f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
17961 #define TSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0x424fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
17963 #define TSDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0x42500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
17965 #define TSDM_REG_RSP_BRB1_DP_DST_EMPTY 0x42504UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
17967 #define TSDM_REG_RSP_BRB1_DP_DST_FULL 0x42508UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
17969 #define TSDM_REG_RSP_BRB1_DP_IF_FULL 0x4250cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
17971 #define TSDM_REG_RSP_BRB1_DP_PEND_EMPTY 0x42510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
17973 #define TSDM_REG_RSP_BRB1_DP_PEND_FULL 0x42514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
17975 #define TSDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0x42518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
17977 #define TSDM_REG_RSP_BRB1_DP_RDATA_FULL 0x4251cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
17979 #define TSDM_REG_RSP_INT_RAM_PEND_EMPTY 0x42520UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
17981 #define TSDM_REG_RSP_INT_RAM_PEND_FULL 0x42524UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
17983 #define TSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0x42528UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
17985 #define TSDM_REG_RSP_INT_RAM_RDATA_FULL 0x4252cUL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
17987 #define TSDM_REG_RSP_PB_IF_FULL 0x42530UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
17989 #define TSDM_REG_RSP_PB_PEND_EMPTY 0x42534UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
17991 #define TSDM_REG_RSP_PB_PEND_FULL 0x42538UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
17993 #define TSDM_REG_RSP_PB_RDATA_EMPTY 0x4253cUL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
17995 #define TSDM_REG_RSP_PB_RDATA_FULL 0x42540UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
17997 #define TSDM_REG_RSP_PXP_CTRL_IF_FULL 0x42544UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
17999 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
18001 #define TSDM_REG_RSP_PXP_CTRL_RDATA_FULL 0x4254cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
18003 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
18005 #define TSDM_REG_SYNC_PARSER_FULL 0x42554UL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
18007 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
18009 #define TSDM_REG_SYNC_SYNC_FULL 0x4255cUL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
18011 #define TSDM_REG_TIMERS_ADDR_EMPTY 0x42560UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
18013 #define TSDM_REG_TIMERS_ADDR_FULL 0x42564UL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
18015 #define TSDM_REG_TIMERS_PEND_EMPTY 0x42568UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
18017 #define TSDM_REG_TIMERS_PEND_FULL 0x4256cUL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
18045 #define TSEM_REG_THREAD_INTER_CNT_ENABLE 0x180018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~tsem_registers_thread_inter_cnt.thread_inter_cnt
18081 #define TSEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
18083 #define TSEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
18085 #define TSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
18087 #define TSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
18089 #define TSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
18091 #define TSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
18093 #define TSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
18095 #define TSEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
18097 #define TSEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
18099 #define TSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
18101 #define TSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
18103 #define TSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
18105 #define TSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
18107 #define TSEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
18109 #define TSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
18112 #define TSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
18114 #define TSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
18116 #define TSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
18118 #define TSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
18120 #define TSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
18122 #define TSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
18124 #define TSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
18126 #define TSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
18128 #define TSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
18130 #define TSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
18139 #define TSEM_REG_CLEAR_WAITP 0x1800c8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
18141 #define TSEM_REG_SLOW_DBG_ACTIVE 0x1800d0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
18142 #define TSEM_REG_DBG_MSG_SRC 0x1800d4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~tsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
18143 #define TSEM_REG_DBG_MODE0_CFG 0x1800d8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~tsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
18145 #define TSEM_REG_DBG_MODE1_CFG 0x1800e0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~tsem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
18146 #define TSEM_REG_DBG_EACH_CYLE 0x1800e4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
18151 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
18153 #define TSEM_TSEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
18155 #define TSEM_TSEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
18157 #define TSEM_TSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
18159 #define TSEM_TSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
18161 #define TSEM_TSEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
18163 #define TSEM_TSEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
18165 #define TSEM_TSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
18167 #define TSEM_TSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
18169 #define TSEM_TSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
18171 #define TSEM_TSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
18173 #define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
18175 #define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
18177 #define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
18179 #define TSEM_TSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
18181 #define TSEM_TSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
18183 #define TSEM_TSEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
18185 #define TSEM_TSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
18187 #define TSEM_TSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
18189 #define TSEM_TSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
18191 #define TSEM_TSEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
18193 #define TSEM_TSEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
18195 #define TSEM_TSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
18197 #define TSEM_TSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
18199 #define TSEM_TSEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
18201 #define TSEM_TSEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
18203 #define TSEM_TSEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
18205 #define TSEM_TSEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
18207 #define TSEM_TSEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
18209 #define TSEM_TSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
18211 #define TSEM_TSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
18213 #define TSEM_TSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
18216 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
18218 #define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
18220 #define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
18222 #define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
18224 #define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
18226 #define TSEM_TSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
18228 #define TSEM_TSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
18230 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
18232 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
18234 #define TSEM_TSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
18236 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
18238 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
18240 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
18242 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
18244 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
18246 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
18248 #define TSEM_TSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
18250 #define TSEM_TSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
18252 #define TSEM_TSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
18254 #define TSEM_TSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
18256 #define TSEM_TSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
18258 #define TSEM_TSEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
18260 #define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
18262 #define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
18264 #define TSEM_TSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
18266 #define TSEM_TSEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
18268 #define TSEM_TSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
18270 #define TSEM_TSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
18272 #define TSEM_TSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
18274 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
18276 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
18278 #define TSEM_TSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
18281 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
18283 #define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
18285 #define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
18287 #define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
18289 #define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
18291 #define TSEM_TSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
18293 #define TSEM_TSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
18295 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
18297 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
18299 #define TSEM_TSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
18301 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
18303 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
18305 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
18307 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
18309 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
18311 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
18313 #define TSEM_TSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
18315 #define TSEM_TSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
18317 #define TSEM_TSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
18319 #define TSEM_TSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
18321 #define TSEM_TSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
18323 #define TSEM_TSEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
18325 #define TSEM_TSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
18327 #define TSEM_TSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
18329 #define TSEM_TSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
18331 #define TSEM_TSEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
18333 #define TSEM_TSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
18335 #define TSEM_TSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
18337 #define TSEM_TSEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
18339 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
18341 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
18343 #define TSEM_TSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
18346 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
18348 #define TSEM_TSEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
18350 #define TSEM_TSEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
18352 #define TSEM_TSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
18354 #define TSEM_TSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
18356 #define TSEM_TSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
18358 #define TSEM_TSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
18360 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
18362 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
18364 #define TSEM_TSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
18366 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
18368 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
18370 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
18372 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
18374 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
18376 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
18378 #define TSEM_TSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
18380 #define TSEM_TSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
18382 #define TSEM_TSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
18384 #define TSEM_TSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
18386 #define TSEM_TSEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
18388 #define TSEM_TSEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
18390 #define TSEM_TSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
18392 #define TSEM_TSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
18394 #define TSEM_TSEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
18396 #define TSEM_TSEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
18398 #define TSEM_TSEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
18400 #define TSEM_TSEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
18402 #define TSEM_TSEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
18404 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
18406 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
18408 #define TSEM_TSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
18411 #define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
18413 #define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
18415 #define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
18417 #define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
18419 #define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
18421 #define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
18423 #define TSEM_TSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
18425 #define TSEM_TSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
18427 #define TSEM_TSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
18429 #define TSEM_TSEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
18431 #define TSEM_TSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
18433 #define TSEM_TSEM_INT_STS_1_REG_VFC_INTERRUPT (0x1<<11)
18435 #define TSEM_TSEM_INT_STS_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
18438 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
18440 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
18442 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
18444 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
18446 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
18448 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
18450 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
18452 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
18454 #define TSEM_TSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
18456 #define TSEM_TSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
18458 #define TSEM_TSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
18460 #define TSEM_TSEM_INT_STS_CLR_1_REG_VFC_INTERRUPT (0x1<<11)
18462 #define TSEM_TSEM_INT_STS_CLR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
18465 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
18467 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
18469 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
18471 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
18473 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
18475 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
18477 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
18479 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
18481 #define TSEM_TSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
18483 #define TSEM_TSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
18485 #define TSEM_TSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
18487 #define TSEM_TSEM_INT_STS_WR_1_REG_VFC_INTERRUPT (0x1<<11)
18489 #define TSEM_TSEM_INT_STS_WR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
18492 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
18494 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
18496 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
18498 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
18500 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
18502 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
18504 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
18506 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
18508 #define TSEM_TSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
18510 #define TSEM_TSEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
18512 #define TSEM_TSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
18514 #define TSEM_TSEM_INT_MASK_1_REG_VFC_INTERRUPT (0x1<<11)
18516 #define TSEM_TSEM_INT_MASK_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
18519 #define TSEM_TSEM_PRTY_STS_0_REG_PARITY (0x1<<0)
18521 #define TSEM_TSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
18523 #define TSEM_TSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
18525 #define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
18527 #define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
18529 #define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
18531 #define TSEM_TSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
18533 #define TSEM_TSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
18535 #define TSEM_TSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
18537 #define TSEM_TSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
18539 #define TSEM_TSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
18541 #define TSEM_TSEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
18543 #define TSEM_TSEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
18545 #define TSEM_TSEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
18547 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
18549 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
18551 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
18553 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
18555 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
18557 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
18559 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
18561 #define TSEM_TSEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
18563 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
18565 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
18567 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
18569 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
18571 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
18573 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
18575 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
18577 #define TSEM_TSEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
18579 #define TSEM_TSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
18581 #define TSEM_TSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
18584 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
18586 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
18588 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
18590 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
18592 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
18594 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
18596 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
18598 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
18600 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
18602 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
18604 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
18606 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
18608 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
18610 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
18612 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
18614 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
18616 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
18618 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
18620 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
18622 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
18624 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
18626 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
18628 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
18630 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
18632 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
18634 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
18636 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
18638 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
18640 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
18642 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
18644 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
18646 #define TSEM_TSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
18649 #define TSEM_TSEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
18651 #define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
18653 #define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
18655 #define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
18657 #define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
18659 #define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
18661 #define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
18663 #define TSEM_TSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
18665 #define TSEM_TSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
18667 #define TSEM_TSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
18669 #define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
18671 #define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
18673 #define TSEM_TSEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
18675 #define TSEM_TSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
18677 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
18679 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
18681 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
18683 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
18685 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
18687 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
18689 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
18691 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
18693 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
18695 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
18697 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
18699 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
18701 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
18703 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
18705 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
18707 #define TSEM_TSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
18709 #define TSEM_TSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
18711 #define TSEM_TSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
18714 #define TSEM_TSEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
18716 #define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
18718 #define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
18720 #define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
18722 #define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
18724 #define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
18726 #define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
18728 #define TSEM_TSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
18730 #define TSEM_TSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
18732 #define TSEM_TSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
18734 #define TSEM_TSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
18736 #define TSEM_TSEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
18738 #define TSEM_TSEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
18740 #define TSEM_TSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
18742 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
18744 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
18746 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
18748 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
18750 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
18752 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
18754 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
18756 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
18758 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
18760 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
18762 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
18764 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
18766 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
18768 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
18770 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
18772 #define TSEM_TSEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
18774 #define TSEM_TSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
18776 #define TSEM_TSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
18779 #define TSEM_TSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
18781 #define TSEM_TSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
18783 #define TSEM_TSEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
18785 #define TSEM_TSEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
18787 #define TSEM_TSEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
18789 #define TSEM_TSEM_PRTY_STS_1_REG_VFC_PARITY (0x1<<5)
18792 #define TSEM_TSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
18794 #define TSEM_TSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
18796 #define TSEM_TSEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
18798 #define TSEM_TSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
18800 #define TSEM_TSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
18802 #define TSEM_TSEM_PRTY_STS_CLR_1_REG_VFC_PARITY (0x1<<5)
18805 #define TSEM_TSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
18807 #define TSEM_TSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
18809 #define TSEM_TSEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
18811 #define TSEM_TSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
18813 #define TSEM_TSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
18815 #define TSEM_TSEM_PRTY_STS_WR_1_REG_VFC_PARITY (0x1<<5)
18818 #define TSEM_TSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
18820 #define TSEM_TSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
18822 #define TSEM_TSEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
18824 #define TSEM_TSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
18826 #define TSEM_TSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
18828 #define TSEM_TSEM_PRTY_MASK_1_REG_VFC_PARITY (0x1<<5)
18844 #define TSEM_REG_DBG_IF_FULL 0x18020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
18846 #define TSEM_REG_DRA_EMPTY 0x180210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
18848 #define TSEM_REG_EXT_PAS_EMPTY 0x180214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
18850 #define TSEM_REG_EXT_PAS_FULL 0x180218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
18854 #define TSEM_REG_EXT_STORE_IF_FULL 0x180220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
18856 #define TSEM_REG_FIC0_DISABLE 0x180224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
18858 #define TSEM_REG_FIC0_EMPTY 0x180228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
18860 #define TSEM_REG_FIC0_FULL 0x18022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
18864 #define TSEM_REG_FIC1_DISABLE 0x180234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
18866 #define TSEM_REG_FIC1_EMPTY 0x180238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
18868 #define TSEM_REG_FIC1_FULL 0x18023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
18876 #define TSEM_REG_PAS_DISABLE 0x18024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
18878 #define TSEM_REG_PAS_IF_FULL 0x180250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
18880 #define TSEM_REG_RAM0_IF_FULL 0x180254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
18882 #define TSEM_REG_RAM1_IF_FULL 0x180258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
18884 #define TSEM_REG_SET0_THREAD_EMPTY 0x18025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
18886 #define TSEM_REG_SET0_THREAD_FULL 0x180260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
18888 #define TSEM_REG_SET1_THREAD_EMPTY 0x180264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
18890 #define TSEM_REG_SET1_THREAD_FULL 0x180268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
18894 #define TSEM_REG_SLOW_DBG_ALM_EMPTY 0x180270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
18896 #define TSEM_REG_SLOW_DBG_ALM_FULL 0x180274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
18898 #define TSEM_REG_SLOW_DBG_EMPTY 0x180278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
18900 #define TSEM_REG_SLOW_DBG_FULL 0x18027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
18902 #define TSEM_REG_SLOW_DRA_FIN_EMPTY 0x180280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
18904 #define TSEM_REG_SLOW_DRA_FIN_FULL 0x180284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
18906 #define TSEM_REG_SLOW_DRA_INT_EMPTY 0x180288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
18908 #define TSEM_REG_SLOW_DRA_INT_FULL 0x18028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
18910 #define TSEM_REG_SLOW_DRA_RD_EMPTY 0x180290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
18912 #define TSEM_REG_SLOW_DRA_RD_FULL 0x180294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
18914 #define TSEM_REG_SLOW_DRA_WR_EMPTY 0x180298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
18916 #define TSEM_REG_SLOW_DRA_WR_FULL 0x18029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
18918 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
18920 #define TSEM_REG_SLOW_EXT_STORE_FULL 0x1802a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
18922 #define TSEM_REG_SLOW_RAM0_RD_EMPTY 0x1802a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
18924 #define TSEM_REG_SLOW_RAM0_RD_FULL 0x1802acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
18926 #define TSEM_REG_SLOW_RAM0_WR_ALM_FULL 0x1802b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
18928 #define TSEM_REG_SLOW_RAM0_WR_EMPTY 0x1802b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
18930 #define TSEM_REG_SLOW_RAM0_WR_FULL 0x1802b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
18932 #define TSEM_REG_SLOW_RAM1_RD_EMPTY 0x1802bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
18934 #define TSEM_REG_SLOW_RAM1_RD_FULL 0x1802c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
18936 #define TSEM_REG_SLOW_RAM1_WR_ALM_FULL 0x1802c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
18938 #define TSEM_REG_SLOW_RAM1_WR_EMPTY 0x1802c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
18940 #define TSEM_REG_SLOW_RAM1_WR_FULL 0x1802ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
18942 #define TSEM_REG_SYNC_DBG_EMPTY 0x1802d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
18944 #define TSEM_REG_SYNC_DBG_FULL 0x1802d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync
19004 #define UCM_REG_INIT 0xe0000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
19005 #define UCM_REG_UCM_STORM0_IFEN 0xe0004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
19006 #define UCM_REG_UCM_STORM1_IFEN 0xe0008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
19007 #define UCM_REG_UCM_UQM_IFEN 0xe000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
19008 #define UCM_REG_STORM_UCM_IFEN 0xe0010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19009 #define UCM_REG_UQM_UCM_IFEN 0xe0014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19010 #define UCM_REG_USDM_IFEN 0xe0018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19011 #define UCM_REG_TM_UCM_IFEN 0xe001cUL //ACCESS:RW DataWidth:0x1 Description: Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19012 #define UCM_REG_UCM_TM_IFEN 0xe0020UL //ACCESS:RW DataWidth:0x1 Description: CM - Timers Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19013 #define UCM_REG_TSEM_IFEN 0xe0024UL //ACCESS:RW DataWidth:0x1 Description: Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19014 #define UCM_REG_CSEM_IFEN 0xe0028UL //ACCESS:RW DataWidth:0x1 Description: Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19015 #define UCM_REG_XSEM_IFEN 0xe002cUL //ACCESS:RW DataWidth:0x1 Description: Input xsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19016 #define UCM_REG_DORQ_IFEN 0xe0030UL //ACCESS:RW DataWidth:0x1 Description: Input dorq Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19017 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034UL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
19018 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19019 #define UCM_REG_CDU_SM_WR_IFEN 0xe003cUL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
19020 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19021 #define UCM_REG_UCM_CFC_IFEN 0xe0044UL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
19058 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID.
19077 #define UCM_REG_GR_ARB_TYPE 0xe0144UL //ACCESS:RW DataWidth:0x1 Description: Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; ~ucm_registers_gr_ld0_pr.gr_ld0_pr and ~ucm_registers_gr_ld1_pr.gr_ld1_pr.
19081 #define UCM_REG_STORM_LENGTH_MIS 0xe0154UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the STORM interface is detected.
19082 #define UCM_REG_USDM_LENGTH_MIS 0xe0158UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the SDM interface is detected.
19083 #define UCM_REG_TSEM_LENGTH_MIS 0xe015cUL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the tsem interface is detected.
19084 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the csem interface is detected.
19085 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the xsem interface isdetected.
19086 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168UL //ACCESS:RC DataWidth:0x1 Description: Set when the message length mismatch (relative to last indication) at the dorq interface is detected.
19089 #define UCM_REG_UNLOCK_MISS 0xe0174UL //ACCESS:RC DataWidth:0x1 Description: Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM; is detected.
19091 #define UCM_REG_CP_BUF_EMPTY 0xe017cUL //ACCESS:R DataWidth:0x1 Description: CP buffer is empty indication.
19111 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
19113 #define UCM_UCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
19115 #define UCM_UCM_INT_STS_REG_STORM_ERR (0x1<<2)
19117 #define UCM_UCM_INT_STS_REG_USDM_ERR (0x1<<3)
19119 #define UCM_UCM_INT_STS_REG_TSEM_ERR (0x1<<4)
19121 #define UCM_UCM_INT_STS_REG_CSEM_ERR (0x1<<5)
19123 #define UCM_UCM_INT_STS_REG_XSEM_ERR (0x1<<6)
19125 #define UCM_UCM_INT_STS_REG_DORQ_ERR (0x1<<7)
19127 #define UCM_UCM_INT_STS_REG_CP0_ERR (0x1<<8)
19129 #define UCM_UCM_INT_STS_REG_CP1_ERR (0x1<<9)
19131 #define UCM_UCM_INT_STS_REG_UM_ERR (0x1<<10)
19134 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
19136 #define UCM_UCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
19138 #define UCM_UCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
19140 #define UCM_UCM_INT_STS_CLR_REG_USDM_ERR (0x1<<3)
19142 #define UCM_UCM_INT_STS_CLR_REG_TSEM_ERR (0x1<<4)
19144 #define UCM_UCM_INT_STS_CLR_REG_CSEM_ERR (0x1<<5)
19146 #define UCM_UCM_INT_STS_CLR_REG_XSEM_ERR (0x1<<6)
19148 #define UCM_UCM_INT_STS_CLR_REG_DORQ_ERR (0x1<<7)
19150 #define UCM_UCM_INT_STS_CLR_REG_CP0_ERR (0x1<<8)
19152 #define UCM_UCM_INT_STS_CLR_REG_CP1_ERR (0x1<<9)
19154 #define UCM_UCM_INT_STS_CLR_REG_UM_ERR (0x1<<10)
19157 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
19159 #define UCM_UCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
19161 #define UCM_UCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
19163 #define UCM_UCM_INT_STS_WR_REG_USDM_ERR (0x1<<3)
19165 #define UCM_UCM_INT_STS_WR_REG_TSEM_ERR (0x1<<4)
19167 #define UCM_UCM_INT_STS_WR_REG_CSEM_ERR (0x1<<5)
19169 #define UCM_UCM_INT_STS_WR_REG_XSEM_ERR (0x1<<6)
19171 #define UCM_UCM_INT_STS_WR_REG_DORQ_ERR (0x1<<7)
19173 #define UCM_UCM_INT_STS_WR_REG_CP0_ERR (0x1<<8)
19175 #define UCM_UCM_INT_STS_WR_REG_CP1_ERR (0x1<<9)
19177 #define UCM_UCM_INT_STS_WR_REG_UM_ERR (0x1<<10)
19180 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
19182 #define UCM_UCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
19184 #define UCM_UCM_INT_MASK_REG_STORM_ERR (0x1<<2)
19186 #define UCM_UCM_INT_MASK_REG_USDM_ERR (0x1<<3)
19188 #define UCM_UCM_INT_MASK_REG_TSEM_ERR (0x1<<4)
19190 #define UCM_UCM_INT_MASK_REG_CSEM_ERR (0x1<<5)
19192 #define UCM_UCM_INT_MASK_REG_XSEM_ERR (0x1<<6)
19194 #define UCM_UCM_INT_MASK_REG_DORQ_ERR (0x1<<7)
19196 #define UCM_UCM_INT_MASK_REG_CP0_ERR (0x1<<8)
19198 #define UCM_UCM_INT_MASK_REG_CP1_ERR (0x1<<9)
19200 #define UCM_UCM_INT_MASK_REG_UM_ERR (0x1<<10)
19203 #define UCM_UCM_PRTY_STS_REG_PARITY (0x1<<0)
19205 #define UCM_UCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
19207 #define UCM_UCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
19209 #define UCM_UCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
19211 #define UCM_UCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
19213 #define UCM_UCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
19215 #define UCM_UCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
19217 #define UCM_UCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
19219 #define UCM_UCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
19221 #define UCM_UCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
19223 #define UCM_UCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
19225 #define UCM_UCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
19227 #define UCM_UCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
19229 #define UCM_UCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
19231 #define UCM_UCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
19233 #define UCM_UCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
19235 #define UCM_UCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
19237 #define UCM_UCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
19239 #define UCM_UCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
19241 #define UCM_UCM_PRTY_STS_REG_USDM_PRTY (0x1<<19)
19243 #define UCM_UCM_PRTY_STS_REG_TSEM_PRTY (0x1<<20)
19245 #define UCM_UCM_PRTY_STS_REG_CSEM_PRTY (0x1<<21)
19247 #define UCM_UCM_PRTY_STS_REG_XSEM_PRTY (0x1<<22)
19249 #define UCM_UCM_PRTY_STS_REG_DORQ_PRTY (0x1<<23)
19251 #define UCM_UCM_PRTY_STS_REG_CP0_PRTY (0x1<<24)
19253 #define UCM_UCM_PRTY_STS_REG_CP1_PRTY (0x1<<25)
19255 #define UCM_UCM_PRTY_STS_REG_UM_PRTY (0x1<<26)
19258 #define UCM_UCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
19260 #define UCM_UCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
19262 #define UCM_UCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
19264 #define UCM_UCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
19266 #define UCM_UCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
19268 #define UCM_UCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
19270 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
19272 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
19274 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
19276 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
19278 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
19280 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
19282 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
19284 #define UCM_UCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
19286 #define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
19288 #define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
19290 #define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
19292 #define UCM_UCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
19294 #define UCM_UCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
19296 #define UCM_UCM_PRTY_STS_CLR_REG_USDM_PRTY (0x1<<19)
19298 #define UCM_UCM_PRTY_STS_CLR_REG_TSEM_PRTY (0x1<<20)
19300 #define UCM_UCM_PRTY_STS_CLR_REG_CSEM_PRTY (0x1<<21)
19302 #define UCM_UCM_PRTY_STS_CLR_REG_XSEM_PRTY (0x1<<22)
19304 #define UCM_UCM_PRTY_STS_CLR_REG_DORQ_PRTY (0x1<<23)
19306 #define UCM_UCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<24)
19308 #define UCM_UCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<25)
19310 #define UCM_UCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<26)
19313 #define UCM_UCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
19315 #define UCM_UCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
19317 #define UCM_UCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
19319 #define UCM_UCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
19321 #define UCM_UCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
19323 #define UCM_UCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
19325 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
19327 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
19329 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
19331 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
19333 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
19335 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
19337 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
19339 #define UCM_UCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
19341 #define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
19343 #define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
19345 #define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
19347 #define UCM_UCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
19349 #define UCM_UCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
19351 #define UCM_UCM_PRTY_STS_WR_REG_USDM_PRTY (0x1<<19)
19353 #define UCM_UCM_PRTY_STS_WR_REG_TSEM_PRTY (0x1<<20)
19355 #define UCM_UCM_PRTY_STS_WR_REG_CSEM_PRTY (0x1<<21)
19357 #define UCM_UCM_PRTY_STS_WR_REG_XSEM_PRTY (0x1<<22)
19359 #define UCM_UCM_PRTY_STS_WR_REG_DORQ_PRTY (0x1<<23)
19361 #define UCM_UCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<24)
19363 #define UCM_UCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<25)
19365 #define UCM_UCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<26)
19368 #define UCM_UCM_PRTY_MASK_REG_PARITY (0x1<<0)
19370 #define UCM_UCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
19372 #define UCM_UCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
19374 #define UCM_UCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
19376 #define UCM_UCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
19378 #define UCM_UCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
19380 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
19382 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
19384 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
19386 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
19388 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
19390 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
19392 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
19394 #define UCM_UCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
19396 #define UCM_UCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
19398 #define UCM_UCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
19400 #define UCM_UCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
19402 #define UCM_UCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
19404 #define UCM_UCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
19406 #define UCM_UCM_PRTY_MASK_REG_USDM_PRTY (0x1<<19)
19408 #define UCM_UCM_PRTY_MASK_REG_TSEM_PRTY (0x1<<20)
19410 #define UCM_UCM_PRTY_MASK_REG_CSEM_PRTY (0x1<<21)
19412 #define UCM_UCM_PRTY_MASK_REG_XSEM_PRTY (0x1<<22)
19414 #define UCM_UCM_PRTY_MASK_REG_DORQ_PRTY (0x1<<23)
19416 #define UCM_UCM_PRTY_MASK_REG_CP0_PRTY (0x1<<24)
19418 #define UCM_UCM_PRTY_MASK_REG_CP1_PRTY (0x1<<25)
19420 #define UCM_UCM_PRTY_MASK_REG_UM_PRTY (0x1<<26)
19430 #define UCM_REG_UM_FIC1_FORCE 0xe0400UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
19524 #define UMAC_IPG_HD_BKP_CNTL_REG_HD_FC_ENA (0x1<<0)
19526 #define UMAC_IPG_HD_BKP_CNTL_REG_HD_FC_BKOFF_OK (0x1<<1)
19531 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
19533 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
19537 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
19539 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
19541 #define UMAC_COMMAND_CONFIG_REG_CRC_FWD (0x1<<6)
19543 #define UMAC_COMMAND_CONFIG_REG_PAUSE_FWD (0x1<<7)
19545 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
19547 #define UMAC_COMMAND_CONFIG_REG_TX_ADDR_INS (0x1<<9)
19549 #define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)
19551 #define UMAC_COMMAND_CONFIG_REG_RX_LOW_LATENCY_EN (0x1<<11)
19553 #define UMAC_COMMAND_CONFIG_REG_OVERFLOW_EN (0x1<<12)
19555 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
19557 #define UMAC_COMMAND_CONFIG_REG_FCS_CORRUPT_URUN_EN (0x1<<14)
19559 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
19561 #define UMAC_COMMAND_CONFIG_REG_MAC_LOOP_CON (0x1<<16)
19563 #define UMAC_COMMAND_CONFIG_REG_SW_OVERRIDE_TX (0x1<<17)
19565 #define UMAC_COMMAND_CONFIG_REG_SW_OVERRIDE_RX (0x1<<18)
19569 #define UMAC_COMMAND_CONFIG_REG_EN_INTERNAL_TX_CRS (0x1<<21)
19571 #define UMAC_COMMAND_CONFIG_REG_ENA_EXT_CONFIG (0x1<<22)
19573 #define UMAC_COMMAND_CONFIG_REG_CNTL_FRM_ENA (0x1<<23)
19575 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
19577 #define UMAC_COMMAND_CONFIG_REG_LINE_LOOPBACK (0x1<<25)
19579 #define UMAC_COMMAND_CONFIG_REG_RX_ERR_DISC (0x1<<26)
19581 #define UMAC_COMMAND_CONFIG_REG_PRBL_ENA (0x1<<27)
19583 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
19585 #define UMAC_COMMAND_CONFIG_REG_UNUSED_1 (0x1<<29)
19587 #define UMAC_COMMAND_CONFIG_REG_RUNT_FILTER_DIS (0x1<<30)
19596 #define UMAC_TX_TS_SEQ_ID_REG_TSTS_VALID (0x1<<16)
19602 #define UMAC_MAC_MODE_REG_MAC_DUPLEX (0x1<<2)
19604 #define UMAC_MAC_MODE_REG_MAC_RX_PAUSE (0x1<<3)
19606 #define UMAC_MAC_MODE_REG_MAC_TX_PAUSE (0x1<<4)
19608 #define UMAC_MAC_MODE_REG_LINK_STATUS (0x1<<5)
19613 #define UMAC_TAG_0_REG_CONFIG_OUTER_TPID_ENABLE (0x1<<16)
19618 #define UMAC_TAG_1_REG_CONFIG_INNER_TPID_ENABLE (0x1<<16)
19623 #define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_CONTROL (0x1<<16)
19625 #define UMAC_RX_PAUSE_QUANTA_SCALE_REG_SCALE_FIX (0x1<<17)
19633 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)
19635 #define UMAC_UMAC_EEE_CTRL_REG_RX_FIFO_CHECK (0x1<<4)
19637 #define UMAC_UMAC_EEE_CTRL_REG_EEE_TXCLK_DIS (0x1<<5)
19639 #define UMAC_UMAC_EEE_CTRL_REG_DIS_EEE_10M (0x1<<6)
19641 #define UMAC_UMAC_EEE_CTRL_REG_LP_IDLE_PREDICTION_MODE (0x1<<7)
19649 #define UMAC_UMAC_TIMESTAMP_ADJUST_REG_EN_1588 (0x1<<9)
19651 #define UMAC_UMAC_TIMESTAMP_ADJUST_REG_AUTO_ADJUST (0x1<<10)
19653 #define UMAC_REG_RX_IPG_INVAL 0x78UL //ACCESS:RW DataWidth:0x1 Description: Debug status; set if MAC receives an IPG less than programmed RX IPG or less than four bytes. Sticky bit. Clears when SW writes 0 into the field or by sw_reset.
19661 #define UMAC_MACSEC_CNTRL_REG_TX_LAUNCH_EN (0x1<<0)
19663 #define UMAC_MACSEC_CNTRL_REG_TX_CRC_CORUPT_EN (0x1<<1)
19665 #define UMAC_MACSEC_CNTRL_REG_TX_CRC_PROGRAM (0x1<<2)
19667 #define UMAC_MACSEC_CNTRL_REG_DIS_PAUSE_DATA_VAR_IPG (0x1<<3)
19670 #define UMAC_TS_STATUS_CNTRL_REG_TX_TS_FIFO_FULL (0x1<<0)
19672 #define UMAC_TS_STATUS_CNTRL_REG_TX_TS_FIFO_EMPTY (0x1<<1)
19680 #define UMAC_PAUSE_CONTROL_REG_ENABLE (0x1<<17)
19682 #define UMAC_REG_FLUSH 0x334UL //ACCESS:RW DataWidth:0x1 Description: Flush enable bit to drop out all packets in Tx FIFO without egressing any packets when set.
19684 #define UMAC_RXFIFO_STAT_REG_RXFIFO_UNDERRUN (0x1<<0)
19686 #define UMAC_RXFIFO_STAT_REG_RXFIFO_OVERRUN (0x1<<1)
19689 #define UMAC_TXFIFO_STAT_REG_TXFIFO_UNDERRUN (0x1<<0)
19691 #define UMAC_TXFIFO_STAT_REG_TXFIFO_OVERRUN (0x1<<1)
19694 #define UMAC_MAC_PFC_CTRL_REG_PFC_TX_ENBL (0x1<<0)
19696 #define UMAC_MAC_PFC_CTRL_REG_PFC_RX_ENBL (0x1<<1)
19698 #define UMAC_MAC_PFC_CTRL_REG_FORCE_PFC_XON (0x1<<2)
19700 #define UMAC_MAC_PFC_CTRL_REG_UNUSED_3 (0x1<<3)
19702 #define UMAC_MAC_PFC_CTRL_REG_RX_PASS_PFC_FRM (0x1<<4)
19704 #define UMAC_MAC_PFC_CTRL_REG_PFC_STATS_EN (0x1<<5)
19707 #define UMAC_MAC_PFC_REFRESH_CTRL_REG_PFC_REFRESH_EN (0x1<<0)
19724 #define USDM_REG_TIMERS_TICK_ENABLE 0xc4004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
19729 #define USDM_REG_COUNTERS_WRAP 0xc4018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
19769 #define USDM_REG_AGG_INT_T_0 0xc40b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
19770 #define USDM_REG_AGG_INT_T_1 0xc40bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
19771 #define USDM_REG_AGG_INT_T_2 0xc40c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
19772 #define USDM_REG_AGG_INT_T_3 0xc40c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
19773 #define USDM_REG_AGG_INT_T_4 0xc40c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
19774 #define USDM_REG_AGG_INT_T_5 0xc40ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
19775 #define USDM_REG_AGG_INT_T_6 0xc40d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
19776 #define USDM_REG_AGG_INT_T_7 0xc40d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
19777 #define USDM_REG_AGG_INT_T_8 0xc40d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
19778 #define USDM_REG_AGG_INT_T_9 0xc40dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
19779 #define USDM_REG_AGG_INT_T_10 0xc40e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
19780 #define USDM_REG_AGG_INT_T_11 0xc40e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
19781 #define USDM_REG_AGG_INT_T_12 0xc40e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
19782 #define USDM_REG_AGG_INT_T_13 0xc40ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
19783 #define USDM_REG_AGG_INT_T_14 0xc40f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
19784 #define USDM_REG_AGG_INT_T_15 0xc40f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
19785 #define USDM_REG_AGG_INT_T_16 0xc40f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
19786 #define USDM_REG_AGG_INT_T_17 0xc40fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
19787 #define USDM_REG_AGG_INT_T_18 0xc4100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
19788 #define USDM_REG_AGG_INT_T_19 0xc4104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
19789 #define USDM_REG_AGG_INT_T_20 0xc4108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
19790 #define USDM_REG_AGG_INT_T_21 0xc410cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
19791 #define USDM_REG_AGG_INT_T_22 0xc4110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
19792 #define USDM_REG_AGG_INT_T_23 0xc4114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
19793 #define USDM_REG_AGG_INT_T_24 0xc4118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
19794 #define USDM_REG_AGG_INT_T_25 0xc411cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
19795 #define USDM_REG_AGG_INT_T_26 0xc4120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
19796 #define USDM_REG_AGG_INT_T_27 0xc4124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
19797 #define USDM_REG_AGG_INT_T_28 0xc4128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
19798 #define USDM_REG_AGG_INT_T_29 0xc412cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
19799 #define USDM_REG_AGG_INT_T_30 0xc4130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
19800 #define USDM_REG_AGG_INT_T_31 0xc4134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
19801 #define USDM_REG_AGG_INT_FIC_0 0xc4138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
19802 #define USDM_REG_AGG_INT_FIC_1 0xc413cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
19803 #define USDM_REG_AGG_INT_FIC_2 0xc4140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
19804 #define USDM_REG_AGG_INT_FIC_3 0xc4144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
19805 #define USDM_REG_AGG_INT_FIC_4 0xc4148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
19806 #define USDM_REG_AGG_INT_FIC_5 0xc414cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
19807 #define USDM_REG_AGG_INT_FIC_6 0xc4150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
19808 #define USDM_REG_AGG_INT_FIC_7 0xc4154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
19809 #define USDM_REG_AGG_INT_FIC_8 0xc4158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
19810 #define USDM_REG_AGG_INT_FIC_9 0xc415cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
19811 #define USDM_REG_AGG_INT_FIC_10 0xc4160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
19812 #define USDM_REG_AGG_INT_FIC_11 0xc4164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
19813 #define USDM_REG_AGG_INT_FIC_12 0xc4168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
19814 #define USDM_REG_AGG_INT_FIC_13 0xc416cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
19815 #define USDM_REG_AGG_INT_FIC_14 0xc4170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
19816 #define USDM_REG_AGG_INT_FIC_15 0xc4174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
19817 #define USDM_REG_AGG_INT_FIC_16 0xc4178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
19818 #define USDM_REG_AGG_INT_FIC_17 0xc417cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
19819 #define USDM_REG_AGG_INT_FIC_18 0xc4180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
19820 #define USDM_REG_AGG_INT_FIC_19 0xc4184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
19821 #define USDM_REG_AGG_INT_FIC_20 0xc4188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
19822 #define USDM_REG_AGG_INT_FIC_21 0xc418cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
19823 #define USDM_REG_AGG_INT_FIC_22 0xc4190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
19824 #define USDM_REG_AGG_INT_FIC_23 0xc4194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
19825 #define USDM_REG_AGG_INT_FIC_24 0xc4198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
19826 #define USDM_REG_AGG_INT_FIC_25 0xc419cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
19827 #define USDM_REG_AGG_INT_FIC_26 0xc41a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
19828 #define USDM_REG_AGG_INT_FIC_27 0xc41a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
19829 #define USDM_REG_AGG_INT_FIC_28 0xc41a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
19830 #define USDM_REG_AGG_INT_FIC_29 0xc41acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
19831 #define USDM_REG_AGG_INT_FIC_30 0xc41b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
19832 #define USDM_REG_AGG_INT_FIC_31 0xc41b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
19833 #define USDM_REG_AGG_INT_MODE_0 0xc41b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19834 #define USDM_REG_AGG_INT_MODE_1 0xc41bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19835 #define USDM_REG_AGG_INT_MODE_2 0xc41c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19836 #define USDM_REG_AGG_INT_MODE_3 0xc41c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19837 #define USDM_REG_AGG_INT_MODE_4 0xc41c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19838 #define USDM_REG_AGG_INT_MODE_5 0xc41ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19839 #define USDM_REG_AGG_INT_MODE_6 0xc41d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19840 #define USDM_REG_AGG_INT_MODE_7 0xc41d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19841 #define USDM_REG_AGG_INT_MODE_8 0xc41d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19842 #define USDM_REG_AGG_INT_MODE_9 0xc41dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19843 #define USDM_REG_AGG_INT_MODE_10 0xc41e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19844 #define USDM_REG_AGG_INT_MODE_11 0xc41e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19845 #define USDM_REG_AGG_INT_MODE_12 0xc41e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19846 #define USDM_REG_AGG_INT_MODE_13 0xc41ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19847 #define USDM_REG_AGG_INT_MODE_14 0xc41f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19848 #define USDM_REG_AGG_INT_MODE_15 0xc41f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19849 #define USDM_REG_AGG_INT_MODE_16 0xc41f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
19850 #define USDM_REG_AGG_INT_MODE_17 0xc41fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
19851 #define USDM_REG_AGG_INT_MODE_18 0xc4200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19852 #define USDM_REG_AGG_INT_MODE_19 0xc4204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19853 #define USDM_REG_AGG_INT_MODE_20 0xc4208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19854 #define USDM_REG_AGG_INT_MODE_21 0xc420cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19855 #define USDM_REG_AGG_INT_MODE_22 0xc4210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19856 #define USDM_REG_AGG_INT_MODE_23 0xc4214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19857 #define USDM_REG_AGG_INT_MODE_24 0xc4218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19858 #define USDM_REG_AGG_INT_MODE_25 0xc421cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19859 #define USDM_REG_AGG_INT_MODE_26 0xc4220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19860 #define USDM_REG_AGG_INT_MODE_27 0xc4224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19861 #define USDM_REG_AGG_INT_MODE_28 0xc4228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19862 #define USDM_REG_AGG_INT_MODE_29 0xc422cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19863 #define USDM_REG_AGG_INT_MODE_30 0xc4230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19864 #define USDM_REG_AGG_INT_MODE_31 0xc4234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
19866 #define USDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
19868 #define USDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
19870 #define USDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
19872 #define USDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
19874 #define USDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
19876 #define USDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
19878 #define USDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
19880 #define USDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
19882 #define USDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
19884 #define USDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
19886 #define USDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
19888 #define USDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
19890 #define USDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
19892 #define USDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
19894 #define USDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
19896 #define USDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
19898 #define USDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
19900 #define USDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
19902 #define USDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
19904 #define USDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
19906 #define USDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
19908 #define USDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
19910 #define USDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
19912 #define USDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
19914 #define USDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
19916 #define USDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
19918 #define USDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
19921 #define USDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
19923 #define USDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
19925 #define USDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
19927 #define USDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
19929 #define USDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
19931 #define USDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
19933 #define USDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
19936 #define USDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
19938 #define USDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
19940 #define USDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
19942 #define USDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
19944 #define USDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
19946 #define USDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
19948 #define USDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
19950 #define USDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
19952 #define USDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
19954 #define USDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
19956 #define USDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
19958 #define USDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
19960 #define USDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
19962 #define USDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
19964 #define USDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
19966 #define USDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
19968 #define USDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
19970 #define USDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
19972 #define USDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
19974 #define USDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
19976 #define USDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
19978 #define USDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
19980 #define USDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
19982 #define USDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
19984 #define USDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
19986 #define USDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
19988 #define USDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
19991 #define USDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
19993 #define USDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
19995 #define USDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
19997 #define USDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
19999 #define USDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
20001 #define USDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
20023 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
20025 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
20027 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
20029 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
20031 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
20033 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
20035 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
20037 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
20039 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
20041 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
20043 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
20045 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
20047 #define USDM_USDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
20049 #define USDM_USDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
20051 #define USDM_USDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
20053 #define USDM_USDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
20055 #define USDM_USDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
20057 #define USDM_USDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
20059 #define USDM_USDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
20061 #define USDM_USDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
20063 #define USDM_USDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
20065 #define USDM_USDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
20067 #define USDM_USDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
20069 #define USDM_USDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
20071 #define USDM_USDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
20073 #define USDM_USDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
20075 #define USDM_USDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
20077 #define USDM_USDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
20079 #define USDM_USDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
20081 #define USDM_USDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
20083 #define USDM_USDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
20085 #define USDM_USDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
20088 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
20090 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
20092 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
20094 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
20096 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
20098 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
20100 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
20102 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
20104 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
20106 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
20108 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
20110 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
20112 #define USDM_USDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
20114 #define USDM_USDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
20116 #define USDM_USDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
20118 #define USDM_USDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
20120 #define USDM_USDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
20122 #define USDM_USDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
20124 #define USDM_USDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
20126 #define USDM_USDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
20128 #define USDM_USDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
20130 #define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
20132 #define USDM_USDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
20134 #define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
20136 #define USDM_USDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
20138 #define USDM_USDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
20140 #define USDM_USDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
20142 #define USDM_USDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
20144 #define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
20146 #define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
20148 #define USDM_USDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
20150 #define USDM_USDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
20153 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
20155 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
20157 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
20159 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
20161 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
20163 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
20165 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
20167 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
20169 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
20171 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
20173 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
20175 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
20177 #define USDM_USDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
20179 #define USDM_USDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
20181 #define USDM_USDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
20183 #define USDM_USDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
20185 #define USDM_USDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
20187 #define USDM_USDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
20189 #define USDM_USDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
20191 #define USDM_USDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
20193 #define USDM_USDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
20195 #define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
20197 #define USDM_USDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
20199 #define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
20201 #define USDM_USDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
20203 #define USDM_USDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
20205 #define USDM_USDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
20207 #define USDM_USDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
20209 #define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
20211 #define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
20213 #define USDM_USDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
20215 #define USDM_USDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
20218 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
20220 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
20222 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
20224 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
20226 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
20228 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
20230 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
20232 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
20234 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
20236 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
20238 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
20240 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
20242 #define USDM_USDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
20244 #define USDM_USDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
20246 #define USDM_USDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
20248 #define USDM_USDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
20250 #define USDM_USDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
20252 #define USDM_USDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
20254 #define USDM_USDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
20256 #define USDM_USDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
20258 #define USDM_USDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
20260 #define USDM_USDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
20262 #define USDM_USDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
20264 #define USDM_USDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
20266 #define USDM_USDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
20268 #define USDM_USDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
20270 #define USDM_USDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
20272 #define USDM_USDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
20274 #define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
20276 #define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
20278 #define USDM_USDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
20280 #define USDM_USDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
20283 #define USDM_USDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
20285 #define USDM_USDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
20287 #define USDM_USDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
20289 #define USDM_USDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
20291 #define USDM_USDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
20293 #define USDM_USDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
20295 #define USDM_USDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
20297 #define USDM_USDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
20299 #define USDM_USDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
20301 #define USDM_USDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
20303 #define USDM_USDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
20305 #define USDM_USDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
20307 #define USDM_USDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
20309 #define USDM_USDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
20312 #define USDM_USDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
20314 #define USDM_USDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
20316 #define USDM_USDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
20318 #define USDM_USDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
20320 #define USDM_USDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
20322 #define USDM_USDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
20324 #define USDM_USDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
20326 #define USDM_USDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
20328 #define USDM_USDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
20330 #define USDM_USDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
20332 #define USDM_USDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
20334 #define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
20336 #define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
20338 #define USDM_USDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
20341 #define USDM_USDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
20343 #define USDM_USDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
20345 #define USDM_USDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
20347 #define USDM_USDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
20349 #define USDM_USDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
20351 #define USDM_USDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
20353 #define USDM_USDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
20355 #define USDM_USDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
20357 #define USDM_USDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
20359 #define USDM_USDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
20361 #define USDM_USDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
20363 #define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
20365 #define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
20367 #define USDM_USDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
20370 #define USDM_USDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
20372 #define USDM_USDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
20374 #define USDM_USDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
20376 #define USDM_USDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
20378 #define USDM_USDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
20380 #define USDM_USDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
20382 #define USDM_USDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
20384 #define USDM_USDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
20386 #define USDM_USDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
20388 #define USDM_USDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
20390 #define USDM_USDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
20392 #define USDM_USDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
20394 #define USDM_USDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
20396 #define USDM_USDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
20399 #define USDM_USDM_PRTY_STS_REG_PARITY (0x1<<0)
20401 #define USDM_USDM_PRTY_STS_REG_TIMERS (0x1<<1)
20403 #define USDM_USDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
20405 #define USDM_USDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
20407 #define USDM_USDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
20409 #define USDM_USDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
20411 #define USDM_USDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
20413 #define USDM_USDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
20415 #define USDM_USDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
20417 #define USDM_USDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
20419 #define USDM_USDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
20422 #define USDM_USDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
20424 #define USDM_USDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
20426 #define USDM_USDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
20428 #define USDM_USDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
20430 #define USDM_USDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
20432 #define USDM_USDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
20434 #define USDM_USDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
20436 #define USDM_USDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
20438 #define USDM_USDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
20440 #define USDM_USDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
20442 #define USDM_USDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
20445 #define USDM_USDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
20447 #define USDM_USDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
20449 #define USDM_USDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
20451 #define USDM_USDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
20453 #define USDM_USDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
20455 #define USDM_USDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
20457 #define USDM_USDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
20459 #define USDM_USDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
20461 #define USDM_USDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
20463 #define USDM_USDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
20465 #define USDM_USDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
20468 #define USDM_USDM_PRTY_MASK_REG_PARITY (0x1<<0)
20470 #define USDM_USDM_PRTY_MASK_REG_TIMERS (0x1<<1)
20472 #define USDM_USDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
20474 #define USDM_USDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
20476 #define USDM_USDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
20478 #define USDM_USDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
20480 #define USDM_USDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
20482 #define USDM_USDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
20484 #define USDM_USDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
20486 #define USDM_USDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
20488 #define USDM_USDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
20509 #define USDM_REG_ASYNC_HOST_EMPTY 0xc4408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
20511 #define USDM_REG_ASYNC_HOST_FULL 0xc440cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
20513 #define USDM_REG_CFC_LOAD_PEND_EMPTY 0xc4410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
20515 #define USDM_REG_CFC_LOAD_PEND_FULL 0xc4414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
20517 #define USDM_REG_CFC_LOAD_RSP_EMPTY 0xc4418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
20519 #define USDM_REG_CFC_LOAD_RSP_FULL 0xc441cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
20521 #define USDM_REG_CM_DELAY_EMPTY 0xc4420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
20523 #define USDM_REG_CM_DELAY_FULL 0xc4424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
20525 #define USDM_REG_CM_QUEUE_EMPTY 0xc4428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
20527 #define USDM_REG_CM_QUEUE_FULL 0xc442cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
20529 #define USDM_REG_DELAY_FIFO_EMPTY 0xc4430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
20531 #define USDM_REG_DELAY_FIFO_FULL 0xc4434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
20533 #define USDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0xc4438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
20535 #define USDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0xc443cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
20537 #define USDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0xc4440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
20539 #define USDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0xc4444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
20541 #define USDM_REG_DST_INT_RAM_IF_FULL 0xc4448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
20543 #define USDM_REG_DST_INT_RAM_WAIT_EMPTY 0xc444cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
20545 #define USDM_REG_DST_INT_RAM_WAIT_FULL 0xc4450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
20547 #define USDM_REG_DST_NONE_PEND_EMPTY 0xc4454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
20549 #define USDM_REG_DST_NONE_PEND_FULL 0xc4458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
20551 #define USDM_REG_DST_PAS_BUF_IF_FULL 0xc445cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
20553 #define USDM_REG_DST_PAS_BUF_WAIT_EMPTY 0xc4460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
20555 #define USDM_REG_DST_PAS_BUF_WAIT_FULL 0xc4464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
20557 #define USDM_REG_DST_PB_IF_FULL 0xc4468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
20559 #define USDM_REG_DST_PB_IMMED_EMPTY 0xc446cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
20561 #define USDM_REG_DST_PB_IMMED_FULL 0xc4470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
20563 #define USDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0xc4474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
20565 #define USDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0xc4478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
20567 #define USDM_REG_DST_PXP_CTRL_IF_FULL 0xc447cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
20569 #define USDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0xc4480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
20571 #define USDM_REG_DST_PXP_CTRL_IMMED_FULL 0xc4484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
20573 #define USDM_REG_DST_PXP_CTRL_LINK_EMPTY 0xc4488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
20575 #define USDM_REG_DST_PXP_CTRL_LINK_FULL 0xc448cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
20577 #define USDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0xc4490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
20579 #define USDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0xc4494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
20581 #define USDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0xc4498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
20583 #define USDM_REG_DST_PXP_DP_DST_PEND_FULL 0xc449cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
20585 #define USDM_REG_DST_PXP_DP_IF_FULL 0xc44a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
20587 #define USDM_REG_DST_PXP_DP_LINK_EMPTY 0xc44a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
20589 #define USDM_REG_DST_PXP_DP_LINK_FULL 0xc44a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
20609 #define USDM_REG_PB_FULL 0xc44d0UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
20611 #define USDM_REG_PBF_FULL 0xc44d4UL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
20613 #define USDM_REG_PXP_DELAY_EMPTY 0xc44d8UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
20615 #define USDM_REG_PXP_DELAY_FULL 0xc44dcUL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
20617 #define USDM_REG_QM_FULL 0xc44e0UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
20629 #define USDM_REG_RSP_BRB1_CTRL_IF_FULL 0xc44f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
20631 #define USDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0xc44fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
20633 #define USDM_REG_RSP_BRB1_CTRL_PEND_FULL 0xc4500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
20635 #define USDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0xc4504UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
20637 #define USDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0xc4508UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
20639 #define USDM_REG_RSP_BRB1_DP_DST_EMPTY 0xc450cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
20641 #define USDM_REG_RSP_BRB1_DP_DST_FULL 0xc4510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
20643 #define USDM_REG_RSP_BRB1_DP_IF_FULL 0xc4514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
20645 #define USDM_REG_RSP_BRB1_DP_PEND_EMPTY 0xc4518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
20647 #define USDM_REG_RSP_BRB1_DP_PEND_FULL 0xc451cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
20649 #define USDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0xc4520UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
20651 #define USDM_REG_RSP_BRB1_DP_RDATA_FULL 0xc4524UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
20653 #define USDM_REG_RSP_INT_RAM_PEND_EMPTY 0xc4528UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
20655 #define USDM_REG_RSP_INT_RAM_PEND_FULL 0xc452cUL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
20657 #define USDM_REG_RSP_INT_RAM_RDATA_EMPTY 0xc4530UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
20659 #define USDM_REG_RSP_INT_RAM_RDATA_FULL 0xc4534UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
20661 #define USDM_REG_RSP_PB_IF_FULL 0xc4538UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
20663 #define USDM_REG_RSP_PB_PEND_EMPTY 0xc453cUL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
20665 #define USDM_REG_RSP_PB_PEND_FULL 0xc4540UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
20667 #define USDM_REG_RSP_PB_RDATA_EMPTY 0xc4544UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
20669 #define USDM_REG_RSP_PB_RDATA_FULL 0xc4548UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
20671 #define USDM_REG_RSP_PXP_CTRL_IF_FULL 0xc454cUL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
20673 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
20675 #define USDM_REG_RSP_PXP_CTRL_RDATA_FULL 0xc4554UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
20677 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
20679 #define USDM_REG_SYNC_PARSER_FULL 0xc455cUL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
20681 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
20683 #define USDM_REG_SYNC_SYNC_FULL 0xc4564UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
20685 #define USDM_REG_TIMERS_ADDR_EMPTY 0xc4568UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
20687 #define USDM_REG_TIMERS_ADDR_FULL 0xc456cUL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
20689 #define USDM_REG_TIMERS_PEND_EMPTY 0xc4570UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
20691 #define USDM_REG_TIMERS_PEND_FULL 0xc4574UL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
20717 #define USEM_REG_THREAD_INTER_CNT_ENABLE 0x300018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~usem_registers_thread_inter_cnt.thread_inter_cnt
20753 #define USEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
20755 #define USEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
20757 #define USEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
20759 #define USEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
20761 #define USEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
20763 #define USEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
20765 #define USEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
20767 #define USEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
20769 #define USEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
20771 #define USEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
20773 #define USEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
20775 #define USEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
20777 #define USEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
20779 #define USEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
20781 #define USEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
20784 #define USEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
20786 #define USEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
20788 #define USEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
20790 #define USEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
20792 #define USEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
20794 #define USEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
20796 #define USEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
20798 #define USEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
20800 #define USEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
20802 #define USEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
20815 #define USEM_REG_CLEAR_WAITP 0x3000d8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
20817 #define USEM_REG_SLOW_DBG_ACTIVE 0x3000e0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
20818 #define USEM_REG_DBG_MSG_SRC 0x3000e4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~usem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
20819 #define USEM_REG_DBG_MODE0_CFG 0x3000e8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~usem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
20821 #define USEM_REG_DBG_MODE1_CFG 0x3000f0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~usem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
20822 #define USEM_REG_DBG_EACH_CYLE 0x3000f4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
20827 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
20829 #define USEM_USEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
20831 #define USEM_USEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
20833 #define USEM_USEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
20835 #define USEM_USEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
20837 #define USEM_USEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
20839 #define USEM_USEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
20841 #define USEM_USEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
20843 #define USEM_USEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
20845 #define USEM_USEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
20847 #define USEM_USEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
20849 #define USEM_USEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
20851 #define USEM_USEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
20853 #define USEM_USEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
20855 #define USEM_USEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
20857 #define USEM_USEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
20859 #define USEM_USEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
20861 #define USEM_USEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
20863 #define USEM_USEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
20865 #define USEM_USEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
20867 #define USEM_USEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
20869 #define USEM_USEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
20871 #define USEM_USEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
20873 #define USEM_USEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
20875 #define USEM_USEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
20877 #define USEM_USEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
20879 #define USEM_USEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
20881 #define USEM_USEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
20883 #define USEM_USEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
20885 #define USEM_USEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
20887 #define USEM_USEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
20889 #define USEM_USEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
20892 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
20894 #define USEM_USEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
20896 #define USEM_USEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
20898 #define USEM_USEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
20900 #define USEM_USEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
20902 #define USEM_USEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
20904 #define USEM_USEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
20906 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
20908 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
20910 #define USEM_USEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
20912 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
20914 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
20916 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
20918 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
20920 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
20922 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
20924 #define USEM_USEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
20926 #define USEM_USEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
20928 #define USEM_USEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
20930 #define USEM_USEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
20932 #define USEM_USEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
20934 #define USEM_USEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
20936 #define USEM_USEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
20938 #define USEM_USEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
20940 #define USEM_USEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
20942 #define USEM_USEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
20944 #define USEM_USEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
20946 #define USEM_USEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
20948 #define USEM_USEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
20950 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
20952 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
20954 #define USEM_USEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
20957 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
20959 #define USEM_USEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
20961 #define USEM_USEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
20963 #define USEM_USEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
20965 #define USEM_USEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
20967 #define USEM_USEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
20969 #define USEM_USEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
20971 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
20973 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
20975 #define USEM_USEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
20977 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
20979 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
20981 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
20983 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
20985 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
20987 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
20989 #define USEM_USEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
20991 #define USEM_USEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
20993 #define USEM_USEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
20995 #define USEM_USEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
20997 #define USEM_USEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
20999 #define USEM_USEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
21001 #define USEM_USEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
21003 #define USEM_USEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
21005 #define USEM_USEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
21007 #define USEM_USEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
21009 #define USEM_USEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
21011 #define USEM_USEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
21013 #define USEM_USEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
21015 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
21017 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
21019 #define USEM_USEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
21022 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
21024 #define USEM_USEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
21026 #define USEM_USEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
21028 #define USEM_USEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
21030 #define USEM_USEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
21032 #define USEM_USEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
21034 #define USEM_USEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
21036 #define USEM_USEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
21038 #define USEM_USEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
21040 #define USEM_USEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
21042 #define USEM_USEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
21044 #define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
21046 #define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
21048 #define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
21050 #define USEM_USEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
21052 #define USEM_USEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
21054 #define USEM_USEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
21056 #define USEM_USEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
21058 #define USEM_USEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
21060 #define USEM_USEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
21062 #define USEM_USEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
21064 #define USEM_USEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
21066 #define USEM_USEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
21068 #define USEM_USEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
21070 #define USEM_USEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
21072 #define USEM_USEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
21074 #define USEM_USEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
21076 #define USEM_USEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
21078 #define USEM_USEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
21080 #define USEM_USEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
21082 #define USEM_USEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
21084 #define USEM_USEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
21087 #define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
21089 #define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
21091 #define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
21093 #define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
21095 #define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
21097 #define USEM_USEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
21099 #define USEM_USEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
21101 #define USEM_USEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
21103 #define USEM_USEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
21105 #define USEM_USEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
21107 #define USEM_USEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
21110 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
21112 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
21114 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
21116 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
21118 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
21120 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
21122 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
21124 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
21126 #define USEM_USEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
21128 #define USEM_USEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
21130 #define USEM_USEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
21133 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
21135 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
21137 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
21139 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
21141 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
21143 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
21145 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
21147 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
21149 #define USEM_USEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
21151 #define USEM_USEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
21153 #define USEM_USEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
21156 #define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
21158 #define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
21160 #define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
21162 #define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
21164 #define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
21166 #define USEM_USEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
21168 #define USEM_USEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
21170 #define USEM_USEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
21172 #define USEM_USEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
21174 #define USEM_USEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
21176 #define USEM_USEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
21179 #define USEM_USEM_PRTY_STS_0_REG_PARITY (0x1<<0)
21181 #define USEM_USEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
21183 #define USEM_USEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
21185 #define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
21187 #define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
21189 #define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
21191 #define USEM_USEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
21193 #define USEM_USEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
21195 #define USEM_USEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
21197 #define USEM_USEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
21199 #define USEM_USEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
21201 #define USEM_USEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
21203 #define USEM_USEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
21205 #define USEM_USEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
21207 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
21209 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
21211 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
21213 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
21215 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
21217 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
21219 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
21221 #define USEM_USEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
21223 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
21225 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
21227 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
21229 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
21231 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
21233 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
21235 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
21237 #define USEM_USEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
21239 #define USEM_USEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
21241 #define USEM_USEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
21244 #define USEM_USEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
21246 #define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
21248 #define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
21250 #define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
21252 #define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
21254 #define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
21256 #define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
21258 #define USEM_USEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
21260 #define USEM_USEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
21262 #define USEM_USEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
21264 #define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
21266 #define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
21268 #define USEM_USEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
21270 #define USEM_USEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
21272 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
21274 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
21276 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
21278 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
21280 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
21282 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
21284 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
21286 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
21288 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
21290 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
21292 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
21294 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
21296 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
21298 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
21300 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
21302 #define USEM_USEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
21304 #define USEM_USEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
21306 #define USEM_USEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
21309 #define USEM_USEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
21311 #define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
21313 #define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
21315 #define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
21317 #define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
21319 #define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
21321 #define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
21323 #define USEM_USEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
21325 #define USEM_USEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
21327 #define USEM_USEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
21329 #define USEM_USEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
21331 #define USEM_USEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
21333 #define USEM_USEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
21335 #define USEM_USEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
21337 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
21339 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
21341 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
21343 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
21345 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
21347 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
21349 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
21351 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
21353 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
21355 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
21357 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
21359 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
21361 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
21363 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
21365 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
21367 #define USEM_USEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
21369 #define USEM_USEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
21371 #define USEM_USEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
21374 #define USEM_USEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
21376 #define USEM_USEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
21378 #define USEM_USEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
21380 #define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
21382 #define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
21384 #define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
21386 #define USEM_USEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
21388 #define USEM_USEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
21390 #define USEM_USEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
21392 #define USEM_USEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
21394 #define USEM_USEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
21396 #define USEM_USEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
21398 #define USEM_USEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
21400 #define USEM_USEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
21402 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
21404 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
21406 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
21408 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
21410 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
21412 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
21414 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
21416 #define USEM_USEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
21418 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
21420 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
21422 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
21424 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
21426 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
21428 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
21430 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
21432 #define USEM_USEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
21434 #define USEM_USEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
21436 #define USEM_USEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
21439 #define USEM_USEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
21441 #define USEM_USEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
21443 #define USEM_USEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
21445 #define USEM_USEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
21447 #define USEM_USEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
21450 #define USEM_USEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
21452 #define USEM_USEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
21454 #define USEM_USEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
21456 #define USEM_USEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
21458 #define USEM_USEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
21461 #define USEM_USEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
21463 #define USEM_USEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
21465 #define USEM_USEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
21467 #define USEM_USEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
21469 #define USEM_USEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
21472 #define USEM_USEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
21474 #define USEM_USEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
21476 #define USEM_USEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
21478 #define USEM_USEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
21480 #define USEM_USEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
21492 #define USEM_REG_DBG_IF_FULL 0x30020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
21494 #define USEM_REG_DRA_EMPTY 0x300210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
21496 #define USEM_REG_EXT_PAS_EMPTY 0x300214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
21498 #define USEM_REG_EXT_PAS_FULL 0x300218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
21502 #define USEM_REG_EXT_STORE_IF_FULL 0x300220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
21504 #define USEM_REG_FIC0_DISABLE 0x300224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
21506 #define USEM_REG_FIC0_EMPTY 0x300228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
21508 #define USEM_REG_FIC0_FULL 0x30022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
21512 #define USEM_REG_FIC1_DISABLE 0x300234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
21514 #define USEM_REG_FIC1_EMPTY 0x300238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
21516 #define USEM_REG_FIC1_FULL 0x30023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
21524 #define USEM_REG_PAS_DISABLE 0x30024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
21526 #define USEM_REG_PAS_IF_FULL 0x300250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
21528 #define USEM_REG_RAM0_IF_FULL 0x300254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
21530 #define USEM_REG_RAM1_IF_FULL 0x300258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
21532 #define USEM_REG_SET0_THREAD_EMPTY 0x30025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
21534 #define USEM_REG_SET0_THREAD_FULL 0x300260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
21536 #define USEM_REG_SET1_THREAD_EMPTY 0x300264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
21538 #define USEM_REG_SET1_THREAD_FULL 0x300268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
21542 #define USEM_REG_SLOW_DBG_ALM_EMPTY 0x300270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
21544 #define USEM_REG_SLOW_DBG_ALM_FULL 0x300274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
21546 #define USEM_REG_SLOW_DBG_EMPTY 0x300278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
21548 #define USEM_REG_SLOW_DBG_FULL 0x30027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
21550 #define USEM_REG_SLOW_DRA_FIN_EMPTY 0x300280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
21552 #define USEM_REG_SLOW_DRA_FIN_FULL 0x300284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
21554 #define USEM_REG_SLOW_DRA_INT_EMPTY 0x300288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
21556 #define USEM_REG_SLOW_DRA_INT_FULL 0x30028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
21558 #define USEM_REG_SLOW_DRA_RD_EMPTY 0x300290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
21560 #define USEM_REG_SLOW_DRA_RD_FULL 0x300294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
21562 #define USEM_REG_SLOW_DRA_WR_EMPTY 0x300298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
21564 #define USEM_REG_SLOW_DRA_WR_FULL 0x30029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
21566 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
21568 #define USEM_REG_SLOW_EXT_STORE_FULL 0x3002a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
21570 #define USEM_REG_SLOW_RAM0_RD_EMPTY 0x3002a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
21572 #define USEM_REG_SLOW_RAM0_RD_FULL 0x3002acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
21574 #define USEM_REG_SLOW_RAM0_WR_ALM_FULL 0x3002b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
21576 #define USEM_REG_SLOW_RAM0_WR_EMPTY 0x3002b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
21578 #define USEM_REG_SLOW_RAM0_WR_FULL 0x3002b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
21580 #define USEM_REG_SLOW_RAM1_RD_EMPTY 0x3002bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
21582 #define USEM_REG_SLOW_RAM1_RD_FULL 0x3002c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
21584 #define USEM_REG_SLOW_RAM1_WR_ALM_FULL 0x3002c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
21586 #define USEM_REG_SLOW_RAM1_WR_EMPTY 0x3002c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
21588 #define USEM_REG_SLOW_RAM1_WR_FULL 0x3002ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
21590 #define USEM_REG_SYNC_DBG_EMPTY 0x3002d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
21592 #define USEM_REG_SYNC_DBG_FULL 0x3002d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync
21655 #define VFC_INTERRUPT_IND_REG_ADDRESS_INTERRUPT (0x1<<0)
21657 #define VFC_INTERRUPT_IND_REG_INP_FIFO_ITERRUPT (0x1<<1)
21659 #define VFC_INTERRUPT_IND_REG_LEN_FIFO_INTERRUPT (0x1<<2)
21661 #define VFC_INTERRUPT_IND_REG_INP_BUF_INTERRUPT (0x1<<3)
21663 #define VFC_INTERRUPT_IND_REG_OUT_BUF_INTERRUPT (0x1<<4)
21665 #define VFC_INTERRUPT_IND_REG_RSS_IND_INTERRUPT (0x1<<5)
21667 #define VFC_INTERRUPT_IND_REG_RSS_INFO_INTERRUPT (0x1<<6)
21669 #define VFC_INTERRUPT_IND_REG_RSS_KEY_LSB_INTERRUPT (0x1<<7)
21671 #define VFC_INTERRUPT_IND_REG_RSS_KEY_MSB_INTERRUPT (0x1<<8)
21673 #define VFC_INTERRUPT_IND_REG_RBC_WRITE_INTERRUPT (0x1<<9)
21675 #define VFC_INTERRUPT_IND_REG_DEADLOCK_INTERRUPT (0x1<<10)
21678 #define VFC_PARITY_IND_REG_RSS_RAM_PARITY (0x1<<0)
21680 #define VFC_PARITY_IND_REG_CAM_PARITY (0x1<<1)
21682 #define VFC_PARITY_IND_REG_INP_FIFO_PARITY (0x1<<2)
21685 #define VFC_INDICATIONS1_REG_INP_FIFO_EMPTY (0x1<<0)
21687 #define VFC_INDICATIONS1_REG_LEN_FIFO_EMPTY (0x1<<1)
21689 #define VFC_INDICATIONS1_REG_INP_BUF_EMPTY (0x1<<2)
21691 #define VFC_INDICATIONS1_REG_OUT_FIFO_EMPTY (0x1<<3)
21693 #define VFC_INDICATIONS1_REG_SEM_FIFO_EMPTY (0x1<<4)
21697 #define VFC_INDICATIONS1_REG_INP_FIFO_FULL (0x1<<8)
21699 #define VFC_INDICATIONS1_REG_LEN_FIFO_FULL (0x1<<9)
21701 #define VFC_INDICATIONS1_REG_INP_BUF_FULL (0x1<<10)
21703 #define VFC_INDICATIONS1_REG_OUT_FIFO_FULL (0x1<<11)
21705 #define VFC_INDICATIONS1_REG_SEM_FIFO_FULL (0x1<<12)
21709 #define VFC_INDICATIONS1_REG_RBC_RSP_RDY (0x1<<16)
21711 #define VFC_INDICATIONS1_REG_VFC_WAITP (0x1<<17)
21729 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
21731 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
21737 #define VFC_REG_STORM_CMD_DISABLE 0x19474UL //ACCESS:RW DataWidth:0x1 Description: When set then it disables selecting of commands from STORM. It will allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted
21747 #define VFC_DEBUG_DATA_REG_CUR_MSG_EMPTY (0x1<<3)
21751 #define VFC_DEBUG_DATA_REG_NEXT_MSG_EMTY (0x1<<7)
21755 #define VFC_DEBUG_DATA_REG_STORM_READY (0x1<<16)
21757 #define VFC_DEBUG_DATA_REG_RBC_READY (0x1<<17)
21772 #define VFC_REG_VFC_PRTY_MASK 0x194e0UL //ACCESS:RW DataWidth:0x1 Description: Parity mask register #0 read/write
21773 #define VFC_VFC_PRTY_MASK_REG_PARITY (0x1<<0)
21775 #define VFC_REG_VFC_PRTY_STS_WR 0x194e4UL //ACCESS:WR DataWidth:0x1 Description: Parity register #0 bit set or clear
21776 #define VFC_VFC_PRTY_STS_WR_REG_PARITY (0x1<<0)
21778 #define VFC_REG_VFC_PRTY_STS_CLR 0x194e8UL //ACCESS:RC DataWidth:0x1 Description: Parity register #0 read clear
21779 #define VFC_VFC_PRTY_STS_CLR_REG_PARITY (0x1<<0)
21781 #define VFC_REG_VFC_PRTY_STS 0x194ecUL //ACCESS:R DataWidth:0x1 Description: Parity register #0 read
21782 #define VFC_VFC_PRTY_STS_REG_PARITY (0x1<<0)
21784 #define VFC_REG_VFC_INT_MASK 0x194f0UL //ACCESS:RW DataWidth:0x1 Description: Interrupt mask register #0 read/write
21785 #define VFC_VFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
21787 #define VFC_REG_VFC_INT_STS_WR 0x194f4UL //ACCESS:WR DataWidth:0x1 Description: Interrupt register #0 bit set or clear
21788 #define VFC_VFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
21790 #define VFC_REG_VFC_INT_STS_CLR 0x194f8UL //ACCESS:RC DataWidth:0x1 Description: Interrupt register #0 read clear
21791 #define VFC_VFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
21793 #define VFC_REG_VFC_INT_STS 0x194fcUL //ACCESS:R DataWidth:0x1 Description: Interrupt register #0 read
21794 #define VFC_VFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
21816 #define VFC_REG_SW_RST 0x19438UL //ACCESS:W DataWidth:0x1 Description: Write to this bit will cause to block reset
21818 #define VFC_REG_CAM_PARITY_EN 0x19440UL //ACCESS:RW DataWidth:0x1 Description: REQUIRED -If this bit is set then background mechanism for parity check will be enabled; 0 - disabled
21826 #define VFC_REG_VFC_CAM_BIST_EN 0x19460UL //ACCESS:RW DataWidth:0x1 Description: Bist enable bit for Cam
21840 #define XCM_REG_INIT 0x20000UL //ACCESS:RW DataWidth:0x1 Description: Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.
21841 #define XCM_REG_XCM_STORM0_IFEN 0x20004UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 0 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
21842 #define XCM_REG_XCM_STORM1_IFEN 0x20008UL //ACCESS:RW DataWidth:0x1 Description: CM - STORM 1 Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
21843 #define XCM_REG_XCM_XQM_IFEN 0x2000cUL //ACCESS:RW DataWidth:0x1 Description: CM - QM Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.
21844 #define XCM_REG_STORM_XCM_IFEN 0x20010UL //ACCESS:RW DataWidth:0x1 Description: STORM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21845 #define XCM_REG_XQM_XCM_IFEN 0x20014UL //ACCESS:RW DataWidth:0x1 Description: QM - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21846 #define XCM_REG_XSDM_IFEN 0x20018UL //ACCESS:RW DataWidth:0x1 Description: Input SDM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21847 #define XCM_REG_TM_XCM_IFEN 0x2001cUL //ACCESS:RW DataWidth:0x1 Description: Timers - CM Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21848 #define XCM_REG_XCM_TM_IFEN 0x20020UL //ACCESS:RW DataWidth:0x1 Description: CM - Timers Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21849 #define XCM_REG_TSEM_IFEN 0x20024UL //ACCESS:RW DataWidth:0x1 Description: Input tsem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21850 #define XCM_REG_CSEM_IFEN 0x20028UL //ACCESS:RW DataWidth:0x1 Description: Input csem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21851 #define XCM_REG_USEM_IFEN 0x2002cUL //ACCESS:RW DataWidth:0x1 Description: Input usem Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21852 #define XCM_REG_DORQ_IFEN 0x20030UL //ACCESS:RW DataWidth:0x1 Description: Input dorq Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21853 #define XCM_REG_PBF_IFEN 0x20034UL //ACCESS:RW DataWidth:0x1 Description: Input pbf Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21854 #define XCM_REG_NIG0_IFEN 0x20038UL //ACCESS:RW DataWidth:0x1 Description: Input nig0 Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21855 #define XCM_REG_NIG1_IFEN 0x2003cUL //ACCESS:RW DataWidth:0x1 Description: Input nig1 Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21856 #define XCM_REG_CDU_AG_WR_IFEN 0x20040UL //ACCESS:RW DataWidth:0x1 Description: CDU AG write Interface enable. If 0 - the request and valid input are disregarded; all other signals are treated as usual; if 1 - normal activity.
21857 #define XCM_REG_CDU_AG_RD_IFEN 0x20044UL //ACCESS:RW DataWidth:0x1 Description: CDU AG read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21858 #define XCM_REG_CDU_SM_WR_IFEN 0x20048UL //ACCESS:RW DataWidth:0x1 Description: CDU STORM write Interface enable. If 0 - the request and valid input is disregarded; all other signals are treated as usual; if 1 - normal activity.
21859 #define XCM_REG_CDU_SM_RD_IFEN 0x2004cUL //ACCESS:RW DataWidth:0x1 Description: CDU STORM read Interface enable. If 0 - the request input is disregarded; valid output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21860 #define XCM_REG_XCM_CFC_IFEN 0x20050UL //ACCESS:RW DataWidth:0x1 Description: CM - CFC Interface enable. If 0 - the valid input is disregarded; acknowledge output is deasserted; all other signals are treated as usual; if 1 - normal activity.
21900 #define XCM_REG_XCM_XQM_USE_Q 0x200f0UL //ACCESS:RW DataWidth:0x1 Description: If set the Q index; received from the QM is inserted to event ID.
21951 #define XCM_REG_GR_ARB_TYPE 0x2020cUL //ACCESS:RW DataWidth:0x1 Description: Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; ~xcm_registers_gr_ld0_pr.gr_ld0_pr and ~xcm_registers_gr_ld1_pr.gr_ld1_pr.
21955 #define XCM_REG_STORM_LENGTH_MIS 0x2021cUL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the STORM interface.
21956 #define XCM_REG_XSDM_LENGTH_MIS 0x20220UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the SDM interface.
21957 #define XCM_REG_TSEM_LENGTH_MIS 0x20224UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the tsem interface.
21958 #define XCM_REG_CSEM_LENGTH_MIS 0x20228UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the csem interface.
21959 #define XCM_REG_USEM_LENGTH_MIS 0x2022cUL //ACCESS:RC DataWidth:0x1 Description: Message length mismatch (relative to last indication) at the usem interface.
21960 #define XCM_REG_DORQ_LENGTH_MIS 0x20230UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the dorq interface.
21961 #define XCM_REG_PBF_LENGTH_MIS 0x20234UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the pbf interface.
21962 #define XCM_REG_NIG0_LENGTH_MIS 0x20238UL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the nig0 interface.
21963 #define XCM_REG_NIG1_LENGTH_MIS 0x2023cUL //ACCESS:RC DataWidth:0x1 Description: Set at message length mismatch (relative to last indication) at the nig1 interface.
21966 #define XCM_REG_UNLOCK_MISS 0x20248UL //ACCESS:RC DataWidth:0x1 Description: Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM; happens.
21968 #define XCM_REG_CP_BUF_EMPTY 0x20250UL //ACCESS:R DataWidth:0x1 Description: CP buffer is empty indication.
21991 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
21993 #define XCM_XCM_INT_STS_REG_XX_UQ_ERR (0x1<<1)
21995 #define XCM_XCM_INT_STS_REG_STORM_ERR (0x1<<2)
21997 #define XCM_XCM_INT_STS_REG_XSDM_ERR (0x1<<3)
21999 #define XCM_XCM_INT_STS_REG_TSEM_ERR (0x1<<4)
22001 #define XCM_XCM_INT_STS_REG_CSEM_ERR (0x1<<5)
22003 #define XCM_XCM_INT_STS_REG_USEM_ERR (0x1<<6)
22005 #define XCM_XCM_INT_STS_REG_DORQ_ERR (0x1<<7)
22007 #define XCM_XCM_INT_STS_REG_PBF_ERR (0x1<<8)
22009 #define XCM_XCM_INT_STS_REG_NIG0_ERR (0x1<<9)
22011 #define XCM_XCM_INT_STS_REG_NIG1_ERR (0x1<<10)
22013 #define XCM_XCM_INT_STS_REG_CP0_ERR (0x1<<11)
22015 #define XCM_XCM_INT_STS_REG_CP1_ERR (0x1<<12)
22017 #define XCM_XCM_INT_STS_REG_UM_ERR (0x1<<13)
22020 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
22022 #define XCM_XCM_INT_STS_CLR_REG_XX_UQ_ERR (0x1<<1)
22024 #define XCM_XCM_INT_STS_CLR_REG_STORM_ERR (0x1<<2)
22026 #define XCM_XCM_INT_STS_CLR_REG_XSDM_ERR (0x1<<3)
22028 #define XCM_XCM_INT_STS_CLR_REG_TSEM_ERR (0x1<<4)
22030 #define XCM_XCM_INT_STS_CLR_REG_CSEM_ERR (0x1<<5)
22032 #define XCM_XCM_INT_STS_CLR_REG_USEM_ERR (0x1<<6)
22034 #define XCM_XCM_INT_STS_CLR_REG_DORQ_ERR (0x1<<7)
22036 #define XCM_XCM_INT_STS_CLR_REG_PBF_ERR (0x1<<8)
22038 #define XCM_XCM_INT_STS_CLR_REG_NIG0_ERR (0x1<<9)
22040 #define XCM_XCM_INT_STS_CLR_REG_NIG1_ERR (0x1<<10)
22042 #define XCM_XCM_INT_STS_CLR_REG_CP0_ERR (0x1<<11)
22044 #define XCM_XCM_INT_STS_CLR_REG_CP1_ERR (0x1<<12)
22046 #define XCM_XCM_INT_STS_CLR_REG_UM_ERR (0x1<<13)
22049 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
22051 #define XCM_XCM_INT_STS_WR_REG_XX_UQ_ERR (0x1<<1)
22053 #define XCM_XCM_INT_STS_WR_REG_STORM_ERR (0x1<<2)
22055 #define XCM_XCM_INT_STS_WR_REG_XSDM_ERR (0x1<<3)
22057 #define XCM_XCM_INT_STS_WR_REG_TSEM_ERR (0x1<<4)
22059 #define XCM_XCM_INT_STS_WR_REG_CSEM_ERR (0x1<<5)
22061 #define XCM_XCM_INT_STS_WR_REG_USEM_ERR (0x1<<6)
22063 #define XCM_XCM_INT_STS_WR_REG_DORQ_ERR (0x1<<7)
22065 #define XCM_XCM_INT_STS_WR_REG_PBF_ERR (0x1<<8)
22067 #define XCM_XCM_INT_STS_WR_REG_NIG0_ERR (0x1<<9)
22069 #define XCM_XCM_INT_STS_WR_REG_NIG1_ERR (0x1<<10)
22071 #define XCM_XCM_INT_STS_WR_REG_CP0_ERR (0x1<<11)
22073 #define XCM_XCM_INT_STS_WR_REG_CP1_ERR (0x1<<12)
22075 #define XCM_XCM_INT_STS_WR_REG_UM_ERR (0x1<<13)
22078 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
22080 #define XCM_XCM_INT_MASK_REG_XX_UQ_ERR (0x1<<1)
22082 #define XCM_XCM_INT_MASK_REG_STORM_ERR (0x1<<2)
22084 #define XCM_XCM_INT_MASK_REG_XSDM_ERR (0x1<<3)
22086 #define XCM_XCM_INT_MASK_REG_TSEM_ERR (0x1<<4)
22088 #define XCM_XCM_INT_MASK_REG_CSEM_ERR (0x1<<5)
22090 #define XCM_XCM_INT_MASK_REG_USEM_ERR (0x1<<6)
22092 #define XCM_XCM_INT_MASK_REG_DORQ_ERR (0x1<<7)
22094 #define XCM_XCM_INT_MASK_REG_PBF_ERR (0x1<<8)
22096 #define XCM_XCM_INT_MASK_REG_NIG0_ERR (0x1<<9)
22098 #define XCM_XCM_INT_MASK_REG_NIG1_ERR (0x1<<10)
22100 #define XCM_XCM_INT_MASK_REG_CP0_ERR (0x1<<11)
22102 #define XCM_XCM_INT_MASK_REG_CP1_ERR (0x1<<12)
22104 #define XCM_XCM_INT_MASK_REG_UM_ERR (0x1<<13)
22107 #define XCM_XCM_PRTY_STS_REG_PARITY (0x1<<0)
22109 #define XCM_XCM_PRTY_STS_REG_XT_PRTY (0x1<<1)
22111 #define XCM_XCM_PRTY_STS_REG_DT_PRTY (0x1<<2)
22113 #define XCM_XCM_PRTY_STS_REG_PM_PRTY0 (0x1<<3)
22115 #define XCM_XCM_PRTY_STS_REG_PM_PRTY1 (0x1<<4)
22117 #define XCM_XCM_PRTY_STS_REG_UQ_PRTY (0x1<<5)
22119 #define XCM_XCM_PRTY_STS_REG_AG_PRTY0 (0x1<<6)
22121 #define XCM_XCM_PRTY_STS_REG_AG_PRTY1 (0x1<<7)
22123 #define XCM_XCM_PRTY_STS_REG_AG_PRTY2 (0x1<<8)
22125 #define XCM_XCM_PRTY_STS_REG_AG_PRTY3 (0x1<<9)
22127 #define XCM_XCM_PRTY_STS_REG_AG_PRTY4 (0x1<<10)
22129 #define XCM_XCM_PRTY_STS_REG_AG_PRTY5 (0x1<<11)
22131 #define XCM_XCM_PRTY_STS_REG_AG_PRTY6 (0x1<<12)
22133 #define XCM_XCM_PRTY_STS_REG_AG_PRTY7 (0x1<<13)
22135 #define XCM_XCM_PRTY_STS_REG_SM_PRTY0 (0x1<<14)
22137 #define XCM_XCM_PRTY_STS_REG_SM_PRTY1 (0x1<<15)
22139 #define XCM_XCM_PRTY_STS_REG_SM_PRTY2 (0x1<<16)
22141 #define XCM_XCM_PRTY_STS_REG_SM_PRTY3 (0x1<<17)
22143 #define XCM_XCM_PRTY_STS_REG_STORM_PRTY (0x1<<18)
22145 #define XCM_XCM_PRTY_STS_REG_XSDM_PRTY (0x1<<19)
22147 #define XCM_XCM_PRTY_STS_REG_TSEM_PRTY (0x1<<20)
22149 #define XCM_XCM_PRTY_STS_REG_CSEM_PRTY (0x1<<21)
22151 #define XCM_XCM_PRTY_STS_REG_USEM_PRTY (0x1<<22)
22153 #define XCM_XCM_PRTY_STS_REG_DORQ_PRTY (0x1<<23)
22155 #define XCM_XCM_PRTY_STS_REG_PBF_PRTY (0x1<<24)
22157 #define XCM_XCM_PRTY_STS_REG_NIG0_PRTY (0x1<<25)
22159 #define XCM_XCM_PRTY_STS_REG_NIG1_PRTY (0x1<<26)
22161 #define XCM_XCM_PRTY_STS_REG_CP0_PRTY (0x1<<27)
22163 #define XCM_XCM_PRTY_STS_REG_CP1_PRTY (0x1<<28)
22165 #define XCM_XCM_PRTY_STS_REG_UM_PRTY (0x1<<29)
22168 #define XCM_XCM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
22170 #define XCM_XCM_PRTY_STS_CLR_REG_XT_PRTY (0x1<<1)
22172 #define XCM_XCM_PRTY_STS_CLR_REG_DT_PRTY (0x1<<2)
22174 #define XCM_XCM_PRTY_STS_CLR_REG_PM_PRTY0 (0x1<<3)
22176 #define XCM_XCM_PRTY_STS_CLR_REG_PM_PRTY1 (0x1<<4)
22178 #define XCM_XCM_PRTY_STS_CLR_REG_UQ_PRTY (0x1<<5)
22180 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY0 (0x1<<6)
22182 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY1 (0x1<<7)
22184 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY2 (0x1<<8)
22186 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY3 (0x1<<9)
22188 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY4 (0x1<<10)
22190 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY5 (0x1<<11)
22192 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY6 (0x1<<12)
22194 #define XCM_XCM_PRTY_STS_CLR_REG_AG_PRTY7 (0x1<<13)
22196 #define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY0 (0x1<<14)
22198 #define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY1 (0x1<<15)
22200 #define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY2 (0x1<<16)
22202 #define XCM_XCM_PRTY_STS_CLR_REG_SM_PRTY3 (0x1<<17)
22204 #define XCM_XCM_PRTY_STS_CLR_REG_STORM_PRTY (0x1<<18)
22206 #define XCM_XCM_PRTY_STS_CLR_REG_XSDM_PRTY (0x1<<19)
22208 #define XCM_XCM_PRTY_STS_CLR_REG_TSEM_PRTY (0x1<<20)
22210 #define XCM_XCM_PRTY_STS_CLR_REG_CSEM_PRTY (0x1<<21)
22212 #define XCM_XCM_PRTY_STS_CLR_REG_USEM_PRTY (0x1<<22)
22214 #define XCM_XCM_PRTY_STS_CLR_REG_DORQ_PRTY (0x1<<23)
22216 #define XCM_XCM_PRTY_STS_CLR_REG_PBF_PRTY (0x1<<24)
22218 #define XCM_XCM_PRTY_STS_CLR_REG_NIG0_PRTY (0x1<<25)
22220 #define XCM_XCM_PRTY_STS_CLR_REG_NIG1_PRTY (0x1<<26)
22222 #define XCM_XCM_PRTY_STS_CLR_REG_CP0_PRTY (0x1<<27)
22224 #define XCM_XCM_PRTY_STS_CLR_REG_CP1_PRTY (0x1<<28)
22226 #define XCM_XCM_PRTY_STS_CLR_REG_UM_PRTY (0x1<<29)
22229 #define XCM_XCM_PRTY_STS_WR_REG_PARITY (0x1<<0)
22231 #define XCM_XCM_PRTY_STS_WR_REG_XT_PRTY (0x1<<1)
22233 #define XCM_XCM_PRTY_STS_WR_REG_DT_PRTY (0x1<<2)
22235 #define XCM_XCM_PRTY_STS_WR_REG_PM_PRTY0 (0x1<<3)
22237 #define XCM_XCM_PRTY_STS_WR_REG_PM_PRTY1 (0x1<<4)
22239 #define XCM_XCM_PRTY_STS_WR_REG_UQ_PRTY (0x1<<5)
22241 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY0 (0x1<<6)
22243 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY1 (0x1<<7)
22245 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY2 (0x1<<8)
22247 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY3 (0x1<<9)
22249 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY4 (0x1<<10)
22251 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY5 (0x1<<11)
22253 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY6 (0x1<<12)
22255 #define XCM_XCM_PRTY_STS_WR_REG_AG_PRTY7 (0x1<<13)
22257 #define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY0 (0x1<<14)
22259 #define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY1 (0x1<<15)
22261 #define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY2 (0x1<<16)
22263 #define XCM_XCM_PRTY_STS_WR_REG_SM_PRTY3 (0x1<<17)
22265 #define XCM_XCM_PRTY_STS_WR_REG_STORM_PRTY (0x1<<18)
22267 #define XCM_XCM_PRTY_STS_WR_REG_XSDM_PRTY (0x1<<19)
22269 #define XCM_XCM_PRTY_STS_WR_REG_TSEM_PRTY (0x1<<20)
22271 #define XCM_XCM_PRTY_STS_WR_REG_CSEM_PRTY (0x1<<21)
22273 #define XCM_XCM_PRTY_STS_WR_REG_USEM_PRTY (0x1<<22)
22275 #define XCM_XCM_PRTY_STS_WR_REG_DORQ_PRTY (0x1<<23)
22277 #define XCM_XCM_PRTY_STS_WR_REG_PBF_PRTY (0x1<<24)
22279 #define XCM_XCM_PRTY_STS_WR_REG_NIG0_PRTY (0x1<<25)
22281 #define XCM_XCM_PRTY_STS_WR_REG_NIG1_PRTY (0x1<<26)
22283 #define XCM_XCM_PRTY_STS_WR_REG_CP0_PRTY (0x1<<27)
22285 #define XCM_XCM_PRTY_STS_WR_REG_CP1_PRTY (0x1<<28)
22287 #define XCM_XCM_PRTY_STS_WR_REG_UM_PRTY (0x1<<29)
22290 #define XCM_XCM_PRTY_MASK_REG_PARITY (0x1<<0)
22292 #define XCM_XCM_PRTY_MASK_REG_XT_PRTY (0x1<<1)
22294 #define XCM_XCM_PRTY_MASK_REG_DT_PRTY (0x1<<2)
22296 #define XCM_XCM_PRTY_MASK_REG_PM_PRTY0 (0x1<<3)
22298 #define XCM_XCM_PRTY_MASK_REG_PM_PRTY1 (0x1<<4)
22300 #define XCM_XCM_PRTY_MASK_REG_UQ_PRTY (0x1<<5)
22302 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY0 (0x1<<6)
22304 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY1 (0x1<<7)
22306 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY2 (0x1<<8)
22308 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY3 (0x1<<9)
22310 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY4 (0x1<<10)
22312 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY5 (0x1<<11)
22314 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY6 (0x1<<12)
22316 #define XCM_XCM_PRTY_MASK_REG_AG_PRTY7 (0x1<<13)
22318 #define XCM_XCM_PRTY_MASK_REG_SM_PRTY0 (0x1<<14)
22320 #define XCM_XCM_PRTY_MASK_REG_SM_PRTY1 (0x1<<15)
22322 #define XCM_XCM_PRTY_MASK_REG_SM_PRTY2 (0x1<<16)
22324 #define XCM_XCM_PRTY_MASK_REG_SM_PRTY3 (0x1<<17)
22326 #define XCM_XCM_PRTY_MASK_REG_STORM_PRTY (0x1<<18)
22328 #define XCM_XCM_PRTY_MASK_REG_XSDM_PRTY (0x1<<19)
22330 #define XCM_XCM_PRTY_MASK_REG_TSEM_PRTY (0x1<<20)
22332 #define XCM_XCM_PRTY_MASK_REG_CSEM_PRTY (0x1<<21)
22334 #define XCM_XCM_PRTY_MASK_REG_USEM_PRTY (0x1<<22)
22336 #define XCM_XCM_PRTY_MASK_REG_DORQ_PRTY (0x1<<23)
22338 #define XCM_XCM_PRTY_MASK_REG_PBF_PRTY (0x1<<24)
22340 #define XCM_XCM_PRTY_MASK_REG_NIG0_PRTY (0x1<<25)
22342 #define XCM_XCM_PRTY_MASK_REG_NIG1_PRTY (0x1<<26)
22344 #define XCM_XCM_PRTY_MASK_REG_CP0_PRTY (0x1<<27)
22346 #define XCM_XCM_PRTY_MASK_REG_CP1_PRTY (0x1<<28)
22348 #define XCM_XCM_PRTY_MASK_REG_UM_PRTY (0x1<<29)
22360 #define XCM_REG_UM_FIC1_FORCE 0x202f0UL //ACCESS:RW DataWidth:0x1 Description: 0-messages unlocked from Pending messages RAM go to the FIC for which they were designated in input message; 1-messages unlocked from Pending messages RAM are forced to FIC1 whether they were destined to FIC0 or FIC1 in original message.
22373 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
22375 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
22377 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201ccUL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
22379 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0UL //ACCESS:RW DataWidth:0x1 SPLIT:4 Description: DA timer command; used in case of window update doorbell.The first index stands for the value DaEnable of that connection. The second index stands for port number. The access to 4 registers corresponding to 4 functions is arranged.
22478 #define XMAC_CTRL_REG_TX_EN (0x1<<0)
22480 #define XMAC_CTRL_REG_RX_EN (0x1<<1)
22482 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)
22484 #define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3)
22486 #define XMAC_CTRL_REG_LINE_REMOTE_LPBK (0x1<<4)
22488 #define XMAC_CTRL_REG_CORE_REMOTE_LPBK (0x1<<5)
22490 #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
22492 #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7)
22494 #define XMAC_CTRL_REG_LOCAL_LPBK_LEAK_ENB (0x1<<8)
22496 #define XMAC_CTRL_REG_REMOTE_LPBK_LEAK_ENB (0x1<<9)
22498 #define XMAC_CTRL_REG_RS_SOFT_RESET (0x1<<10)
22500 #define XMAC_CTRL_REG_XGMII_IPG_CHECK_DISABLE (0x1<<11)
22505 #define XMAC_MODE_REG_NO_SOP_FOR_CRC_HG (0x1<<3)
22514 #define XMAC_TX_CTRL_REG_DISCARD (0x1<<2)
22516 #define XMAC_TX_CTRL_REG_TX_ANY_START (0x1<<3)
22518 #define XMAC_TX_CTRL_REG_PAD_EN (0x1<<4)
22529 #define XMAC_TX_CTRL_HI_REG_THROT_DENOM_HI (0x1<<0)
22533 #define XMAC_TX_CTRL_HI_REG_TX_64BYTE_BUFFER_EN (0x1<<5)
22538 #define XMAC_RX_CTRL_REG_RX_PASS_CTRL (0x1<<0)
22540 #define XMAC_RX_CTRL_REG_RX_ANY_START (0x1<<1)
22542 #define XMAC_RX_CTRL_REG_STRIP_CRC (0x1<<2)
22544 #define XMAC_RX_CTRL_REG_STRICT_PREAMBLE (0x1<<3)
22548 #define XMAC_RX_CTRL_REG_RECEIVE_18_BYTE_PKTS (0x1<<11)
22550 #define XMAC_RX_CTRL_REG_PROCESS_VARIABLE_PREAMBLE (0x1<<12)
22561 #define XMAC_RX_VLAN_TAG_HI_REG_INNER_VLAN_TAG_ENABLE (0x1<<0)
22563 #define XMAC_RX_VLAN_TAG_HI_REG_OUTER_VLAN_TAG_ENABLE (0x1<<1)
22566 #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0)
22568 #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1)
22570 #define XMAC_RX_LSS_CTRL_REG_USE_EXTERNAL_FAULTS_FOR_TX (0x1<<2)
22573 #define XMAC_RX_LSS_STATUS_REG_LOCAL_FAULT_STATUS (0x1<<0)
22575 #define XMAC_RX_LSS_STATUS_REG_REMOTE_FAULT_STATUS (0x1<<1)
22578 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
22580 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
22585 #define XMAC_PAUSE_CTRL_REG_PAUSE_REFRESH_EN (0x1<<16)
22587 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
22589 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
22591 #define XMAC_PAUSE_CTRL_REG_RX_PASS_PAUSE (0x1<<19)
22593 #define XMAC_PAUSE_CTRL_REG_PAUSE_GMII_ON_TX_LINE_SIDE (0x1<<20)
22601 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
22603 #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)
22605 #define XMAC_PFC_CTRL_HI_REG_RX_PASS_PFC (0x1<<2)
22607 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
22609 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
22611 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
22618 #define XMAC_LLFC_CTRL_REG_TX_LLFC_EN (0x1<<0)
22620 #define XMAC_LLFC_CTRL_REG_RX_LLFC_EN (0x1<<1)
22622 #define XMAC_LLFC_CTRL_REG_LLFC_IN_IPG_ONLY (0x1<<2)
22624 #define XMAC_LLFC_CTRL_REG_LLFC_CUT_THROUGH_MODE (0x1<<3)
22626 #define XMAC_LLFC_CTRL_REG_LLFC_CRC_IGNORE (0x1<<4)
22628 #define XMAC_LLFC_CTRL_REG_NO_SOM_FOR_CRC_LLFC (0x1<<5)
22649 #define XMAC_HCFC_CTRL_REG_TX_HCFC_EN (0x1<<0)
22651 #define XMAC_HCFC_CTRL_REG_RX_HCFC_EN (0x1<<1)
22653 #define XMAC_HCFC_CTRL_REG_HCFC_CRC_IGNORE (0x1<<2)
22655 #define XMAC_HCFC_CTRL_REG_NO_SOM_FOR_CRC_HCFC (0x1<<3)
22657 #define XMAC_HCFC_CTRL_REG_HCFC_IN_IPG_ONLY (0x1<<4)
22667 #define XMAC_TX_TIMESTAMP_FIFO_DATA_HI_REG_TS_ENTRY_VALID (0x1<<16)
22670 #define XMAC_FIFO_STATUS_REG_RX_PKT_OVERFLOW (0x1<<0)
22672 #define XMAC_FIFO_STATUS_REG_RX_MSG_OVERFLOW (0x1<<1)
22674 #define XMAC_FIFO_STATUS_REG_TX_PKT_UNDERFLOW (0x1<<2)
22676 #define XMAC_FIFO_STATUS_REG_TX_PKT_OVERFLOW (0x1<<3)
22678 #define XMAC_FIFO_STATUS_REG_TX_HCFC_MSG_OVERFLOW (0x1<<4)
22680 #define XMAC_FIFO_STATUS_REG_TX_LLFC_MSG_OVERFLOW (0x1<<5)
22683 #define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_RX_PKT_OVERFLOW (0x1<<0)
22685 #define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_RX_MSG_OVERFLOW (0x1<<1)
22687 #define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_PKT_UNDERFLOW (0x1<<2)
22689 #define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_PKT_OVERFLOW (0x1<<3)
22691 #define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_HCFC_MSG_OVERFLOW (0x1<<4)
22693 #define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_LLFC_MSG_OVERFLOW (0x1<<5)
22695 #define XMAC_CLEAR_FIFO_STATUS_REG_CLEAR_TX_TS_FIFO_OVERFLOW (0x1<<6)
22705 #define XMAC_EEE_CTRL_REG_EEE_EN (0x1<<0)
22707 #define XMAC_EEE_CTRL_REG_EEE_DISABLE_TX_PAUSE_XOFF (0x1<<1)
22709 #define XMAC_EEE_CTRL_REG_EEE_DISABLE_TX_PFC_XOFF (0x1<<2)
22711 #define XMAC_EEE_CTRL_REG_EEE_DISABLE_RX_PAUSE_ACTIVE (0x1<<3)
22722 #define XMAC_GMII_EEE_CTRL_REG_GMII_LPI_PREDICT_MODE_EN (0x1<<16)
22724 #define XMAC_GMII_EEE_CTRL_REG_GMII_TXCLK_DIS (0x1<<17)
22727 #define XMAC_MACSEC_CTRL_REG_MACSEC_TX_LAUNCH_EN (0x1<<0)
22729 #define XMAC_MACSEC_CTRL_REG_MACSEC_TX_CRC_CORRUPT_EN (0x1<<1)
22731 #define XMAC_MACSEC_CTRL_REG_MACSEC_TX_CRC_CORRUPTION_MODE (0x1<<2)
22803 #define XSDM_REG_TIMERS_TICK_ENABLE 0x166004UL //ACCESS:RW DataWidth:0x1 Description: Enable for tick counter.
22808 #define XSDM_REG_COUNTERS_WRAP 0x166018UL //ACCESS:RW DataWidth:0x1 Description: Indicates if the 204 statistics counters should stop counting when reaching an all-ones value or should wrap-around 0=stop counting 1=wrap-around.
22848 #define XSDM_REG_AGG_INT_T_0 0x1660b8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 0
22849 #define XSDM_REG_AGG_INT_T_1 0x1660bcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 1
22850 #define XSDM_REG_AGG_INT_T_2 0x1660c0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 2
22851 #define XSDM_REG_AGG_INT_T_3 0x1660c4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 3
22852 #define XSDM_REG_AGG_INT_T_4 0x1660c8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 4
22853 #define XSDM_REG_AGG_INT_T_5 0x1660ccUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 5
22854 #define XSDM_REG_AGG_INT_T_6 0x1660d0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 6
22855 #define XSDM_REG_AGG_INT_T_7 0x1660d4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 7
22856 #define XSDM_REG_AGG_INT_T_8 0x1660d8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 8
22857 #define XSDM_REG_AGG_INT_T_9 0x1660dcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 9
22858 #define XSDM_REG_AGG_INT_T_10 0x1660e0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 10
22859 #define XSDM_REG_AGG_INT_T_11 0x1660e4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 11
22860 #define XSDM_REG_AGG_INT_T_12 0x1660e8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 12
22861 #define XSDM_REG_AGG_INT_T_13 0x1660ecUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 13
22862 #define XSDM_REG_AGG_INT_T_14 0x1660f0UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 14
22863 #define XSDM_REG_AGG_INT_T_15 0x1660f4UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 15
22864 #define XSDM_REG_AGG_INT_T_16 0x1660f8UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 16
22865 #define XSDM_REG_AGG_INT_T_17 0x1660fcUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 17
22866 #define XSDM_REG_AGG_INT_T_18 0x166100UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 18
22867 #define XSDM_REG_AGG_INT_T_19 0x166104UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 19
22868 #define XSDM_REG_AGG_INT_T_20 0x166108UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 20
22869 #define XSDM_REG_AGG_INT_T_21 0x16610cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 21
22870 #define XSDM_REG_AGG_INT_T_22 0x166110UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 22
22871 #define XSDM_REG_AGG_INT_T_23 0x166114UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 23
22872 #define XSDM_REG_AGG_INT_T_24 0x166118UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 24
22873 #define XSDM_REG_AGG_INT_T_25 0x16611cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 25
22874 #define XSDM_REG_AGG_INT_T_26 0x166120UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 26
22875 #define XSDM_REG_AGG_INT_T_27 0x166124UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 27
22876 #define XSDM_REG_AGG_INT_T_28 0x166128UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 28
22877 #define XSDM_REG_AGG_INT_T_29 0x16612cUL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 29
22878 #define XSDM_REG_AGG_INT_T_30 0x166130UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 30
22879 #define XSDM_REG_AGG_INT_T_31 0x166134UL //ACCESS:RW DataWidth:0x1 Description: The T bit for aggregated interrupt 31
22880 #define XSDM_REG_AGG_INT_FIC_0 0x166138UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 0
22881 #define XSDM_REG_AGG_INT_FIC_1 0x16613cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 1
22882 #define XSDM_REG_AGG_INT_FIC_2 0x166140UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 2
22883 #define XSDM_REG_AGG_INT_FIC_3 0x166144UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 3
22884 #define XSDM_REG_AGG_INT_FIC_4 0x166148UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 4
22885 #define XSDM_REG_AGG_INT_FIC_5 0x16614cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 5
22886 #define XSDM_REG_AGG_INT_FIC_6 0x166150UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 6
22887 #define XSDM_REG_AGG_INT_FIC_7 0x166154UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 7
22888 #define XSDM_REG_AGG_INT_FIC_8 0x166158UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 8
22889 #define XSDM_REG_AGG_INT_FIC_9 0x16615cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 9
22890 #define XSDM_REG_AGG_INT_FIC_10 0x166160UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 10
22891 #define XSDM_REG_AGG_INT_FIC_11 0x166164UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 11
22892 #define XSDM_REG_AGG_INT_FIC_12 0x166168UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 12
22893 #define XSDM_REG_AGG_INT_FIC_13 0x16616cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 13
22894 #define XSDM_REG_AGG_INT_FIC_14 0x166170UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 14
22895 #define XSDM_REG_AGG_INT_FIC_15 0x166174UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 15
22896 #define XSDM_REG_AGG_INT_FIC_16 0x166178UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 16
22897 #define XSDM_REG_AGG_INT_FIC_17 0x16617cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 17
22898 #define XSDM_REG_AGG_INT_FIC_18 0x166180UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 18
22899 #define XSDM_REG_AGG_INT_FIC_19 0x166184UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 19
22900 #define XSDM_REG_AGG_INT_FIC_20 0x166188UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 20
22901 #define XSDM_REG_AGG_INT_FIC_21 0x16618cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 21
22902 #define XSDM_REG_AGG_INT_FIC_22 0x166190UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 22
22903 #define XSDM_REG_AGG_INT_FIC_23 0x166194UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 23
22904 #define XSDM_REG_AGG_INT_FIC_24 0x166198UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 24
22905 #define XSDM_REG_AGG_INT_FIC_25 0x16619cUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 25
22906 #define XSDM_REG_AGG_INT_FIC_26 0x1661a0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 26
22907 #define XSDM_REG_AGG_INT_FIC_27 0x1661a4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 27
22908 #define XSDM_REG_AGG_INT_FIC_28 0x1661a8UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 28
22909 #define XSDM_REG_AGG_INT_FIC_29 0x1661acUL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 29
22910 #define XSDM_REG_AGG_INT_FIC_30 0x1661b0UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 30
22911 #define XSDM_REG_AGG_INT_FIC_31 0x1661b4UL //ACCESS:RW DataWidth:0x1 Description: The destination FIC for aggregated interrupt 31
22912 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22913 #define XSDM_REG_AGG_INT_MODE_1 0x1661bcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22914 #define XSDM_REG_AGG_INT_MODE_2 0x1661c0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22915 #define XSDM_REG_AGG_INT_MODE_3 0x1661c4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22916 #define XSDM_REG_AGG_INT_MODE_4 0x1661c8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22917 #define XSDM_REG_AGG_INT_MODE_5 0x1661ccUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22918 #define XSDM_REG_AGG_INT_MODE_6 0x1661d0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22919 #define XSDM_REG_AGG_INT_MODE_7 0x1661d4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22920 #define XSDM_REG_AGG_INT_MODE_8 0x1661d8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22921 #define XSDM_REG_AGG_INT_MODE_9 0x1661dcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22922 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22923 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22924 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22925 #define XSDM_REG_AGG_INT_MODE_13 0x1661ecUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22926 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22927 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22928 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (16) or auto-mask-mode (1)
22929 #define XSDM_REG_AGG_INT_MODE_17 0x1661fcUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (17)
22930 #define XSDM_REG_AGG_INT_MODE_18 0x166200UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22931 #define XSDM_REG_AGG_INT_MODE_19 0x166204UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22932 #define XSDM_REG_AGG_INT_MODE_20 0x166208UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22933 #define XSDM_REG_AGG_INT_MODE_21 0x16620cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22934 #define XSDM_REG_AGG_INT_MODE_22 0x166210UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22935 #define XSDM_REG_AGG_INT_MODE_23 0x166214UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22936 #define XSDM_REG_AGG_INT_MODE_24 0x166218UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22937 #define XSDM_REG_AGG_INT_MODE_25 0x16621cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22938 #define XSDM_REG_AGG_INT_MODE_26 0x166220UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22939 #define XSDM_REG_AGG_INT_MODE_27 0x166224UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22940 #define XSDM_REG_AGG_INT_MODE_28 0x166228UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22941 #define XSDM_REG_AGG_INT_MODE_29 0x16622cUL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22942 #define XSDM_REG_AGG_INT_MODE_30 0x166230UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22943 #define XSDM_REG_AGG_INT_MODE_31 0x166234UL //ACCESS:RW DataWidth:0x1 Description: For each aggregated interrupt index whether the mode is normal (0) or auto-mask-mode (1)
22945 #define XSDM_ENABLE_IN1_REG_EXT_STORE_IN_EN (0x1<<0)
22947 #define XSDM_ENABLE_IN1_REG_INT_RAM_DATA_IN_EN (0x1<<1)
22949 #define XSDM_ENABLE_IN1_REG_INT_RAM_DONE_IN_EN (0x1<<2)
22951 #define XSDM_ENABLE_IN1_REG_INT_RAM_FULL_IN_EN (0x1<<3)
22953 #define XSDM_ENABLE_IN1_REG_PAS_BUF_DONE_IN_EN (0x1<<4)
22955 #define XSDM_ENABLE_IN1_REG_PAS_BUF_FULL_IN_EN (0x1<<5)
22957 #define XSDM_ENABLE_IN1_REG_PXP_CTRL_DONE_IN_EN (0x1<<6)
22959 #define XSDM_ENABLE_IN1_REG_PXP_DP_DONE_IN_EN (0x1<<7)
22961 #define XSDM_ENABLE_IN1_REG_PXP_CTRL_FULL_IN_EN (0x1<<8)
22963 #define XSDM_ENABLE_IN1_REG_PXP_DP_FULL_IN_EN (0x1<<9)
22965 #define XSDM_ENABLE_IN1_REG_PXP_CTRL_DATA_IN_EN (0x1<<10)
22967 #define XSDM_ENABLE_IN1_REG_PXP_INT_DONE_IN_EN (0x1<<11)
22969 #define XSDM_ENABLE_IN1_REG_PXP_DP_DATA_IN_EN (0x1<<12)
22971 #define XSDM_ENABLE_IN1_REG_PXP_CTRL_ACK_IN_EN (0x1<<13)
22973 #define XSDM_ENABLE_IN1_REG_PXP_DP_ACK_IN_EN (0x1<<14)
22975 #define XSDM_ENABLE_IN1_REG_BRB1_CTRL_DATA_IN_EN (0x1<<15)
22977 #define XSDM_ENABLE_IN1_REG_BRB1_DP_DATA_IN_EN (0x1<<16)
22979 #define XSDM_ENABLE_IN1_REG_PB_DATA_IN_EN (0x1<<17)
22981 #define XSDM_ENABLE_IN1_REG_PRS_MSG_IN_EN (0x1<<18)
22983 #define XSDM_ENABLE_IN1_REG_SDM_WAKE_IN_EN (0x1<<19)
22985 #define XSDM_ENABLE_IN1_REG_PXP_REQ_IN_EN (0x1<<20)
22987 #define XSDM_ENABLE_IN1_REG_CFC_LOAD_ACK_IN_EN (0x1<<21)
22989 #define XSDM_ENABLE_IN1_REG_CFC_LOAD_RSP_IN_EN (0x1<<22)
22991 #define XSDM_ENABLE_IN1_REG_CFC_ACINC_ACK_IN_EN (0x1<<23)
22993 #define XSDM_ENABLE_IN1_REG_CFC_ACDEC_ACK_IN_EN (0x1<<24)
22995 #define XSDM_ENABLE_IN1_REG_CFC_PB_ACK_IN_EN (0x1<<25)
22997 #define XSDM_ENABLE_IN1_REG_QM_EXT_WR_FULL_IN_EN (0x1<<26)
23000 #define XSDM_ENABLE_IN2_REG_SDM_ACK_IN_EN (0x1<<0)
23002 #define XSDM_ENABLE_IN2_REG_CM_ACK_IN_EN (0x1<<1)
23004 #define XSDM_ENABLE_IN2_REG_PB_STATUS_IN_EN (0x1<<2)
23006 #define XSDM_ENABLE_IN2_REG_PB_FULL_IN_EN (0x1<<3)
23008 #define XSDM_ENABLE_IN2_REG_PBF_EXT_WR_FULL_IN_EN (0x1<<4)
23010 #define XSDM_ENABLE_IN2_REG_PB_EXT_WR_FULL_IN_EN (0x1<<5)
23012 #define XSDM_ENABLE_IN2_REG_DORQ_REQ_IN_EN (0x1<<6)
23015 #define XSDM_ENABLE_OUT1_REG_PXP_INT_OUT_EN (0x1<<0)
23017 #define XSDM_ENABLE_OUT1_REG_THREADREADY_OUT_EN (0x1<<1)
23019 #define XSDM_ENABLE_OUT1_REG_CFC_LOAD_OUT_EN (0x1<<2)
23021 #define XSDM_ENABLE_OUT1_REG_CFC_ACINC_OUT_EN (0x1<<3)
23023 #define XSDM_ENABLE_OUT1_REG_CFC_ACDEC_OUT_EN (0x1<<4)
23025 #define XSDM_ENABLE_OUT1_REG_CFC_PB_OUT_EN (0x1<<5)
23027 #define XSDM_ENABLE_OUT1_REG_PXP_CTRL_REQ_OUT_EN (0x1<<6)
23029 #define XSDM_ENABLE_OUT1_REG_PXP_DP_REQ_OUT_EN (0x1<<7)
23031 #define XSDM_ENABLE_OUT1_REG_BRB1_CTRL_REQ_OUT_EN (0x1<<8)
23033 #define XSDM_ENABLE_OUT1_REG_BRB1_DP_REQ_OUT_EN (0x1<<9)
23035 #define XSDM_ENABLE_OUT1_REG_PRS_SYNC_OUT_EN (0x1<<10)
23037 #define XSDM_ENABLE_OUT1_REG_PRS_ACK_OUT_EN (0x1<<11)
23039 #define XSDM_ENABLE_OUT1_REG_INT_RAM_OUT_EN (0x1<<12)
23041 #define XSDM_ENABLE_OUT1_REG_PAS_BUF_OUT_EN (0x1<<13)
23043 #define XSDM_ENABLE_OUT1_REG_PXP_ASYNC_OUT_EN (0x1<<14)
23045 #define XSDM_ENABLE_OUT1_REG_PXP_CTRL_OUT_EN (0x1<<15)
23047 #define XSDM_ENABLE_OUT1_REG_PXP_DP_OUT_EN (0x1<<16)
23049 #define XSDM_ENABLE_OUT1_REG_BRB1_CTRL_FULL_OUT_EN (0x1<<17)
23051 #define XSDM_ENABLE_OUT1_REG_BRB1_DP_FULL_OUT_EN (0x1<<18)
23053 #define XSDM_ENABLE_OUT1_REG_PB_FULL_OUT_EN (0x1<<19)
23055 #define XSDM_ENABLE_OUT1_REG_PXP_CTRL_FULL_OUT_EN (0x1<<20)
23057 #define XSDM_ENABLE_OUT1_REG_EXT_FULL_OUT_EN (0x1<<21)
23059 #define XSDM_ENABLE_OUT1_REG_PXP_REQ_DONE_OUT_EN (0x1<<22)
23061 #define XSDM_ENABLE_OUT1_REG_CM_MSG_OUT_EN (0x1<<23)
23063 #define XSDM_ENABLE_OUT1_REG_CFC_SDM_ACK_OUT_EN (0x1<<24)
23065 #define XSDM_ENABLE_OUT1_REG_PB_OUT_EN (0x1<<25)
23067 #define XSDM_ENABLE_OUT1_REG_PBF_EXT_WR_OUT_EN (0x1<<26)
23070 #define XSDM_ENABLE_OUT2_REG_PB_EXT_WR_OUT_EN (0x1<<0)
23072 #define XSDM_ENABLE_OUT2_REG_DQ_EXT_WR_OUT_EN (0x1<<1)
23074 #define XSDM_ENABLE_OUT2_REG_QM_EXT_WR_OUT_EN (0x1<<2)
23076 #define XSDM_ENABLE_OUT2_REG_SDM_EXT_WR_OUT_EN (0x1<<3)
23078 #define XSDM_ENABLE_OUT2_REG_VFPF_ERR_OUT_EN (0x1<<4)
23080 #define XSDM_ENABLE_OUT2_REG_DORQ_REQ_DONE_OUT_EN (0x1<<5)
23101 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
23103 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE0_ERROR (0x1<<1)
23105 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE1_ERROR (0x1<<2)
23107 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE2_ERROR (0x1<<3)
23109 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE3_ERROR (0x1<<4)
23111 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE4_ERROR (0x1<<5)
23113 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE5_ERROR (0x1<<6)
23115 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE6_ERROR (0x1<<7)
23117 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE7_ERROR (0x1<<8)
23119 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE8_ERROR (0x1<<9)
23121 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE9_ERROR (0x1<<10)
23123 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE10_ERROR (0x1<<11)
23125 #define XSDM_XSDM_INT_STS_0_REG_INP_QUEUE11_ERROR (0x1<<12)
23127 #define XSDM_XSDM_INT_STS_0_REG_DELAY_FIFO_ERROR (0x1<<13)
23129 #define XSDM_XSDM_INT_STS_0_REG_ASYNC_HOST_ERROR (0x1<<14)
23131 #define XSDM_XSDM_INT_STS_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
23133 #define XSDM_XSDM_INT_STS_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
23135 #define XSDM_XSDM_INT_STS_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
23137 #define XSDM_XSDM_INT_STS_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
23139 #define XSDM_XSDM_INT_STS_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
23141 #define XSDM_XSDM_INT_STS_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
23143 #define XSDM_XSDM_INT_STS_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
23145 #define XSDM_XSDM_INT_STS_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
23147 #define XSDM_XSDM_INT_STS_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
23149 #define XSDM_XSDM_INT_STS_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
23151 #define XSDM_XSDM_INT_STS_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
23153 #define XSDM_XSDM_INT_STS_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
23155 #define XSDM_XSDM_INT_STS_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
23157 #define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
23159 #define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
23161 #define XSDM_XSDM_INT_STS_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
23163 #define XSDM_XSDM_INT_STS_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
23166 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
23168 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
23170 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
23172 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
23174 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
23176 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
23178 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
23180 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
23182 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
23184 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
23186 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
23188 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
23190 #define XSDM_XSDM_INT_STS_CLR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
23192 #define XSDM_XSDM_INT_STS_CLR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
23194 #define XSDM_XSDM_INT_STS_CLR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
23196 #define XSDM_XSDM_INT_STS_CLR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
23198 #define XSDM_XSDM_INT_STS_CLR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
23200 #define XSDM_XSDM_INT_STS_CLR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
23202 #define XSDM_XSDM_INT_STS_CLR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
23204 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
23206 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
23208 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
23210 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
23212 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
23214 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
23216 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
23218 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
23220 #define XSDM_XSDM_INT_STS_CLR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
23222 #define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
23224 #define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
23226 #define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
23228 #define XSDM_XSDM_INT_STS_CLR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
23231 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
23233 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE0_ERROR (0x1<<1)
23235 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE1_ERROR (0x1<<2)
23237 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE2_ERROR (0x1<<3)
23239 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE3_ERROR (0x1<<4)
23241 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE4_ERROR (0x1<<5)
23243 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE5_ERROR (0x1<<6)
23245 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE6_ERROR (0x1<<7)
23247 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE7_ERROR (0x1<<8)
23249 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE8_ERROR (0x1<<9)
23251 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE9_ERROR (0x1<<10)
23253 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE10_ERROR (0x1<<11)
23255 #define XSDM_XSDM_INT_STS_WR_0_REG_INP_QUEUE11_ERROR (0x1<<12)
23257 #define XSDM_XSDM_INT_STS_WR_0_REG_DELAY_FIFO_ERROR (0x1<<13)
23259 #define XSDM_XSDM_INT_STS_WR_0_REG_ASYNC_HOST_ERROR (0x1<<14)
23261 #define XSDM_XSDM_INT_STS_WR_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
23263 #define XSDM_XSDM_INT_STS_WR_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
23265 #define XSDM_XSDM_INT_STS_WR_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
23267 #define XSDM_XSDM_INT_STS_WR_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
23269 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
23271 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
23273 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
23275 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
23277 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
23279 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
23281 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
23283 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
23285 #define XSDM_XSDM_INT_STS_WR_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
23287 #define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
23289 #define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
23291 #define XSDM_XSDM_INT_STS_WR_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
23293 #define XSDM_XSDM_INT_STS_WR_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
23296 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
23298 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE0_ERROR (0x1<<1)
23300 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE1_ERROR (0x1<<2)
23302 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE2_ERROR (0x1<<3)
23304 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE3_ERROR (0x1<<4)
23306 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE4_ERROR (0x1<<5)
23308 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE5_ERROR (0x1<<6)
23310 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE6_ERROR (0x1<<7)
23312 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE7_ERROR (0x1<<8)
23314 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE8_ERROR (0x1<<9)
23316 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE9_ERROR (0x1<<10)
23318 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE10_ERROR (0x1<<11)
23320 #define XSDM_XSDM_INT_MASK_0_REG_INP_QUEUE11_ERROR (0x1<<12)
23322 #define XSDM_XSDM_INT_MASK_0_REG_DELAY_FIFO_ERROR (0x1<<13)
23324 #define XSDM_XSDM_INT_MASK_0_REG_ASYNC_HOST_ERROR (0x1<<14)
23326 #define XSDM_XSDM_INT_MASK_0_REG_SYNC_PRS_FIFO_ERROR (0x1<<15)
23328 #define XSDM_XSDM_INT_MASK_0_REG_SYNC_SER_FIFO_ERROR (0x1<<16)
23330 #define XSDM_XSDM_INT_MASK_0_REG_CFC_LOAD_RSP_ERROR (0x1<<17)
23332 #define XSDM_XSDM_INT_MASK_0_REG_CFC_LOAD_PEND_ERROR (0x1<<18)
23334 #define XSDM_XSDM_INT_MASK_0_REG_DST_INT_RAM_WAIT_ERROR (0x1<<19)
23336 #define XSDM_XSDM_INT_MASK_0_REG_DST_PAS_BUF_WAIT_ERROR (0x1<<20)
23338 #define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_CTRL_IMMED_ERROR (0x1<<21)
23340 #define XSDM_XSDM_INT_MASK_0_REG_DST_PB_IMMED_ERROR (0x1<<22)
23342 #define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_CTRL_DST_PEND_ERROR (0x1<<23)
23344 #define XSDM_XSDM_INT_MASK_0_REG_DST_PXP_DP_DST_PEND_ERROR (0x1<<24)
23346 #define XSDM_XSDM_INT_MASK_0_REG_DST_BRB1_SRC_PEND_ERROR (0x1<<25)
23348 #define XSDM_XSDM_INT_MASK_0_REG_DST_BRB1_SRC_ADDR_ERROR (0x1<<26)
23350 #define XSDM_XSDM_INT_MASK_0_REG_DST_NONE_DP_DST_PEND_ERROR (0x1<<27)
23352 #define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_CTRL_PEND_ERROR (0x1<<28)
23354 #define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_DP_PEND_ERROR (0x1<<29)
23356 #define XSDM_XSDM_INT_MASK_0_REG_RSP_BRB1_DP_DST_ERROR (0x1<<30)
23358 #define XSDM_XSDM_INT_MASK_0_REG_RSP_INT_RAM_PEND_ERROR (0x1<<31)
23361 #define XSDM_XSDM_INT_STS_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
23363 #define XSDM_XSDM_INT_STS_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
23365 #define XSDM_XSDM_INT_STS_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
23367 #define XSDM_XSDM_INT_STS_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
23369 #define XSDM_XSDM_INT_STS_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
23371 #define XSDM_XSDM_INT_STS_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
23373 #define XSDM_XSDM_INT_STS_1_REG_CM_DELAY_ERROR (0x1<<6)
23375 #define XSDM_XSDM_INT_STS_1_REG_PXP_DELAY_ERROR (0x1<<7)
23377 #define XSDM_XSDM_INT_STS_1_REG_TIMER_ADDR_ERROR (0x1<<8)
23379 #define XSDM_XSDM_INT_STS_1_REG_TIMER_PEND_ERROR (0x1<<9)
23381 #define XSDM_XSDM_INT_STS_1_REG_DORQ_DPM_ERROR (0x1<<10)
23383 #define XSDM_XSDM_INT_STS_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
23385 #define XSDM_XSDM_INT_STS_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
23387 #define XSDM_XSDM_INT_STS_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
23390 #define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
23392 #define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
23394 #define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
23396 #define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
23398 #define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
23400 #define XSDM_XSDM_INT_STS_CLR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
23402 #define XSDM_XSDM_INT_STS_CLR_1_REG_CM_DELAY_ERROR (0x1<<6)
23404 #define XSDM_XSDM_INT_STS_CLR_1_REG_PXP_DELAY_ERROR (0x1<<7)
23406 #define XSDM_XSDM_INT_STS_CLR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
23408 #define XSDM_XSDM_INT_STS_CLR_1_REG_TIMER_PEND_ERROR (0x1<<9)
23410 #define XSDM_XSDM_INT_STS_CLR_1_REG_DORQ_DPM_ERROR (0x1<<10)
23412 #define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
23414 #define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
23416 #define XSDM_XSDM_INT_STS_CLR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
23419 #define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
23421 #define XSDM_XSDM_INT_STS_WR_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
23423 #define XSDM_XSDM_INT_STS_WR_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
23425 #define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
23427 #define XSDM_XSDM_INT_STS_WR_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
23429 #define XSDM_XSDM_INT_STS_WR_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
23431 #define XSDM_XSDM_INT_STS_WR_1_REG_CM_DELAY_ERROR (0x1<<6)
23433 #define XSDM_XSDM_INT_STS_WR_1_REG_PXP_DELAY_ERROR (0x1<<7)
23435 #define XSDM_XSDM_INT_STS_WR_1_REG_TIMER_ADDR_ERROR (0x1<<8)
23437 #define XSDM_XSDM_INT_STS_WR_1_REG_TIMER_PEND_ERROR (0x1<<9)
23439 #define XSDM_XSDM_INT_STS_WR_1_REG_DORQ_DPM_ERROR (0x1<<10)
23441 #define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
23443 #define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
23445 #define XSDM_XSDM_INT_STS_WR_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
23448 #define XSDM_XSDM_INT_MASK_1_REG_RSP_PB_PEND_ERROR (0x1<<0)
23450 #define XSDM_XSDM_INT_MASK_1_REG_RSP_BRB1_CTRL_RD_DATA_ERROR (0x1<<1)
23452 #define XSDM_XSDM_INT_MASK_1_REG_RSP_BRB1_DP_RD_DATA_ERROR (0x1<<2)
23454 #define XSDM_XSDM_INT_MASK_1_REG_RSP_PB_RD_DATA_ERROR (0x1<<3)
23456 #define XSDM_XSDM_INT_MASK_1_REG_RSP_INT_RAM_RD_DATA_ERROR (0x1<<4)
23458 #define XSDM_XSDM_INT_MASK_1_REG_RSP_PXP_CTRL_RD_DATA_ERROR (0x1<<5)
23460 #define XSDM_XSDM_INT_MASK_1_REG_CM_DELAY_ERROR (0x1<<6)
23462 #define XSDM_XSDM_INT_MASK_1_REG_PXP_DELAY_ERROR (0x1<<7)
23464 #define XSDM_XSDM_INT_MASK_1_REG_TIMER_ADDR_ERROR (0x1<<8)
23466 #define XSDM_XSDM_INT_MASK_1_REG_TIMER_PEND_ERROR (0x1<<9)
23468 #define XSDM_XSDM_INT_MASK_1_REG_DORQ_DPM_ERROR (0x1<<10)
23470 #define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_DP_SRC_DONE_ERROR (0x1<<11)
23472 #define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_DP_DST_DONE_ERROR (0x1<<12)
23474 #define XSDM_XSDM_INT_MASK_1_REG_DST_PXP_CTRL_DONE_ERROR (0x1<<13)
23477 #define XSDM_XSDM_PRTY_STS_REG_PARITY (0x1<<0)
23479 #define XSDM_XSDM_PRTY_STS_REG_TIMERS (0x1<<1)
23481 #define XSDM_XSDM_PRTY_STS_REG_INP_QUEUE (0x1<<2)
23483 #define XSDM_XSDM_PRTY_STS_REG_ASYNC_RD_DATA (0x1<<3)
23485 #define XSDM_XSDM_PRTY_STS_REG_BRB1_CTRL_RD_DATA (0x1<<4)
23487 #define XSDM_XSDM_PRTY_STS_REG_BRB1_DP_RD_DATA (0x1<<5)
23489 #define XSDM_XSDM_PRTY_STS_REG_PB_RD_DATA (0x1<<6)
23491 #define XSDM_XSDM_PRTY_STS_REG_PXP_CTRL_RD_DATA (0x1<<7)
23493 #define XSDM_XSDM_PRTY_STS_REG_INT_RAM_RD_DATA (0x1<<8)
23495 #define XSDM_XSDM_PRTY_STS_REG_STAT_RD_DATA (0x1<<9)
23497 #define XSDM_XSDM_PRTY_STS_REG_CM_QUEUE_RD_DATA (0x1<<10)
23500 #define XSDM_XSDM_PRTY_STS_CLR_REG_PARITY (0x1<<0)
23502 #define XSDM_XSDM_PRTY_STS_CLR_REG_TIMERS (0x1<<1)
23504 #define XSDM_XSDM_PRTY_STS_CLR_REG_INP_QUEUE (0x1<<2)
23506 #define XSDM_XSDM_PRTY_STS_CLR_REG_ASYNC_RD_DATA (0x1<<3)
23508 #define XSDM_XSDM_PRTY_STS_CLR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
23510 #define XSDM_XSDM_PRTY_STS_CLR_REG_BRB1_DP_RD_DATA (0x1<<5)
23512 #define XSDM_XSDM_PRTY_STS_CLR_REG_PB_RD_DATA (0x1<<6)
23514 #define XSDM_XSDM_PRTY_STS_CLR_REG_PXP_CTRL_RD_DATA (0x1<<7)
23516 #define XSDM_XSDM_PRTY_STS_CLR_REG_INT_RAM_RD_DATA (0x1<<8)
23518 #define XSDM_XSDM_PRTY_STS_CLR_REG_STAT_RD_DATA (0x1<<9)
23520 #define XSDM_XSDM_PRTY_STS_CLR_REG_CM_QUEUE_RD_DATA (0x1<<10)
23523 #define XSDM_XSDM_PRTY_STS_WR_REG_PARITY (0x1<<0)
23525 #define XSDM_XSDM_PRTY_STS_WR_REG_TIMERS (0x1<<1)
23527 #define XSDM_XSDM_PRTY_STS_WR_REG_INP_QUEUE (0x1<<2)
23529 #define XSDM_XSDM_PRTY_STS_WR_REG_ASYNC_RD_DATA (0x1<<3)
23531 #define XSDM_XSDM_PRTY_STS_WR_REG_BRB1_CTRL_RD_DATA (0x1<<4)
23533 #define XSDM_XSDM_PRTY_STS_WR_REG_BRB1_DP_RD_DATA (0x1<<5)
23535 #define XSDM_XSDM_PRTY_STS_WR_REG_PB_RD_DATA (0x1<<6)
23537 #define XSDM_XSDM_PRTY_STS_WR_REG_PXP_CTRL_RD_DATA (0x1<<7)
23539 #define XSDM_XSDM_PRTY_STS_WR_REG_INT_RAM_RD_DATA (0x1<<8)
23541 #define XSDM_XSDM_PRTY_STS_WR_REG_STAT_RD_DATA (0x1<<9)
23543 #define XSDM_XSDM_PRTY_STS_WR_REG_CM_QUEUE_RD_DATA (0x1<<10)
23546 #define XSDM_XSDM_PRTY_MASK_REG_PARITY (0x1<<0)
23548 #define XSDM_XSDM_PRTY_MASK_REG_TIMERS (0x1<<1)
23550 #define XSDM_XSDM_PRTY_MASK_REG_INP_QUEUE (0x1<<2)
23552 #define XSDM_XSDM_PRTY_MASK_REG_ASYNC_RD_DATA (0x1<<3)
23554 #define XSDM_XSDM_PRTY_MASK_REG_BRB1_CTRL_RD_DATA (0x1<<4)
23556 #define XSDM_XSDM_PRTY_MASK_REG_BRB1_DP_RD_DATA (0x1<<5)
23558 #define XSDM_XSDM_PRTY_MASK_REG_PB_RD_DATA (0x1<<6)
23560 #define XSDM_XSDM_PRTY_MASK_REG_PXP_CTRL_RD_DATA (0x1<<7)
23562 #define XSDM_XSDM_PRTY_MASK_REG_INT_RAM_RD_DATA (0x1<<8)
23564 #define XSDM_XSDM_PRTY_MASK_REG_STAT_RD_DATA (0x1<<9)
23566 #define XSDM_XSDM_PRTY_MASK_REG_CM_QUEUE_RD_DATA (0x1<<10)
23584 #define XSDM_REG_ASYNC_HOST_EMPTY 0x166408UL //ACCESS:R DataWidth:0x1 Description: async fifo empty in sdm_async block
23586 #define XSDM_REG_ASYNC_HOST_FULL 0x16640cUL //ACCESS:R DataWidth:0x1 Description: async fifo full in sdm_async block
23588 #define XSDM_REG_CFC_LOAD_PEND_EMPTY 0x166410UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo empty in sdm_dma_dst block
23590 #define XSDM_REG_CFC_LOAD_PEND_FULL 0x166414UL //ACCESS:R DataWidth:0x1 Description: cfc load pending fifo full in sdm_cfc block
23592 #define XSDM_REG_CFC_LOAD_RSP_EMPTY 0x166418UL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo empty in sdm_dma_dst block
23594 #define XSDM_REG_CFC_LOAD_RSP_FULL 0x16641cUL //ACCESS:R DataWidth:0x1 Description: cfc load rsp fifo full in sdm_cfcblock
23596 #define XSDM_REG_CM_DELAY_EMPTY 0x166420UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo empty in sdm_dma_dst block
23598 #define XSDM_REG_CM_DELAY_FULL 0x166424UL //ACCESS:R DataWidth:0x1 Description: cm delay fifo full in sdm_cm block
23600 #define XSDM_REG_CM_QUEUE_EMPTY 0x166428UL //ACCESS:R DataWidth:0x1 Description: cm queue fifo empty in sdm_dma_dst block
23602 #define XSDM_REG_CM_QUEUE_FULL 0x16642cUL //ACCESS:R DataWidth:0x1 Description: cm queue fifo full in sdm_cm block
23604 #define XSDM_REG_DELAY_FIFO_EMPTY 0x166430UL //ACCESS:R DataWidth:0x1 Description: delay FIFO empty in sdm_inp block
23606 #define XSDM_REG_DELAY_FIFO_FULL 0x166434UL //ACCESS:R DataWidth:0x1 Description: delay FIFO full in sdm_inp block
23608 #define XSDM_REG_DST_BRB1_CTRL_SRC_ADDR_EMPTY 0x166438UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo empty in sdm_dma_dst block
23610 #define XSDM_REG_DST_BRB1_CTRL_SRC_ADDR_FULL 0x16643cUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src address fifo full in sdm_dma_dst block
23612 #define XSDM_REG_DST_BRB1_CTRL_SRC_PEND_EMPTY 0x166440UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo empty in sdm_dma_dst block
23614 #define XSDM_REG_DST_BRB1_CTRL_SRC_PEND_FULL 0x166444UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl_src pending fifo full in sdm_dma_dst block
23616 #define XSDM_REG_DST_INT_RAM_IF_FULL 0x166448UL //ACCESS:R DataWidth:0x1 Description: int_ram if full in sdm_dma_dst block
23618 #define XSDM_REG_DST_INT_RAM_WAIT_EMPTY 0x16644cUL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo empty in sdm_dma_dst block
23620 #define XSDM_REG_DST_INT_RAM_WAIT_FULL 0x166450UL //ACCESS:R DataWidth:0x1 Description: int_ram_wait fifo full in sdm_dma_dst block
23622 #define XSDM_REG_DST_NONE_PEND_EMPTY 0x166454UL //ACCESS:R DataWidth:0x1 Description: none pending fifo empty in sdm_dma_dst block
23624 #define XSDM_REG_DST_NONE_PEND_FULL 0x166458UL //ACCESS:R DataWidth:0x1 Description: none pending fifo full in sdm_dma_dst block
23626 #define XSDM_REG_DST_PAS_BUF_IF_FULL 0x16645cUL //ACCESS:R DataWidth:0x1 Description: pas_buf if full in sdm_dma_dst block
23628 #define XSDM_REG_DST_PAS_BUF_WAIT_EMPTY 0x166460UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo empty in sdm_dma_dst block
23630 #define XSDM_REG_DST_PAS_BUF_WAIT_FULL 0x166464UL //ACCESS:R DataWidth:0x1 Description: pas_buf_wait fifo full in sdm_dma_dst block
23632 #define XSDM_REG_DST_PB_IF_FULL 0x166468UL //ACCESS:R DataWidth:0x1 Description: pb if full in sdm_dma_dst block
23634 #define XSDM_REG_DST_PB_IMMED_EMPTY 0x16646cUL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo empty in sdm_dma_dst block
23636 #define XSDM_REG_DST_PB_IMMED_FULL 0x166470UL //ACCESS:R DataWidth:0x1 Description: pb immediate fifo full in sdm_dma_dst block
23638 #define XSDM_REG_DST_PXP_CTRL_DST_PEND_EMPTY 0x166474UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo empty in sdm_dma_dst block
23640 #define XSDM_REG_DST_PXP_CTRL_DST_PEND_FULL 0x166478UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_dst pending fifo full in sdm_dma_dst block
23642 #define XSDM_REG_DST_PXP_CTRL_IF_FULL 0x16647cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl if full in sdm_dma_dst block
23644 #define XSDM_REG_DST_PXP_CTRL_IMMED_EMPTY 0x166480UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo empty in sdm_dma_dst block
23646 #define XSDM_REG_DST_PXP_CTRL_IMMED_FULL 0x166484UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl immediate fifo full in sdm_dma_dst block
23648 #define XSDM_REG_DST_PXP_CTRL_LINK_EMPTY 0x166488UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list empty in sdm_dma_dst block
23650 #define XSDM_REG_DST_PXP_CTRL_LINK_FULL 0x16648cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl link list full in sdm_dma_dst block
23652 #define XSDM_REG_DST_PXP_CTRL_SRC_PEND_EMPTY 0x166490UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo empty in sdm_dma_dst block
23654 #define XSDM_REG_DST_PXP_CTRL_SRC_PEND_FULL 0x166494UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl_src pending fifo full in sdm_dma_dst block
23656 #define XSDM_REG_DST_PXP_DP_DST_PEND_EMPTY 0x166498UL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo empty in sdm_dma_dst block
23658 #define XSDM_REG_DST_PXP_DP_DST_PEND_FULL 0x16649cUL //ACCESS:R DataWidth:0x1 Description: pxp_dp_dst pending fifo full in sdm_dma_dst block
23660 #define XSDM_REG_DST_PXP_DP_IF_FULL 0x1664a0UL //ACCESS:R DataWidth:0x1 Description: pxp_dp if full in sdm_dma_dst block
23662 #define XSDM_REG_DST_PXP_DP_LINK_EMPTY 0x1664a4UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list empty in sdm_dma_dst block
23664 #define XSDM_REG_DST_PXP_DP_LINK_FULL 0x1664a8UL //ACCESS:R DataWidth:0x1 Description: pxp_dp link list full in sdm_dma_dst block
23680 #define XSDM_REG_PB_FULL 0x1664c8UL //ACCESS:R DataWidth:0x1 Description: UPB IF full in sdm_inp block
23682 #define XSDM_REG_PBF_FULL 0x1664ccUL //ACCESS:R DataWidth:0x1 Description: PBF if full in sdm_inp block
23684 #define XSDM_REG_PXP_DELAY_EMPTY 0x1664d0UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo empty in sdm_dma_dst block
23686 #define XSDM_REG_PXP_DELAY_FULL 0x1664d4UL //ACCESS:R DataWidth:0x1 Description: pxp switch delay fifo full in sdm_cm block
23688 #define XSDM_REG_QM_FULL 0x1664d8UL //ACCESS:R DataWidth:0x1 Description: QM IF full in sdm_inp block
23700 #define XSDM_REG_RSP_BRB1_CTRL_IF_FULL 0x1664f0UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl if is full in sdm_dma_rsp block
23702 #define XSDM_REG_RSP_BRB1_CTRL_PEND_EMPTY 0x1664f4UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo empty in sdm_dma_rsp block
23704 #define XSDM_REG_RSP_BRB1_CTRL_PEND_FULL 0x1664f8UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl pending fifo full in sdm_dma_rsp block
23706 #define XSDM_REG_RSP_BRB1_CTRL_RDATA_EMPTY 0x1664fcUL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo empty in sdm_dma_rsp block
23708 #define XSDM_REG_RSP_BRB1_CTRL_RDATA_FULL 0x166500UL //ACCESS:R DataWidth:0x1 Description: brb1_ctrl rd_data fifo full in sdm_dma_rsp block
23710 #define XSDM_REG_RSP_BRB1_DP_DST_EMPTY 0x166504UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo empty in sdm_dma_rsp block
23712 #define XSDM_REG_RSP_BRB1_DP_DST_FULL 0x166508UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending dst fifo full in sdm_dma_rsp block
23714 #define XSDM_REG_RSP_BRB1_DP_IF_FULL 0x16650cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp if is full in sdm_dma_rsp block
23716 #define XSDM_REG_RSP_BRB1_DP_PEND_EMPTY 0x166510UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo empty in sdm_dma_rsp block
23718 #define XSDM_REG_RSP_BRB1_DP_PEND_FULL 0x166514UL //ACCESS:R DataWidth:0x1 Description: brb1_dp pending fifo full in sdm_dma_rsp block
23720 #define XSDM_REG_RSP_BRB1_DP_RDATA_EMPTY 0x166518UL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo empty in sdm_dma_rsp block
23722 #define XSDM_REG_RSP_BRB1_DP_RDATA_FULL 0x16651cUL //ACCESS:R DataWidth:0x1 Description: brb1_dp rd_data fifo full in sdm_dma_rsp block
23724 #define XSDM_REG_RSP_INT_RAM_PEND_EMPTY 0x166520UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo empty in sdm_dma_rsp block
23726 #define XSDM_REG_RSP_INT_RAM_PEND_FULL 0x166524UL //ACCESS:R DataWidth:0x1 Description: int_ram pending fifo full in sdm_dma_rsp block
23728 #define XSDM_REG_RSP_INT_RAM_RDATA_EMPTY 0x166528UL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo empty in sdm_dma_rsp block
23730 #define XSDM_REG_RSP_INT_RAM_RDATA_FULL 0x16652cUL //ACCESS:R DataWidth:0x1 Description: int_ram rd_data fifo full in sdm_dma_rsp block
23732 #define XSDM_REG_RSP_PB_IF_FULL 0x166530UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
23734 #define XSDM_REG_RSP_PB_PEND_EMPTY 0x166534UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo empty in sdm_dma_rsp block
23736 #define XSDM_REG_RSP_PB_PEND_FULL 0x166538UL //ACCESS:R DataWidth:0x1 Description: pb pending fifo full in sdm_dma_rsp block
23738 #define XSDM_REG_RSP_PB_RDATA_EMPTY 0x16653cUL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo empty in sdm_dma_rsp block
23740 #define XSDM_REG_RSP_PB_RDATA_FULL 0x166540UL //ACCESS:R DataWidth:0x1 Description: pb rd_data fifo full in sdm_dma_rsp block
23742 #define XSDM_REG_RSP_PXP_CTRL_IF_FULL 0x166544UL //ACCESS:R DataWidth:0x1 Description: pb if is full in sdm_dma_rsp block
23744 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548UL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo empty in sdm_dma_rsp block
23746 #define XSDM_REG_RSP_PXP_CTRL_RDATA_FULL 0x16654cUL //ACCESS:R DataWidth:0x1 Description: pxp_ctrl rd_data fifo full in sdm_dma_rsp block
23748 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550UL //ACCESS:R DataWidth:0x1 Description: parser fifo empty in sdm_sync block
23750 #define XSDM_REG_SYNC_PARSER_FULL 0x166554UL //ACCESS:R DataWidth:0x1 Description: parser fifo full in sdm_sync block
23752 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558UL //ACCESS:R DataWidth:0x1 Description: parser serial fifo empty in sdm_sync block
23754 #define XSDM_REG_SYNC_SYNC_FULL 0x16655cUL //ACCESS:R DataWidth:0x1 Description: parser serial fifo full in sdm_sync block
23756 #define XSDM_REG_TIMERS_ADDR_EMPTY 0x166560UL //ACCESS:R DataWidth:0x1 Description: address FIFO empty in sdm_timers block
23758 #define XSDM_REG_TIMERS_ADDR_FULL 0x166564UL //ACCESS:R DataWidth:0x1 Description: address FIFO full in sdm_timers block
23760 #define XSDM_REG_TIMERS_PEND_EMPTY 0x166568UL //ACCESS:R DataWidth:0x1 Description: pending FIFO empty in sdm_timers block
23762 #define XSDM_REG_TIMERS_PEND_FULL 0x16656cUL //ACCESS:R DataWidth:0x1 Description: pending FIFO full in sdm_timers block
23786 #define XSEM_REG_THREAD_INTER_CNT_ENABLE 0x280018UL //ACCESS:RW DataWidth:0x1 Description: Enable for start count of counter ~xsem_registers_thread_inter_cnt.thread_inter_cnt
23822 #define XSEM_ENABLE_IN_REG_FIC0_ENABLE_IN (0x1<<0)
23824 #define XSEM_ENABLE_IN_REG_FIC1_ENABLE_IN (0x1<<1)
23826 #define XSEM_ENABLE_IN_REG_PASSIVE_ENABLE_IN (0x1<<2)
23828 #define XSEM_ENABLE_IN_REG_GENERAL_ENABLE_IN (0x1<<3)
23830 #define XSEM_ENABLE_IN_REG_THREAD_RDY_ENABLE_IN (0x1<<4)
23832 #define XSEM_ENABLE_IN_REG_EXT_RD_DATA_ENABLE_IN (0x1<<5)
23834 #define XSEM_ENABLE_IN_REG_EXT_FULL_ENABLE_IN (0x1<<6)
23836 #define XSEM_ENABLE_IN_REG_RAM0_ENABLE_IN (0x1<<7)
23838 #define XSEM_ENABLE_IN_REG_RAM1_ENABLE_IN (0x1<<8)
23840 #define XSEM_ENABLE_IN_REG_FOC0_ACK_ENABLE_IN (0x1<<9)
23842 #define XSEM_ENABLE_IN_REG_FOC1_ACK_ENABLE_IN (0x1<<10)
23844 #define XSEM_ENABLE_IN_REG_FOC2_ACK_ENABLE_IN (0x1<<11)
23846 #define XSEM_ENABLE_IN_REG_FOC3_ACK_ENABLE_IN (0x1<<12)
23848 #define XSEM_ENABLE_IN_REG_WAITP_ENABLE_IN (0x1<<13)
23850 #define XSEM_ENABLE_IN_REG_VFPF_ERROR_ENABLE_IN (0x1<<14)
23853 #define XSEM_ENABLE_OUT_REG_EXT_RD_REQ_ENABLE_OUT (0x1<<0)
23855 #define XSEM_ENABLE_OUT_REG_EXT_WR_REQ_ENABLE_OUT (0x1<<1)
23857 #define XSEM_ENABLE_OUT_REG_FOC0_ENABLE_OUT (0x1<<2)
23859 #define XSEM_ENABLE_OUT_REG_FOC1_ENABLE_OUT (0x1<<3)
23861 #define XSEM_ENABLE_OUT_REG_FOC2_ENABLE_OUT (0x1<<4)
23863 #define XSEM_ENABLE_OUT_REG_FOC3_ENABLE_OUT (0x1<<5)
23865 #define XSEM_ENABLE_OUT_REG_PASSIVE_ENABLE_OUT (0x1<<6)
23867 #define XSEM_ENABLE_OUT_REG_RAM0_ENABLE_OUT (0x1<<7)
23869 #define XSEM_ENABLE_OUT_REG_RAM1_ENABLE_OUT (0x1<<8)
23871 #define XSEM_ENABLE_OUT_REG_WAITP_ENABLE_OUT (0x1<<9)
23884 #define XSEM_REG_CLEAR_WAITP 0x2800d8UL //ACCESS:RW DataWidth:0x1 Description: Write 1 to this register will disable waitp from this storm to other storms
23886 #define XSEM_REG_SLOW_DBG_ACTIVE 0x2800e0UL //ACCESS:RW DataWidth:0x1 Description: debug mode is active
23887 #define XSEM_REG_DBG_MSG_SRC 0x2800e4UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~xsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0only FIC-s output to debug bus; 1=both FIC-s and passive buffer.
23888 #define XSEM_REG_DBG_MODE0_CFG 0x2800e8UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~xsem_registers_slow_dbg_mode.slow_dbg_mode =0. If =0 all the message output to debug bus; 1=partial message.
23890 #define XSEM_REG_DBG_MODE1_CFG 0x2800f0UL //ACCESS:RW DataWidth:0x1 Description: Applicable only when ~xsem_registers_slow_dbg_mode.slow_dbg_mode =1. If=0 output to debug bus without the data; 1=with the data.
23891 #define XSEM_REG_DBG_EACH_CYLE 0x2800f4UL //ACCESS:RW DataWidth:0x1 Description: If=0 output every cycle full indication or thread status; 1= output only when there is a change.
23896 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
23898 #define XSEM_XSEM_INT_STS_0_REG_FIC0_LAST_ERROR (0x1<<1)
23900 #define XSEM_XSEM_INT_STS_0_REG_FIC1_LAST_ERROR (0x1<<2)
23902 #define XSEM_XSEM_INT_STS_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
23904 #define XSEM_XSEM_INT_STS_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
23906 #define XSEM_XSEM_INT_STS_0_REG_FIC0_FIFO_ERROR (0x1<<5)
23908 #define XSEM_XSEM_INT_STS_0_REG_FIC1_FIFO_ERROR (0x1<<6)
23910 #define XSEM_XSEM_INT_STS_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
23912 #define XSEM_XSEM_INT_STS_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
23914 #define XSEM_XSEM_INT_STS_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
23916 #define XSEM_XSEM_INT_STS_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
23918 #define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
23920 #define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
23922 #define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
23924 #define XSEM_XSEM_INT_STS_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
23926 #define XSEM_XSEM_INT_STS_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
23928 #define XSEM_XSEM_INT_STS_0_REG_MAX_HANDLER_ERROR (0x1<<16)
23930 #define XSEM_XSEM_INT_STS_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
23932 #define XSEM_XSEM_INT_STS_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
23934 #define XSEM_XSEM_INT_STS_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
23936 #define XSEM_XSEM_INT_STS_0_REG_RD_EMPTY_CAM (0x1<<20)
23938 #define XSEM_XSEM_INT_STS_0_REG_WR_FULL_CAM (0x1<<21)
23940 #define XSEM_XSEM_INT_STS_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
23942 #define XSEM_XSEM_INT_STS_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
23944 #define XSEM_XSEM_INT_STS_0_REG_CAM_OUT_FIFO (0x1<<24)
23946 #define XSEM_XSEM_INT_STS_0_REG_FIN_FIFO (0x1<<25)
23948 #define XSEM_XSEM_INT_STS_0_REG_SET0_THREAD_ERROR (0x1<<26)
23950 #define XSEM_XSEM_INT_STS_0_REG_SET1_THREAD_ERROR (0x1<<27)
23952 #define XSEM_XSEM_INT_STS_0_REG_THREAD_OVERRUN (0x1<<28)
23954 #define XSEM_XSEM_INT_STS_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
23956 #define XSEM_XSEM_INT_STS_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
23958 #define XSEM_XSEM_INT_STS_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
23961 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
23963 #define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_LAST_ERROR (0x1<<1)
23965 #define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_LAST_ERROR (0x1<<2)
23967 #define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
23969 #define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
23971 #define XSEM_XSEM_INT_STS_CLR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
23973 #define XSEM_XSEM_INT_STS_CLR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
23975 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
23977 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
23979 #define XSEM_XSEM_INT_STS_CLR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
23981 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
23983 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
23985 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
23987 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
23989 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
23991 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
23993 #define XSEM_XSEM_INT_STS_CLR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
23995 #define XSEM_XSEM_INT_STS_CLR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
23997 #define XSEM_XSEM_INT_STS_CLR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
23999 #define XSEM_XSEM_INT_STS_CLR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
24001 #define XSEM_XSEM_INT_STS_CLR_0_REG_RD_EMPTY_CAM (0x1<<20)
24003 #define XSEM_XSEM_INT_STS_CLR_0_REG_WR_FULL_CAM (0x1<<21)
24005 #define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
24007 #define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
24009 #define XSEM_XSEM_INT_STS_CLR_0_REG_CAM_OUT_FIFO (0x1<<24)
24011 #define XSEM_XSEM_INT_STS_CLR_0_REG_FIN_FIFO (0x1<<25)
24013 #define XSEM_XSEM_INT_STS_CLR_0_REG_SET0_THREAD_ERROR (0x1<<26)
24015 #define XSEM_XSEM_INT_STS_CLR_0_REG_SET1_THREAD_ERROR (0x1<<27)
24017 #define XSEM_XSEM_INT_STS_CLR_0_REG_THREAD_OVERRUN (0x1<<28)
24019 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
24021 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
24023 #define XSEM_XSEM_INT_STS_CLR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
24026 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
24028 #define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_LAST_ERROR (0x1<<1)
24030 #define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_LAST_ERROR (0x1<<2)
24032 #define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
24034 #define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
24036 #define XSEM_XSEM_INT_STS_WR_0_REG_FIC0_FIFO_ERROR (0x1<<5)
24038 #define XSEM_XSEM_INT_STS_WR_0_REG_FIC1_FIFO_ERROR (0x1<<6)
24040 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
24042 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
24044 #define XSEM_XSEM_INT_STS_WR_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
24046 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
24048 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
24050 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
24052 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
24054 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
24056 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
24058 #define XSEM_XSEM_INT_STS_WR_0_REG_MAX_HANDLER_ERROR (0x1<<16)
24060 #define XSEM_XSEM_INT_STS_WR_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
24062 #define XSEM_XSEM_INT_STS_WR_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
24064 #define XSEM_XSEM_INT_STS_WR_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
24066 #define XSEM_XSEM_INT_STS_WR_0_REG_RD_EMPTY_CAM (0x1<<20)
24068 #define XSEM_XSEM_INT_STS_WR_0_REG_WR_FULL_CAM (0x1<<21)
24070 #define XSEM_XSEM_INT_STS_WR_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
24072 #define XSEM_XSEM_INT_STS_WR_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
24074 #define XSEM_XSEM_INT_STS_WR_0_REG_CAM_OUT_FIFO (0x1<<24)
24076 #define XSEM_XSEM_INT_STS_WR_0_REG_FIN_FIFO (0x1<<25)
24078 #define XSEM_XSEM_INT_STS_WR_0_REG_SET0_THREAD_ERROR (0x1<<26)
24080 #define XSEM_XSEM_INT_STS_WR_0_REG_SET1_THREAD_ERROR (0x1<<27)
24082 #define XSEM_XSEM_INT_STS_WR_0_REG_THREAD_OVERRUN (0x1<<28)
24084 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
24086 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
24088 #define XSEM_XSEM_INT_STS_WR_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
24091 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
24093 #define XSEM_XSEM_INT_MASK_0_REG_FIC0_LAST_ERROR (0x1<<1)
24095 #define XSEM_XSEM_INT_MASK_0_REG_FIC1_LAST_ERROR (0x1<<2)
24097 #define XSEM_XSEM_INT_MASK_0_REG_FIC0_LENGTH_ERROR (0x1<<3)
24099 #define XSEM_XSEM_INT_MASK_0_REG_FIC1_LENGTH_ERROR (0x1<<4)
24101 #define XSEM_XSEM_INT_MASK_0_REG_FIC0_FIFO_ERROR (0x1<<5)
24103 #define XSEM_XSEM_INT_MASK_0_REG_FIC1_FIFO_ERROR (0x1<<6)
24105 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_INT_PUSH_ERROR (0x1<<7)
24107 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_INT_POP_ERROR (0x1<<8)
24109 #define XSEM_XSEM_INT_MASK_0_REG_PAS_BUF_FIFO_ERROR (0x1<<9)
24111 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_FIN_POP_ERROR (0x1<<10)
24113 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_WR_PUSH_ERROR (0x1<<11)
24115 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_WR_POP_ERROR (0x1<<12)
24117 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_RD_PUSH_ERROR (0x1<<13)
24119 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_DRA_RD_POP_ERROR (0x1<<14)
24121 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_FIN_PUSH_ERROR (0x1<<15)
24123 #define XSEM_XSEM_INT_MASK_0_REG_MAX_HANDLER_ERROR (0x1<<16)
24125 #define XSEM_XSEM_INT_MASK_0_REG_DRA_DATA_WR_ERROR (0x1<<17)
24127 #define XSEM_XSEM_INT_MASK_0_REG_RD_EMPTY_LOAD_FIFO (0x1<<18)
24129 #define XSEM_XSEM_INT_MASK_0_REG_WR_FULL_LOAD_FIFO (0x1<<19)
24131 #define XSEM_XSEM_INT_MASK_0_REG_RD_EMPTY_CAM (0x1<<20)
24133 #define XSEM_XSEM_INT_MASK_0_REG_WR_FULL_CAM (0x1<<21)
24135 #define XSEM_XSEM_INT_MASK_0_REG_CAM_LSB_INP_FIFO (0x1<<22)
24137 #define XSEM_XSEM_INT_MASK_0_REG_CAM_MSB_INP_FIFO (0x1<<23)
24139 #define XSEM_XSEM_INT_MASK_0_REG_CAM_OUT_FIFO (0x1<<24)
24141 #define XSEM_XSEM_INT_MASK_0_REG_FIN_FIFO (0x1<<25)
24143 #define XSEM_XSEM_INT_MASK_0_REG_SET0_THREAD_ERROR (0x1<<26)
24145 #define XSEM_XSEM_INT_MASK_0_REG_SET1_THREAD_ERROR (0x1<<27)
24147 #define XSEM_XSEM_INT_MASK_0_REG_THREAD_OVERRUN (0x1<<28)
24149 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_EXT_STORE_PUSH_ERROR (0x1<<29)
24151 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_EXT_STORE_POP_ERROR (0x1<<30)
24153 #define XSEM_XSEM_INT_MASK_0_REG_SYNC_RAM0_RD_PUSH_ERROR (0x1<<31)
24156 #define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
24158 #define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
24160 #define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
24162 #define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
24164 #define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
24166 #define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
24168 #define XSEM_XSEM_INT_STS_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
24170 #define XSEM_XSEM_INT_STS_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
24172 #define XSEM_XSEM_INT_STS_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
24174 #define XSEM_XSEM_INT_STS_1_REG_DBG_FIFO_ERROR (0x1<<9)
24176 #define XSEM_XSEM_INT_STS_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
24178 #define XSEM_XSEM_INT_STS_1_REG_VFC_INTERRUPT (0x1<<11)
24180 #define XSEM_XSEM_INT_STS_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
24183 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
24185 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
24187 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
24189 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
24191 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
24193 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
24195 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
24197 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
24199 #define XSEM_XSEM_INT_STS_CLR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
24201 #define XSEM_XSEM_INT_STS_CLR_1_REG_DBG_FIFO_ERROR (0x1<<9)
24203 #define XSEM_XSEM_INT_STS_CLR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
24205 #define XSEM_XSEM_INT_STS_CLR_1_REG_VFC_INTERRUPT (0x1<<11)
24207 #define XSEM_XSEM_INT_STS_CLR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
24210 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
24212 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
24214 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
24216 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
24218 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
24220 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
24222 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
24224 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
24226 #define XSEM_XSEM_INT_STS_WR_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
24228 #define XSEM_XSEM_INT_STS_WR_1_REG_DBG_FIFO_ERROR (0x1<<9)
24230 #define XSEM_XSEM_INT_STS_WR_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
24232 #define XSEM_XSEM_INT_STS_WR_1_REG_VFC_INTERRUPT (0x1<<11)
24234 #define XSEM_XSEM_INT_STS_WR_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
24237 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_RD_PUSH_ERROR (0x1<<0)
24239 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_RD_POP_ERROR (0x1<<1)
24241 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_RD_POP_ERROR (0x1<<2)
24243 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_WR_POP_ERROR (0x1<<3)
24245 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_WR_POP_ERROR (0x1<<4)
24247 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM0_WR_PUSH_ERROR (0x1<<5)
24249 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_RAM1_WR_PUSH_ERROR (0x1<<6)
24251 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_DBG_PUSH_ERROR (0x1<<7)
24253 #define XSEM_XSEM_INT_MASK_1_REG_SYNC_DBG_POP_ERROR (0x1<<8)
24255 #define XSEM_XSEM_INT_MASK_1_REG_DBG_FIFO_ERROR (0x1<<9)
24257 #define XSEM_XSEM_INT_MASK_1_REG_CAM_MSB2_INP_FIFO (0x1<<10)
24259 #define XSEM_XSEM_INT_MASK_1_REG_VFC_INTERRUPT (0x1<<11)
24261 #define XSEM_XSEM_INT_MASK_1_REG_VFC_OUT_FIFO_ERROR (0x1<<12)
24264 #define XSEM_XSEM_PRTY_STS_0_REG_PARITY (0x1<<0)
24266 #define XSEM_XSEM_PRTY_STS_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
24268 #define XSEM_XSEM_PRTY_STS_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
24270 #define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
24272 #define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
24274 #define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
24276 #define XSEM_XSEM_PRTY_STS_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
24278 #define XSEM_XSEM_PRTY_STS_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
24280 #define XSEM_XSEM_PRTY_STS_0_REG_FIC0_FIFO_PARITY (0x1<<8)
24282 #define XSEM_XSEM_PRTY_STS_0_REG_FIC1_FIFO_PARITY (0x1<<9)
24284 #define XSEM_XSEM_PRTY_STS_0_REG_PAS_FIFO_PARITY (0x1<<10)
24286 #define XSEM_XSEM_PRTY_STS_0_REG_PAS_PARITY0 (0x1<<11)
24288 #define XSEM_XSEM_PRTY_STS_0_REG_PAS_PARITY1 (0x1<<12)
24290 #define XSEM_XSEM_PRTY_STS_0_REG_INT_TABLE_PARITY (0x1<<13)
24292 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY0 (0x1<<14)
24294 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY1 (0x1<<15)
24296 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY2 (0x1<<16)
24298 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY3 (0x1<<17)
24300 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY4 (0x1<<18)
24302 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY5 (0x1<<19)
24304 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY6 (0x1<<20)
24306 #define XSEM_XSEM_PRTY_STS_0_REG_RAM0_PARITY7 (0x1<<21)
24308 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY0 (0x1<<22)
24310 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY1 (0x1<<23)
24312 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY2 (0x1<<24)
24314 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY3 (0x1<<25)
24316 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY4 (0x1<<26)
24318 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY5 (0x1<<27)
24320 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY6 (0x1<<28)
24322 #define XSEM_XSEM_PRTY_STS_0_REG_RAM1_PARITY7 (0x1<<29)
24324 #define XSEM_XSEM_PRTY_STS_0_REG_PRAM_LOW_PARITY (0x1<<30)
24326 #define XSEM_XSEM_PRTY_STS_0_REG_PRAM_HIGH_PARITY (0x1<<31)
24329 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_PARITY (0x1<<0)
24331 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
24333 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
24335 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
24337 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
24339 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
24341 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
24343 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
24345 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
24347 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
24349 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_FIFO_PARITY (0x1<<10)
24351 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_PARITY0 (0x1<<11)
24353 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_PAS_PARITY1 (0x1<<12)
24355 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_INT_TABLE_PARITY (0x1<<13)
24357 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY0 (0x1<<14)
24359 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY1 (0x1<<15)
24361 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY2 (0x1<<16)
24363 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY3 (0x1<<17)
24365 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY4 (0x1<<18)
24367 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY5 (0x1<<19)
24369 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY6 (0x1<<20)
24371 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM0_PARITY7 (0x1<<21)
24373 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY0 (0x1<<22)
24375 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY1 (0x1<<23)
24377 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY2 (0x1<<24)
24379 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY3 (0x1<<25)
24381 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY4 (0x1<<26)
24383 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY5 (0x1<<27)
24385 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY6 (0x1<<28)
24387 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_RAM1_PARITY7 (0x1<<29)
24389 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_PRAM_LOW_PARITY (0x1<<30)
24391 #define XSEM_XSEM_PRTY_STS_CLR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
24394 #define XSEM_XSEM_PRTY_STS_WR_0_REG_PARITY (0x1<<0)
24396 #define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
24398 #define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
24400 #define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
24402 #define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
24404 #define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
24406 #define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
24408 #define XSEM_XSEM_PRTY_STS_WR_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
24410 #define XSEM_XSEM_PRTY_STS_WR_0_REG_FIC0_FIFO_PARITY (0x1<<8)
24412 #define XSEM_XSEM_PRTY_STS_WR_0_REG_FIC1_FIFO_PARITY (0x1<<9)
24414 #define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_FIFO_PARITY (0x1<<10)
24416 #define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_PARITY0 (0x1<<11)
24418 #define XSEM_XSEM_PRTY_STS_WR_0_REG_PAS_PARITY1 (0x1<<12)
24420 #define XSEM_XSEM_PRTY_STS_WR_0_REG_INT_TABLE_PARITY (0x1<<13)
24422 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY0 (0x1<<14)
24424 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY1 (0x1<<15)
24426 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY2 (0x1<<16)
24428 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY3 (0x1<<17)
24430 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY4 (0x1<<18)
24432 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY5 (0x1<<19)
24434 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY6 (0x1<<20)
24436 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM0_PARITY7 (0x1<<21)
24438 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY0 (0x1<<22)
24440 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY1 (0x1<<23)
24442 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY2 (0x1<<24)
24444 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY3 (0x1<<25)
24446 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY4 (0x1<<26)
24448 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY5 (0x1<<27)
24450 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY6 (0x1<<28)
24452 #define XSEM_XSEM_PRTY_STS_WR_0_REG_RAM1_PARITY7 (0x1<<29)
24454 #define XSEM_XSEM_PRTY_STS_WR_0_REG_PRAM_LOW_PARITY (0x1<<30)
24456 #define XSEM_XSEM_PRTY_STS_WR_0_REG_PRAM_HIGH_PARITY (0x1<<31)
24459 #define XSEM_XSEM_PRTY_MASK_0_REG_PARITY (0x1<<0)
24461 #define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_DRA_WR_FIFO_PARITY (0x1<<1)
24463 #define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_DRA_RD_FIFO_PARITY (0x1<<2)
24465 #define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM0_RD_FIFO_PARITY (0x1<<3)
24467 #define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM1_RD_FIFO_PARITY (0x1<<4)
24469 #define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM0_WR_FIFO_PARITY (0x1<<5)
24471 #define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_RAM1_WR_FIFO_PARITY (0x1<<6)
24473 #define XSEM_XSEM_PRTY_MASK_0_REG_SYNC_EXT_FIFO_PARITY (0x1<<7)
24475 #define XSEM_XSEM_PRTY_MASK_0_REG_FIC0_FIFO_PARITY (0x1<<8)
24477 #define XSEM_XSEM_PRTY_MASK_0_REG_FIC1_FIFO_PARITY (0x1<<9)
24479 #define XSEM_XSEM_PRTY_MASK_0_REG_PAS_FIFO_PARITY (0x1<<10)
24481 #define XSEM_XSEM_PRTY_MASK_0_REG_PAS_PARITY0 (0x1<<11)
24483 #define XSEM_XSEM_PRTY_MASK_0_REG_PAS_PARITY1 (0x1<<12)
24485 #define XSEM_XSEM_PRTY_MASK_0_REG_INT_TABLE_PARITY (0x1<<13)
24487 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY0 (0x1<<14)
24489 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY1 (0x1<<15)
24491 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY2 (0x1<<16)
24493 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY3 (0x1<<17)
24495 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY4 (0x1<<18)
24497 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY5 (0x1<<19)
24499 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY6 (0x1<<20)
24501 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM0_PARITY7 (0x1<<21)
24503 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY0 (0x1<<22)
24505 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY1 (0x1<<23)
24507 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY2 (0x1<<24)
24509 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY3 (0x1<<25)
24511 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY4 (0x1<<26)
24513 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY5 (0x1<<27)
24515 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY6 (0x1<<28)
24517 #define XSEM_XSEM_PRTY_MASK_0_REG_RAM1_PARITY7 (0x1<<29)
24519 #define XSEM_XSEM_PRTY_MASK_0_REG_PRAM_LOW_PARITY (0x1<<30)
24521 #define XSEM_XSEM_PRTY_MASK_0_REG_PRAM_HIGH_PARITY (0x1<<31)
24524 #define XSEM_XSEM_PRTY_STS_1_REG_SYNC_DBG_PARITY (0x1<<0)
24526 #define XSEM_XSEM_PRTY_STS_1_REG_SLOW_DBG_PARITY (0x1<<1)
24528 #define XSEM_XSEM_PRTY_STS_1_REG_CAM_PARITY (0x1<<2)
24530 #define XSEM_XSEM_PRTY_STS_1_REG_STORM_RF0_PARITY (0x1<<3)
24532 #define XSEM_XSEM_PRTY_STS_1_REG_STORM_RF1_PARITY (0x1<<4)
24534 #define XSEM_XSEM_PRTY_STS_1_REG_VFC_PARITY (0x1<<5)
24537 #define XSEM_XSEM_PRTY_STS_CLR_1_REG_SYNC_DBG_PARITY (0x1<<0)
24539 #define XSEM_XSEM_PRTY_STS_CLR_1_REG_SLOW_DBG_PARITY (0x1<<1)
24541 #define XSEM_XSEM_PRTY_STS_CLR_1_REG_CAM_PARITY (0x1<<2)
24543 #define XSEM_XSEM_PRTY_STS_CLR_1_REG_STORM_RF0_PARITY (0x1<<3)
24545 #define XSEM_XSEM_PRTY_STS_CLR_1_REG_STORM_RF1_PARITY (0x1<<4)
24547 #define XSEM_XSEM_PRTY_STS_CLR_1_REG_VFC_PARITY (0x1<<5)
24550 #define XSEM_XSEM_PRTY_STS_WR_1_REG_SYNC_DBG_PARITY (0x1<<0)
24552 #define XSEM_XSEM_PRTY_STS_WR_1_REG_SLOW_DBG_PARITY (0x1<<1)
24554 #define XSEM_XSEM_PRTY_STS_WR_1_REG_CAM_PARITY (0x1<<2)
24556 #define XSEM_XSEM_PRTY_STS_WR_1_REG_STORM_RF0_PARITY (0x1<<3)
24558 #define XSEM_XSEM_PRTY_STS_WR_1_REG_STORM_RF1_PARITY (0x1<<4)
24560 #define XSEM_XSEM_PRTY_STS_WR_1_REG_VFC_PARITY (0x1<<5)
24563 #define XSEM_XSEM_PRTY_MASK_1_REG_SYNC_DBG_PARITY (0x1<<0)
24565 #define XSEM_XSEM_PRTY_MASK_1_REG_SLOW_DBG_PARITY (0x1<<1)
24567 #define XSEM_XSEM_PRTY_MASK_1_REG_CAM_PARITY (0x1<<2)
24569 #define XSEM_XSEM_PRTY_MASK_1_REG_STORM_RF0_PARITY (0x1<<3)
24571 #define XSEM_XSEM_PRTY_MASK_1_REG_STORM_RF1_PARITY (0x1<<4)
24573 #define XSEM_XSEM_PRTY_MASK_1_REG_VFC_PARITY (0x1<<5)
24585 #define XSEM_REG_DBG_IF_FULL 0x28020cUL //ACCESS:R DataWidth:0x1 Description: DBG IF is full in sem_slow_ls_dbg
24587 #define XSEM_REG_DRA_EMPTY 0x280210UL //ACCESS:R DataWidth:0x1 Description: This register is active when FIN FIO is empty and DRA RD FIFO is empty
24589 #define XSEM_REG_EXT_PAS_EMPTY 0x280214UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO empty in sem_slow
24591 #define XSEM_REG_EXT_PAS_FULL 0x280218UL //ACCESS:R DataWidth:0x1 Description: EXT_PAS FIFO Full in sem_slow
24595 #define XSEM_REG_EXT_STORE_IF_FULL 0x280220UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE IF is full in sem_slow_ls_ext
24597 #define XSEM_REG_FIC0_DISABLE 0x280224UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC0 May be updated during run_time by the microcode
24599 #define XSEM_REG_FIC0_EMPTY 0x280228UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
24601 #define XSEM_REG_FIC0_FULL 0x28022cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
24605 #define XSEM_REG_FIC1_DISABLE 0x280234UL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from FIC1 May be updated during run_time by the microcode
24607 #define XSEM_REG_FIC1_EMPTY 0x280238UL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO empty in sem_slow_fic
24609 #define XSEM_REG_FIC1_FULL 0x28023cUL //ACCESS:R DataWidth:0x1 Description: FIC0 FIFO Full in sem_slow_fic
24617 #define XSEM_REG_PAS_DISABLE 0x28024cUL //ACCESS:RW DataWidth:0x1 Description: Disables input messages from the passive buffer May be updated during run_time by the microcode
24619 #define XSEM_REG_PAS_IF_FULL 0x280250UL //ACCESS:R DataWidth:0x1 Description: Full from passive buffer asserted toward SDM
24621 #define XSEM_REG_RAM0_IF_FULL 0x280254UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM0 IF is full in sem_slow_ls_ram
24623 #define XSEM_REG_RAM1_IF_FULL 0x280258UL //ACCESS:R DataWidth:0x1 Description: EXT_RAM1 IF is full in sem_slow_ls_ram
24625 #define XSEM_REG_SET0_THREAD_EMPTY 0x28025cUL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is empty in sem_slow_dra_wr
24627 #define XSEM_REG_SET0_THREAD_FULL 0x280260UL //ACCESS:R DataWidth:0x1 Description: SET0_THREAD fifo is full in sem_slow_dra_wr
24629 #define XSEM_REG_SET1_THREAD_EMPTY 0x280264UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is empty in sem_slow_dra_wr
24631 #define XSEM_REG_SET1_THREAD_FULL 0x280268UL //ACCESS:R DataWidth:0x1 Description: SET1_THREAD fifo is full in sem_slow_dra_wr
24635 #define XSEM_REG_SLOW_DBG_ALM_EMPTY 0x280270UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg (31 entry inside fifo)
24637 #define XSEM_REG_SLOW_DBG_ALM_FULL 0x280274UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is almost empty in sem_slow_ls_dbg according to configuration
24639 #define XSEM_REG_SLOW_DBG_EMPTY 0x280278UL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is empty in sem_slow_ls_dbg
24641 #define XSEM_REG_SLOW_DBG_FULL 0x28027cUL //ACCESS:R DataWidth:0x1 Description: DBG FIFO is full in sem_slow_ls_dbg
24643 #define XSEM_REG_SLOW_DRA_FIN_EMPTY 0x280280UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is empty in sem_slow_dra_sync
24645 #define XSEM_REG_SLOW_DRA_FIN_FULL 0x280284UL //ACCESS:R DataWidth:0x1 Description: FIN fifo is full in sem_slow_dra_sync (never may be active)
24647 #define XSEM_REG_SLOW_DRA_INT_EMPTY 0x280288UL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is empty in sem_slow_dra_sync
24649 #define XSEM_REG_SLOW_DRA_INT_FULL 0x28028cUL //ACCESS:R DataWidth:0x1 Description: Interrupt fifo is full in sem_slow_dra_int
24651 #define XSEM_REG_SLOW_DRA_RD_EMPTY 0x280290UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is empty in sem_slow_dra_sync
24653 #define XSEM_REG_SLOW_DRA_RD_FULL 0x280294UL //ACCESS:R DataWidth:0x1 Description: DRA_RD pop fifo is full in sem_slow_dra_sync
24655 #define XSEM_REG_SLOW_DRA_WR_EMPTY 0x280298UL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is empty in sem_slow_dra_sync
24657 #define XSEM_REG_SLOW_DRA_WR_FULL 0x28029cUL //ACCESS:R DataWidth:0x1 Description: DRA_WR push fifo is full in sem_slow_dra_sync
24659 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is empty in sem_slow_ls_ext
24661 #define XSEM_REG_SLOW_EXT_STORE_FULL 0x2802a4UL //ACCESS:R DataWidth:0x1 Description: EXT_STORE FIFO is full in sem_slow_ls_ext
24663 #define XSEM_REG_SLOW_RAM0_RD_EMPTY 0x2802a8UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is empty in sem_slow_ls_ext
24665 #define XSEM_REG_SLOW_RAM0_RD_FULL 0x2802acUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM0 FIFO is full in sem_slow_ls_ext
24667 #define XSEM_REG_SLOW_RAM0_WR_ALM_FULL 0x2802b0UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
24669 #define XSEM_REG_SLOW_RAM0_WR_EMPTY 0x2802b4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is empty in sem_slow_ls_ext
24671 #define XSEM_REG_SLOW_RAM0_WR_FULL 0x2802b8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM0 FIFO is full in sem_slow_ls_ext
24673 #define XSEM_REG_SLOW_RAM1_RD_EMPTY 0x2802bcUL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is empty in sem_slow_ls_ext
24675 #define XSEM_REG_SLOW_RAM1_RD_FULL 0x2802c0UL //ACCESS:R DataWidth:0x1 Description: EXT_RD_RAM1 FIFO is full in sem_slow_ls_ext
24677 #define XSEM_REG_SLOW_RAM1_WR_ALM_FULL 0x2802c4UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is almost full in sem_slow_ls_ext
24679 #define XSEM_REG_SLOW_RAM1_WR_EMPTY 0x2802c8UL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is empty in sem_slow_ls_ext
24681 #define XSEM_REG_SLOW_RAM1_WR_FULL 0x2802ccUL //ACCESS:R DataWidth:0x1 Description: EXT_WR_RAM1 FIFO is full in sem_slow_ls_ext
24683 #define XSEM_REG_SYNC_DBG_EMPTY 0x2802d0UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is empty in sem_slow_ls_sync
24685 #define XSEM_REG_SYNC_DBG_FULL 0x2802d4UL //ACCESS:R DataWidth:0x1 Description: DBG FAST SYNC FIFO is full in sem_slow_ls_sync