Lines Matching refs:base
36 #define COMMON_SB_SIZE (IRO[0].base)
37 #define COMMON_SB_DATA_SIZE (IRO[1].base)
38 #define COMMON_SP_SB_SIZE (IRO[2].base)
39 #define COMMON_SP_SB_DATA_SIZE (IRO[3].base)
40 #define COMMON_DYNAMIC_HC_CONFIG_SIZE (IRO[4].base)
41 #define COMMON_ASM_ASSERT_MSG_SIZE (IRO[5].base)
42 #define COMMON_ASM_ASSERT_INDEX_SIZE (IRO[6].base)
43 #define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)
44 #define COMMON_RAM1_TEST_EVENT_ID (IRO[8].base)
45 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVENT_ID (IRO[9].base)
46 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_OFFSET (IRO[10].base)
47 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_OFFSET (IRO[11].base)
48 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_OFFSET (IRO[12].base)
49 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_RESULT_OFFSET (IRO[13].base)
50 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_RESULT_OFFSET (IRO[14].base)
51 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_RESULT_OFFSET (IRO[15].base)
52 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_1_MASK (IRO[16].base)
53 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_2_MASK (IRO[17].base)
54 #define COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_3_MASK (IRO[18].base)
55 #define COMMON_KUKU_TEST_AGG_INT (IRO[19].base)
56 #define COMMON_KUKU_TEST_EVENTID (IRO[20].base)
57 #define COMMON_KUKU_PCI_READ_OPCODE (IRO[21].base)
58 #define COMMON_KUKU_LOAD_CONTEXT_OPCODE (IRO[22].base)
59 #define COMMON_KUKU_LOAD_CONTEXT_INCVAL (IRO[23].base)
60 #define COMMON_KUKU_LOAD_CONTEXT_REGION (IRO[24].base)
61 #define COMMON_KUKU_LOAD_CONTEXT_CID (IRO[25].base)
62 #define COMMON_KUKU_LOAD_CONTEXT_RUN_PBF_ECHO_TEST (IRO[26].base)
63 #define COMMON_KUKU_QM_PAUSE_OPCODE (IRO[27].base)
64 #define COMMON_KUKU_TEST_UNUSED_FOCS_SUCCESS_OPCODE_VALUE (IRO[28].base)
65 #define COMMON_KUKU_TEST_UNUSED_FOCS_OPCODE_VALUE (IRO[29].base)
67 #define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) (IRO[30].base + ((funcId) * IR…
70 #define XSTORM_SPQ_PROD_OFFSET(funcId) (IRO[31].base + ((funcId) * IR…
73 #define XSTORM_SPQ_DATA_OFFSET(funcId) (IRO[32].base + ((funcId) * IR…
75 #define XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId) (IRO[33].base + ((portId) * IR…
78 #define XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId) (IRO[34].base + ((vfId) * IRO[…
81 #define XSTORM_VF_SPQ_PROD_OFFSET(vfId) (IRO[35].base + ((vfId) * IRO[…
84 #define XSTORM_VF_SPQ_DATA_OFFSET(vfId) (IRO[36].base + ((vfId) * IRO[…
86 #define XSTORM_JUMBO_SUPPORT_OFFSET(pfId) (IRO[37].base + (((pfId)>>1) *…
88 #define XSTORM_COMMON_IP_ID_MASK_OFFSET (IRO[38].base)
91 #define XSTORM_COMMON_RTC_PARAMS_OFFSET (IRO[39].base)
94 #define XSTORM_COMMON_RTC_RESOLUTION_OFFSET (IRO[40].base)
97 #define XSTORM_FW_VERSION_OFFSET (IRO[41].base)
100 #define XSTORM_LICENSE_VALUES_OFFSET(pfId) (IRO[42].base + ((pfId) * IRO[…
103 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) (IRO[43].base + ((portId) * IR…
106 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) (IRO[44].base + ((pfId) * IRO[…
109 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) (IRO[45].base + ((pfId) * IRO[…
112 #define XSTORM_PER_QUEUE_STATS_OFFSET(xStatQueueId) (IRO[46].base + ((xStatQueueId…
115 #define XSTORM_FUNC_EN_OFFSET(funcId) (IRO[47].base + ((funcId) * IR…
118 #define XSTORM_VF_TO_PF_OFFSET(funcId) (IRO[48].base + ((funcId) * IR…
121 #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) (IRO[49].base + ((funcId) * IR…
124 #define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[50].base + ((assertListEn…
127 #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
129 #define XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET (IRO[52].base)
131 #define PCI_READ_KUKUE_CODE_OPPCOE (IRO[53].base)
132 #define LOAD_CONTEXT_KUKUE_CODE_OPPCOE (IRO[54].base)
133 #define QM_PAUSE_KUKUE_CODE_OPPCOE (IRO[55].base)
134 #define PAUSE_TEST_XOFF_PORT0_KUKUE_CODE_OPPCOE (IRO[56].base)
135 #define PAUSE_TEST_XON_PORT0_KUKUE_CODE_OPPCOE (IRO[57].base)
136 #define PAUSE_TEST_XOFF_PORT1_KUKUE_CODE_OPPCOE (IRO[58].base)
137 #define PAUSE_TEST_XON_PORT1_KUKUE_CODE_OPPCOE (IRO[59].base)
138 #define TEST_UNUSED_FOCS_KUKUE_CODE_OPPCOE (IRO[60].base)
139 #define PBF_ECHO_KUKUE_CODE_OPPCOE (IRO[61].base)
140 #define TIME_SYNC_PORT0_KUKUE_CODE_OPPCOE (IRO[62].base)
141 #define TIME_SYNC_PORT1_KUKUE_CODE_OPPCOE (IRO[63].base)
142 #define IGU_TEST_KUKUE_CODE_OPPCOE (IRO[64].base)
143 #define XSTORM_AGG_INT_INITIAL_CLEANUP_INDEX (IRO[65].base)
144 #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
145 #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
147 #define XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET (IRO[68].base)
149 #define XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET (IRO[69].base)
152 #define XSTORM_QUEUE_ZONE_OFFSET(queueId) (IRO[70].base + ((queueId) * I…
155 #define XSTORM_VF_ZONE_OFFSET(vfId) (IRO[71].base + ((vfId) * IRO[…
157 #define XSTORM_FIVE_TUPLE_SRC_EN_OFFSET (IRO[72].base)
159 #define XSTORM_E2_INTEG_RAM_OFFSET (IRO[73].base)
161 #define XSTORM_QM_OPPORTUNISTIC_RAM_OFFSET (IRO[74].base)
163 #define XSTORM_SIDE_INFO_INPUT_LSB_OFFSET (IRO[75].base)
165 #define XSTORM_E2_INTEG_VLAN_ID_OFFSET (IRO[76].base)
167 #define XSTORM_E2_INTEG_VLAN_ID_EN_OFFSET (IRO[77].base)
169 #define XSTORM_VFC_TEST_LINE_OFFSET (IRO[78].base)
171 #define XSTORM_VFC_TEST_RESULT_OFFSET (IRO[79].base)
173 #define XSTORM_VFC_OP_GEN_VALUE (IRO[80].base)
174 #define XSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES (IRO[81].base)
175 #define XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX (IRO[82].base)
176 #define XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX (IRO[83].base)
177 #define XSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX (IRO[84].base)
178 #define XSTORM_DPM_BUFFER_OFFSET (IRO[85].base)
180 #define XSTORM_KUKU_TEST_OPCODE_OFFSET (IRO[86].base)
182 #define XSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET (IRO[87].base)
184 #define XSTORM_KUKU_OP_GEN_VALUE (IRO[88].base)
185 #define XSTORM_QM_PAUSE_TEST_QUEUE_MASK_OFFSET (IRO[89].base)
187 #define XSTORM_QM_PAUSE_TEST_GROUP_OFFSET (IRO[90].base)
189 #define XSTORM_QM_PAUSE_TEST_PORT_OFFSET (IRO[91].base)
191 #define XSTORM_KUKU_PBF_ECHO_OPCODE (IRO[92].base)
192 #define XSTORM_KUKU_PBF_ECHO_INCVAL (IRO[93].base)
193 #define XSTORM_KUKU_PBF_ECHO_REGION (IRO[94].base)
194 #define XSTORM_KUKU_PBF_ECHO_RUN_PBF_ECHO_TEST (IRO[95].base)
195 #define XSTORM_KUKU_PBF_ECHO_CID (IRO[96].base)
196 #define XSTORM_KUKU_PBF_ECHO_SUCCESS_VALUE (IRO[97].base)
197 #define XSTORM_KUKU_TIME_SYNC_FLG_OFFSET(funcId) (IRO[98].base + ((funcId) * IR…
199 #define TSTORM_INDIRECTION_TABLE_ENTRY_SIZE (IRO[99].base)
201 #define TSTORM_COMMON_RTC_PARAMS_OFFSET (IRO[100].base)
204 #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[101].base + ((assertListE…
207 #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
210 #define TSTORM_MEASURE_PCI_LATENCY_CTRL_OFFSET (IRO[103].base)
213 #define TSTORM_MEASURE_PCI_LATENCY_DATA_OFFSET (IRO[104].base)
215 #define TSTORM_AGG_MEASURE_PCI_LATENCY_INDEX (IRO[105].base)
216 #define TSTORM_AGG_MEASURE_PCI_LATENCY_COMP_TYPE (IRO[106].base)
218 #define TSTORM_FUNC_EN_OFFSET(funcId) (IRO[107].base + ((funcId) * I…
221 #define TSTORM_VF_TO_PF_OFFSET(funcId) (IRO[108].base + ((funcId) * I…
224 #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) (IRO[109].base + ((funcId) * I…
227 #define TSTORM_PER_QUEUE_STATS_OFFSET(tStatQueueId) (IRO[110].base + ((tStatQueueI…
230 #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET (IRO[111].base)
233 #define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET (IRO[112].base)
236 #define TSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET (IRO[113].base)
238 #define TSTORM_VFC_TEST_RSS_KEY_OFFSET(portId) (IRO[114].base + ((portId) * I…
241 #define TSTORM_QUEUE_ZONE_OFFSET(queueId) (IRO[115].base + ((queueId) * …
244 #define TSTORM_VF_ZONE_OFFSET(vfId) (IRO[116].base + ((vfId) * IRO…
246 #define TSTORM_E2_INTEG_RAM_OFFSET (IRO[117].base)
248 #define TSTORM_LSB_SIDE_BAND_INFO_OFFSET (IRO[118].base)
250 #define TSTORM_MSB_SIDE_BAND_INFO_OFFSET (IRO[119].base)
252 #define TSTORM_VFC_TEST_LINE_OFFSET (IRO[120].base)
254 #define TSTORM_VFC_TEST_RESULT_OFFSET (IRO[121].base)
256 #define TSTORM_VFC_OP_GEN_VALUE (IRO[122].base)
257 #define TSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES (IRO[123].base)
258 #define TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX (IRO[124].base)
259 #define TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX (IRO[125].base)
260 #define TSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX (IRO[126].base)
261 #define TSTORM_KUKU_TEST_OPCODE_OFFSET (IRO[127].base)
263 #define TSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET (IRO[128].base)
265 #define TSTORM_KUKU_OP_GEN_VALUE (IRO[129].base)
266 #define TSTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET (IRO[130].base)
268 #define TSTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET (IRO[131].base)
270 #define TSTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET (IRO[132].base)
272 #define TSTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET (IRO[133].base)
274 #define TSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET (IRO[134].base)
276 #define TSTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET (IRO[135].base)
279 #define CSTORM_STATUS_BLOCK_OFFSET(sbId) (IRO[136].base + ((sbId) * IRO…
282 #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) (IRO[137].base + ((sbId) * IRO…
285 #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) (IRO[138].base + ((sbId) * IRO…
288 #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId,hcIndex) (IRO[139].base + ((sbId) * IRO…
291 #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId,hcIndex) (IRO[140].base + ((sbId) * IRO…
294 #define CSTORM_SYNC_BLOCK_OFFSET(sbId) (IRO[141].base + ((sbId) * IRO…
297 #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex,sbId) (IRO[142].base + (((hcIndex)>>…
300 #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex,sbId) (IRO[143].base + ((hcIndex) * …
303 #define CSTORM_HC_SYNC_LINE_DHC_OFFSET(sbSyncLines,sbId) (IRO[144].base + ((sbSyncLines…
306 #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) (IRO[145].base + ((pfId) * IRO…
309 #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) (IRO[146].base + ((pfId) * IRO…
312 #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) (IRO[147].base + ((pfId) * IRO…
315 #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) (IRO[148].base + ((pfId) * IRO…
318 #define CSTORM_SP_HC_SYNC_LINE_INDEX_OFFSET(hcSpIndex,pfId) (IRO[149].base + ((hcSpIndex) …
321 #define CSTORM_DYNAMIC_HC_CONFIG_OFFSET(pfId) (IRO[150].base + ((pfId) * IRO…
324 #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[151].base + ((assertListE…
327 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
330 #define CSTORM_FUNC_EN_OFFSET(funcId) (IRO[153].base + ((funcId) * I…
333 #define CSTORM_VF_TO_PF_OFFSET(funcId) (IRO[154].base + ((funcId) * I…
336 #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) (IRO[155].base + ((funcId) * I…
339 #define CSTORM_BYTE_COUNTER_OFFSET(sbId,dhcIndex) (IRO[156].base + ((sbId) * IRO…
342 #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) (IRO[157].base + (((pfId)>>1) …
345 #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) (IRO[158].base + (((pfId)>>1) …
348 #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) (IRO[159].base + ((vfId) * IRO…
350 #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) (IRO[160].base + ((vfId) * IRO…
353 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
356 #define CSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET (IRO[162].base)
359 #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) (IRO[163].base + ((funcId) * I…
362 #define CSTORM_QUEUE_ZONE_OFFSET(queueId) (IRO[164].base + ((queueId) * …
365 #define CSTORM_VF_ZONE_OFFSET(vfId) (IRO[165].base + ((vfId) * IRO…
367 #define CSTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES (IRO[166].base)
368 #define CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX (IRO[167].base)
369 #define CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX (IRO[168].base)
370 #define CSTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX (IRO[169].base)
371 #define CSTORM_KUKU_TEST_OPCODE_OFFSET (IRO[170].base)
373 #define CSTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET (IRO[171].base)
375 #define CSTORM_KUKU_OP_GEN_VALUE (IRO[172].base)
376 #define CSTORM_IGU_TEST_PF_ID_OFFSET (IRO[173].base)
378 #define CSTORM_IGU_TEST_VF_ID_OFFSET (IRO[174].base)
380 #define CSTORM_IGU_TEST_VF_VALID_OFFSET (IRO[175].base)
382 #define CSTORM_IGU_TEST_ADDRESS_OFFSET (IRO[176].base)
384 #define CSTORM_IGU_TEST_IGU_COMMAND_OFFSET (IRO[177].base)
386 #define USTORM_INDIRECTION_TABLE_OFFSET(portId) (IRO[178].base + ((portId) * I…
388 #define USTORM_INDIRECTION_TABLE_ENTRY_SIZE (IRO[179].base)
390 #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) (IRO[180].base + ((assertListE…
393 #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
396 #define USTORM_FUNC_EN_OFFSET(funcId) (IRO[182].base + ((funcId) * I…
399 #define USTORM_VF_TO_PF_OFFSET(funcId) (IRO[183].base + ((funcId) * I…
402 #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) (IRO[184].base + ((funcId) * I…
405 #define USTORM_PER_QUEUE_STATS_OFFSET(uStatQueueId) (IRO[185].base + ((uStatQueueI…
408 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) (IRO[186].base + ((pfId) * IRO…
411 #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) (IRO[187].base + ((portId) * I…
414 #define USTORM_TOE_PAUSE_ENABLED_OFFSET(portId) (IRO[188].base + ((portId) * I…
417 #define USTORM_MAX_PAUSE_TIME_USEC_OFFSET(portId) (IRO[189].base + ((portId) * I…
420 #define USTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET (IRO[190].base)
423 #define USTORM_QUEUE_ZONE_OFFSET(queueId) (IRO[191].base + ((queueId) * …
426 #define USTORM_VF_ZONE_OFFSET(vfId) (IRO[192].base + ((vfId) * IRO…
428 #define USTORM_INBOUND_INTERRUPT_TEST_VF_INFO_SIZE_IN_BYTES (IRO[193].base)
429 #define USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_1_INDEX (IRO[194].base)
430 #define USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_2_INDEX (IRO[195].base)
431 #define USTORM_INBOUND_INTERRUPT_TEST_AGG_INT_3_INDEX (IRO[196].base)
432 #define USTORM_KUKU_TEST_OPCODE_OFFSET (IRO[197].base)
434 #define USTORM_KUKU_LOAD_CONTEXT_TEST_OFFSET (IRO[198].base)
436 #define USTORM_KUKU_OP_GEN_VALUE (IRO[199].base)
437 #define USTORM_PCI_READ_TEST_ADDRESS_LO_OFFSET (IRO[200].base)
439 #define USTORM_PCI_READ_TEST_ADDRESS_HI_OFFSET (IRO[201].base)
441 #define USTORM_PCI_READ_TEST_RAM_ADDRESS_OFFSET (IRO[202].base)
443 #define USTORM_PCI_READ_TEST_PCI_ENTITY_OFFSET (IRO[203].base)
445 #define USTORM_KUKU_NIG_PAUSE_TEST_MASK_OFFSET (IRO[204].base)
448 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) (IRO[205].base + ((pfId) * IRO…
451 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) (IRO[206].base + ((pfId) * IRO…
454 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) (IRO[207].base + ((pfId) * IRO…
457 #define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[208].base)
460 #define TSTORM_ACCEPT_CLASSIFY_FAIL_E2_ENABLE_OFFSET(portId) (IRO[209].base + ((portId) * I…
463 #define TSTORM_ACCEPT_CLASSIFY_FAIL_E2_VNIC_OFFSET(portId) (IRO[210].base + ((portId) * I…
465 #define USTORM_CQE_PAGE_NEXT_OFFSET(portId,clientId) (IRO[211].base + ((portId) * I…
468 #define USTORM_AGG_DATA_OFFSET (IRO[212].base)
471 #define USTORM_TPA_BTR_OFFSET (IRO[213].base)
474 #define USTORM_ETH_DYNAMIC_HC_PARAM_OFFSET (IRO[214].base)
477 #define USTORM_RX_PRODS_E1X_OFFSET(portId,clientId) (IRO[215].base + ((portId) * I…
480 #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) (IRO[216].base + ((qzoneId) * …
482 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) (IRO[217].base + ((portId) * I…
484 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) (IRO[218].base + ((portId) * I…
486 #define XSTORM_TCP_IPID_OFFSET(pfId) (IRO[219].base + (((pfId)>>1) …
488 #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) (IRO[220].base + (((pfId)>>1) …
490 #define XSTORM_TCP_TX_SWITCHING_EN_OFFSET(portId) (IRO[221].base + ((portId) * I…
492 #define TSTORM_TCP_DUPLICATE_ACK_THRESHOLD_OFFSET(pfId) (IRO[222].base + ((pfId) * IRO…
494 #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) (IRO[223].base + ((pfId) * IRO…
496 #define TSTORM_TCP_GLOBAL_PARAMS_OFFSET (IRO[224].base)
498 #define TSTORM_TCP_ISLES_ARRAY_DESCRIPTOR_OFFSET (IRO[225].base)
500 #define TSTORM_TCP_ISLES_ARRAY_OFFSET (IRO[226].base)
502 #define XSTORM_TOE_LLC_SNAP_ENABLED_OFFSET(pfId) (IRO[227].base + (((pfId)>>1) …
504 #define XSTORM_OUT_OCTETS_OFFSET (IRO[228].base)
506 #define TSTORM_TOE_MAX_SEG_RETRANSMIT_OFFSET(pfId) (IRO[229].base + ((pfId) * IRO…
508 #define TSTORM_TOE_DOUBT_REACHABILITY_OFFSET(pfId) (IRO[230].base + ((pfId) * IRO…
510 #define TSTORM_TOE_MAX_DOMINANCE_VALUE_OFFSET (IRO[231].base)
512 #define TSTORM_TOE_DOMINANCE_THRESHOLD_OFFSET (IRO[232].base)
514 #define CSTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId) (IRO[233].base + ((rssId) * IR…
516 #define CSTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId) (IRO[234].base + ((rssId) * IR…
518 #define CSTORM_TOE_CQ_PROD_OFFSET(rssId,portId) (IRO[235].base + ((rssId) * IR…
520 #define CSTORM_TOE_CQ_CONS_OFFSET(rssId,portId) (IRO[236].base + ((rssId) * IR…
522 #define CSTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId) (IRO[237].base + ((rssId) * IR…
524 #define CSTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId) (IRO[238].base + ((rssId) * IR…
526 #define CSTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId) (IRO[239].base + ((rssId) * IR…
528 #define CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId) (IRO[240].base + ((rssId) * IR…
530 #define CSTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId) (IRO[241].base + ((rssId) * IR…
532 #define CSTORM_TOE_DYNAMIC_HC_PROD_OFFSET(rssId,portId) (IRO[242].base + ((rssId) * IR…
534 #define CSTORM_TOE_DYNAMIC_HC_CONS_OFFSET(rssId,portId) (IRO[243].base + ((rssId) * IR…
536 #define USTORM_GRQ_CACHE_BD_LO_OFFSET(rssId,portId,grqBdId) (IRO[244].base + ((rssId) * IR…
538 #define USTORM_GRQ_CACHE_BD_HI_OFFSET(rssId,portId,grqBdId) (IRO[245].base + ((rssId) * IR…
540 #define USTORM_TOE_GRQ_CACHE_NUM_BDS (IRO[246].base)
541 #define USTORM_TOE_GRQ_LOCAL_PROD_OFFSET(rssId,portId) (IRO[247].base + ((rssId) * IR…
543 #define USTORM_TOE_GRQ_LOCAL_CONS_OFFSET(rssId,portId) (IRO[248].base + ((rssId) * IR…
545 #define USTORM_TOE_GRQ_CONS_OFFSET(rssId,portId) (IRO[249].base + ((rssId) * IR…
547 #define USTORM_TOE_GRQ_PROD_OFFSET(rssId,portId) (IRO[250].base + ((rssId) * IR…
549 #define USTORM_TOE_GRQ_CONS_PTR_LO_OFFSET(rssId,portId) (IRO[251].base + ((rssId) * IR…
551 #define USTORM_TOE_GRQ_CONS_PTR_HI_OFFSET(rssId,portId) (IRO[252].base + ((rssId) * IR…
553 #define USTORM_TOE_GRQ_BUF_SIZE_OFFSET(rssId,portId) (IRO[253].base + ((rssId) * IR…
555 #define USTORM_TOE_CQ_NXT_PAGE_ADDR_VALID_OFFSET(rssId,portId) (IRO[254].base + ((rssId) * IR…
557 #define USTORM_TOE_CQ_CONS_OFFSET(rssId,portId) (IRO[255].base + ((rssId) * IR…
559 #define USTORM_TOE_CQ_PROD_OFFSET(rssId,portId) (IRO[256].base + ((rssId) * IR…
561 #define USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_LO_OFFSET(rssId,portId) (IRO[257].base + ((rssId) * IR…
563 #define USTORM_TOE_CQ_NEXT_PAGE_BASE_ADDR_HI_OFFSET(rssId,portId) (IRO[258].base + ((rssId) * IR…
565 #define USTORM_TOE_CQ_CONS_PTR_LO_OFFSET(rssId,portId) (IRO[259].base + ((rssId) * IR…
567 #define USTORM_TOE_CQ_CONS_PTR_HI_OFFSET(rssId,portId) (IRO[260].base + ((rssId) * IR…
569 #define USTORM_TOE_STATUS_BLOCK_ID_OFFSET(rssId,portId) (IRO[261].base + ((rssId) * IR…
571 #define USTORM_TOE_STATUS_BLOCK_INDEX_OFFSET(rssId,portId) (IRO[262].base + ((rssId) * IR…
573 #define USTORM_TOE_TCP_PUSH_TIMER_TICKS_OFFSET(pfId) (IRO[263].base + ((pfId) * IRO…
575 #define USTORM_TOE_GRQ_XOFF_COUNTER_OFFSET(pfId) (IRO[264].base + ((pfId) * IRO…
577 #define USTORM_TOE_RCQ_XOFF_COUNTER_OFFSET(pfId) (IRO[265].base + ((pfId) * IRO…
579 #define USTORM_TOE_CQ_THR_LOW_OFFSET (IRO[266].base)
581 #define USTORM_TOE_GRQ_THR_LOW_OFFSET (IRO[267].base)
583 #define USTORM_TOE_CQ_THR_HIGH_OFFSET (IRO[268].base)
585 #define USTORM_TOE_GRQ_THR_HIGH_OFFSET (IRO[269].base)
587 #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) (IRO[270].base + ((pfId) * IRO…
589 #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) (IRO[271].base + ((pfId) * IRO…
591 #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) (IRO[272].base + ((pfId) * IRO…
593 #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) (IRO[273].base + ((pfId) * IRO…
595 #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) (IRO[274].base + ((pfId) * IRO…
597 #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) (IRO[275].base + ((pfId) * IRO…
599 #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) (IRO[276].base + ((pfId) * IRO…
601 #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) (IRO[277].base + ((pfId) * IRO…
603 #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) (IRO[278].base + ((pfId) * IRO…
605 #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) (IRO[279].base + ((pfId) * IRO…
607 #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) (IRO[280].base + ((pfId) * IRO…
609 #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) (IRO[281].base + ((pfId) * IRO…
611 #define TSTORM_ISCSI_L2_ISCSI_OOO_RX_BDS_THRSHLD_OFFSET(pfId) (IRO[282].base + ((pfId) * IRO…
613 #define TSTORM_ISCSI_L2_ISCSI_OOO_CONS_OFFSET(pfId) (IRO[283].base + ((pfId) * IRO…
615 #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) (IRO[284].base + ((pfId) * IRO…
617 #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) (IRO[285].base + ((pfId) * IRO…
619 #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) (IRO[286].base + ((pfId) * IRO…
621 #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) (IRO[287].base + ((pfId) * IRO…
623 #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) (IRO[288].base + ((pfId) * IRO…
625 #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) (IRO[289].base + ((pfId) * IRO…
627 #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) (IRO[290].base + ((pfId) * IRO…
629 #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) (IRO[291].base + ((pfId) * IRO…
631 #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) (IRO[292].base + ((pfId) * IRO…
633 #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) (IRO[293].base + ((pfId) * IRO…
635 #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) (IRO[294].base + ((pfId) * IRO…
637 #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) (IRO[295].base + ((pfId) * IRO…
639 #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) (IRO[296].base + ((pfId) * IRO…
641 #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) (IRO[297].base + ((pfId) * IRO…
643 #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) (IRO[298].base + ((pfId) * IRO…
645 #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) (IRO[299].base + ((pfId) * IRO…
647 #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) (IRO[300].base + ((pfId) * IRO…
649 #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) (IRO[301].base + ((pfId) * IRO…
651 #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) (IRO[302].base + ((pfId) * IRO…
653 #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) (IRO[303].base + ((pfId) * IRO…
655 #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) (IRO[304].base + ((pfId) * IRO…
657 #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) (IRO[305].base + ((pfId) * IRO…
659 #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) (IRO[306].base + ((pfId) * IRO…
661 #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) (IRO[307].base + ((pfId) * IRO…
663 #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) (IRO[308].base + ((pfId) * IRO…
665 #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) (IRO[309].base + ((pfId) * IRO…
667 #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) (IRO[310].base + ((pfId) * IRO…
669 #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) (IRO[311].base + ((pfId) * IRO…
671 #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) (IRO[312].base + ((pfId) * IRO…
673 #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) (IRO[313].base + ((pfId) * IRO…
675 #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) (IRO[314].base + ((pfId) * IRO…
677 #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId,iscsiEqId) (IRO[315].base + ((pfId) * IRO…
679 #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId,iscsiEqId) (IRO[316].base + ((pfId) * IRO…
681 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId,iscsiEqId) (IRO[317].base + ((pfId) * IRO…
683 #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId,iscsiEqId) (IRO[318].base + ((pfId) * IRO…
685 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId,iscsiEqId) (IRO[319].base + ((pfId) * IRO…
687 #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId,iscsiEqId) (IRO[320].base + ((pfId) * IRO…
689 #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId,iscsiEqId) (IRO[321].base + ((pfId) * IRO…
691 #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) (IRO[322].base + ((pfId) * IRO…
693 #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) (IRO[323].base + ((pfId) * IRO…
695 #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) (IRO[324].base + ((pfId) * IRO…
697 #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) (IRO[325].base + ((pfId) * IRO…
699 #define USTORM_FCOE_TIMER_PARAM_OFFSET (IRO[326].base)
701 #define USTORM_TIMER_ARRAY_OFFSET (IRO[327].base)
703 #define USTORM_STAT_FC_CRC_CNT_OFFSET (IRO[328].base)
705 #define USTORM_STAT_EOFA_DEL_CNT_OFFSET (IRO[329].base)
707 #define USTORM_STAT_MISS_FRAME_CNT_OFFSET (IRO[330].base)
709 #define USTORM_STAT_SEQ_TIMEOUT_CNT_OFFSET (IRO[331].base)
711 #define USTORM_STAT_DROP_SEQ_CNT_OFFSET (IRO[332].base)
713 #define USTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET (IRO[333].base)
715 #define USTORM_STAT_FCP_RX_PKT_CNT_OFFSET (IRO[334].base)
717 #define USTORM_STAT_OFFSET (IRO[335].base)
719 #define USTORM_DEBUG_DROP_PKT_CNT_OFFSET (IRO[336].base)
721 #define USTORM_DEBUG_OFFSET (IRO[337].base)
723 #define USTORM_CACHED_TCE_MNG_INFO_DWORD_ONE_OFFSET(cached_tbl_size) (IRO[338].base + ((cached_tbl_…
725 #define USTORM_CACHED_TCE_MNG_INFO_DWORD_TWO_OFFSET(cached_tbl_size) (IRO[339].base + ((cached_tbl_…
727 #define USTORM_CACHED_TCE_ENTRY_TCE_OFFSET (IRO[340].base)
729 #define USTORM_CACHED_TCE_ENTRY_MNG_INFO_OFFSET (IRO[341].base)
731 #define USTORM_FCOE_CACHED_TCE_TBL_BIT_MAP_OFFSET (IRO[342].base)
733 #define USTORM_DEBUG_CACHED_TCE_WAIT_4_BD_READ_OFFSET (IRO[343].base)
735 #define USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_DATA_OFFSET (IRO[344].base)
737 #define USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_NON_DATA_OFFSET (IRO[345].base)
739 #define USTORM_DEBUG_CACHED_TCE_WAKE_ANOTHER_THREAD_ERR_OFFSET (IRO[346].base)
741 #define USTORM_DEBUG_CACHED_TCE_GLOBAL_TIMER_TASK_IN_USE_OFFSET (IRO[347].base)
743 #define USTORM_DEBUG_CACHED_TCE_DEL_CACHED_TASK_OFFSET (IRO[348].base)
745 #define USTORM_DEBUG_CACHED_TCE_SILENT_DROP_CACHED_TASK_OFFSET (IRO[349].base)
747 #define USTORM_DEBUG_CACHED_TCE_OFFSET (IRO[350].base)
749 #define USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_DROP_OFFSET (IRO[351].base)
751 #define USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_CRC_ERROR_OFFSET (IRO[352].base)
753 #define USTORM_FCOE_DEBUG_CACHED_TCE_SEQ_CNT_ON_ERROR_OFFSET (IRO[353].base)
755 #define USTORM_FCOE_DEBUG_CACHED_TCE_PREVIOUS_THREAD_OFFSET (IRO[354].base)
757 #define USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DATA_IN_OFFSET (IRO[355].base)
759 #define USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_READ_TCE_OFFSET (IRO[356].base)
761 #define USTORM_FCOE_DEBUG_CACHED_TCE_CRC_ERR_DETECT_DROP_ERR_OFFSET (IRO[357].base)
763 #define USTORM_FCOE_DEBUG_PARAMS_ERRORS_NUMBER_OFFSET (IRO[358].base)
765 #define USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_NUMBER_OFFSET (IRO[359].base)
767 #define USTORM_FCOE_DEBUG_PARAMS_SILENT_DROP_BITMAP_OFFSET (IRO[360].base)
769 #define USTORM_FCOE_DEBUG_PARAMS_ENABLE_CONN_RACE_OFFSET (IRO[361].base)
771 #define USTORM_FCOE_DEBUG_PARAMS_TASK_IN_USE_OFFSET (IRO[362].base)
773 #define USTORM_FCOE_DEBUG_PARAMS_CRC_ERROR_TASK_IN_USE_OFFSET (IRO[363].base)
775 #define XSTORM_FCOE_TIMER_PARAM_OFFSET (IRO[364].base)
777 #define XSTORM_TIMER_ARRAY_OFFSET (IRO[365].base)
779 #define XSTORM_STAT_FCOE_TX_PKT_CNT_OFFSET (IRO[366].base)
781 #define XSTORM_STAT_FCOE_TX_BYTE_CNT_OFFSET (IRO[367].base)
783 #define XSTORM_STAT_FCP_TX_PKT_CNT_OFFSET (IRO[368].base)
785 #define XSTORM_STAT_OFFSET (IRO[369].base)
787 #define XSTORM_DEBUG_ABTS_BLOCK_SQ_CNT_OFFSET (IRO[370].base)
789 #define XSTORM_DEBUG_CLEANUP_BLOCK_SQ_CNT_OFFSET (IRO[371].base)
791 #define XSTORM_DEBUG_OFFSET (IRO[372].base)
793 #define TSTORM_STAT_FCOE_VER_CNT_OFFSET (IRO[373].base)
795 #define TSTORM_STAT_FCOE_RX_PKT_CNT_OFFSET (IRO[374].base)
797 #define TSTORM_STAT_FCOE_RX_BYTE_CNT_OFFSET (IRO[375].base)
799 #define TSTORM_STAT_FCOE_RX_DROP_PKT_CNT_OFFSET (IRO[376].base)
801 #define TSTORM_STAT_OFFSET (IRO[377].base)
803 #define TSTORM_PORT_DEBUG_WAIT_FOR_YOUR_TURN_SP_CNT_OFFSET (IRO[378].base)
805 #define TSTORM_PORT_DEBUG_AFEX_ERROR_PACKETS_OFFSET (IRO[379].base)
807 #define TSTORM_PORT_DEBUG_OFFSET (IRO[380].base)
809 #define TSTORM_REORDER_DATA_OFFSET (IRO[381].base)
811 #define TSTORM_REORDER_WAITING_TABLE_OFFSET (IRO[382].base)
813 #define TSTORM_WAITING_LIST_SIZE (IRO[383].base)
814 #define TSTORM_REORDER_WAITING_ENTRY_OFFSET (IRO[384].base)