Lines Matching refs:val
33 u32_t val; in fw_reset_sync() local
91 val = 0; in fw_reset_sync()
102 &val); in fw_reset_sync()
103 if((val & FW_MSG_ACK) == (msg_data & DRV_MSG_SEQ)) in fw_reset_sync()
109 if((val & FW_MSG_ACK) != (msg_data & DRV_MSG_SEQ)) in fw_reset_sync()
303 u32_t val; in init_context_5709() local
307 val = 0x3001; in init_context_5709()
308 val |= (LM_PAGE_BITS - 8) << 16; in init_context_5709()
309 REG_WR(pdev, context.ctx_command, val); in init_context_5709()
344 REG_RD(pdev, context.ctx_host_page_tbl_ctrl, &val); in init_context_5709()
346 if(!(val & CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ)) in init_context_5709()
354 DbgBreakIf(val & CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); in init_context_5709()
380 u32_t val; in alloc_bad_rbuf_5706_a0_wa() local
390 REG_RD_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_status1), &val); in alloc_bad_rbuf_5706_a0_wa()
391 while(val & RBUF_STATUS1_FREE_COUNT) in alloc_bad_rbuf_5706_a0_wa()
401 &val); in alloc_bad_rbuf_5706_a0_wa()
402 val &= RBUF_FW_BUF_ALLOC_VALUE; in alloc_bad_rbuf_5706_a0_wa()
405 if(!(val & (1 << 9))) in alloc_bad_rbuf_5706_a0_wa()
409 good_mbuf[good_mbuf_cnt] = (u16_t) val; in alloc_bad_rbuf_5706_a0_wa()
413 REG_RD_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_status1), &val); in alloc_bad_rbuf_5706_a0_wa()
422 val = good_mbuf[good_mbuf_cnt]; in alloc_bad_rbuf_5706_a0_wa()
423 val = (val << 9) | val | 1; in alloc_bad_rbuf_5706_a0_wa()
425 REG_WR_IND(pdev, OFFSETOF(reg_space_t, rbuf.rbuf_fw_buf_free), val); in alloc_bad_rbuf_5706_a0_wa()
441 u32_t val; in lm_chip_reset() local
466 &val); in lm_chip_reset()
467 val &= ~PCICFG_COMMAND_BUS_MASTER; in lm_chip_reset()
471 val); in lm_chip_reset()
476 REG_RD(pdev, misc.misc_new_core_ctl, &val); in lm_chip_reset()
477 val &= ~(1 << 16); in lm_chip_reset()
478 REG_WR(pdev, misc.misc_new_core_ctl, val); in lm_chip_reset()
487 &val); in lm_chip_reset()
488 if((val & (PCICFG_DEVICE_STATUS_NO_PEND << 16)) == 0) in lm_chip_reset()
502 &val); in lm_chip_reset()
504 if((val & CAPABILITY_SIGNATURE_MASK) == FW_CAP_SIGNATURE) in lm_chip_reset()
506 val = DRV_ACK_CAP_SIGNATURE; in lm_chip_reset()
512 val |= FW_CAP_REMOTE_PHY_CAPABLE; in lm_chip_reset()
516 val &= ~FW_CAP_REMOTE_PHY_CAPABLE; in lm_chip_reset()
524 val); in lm_chip_reset()
547 REG_RD(pdev, misc.misc_id, &val); in lm_chip_reset()
577 REG_RD(pdev, pci_config.pcicfg_misc_config, &val); in lm_chip_reset()
581 if((val & ( in lm_chip_reset()
589 DbgBreakIf(val & ( in lm_chip_reset()
598 REG_RD( pdev, misc.misc_command, &val); in lm_chip_reset()
605 REG_RD(pdev, misc.misc_command, &val); in lm_chip_reset()
609 if((val & MISC_COMMAND_SW_RESET) == 0) in lm_chip_reset()
615 DbgBreakIf(val & MISC_COMMAND_SW_RESET); in lm_chip_reset()
628 &val); in lm_chip_reset()
629 val |= PCICFG_COMMAND_BUS_MASTER; in lm_chip_reset()
633 val); in lm_chip_reset()
636 REG_RD(pdev, tsch.tsch_ctx_access_cfg, &val); in lm_chip_reset()
637 val &= ~TSCH_CTX_ACCESS_CFG_L5_TCMD_PREFETCH_SIZE; in lm_chip_reset()
638 REG_WR(pdev, tsch.tsch_ctx_access_cfg, val); in lm_chip_reset()
645 REG_RD(pdev, misc.misc_new_core_ctl, &val); in lm_chip_reset()
646 val |= (1 << 16); in lm_chip_reset()
647 REG_WR(pdev, misc.misc_new_core_ctl, val); in lm_chip_reset()
657 REG_RD(pdev, mq.mq_config, &val); in lm_chip_reset()
658 REG_WR(pdev, mq.mq_config, val | MQ_CONFIG_HALT_DIS); in lm_chip_reset()
668 REG_RD(pdev, pci.pci_swap_diag0, &val); in lm_chip_reset()
670 DbgBreakIf(val != 0x01020304); in lm_chip_reset()
707 REG_RD(pdev, misc.misc_eco_hw_ctl, &val); in lm_chip_reset()
708 val |= MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN; in lm_chip_reset()
709 REG_WR(pdev, misc.misc_eco_hw_ctl, val); in lm_chip_reset()
713 REG_RD(pdev, misc.misc_eco_hw_ctl, &val); in lm_chip_reset()
714 val &= ~MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN; in lm_chip_reset()
715 REG_WR(pdev, misc.misc_eco_hw_ctl, val); in lm_chip_reset()
742 val = pdev->params.mac_addr[0] + in lm_chip_reset()
748 REG_WR(pdev, emac.emac_backoff_seed, val); in lm_chip_reset()
762 val = pdev->vars.drv_pulse_wr_seq | DRV_PULSE_ALWAYS_ALIVE; in lm_chip_reset()
768 val); in lm_chip_reset()
865 u32_t val; in l4_reset_setup() local
886 val = L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE << 24; in l4_reset_setup()
887 val |= (((sizeof(l2_bd_chain_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; in l4_reset_setup()
888 val |= 0x2 << 8; in l4_reset_setup()
893 val); in l4_reset_setup()
895 val = pdev->ofld.gen_chain.bd_chain_phy.as_u32.high; in l4_reset_setup()
900 val); in l4_reset_setup()
902 val = pdev->ofld.gen_chain.bd_chain_phy.as_u32.low; in l4_reset_setup()
907 val); in l4_reset_setup()
928 val = L4CTX_TYPE_TYPE_L2 << 24; in l4_reset_setup()
929 val |= (((sizeof(l4_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; in l4_reset_setup()
934 val); in l4_reset_setup()
936 val = (CCELL_CMD_TYPE_TYPE_L2 | ((LM_PAGE_BITS-8) << 4)) << 24; in l4_reset_setup()
937 val |= 8 << 16; in l4_reset_setup()
942 val); in l4_reset_setup()
944 val = pdev->ofld.hcopy_chain.bd_chain_phy.as_u32.high; in l4_reset_setup()
951 val); in l4_reset_setup()
953 val = pdev->ofld.hcopy_chain.bd_chain_phy.as_u32.low; in l4_reset_setup()
960 val); in l4_reset_setup()
1011 u32_t val; in init_l2txq() local
1041 val = (L4CTX_TYPE_TYPE_L2 << 24) | in init_l2txq()
1046 val = (0x10 << 24) | in init_l2txq()
1060 CTX_WR(pdev, txq->cid_addr, offset, val); in init_l2txq()
1072 val = (CCELL_CMD_TYPE_TYPE_L2 | ((LM_PAGE_BITS-8) << 4)) << 24; in init_l2txq()
1073 val |= 8 << 16; in init_l2txq()
1074 CTX_WR(pdev, txq->cid_addr, offset, val); in init_l2txq()
1076 val = txq->bd_chain_phy.as_u32.high; in init_l2txq()
1082 val); in init_l2txq()
1084 val = txq->bd_chain_phy.as_u32.low; in init_l2txq()
1090 val); in init_l2txq()
1109 u32_t val; in init_l2rxq() local
1138 val = L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE << 24; in init_l2rxq()
1139 val |= (((sizeof(l2_bd_chain_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; in init_l2rxq()
1140 val |= 0x02 << 8; in init_l2rxq()
1145 val); in init_l2rxq()
1147 val = rxq->bd_chain_phy.as_u32.high; in init_l2rxq()
1152 val); in init_l2rxq()
1154 val = rxq->bd_chain_phy.as_u32.low; in init_l2rxq()
1159 val); in init_l2rxq()
1190 u32_t val; in init_kq() local
1210 val = KRNLQ_TYPE_TYPE_KRNLQ << 24; in init_kq()
1211 val |= (((sizeof(krnlq_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; in init_kq()
1212 val |= LM_PAGE_BITS-8; in init_kq()
1213 val |= KRNLQ_FLAGS_QE_SELF_SEQ; in init_kq()
1218 val); in init_kq()
1220 val = (LM_PAGE_SIZE/sizeof(kwqe_t) - 1) << 16; in init_kq()
1225 val); in init_kq()
1227 val = (LM_PAGE_SIZE/sizeof(kwqe_t)) << 16; in init_kq()
1228 val |= pdev->params.kwq_page_cnt; in init_kq()
1233 val); in init_kq()
1235 val = kq->kwq_pgtbl_phy.as_u32.high; in init_kq()
1240 val); in init_kq()
1242 val = kq->kwq_pgtbl_phy.as_u32.low; in init_kq()
1247 val); in init_kq()
1265 val = KRNLQ_TYPE_TYPE_KRNLQ << 24; in init_kq()
1266 val |= (((sizeof(krnlq_context_t) + 0x1f) & ~0x1f) / 0x20) << 16; in init_kq()
1267 val |= LM_PAGE_BITS-8; in init_kq()
1268 val |= KRNLQ_FLAGS_QE_SELF_SEQ; in init_kq()
1273 val); in init_kq()
1275 val = (LM_PAGE_SIZE/sizeof(kwqe_t) - 1) << 16; in init_kq()
1280 val); in init_kq()
1282 val = (LM_PAGE_SIZE/sizeof(kcqe_t)) << 16; in init_kq()
1283 val |= pdev->params.kcq_page_cnt; in init_kq()
1288 val); in init_kq()
1290 val = kq->kcq_pgtbl_phy.as_u32.high; in init_kq()
1295 val); in init_kq()
1297 val = kq->kcq_pgtbl_phy.as_u32.low; in init_kq()
1302 val); in init_kq()
1345 u32_t *val, in get_trip_val() argument
1369 *val = 0; in get_trip_val()
1373 *val += isolate_rbuf_trip_tbl[type][1]; in get_trip_val()
1375 *val += trip_tbl[type][1]; in get_trip_val()
1380 *val = *val + (isolate_rbuf_trip_tbl[type][0] - (mbuf_cnt_adj<<16 | mbuf_cnt_adj)); in get_trip_val()
1382 *val = *val + trip_tbl[type][0]; in get_trip_val()
1509 u32_t val; in init_5709_for_msix() local
1522 REG_RD(pdev, pci_config.pcicfg_msix_control, &val); in init_5709_for_msix()
1538 &val); in init_5709_for_msix()
1539 val &= PCICFG_MSI_CONTROL_MENA; in init_5709_for_msix()
1540 val |= PCICFG_MSI_CONTROL_MENA_16; in init_5709_for_msix()
1543 (u16_t)val); in init_5709_for_msix()
1548 if(val & PCICFG_MSIX_CONTROL_MSIX_ENABLE) in init_5709_for_msix()
1594 &val); in init_5709_for_msix()
1595 val &= ~PCICFG_MSI_CONTROL_MENA; in init_5709_for_msix()
1598 (u16_t)val); in init_5709_for_msix()
1632 u32_t val; in init_hc() local
1635 REG_RD(pdev, hc.hc_config, &val); in init_hc()
1636 val &= ~(HC_CONFIG_RX_TMR_MODE | HC_CONFIG_TX_TMR_MODE | in init_hc()
1641 val |= HC_CONFIG_RX_TMR_MODE; in init_hc()
1646 val |= HC_CONFIG_TX_TMR_MODE; in init_hc()
1651 val |= HC_CONFIG_COM_TMR_MODE; in init_hc()
1656 val |= HC_CONFIG_CMD_TMR_MODE; in init_hc()
1661 val &= ~HC_CONFIG_SET_MASK_AT_RD; in init_hc()
1668 REG_WR(pdev, hc.hc_config, val); in init_hc()
1672 REG_RD(pdev, hc.hc_attn_bits_enable, &val); in init_hc()
1673 val |= STATUS_ATTN_BITS_TIMER_ABORT; in init_hc()
1674 REG_WR(pdev, hc.hc_attn_bits_enable, val); in init_hc()
1718 val = pdev->params.stats_ticks; in init_hc()
1721 val = val / 1000; in init_hc()
1722 if(val < 0x100) in init_hc()
1724 val = 0x100; in init_hc()
1727 REG_WR(pdev, hc.hc_stats_ticks, val); in init_hc()
1968 u32_t val; in lm_reset_setup() local
1979 &val); in lm_reset_setup()
1980 val &= ~(PCICFG_PCIX_COMMAND_RELAX_ORDER << 16); in lm_reset_setup()
1984 val); in lm_reset_setup()
2007 val = DMA_CONFIG_DATA_BYTE_SWAP_TE | in lm_reset_setup()
2019 val |= DMA_CONFIG_CNTL_PING_PONG_DMA_TE; in lm_reset_setup()
2025 val |= (0x2<<20) | (1<<11); in lm_reset_setup()
2032 val |= 1 << 23; in lm_reset_setup()
2038 val |= 0x100; in lm_reset_setup()
2041 REG_WR(pdev, dma.dma_config, val); in lm_reset_setup()
2045 REG_RD(pdev, tdma.tdma_config, &val); in lm_reset_setup()
2046 val |= TDMA_CONFIG_ONE_DMA; in lm_reset_setup()
2047 REG_WR(pdev, tdma.tdma_config, val); in lm_reset_setup()
2052 REG_RD(pdev, pci.pci_config_2, &val); in lm_reset_setup()
2053 val &= ~0x02000000; in lm_reset_setup()
2054 REG_WR(pdev, pci.pci_config_2, val); in lm_reset_setup()
2133 REG_RD(pdev, mq.mq_config, &val); in lm_reset_setup()
2134 val &= ~MQ_CONFIG_KNL_BYP_BLK_SIZE; in lm_reset_setup()
2138 val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_256; in lm_reset_setup()
2142 val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_512; in lm_reset_setup()
2146 val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_1K; in lm_reset_setup()
2150 val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_2K; in lm_reset_setup()
2154 val |= MQ_CONFIG_KNL_BYP_BLK_SIZE_4K; in lm_reset_setup()
2166 val |= MQ_CONFIG_BIN_MQ_MODE; in lm_reset_setup()
2169 REG_WR(pdev, mq.mq_config, val); in lm_reset_setup()
2173 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); in lm_reset_setup()
2174 REG_WR(pdev, mq.mq_knl_byp_wind_start, val); in lm_reset_setup()
2175 REG_WR(pdev, mq.mq_knl_wind_end, val); in lm_reset_setup()
2178 REG_RD(pdev, tbdr.tbdr_config, &val); in lm_reset_setup()
2179 val &= ~TBDR_CONFIG_PAGE_SIZE; in lm_reset_setup()
2180 val |= (LM_PAGE_BITS - 8) << 24 | 0x40; in lm_reset_setup()
2181 REG_WR(pdev, tbdr.tbdr_config, val); in lm_reset_setup()
2184 val = pdev->params.mtu+4; in lm_reset_setup()
2187 val |= EMAC_RX_MTU_SIZE_JUMBO_ENA; in lm_reset_setup()
2189 REG_WR(pdev, emac.emac_rx_mtu_size, val); in lm_reset_setup()
2214 &val, in lm_reset_setup()
2221 val); in lm_reset_setup()
2226 &val, in lm_reset_setup()
2233 val); in lm_reset_setup()
2237 get_trip_val(TRIP_CU, pdev->params.mtu, &val, 0, 0); in lm_reset_setup()
2241 val); in lm_reset_setup()
2249 &val); in lm_reset_setup()
2250 val |= RBUF_COMMAND_CU_ISOLATE_XI; in lm_reset_setup()
2254 val); in lm_reset_setup()
2262 val = pdev->vars.cu_mbuf_cnt; in lm_reset_setup()
2266 val); in lm_reset_setup()
2274 &val); in lm_reset_setup()
2277 val -= 1; in lm_reset_setup()
2278 val *= 128; in lm_reset_setup()
2282 val); in lm_reset_setup()
2310 REG_RD(pdev, emac.emac_mdio_mode, &val); in lm_reset_setup()
2311 val |= EMAC_MDIO_MODE_AUTO_POLL; in lm_reset_setup()
2312 REG_WR(pdev, emac.emac_mdio_mode, val); in lm_reset_setup()
2404 REG_RD(pdev, mq.mq_config2, &val); in lm_reset_setup()
2406 pdev->hw_info.first_l4_l5_bin = (u16_t) (val & MQ_CONFIG2_FIRST_L4L5); in lm_reset_setup()
2407 pdev->hw_info.bin_size = (u8_t) (val & MQ_CONFIG2_CONT_SZ) >> 3; in lm_reset_setup()
2411 val = (LM_PAGE_BITS - 8) << 24; in lm_reset_setup()
2412 REG_WR(pdev, rv2p.rv2p_config, val); in lm_reset_setup()