Lines Matching refs:dev
95 static void audigyls_configure_mixer(audigyls_dev_t *dev);
149 read_chan(audigyls_dev_t *dev, int reg, int chn) in read_chan() argument
153 mutex_enter(&dev->low_mutex); in read_chan()
155 OUTL(dev, PR, (reg << 16) | (chn & 0xffff)); in read_chan()
157 val = INL(dev, DR); in read_chan()
158 mutex_exit(&dev->low_mutex); in read_chan()
164 write_chan(audigyls_dev_t *dev, int reg, int chn, uint32_t value) in write_chan() argument
166 mutex_enter(&dev->low_mutex); in write_chan()
168 OUTL(dev, PR, (reg << 16) | (chn & 0x7)); in write_chan()
170 OUTL(dev, DR, value); in write_chan()
171 mutex_exit(&dev->low_mutex); in write_chan()
175 read_reg(audigyls_dev_t *dev, int reg) in read_reg() argument
177 return (read_chan(dev, reg, 0)); in read_reg()
181 write_reg(audigyls_dev_t *dev, int reg, uint32_t value) in write_reg() argument
183 write_chan(dev, reg, 0, value); in write_reg()
190 audigyls_dev_t *dev = arg; in audigyls_read_ac97() local
194 mutex_enter(&dev->low_mutex); in audigyls_read_ac97()
195 OUTB(dev, AC97A, index); in audigyls_read_ac97()
197 if (INB(dev, AC97A) & 0x80) in audigyls_read_ac97()
201 mutex_exit(&dev->low_mutex); in audigyls_read_ac97()
204 dtemp = INW(dev, AC97D); in audigyls_read_ac97()
205 mutex_exit(&dev->low_mutex); in audigyls_read_ac97()
213 audigyls_dev_t *dev = arg; in audigyls_write_ac97() local
216 mutex_enter(&dev->low_mutex); in audigyls_write_ac97()
217 OUTB(dev, AC97A, index); in audigyls_write_ac97()
219 if (INB(dev, AC97A) & 0x80) in audigyls_write_ac97()
223 mutex_exit(&dev->low_mutex); in audigyls_write_ac97()
226 OUTW(dev, AC97D, data); in audigyls_write_ac97()
227 mutex_exit(&dev->low_mutex); in audigyls_write_ac97()
231 select_digital_enable(audigyls_dev_t *dev, int mode) in select_digital_enable() argument
239 write_reg(dev, SPC, 0x00000f00); in select_digital_enable()
241 write_reg(dev, SPC, 0x0000000f); in select_digital_enable()
247 audigyls_i2c_write(audigyls_dev_t *dev, int reg, int data) in audigyls_i2c_write() argument
253 write_reg(dev, I2C_1, tmp); in audigyls_i2c_write()
255 tmp = read_reg(dev, I2C_A) & ~0x6fe; in audigyls_i2c_write()
258 write_reg(dev, I2C_A, tmp); in audigyls_i2c_write()
262 tmp = read_reg(dev, I2C_A); in audigyls_i2c_write()
279 audigyls_spi_write(audigyls_dev_t *dev, int data) in audigyls_spi_write() argument
285 tmp = read_reg(dev, SPI); in audigyls_spi_write()
287 write_reg(dev, SPI, orig | data); in audigyls_spi_write()
292 tmp = read_reg(dev, SPI); in audigyls_spi_write()
312 audigyls_dev_t *dev = port->dev; in audigyls_open() local
316 mutex_enter(&dev->mutex); in audigyls_open()
321 mutex_exit(&dev->mutex); in audigyls_open()
336 audigyls_dev_t *dev = port->dev; in audigyls_start() local
339 mutex_enter(&dev->mutex); in audigyls_start()
345 write_chan(dev, PTCA, 0, 0); in audigyls_start()
346 write_chan(dev, CPFA, 0, 0); in audigyls_start()
347 write_chan(dev, CPCAV, 0, 0); in audigyls_start()
348 write_chan(dev, PTCA, 1, 0); in audigyls_start()
349 write_chan(dev, CPFA, 1, 0); in audigyls_start()
350 write_chan(dev, CPCAV, 1, 0); in audigyls_start()
351 write_chan(dev, PTCA, 3, 0); in audigyls_start()
352 write_chan(dev, CPFA, 3, 0); in audigyls_start()
353 write_chan(dev, CPCAV, 3, 0); in audigyls_start()
355 tmp = read_reg(dev, SA); in audigyls_start()
359 write_reg(dev, SA, tmp); in audigyls_start()
363 write_chan(dev, CRFA, 2, 0); in audigyls_start()
364 write_chan(dev, CRCAV, 2, 0); in audigyls_start()
366 tmp = read_reg(dev, SA); in audigyls_start()
368 write_reg(dev, SA, tmp); in audigyls_start()
372 mutex_exit(&dev->mutex); in audigyls_start()
380 audigyls_dev_t *dev = port->dev; in audigyls_stop() local
383 mutex_enter(&dev->mutex); in audigyls_stop()
387 tmp = read_reg(dev, SA); in audigyls_stop()
391 write_reg(dev, SA, tmp); in audigyls_stop()
395 tmp = read_reg(dev, SA); in audigyls_stop()
397 write_reg(dev, SA, tmp); in audigyls_stop()
401 mutex_exit(&dev->mutex); in audigyls_stop()
441 audigyls_dev_t *dev = port->dev; in audigyls_count() local
445 mutex_enter(&dev->mutex); in audigyls_count()
448 offset = read_chan(dev, CPFA, 0); in audigyls_count()
450 offset = read_chan(dev, CRFA, 2); in audigyls_count()
465 mutex_exit(&dev->mutex); in audigyls_count()
486 audigyls_alloc_port(audigyls_dev_t *dev, int num) in audigyls_alloc_port() argument
496 adev = dev->adev; in audigyls_alloc_port()
498 dev->port[num] = port; in audigyls_alloc_port()
499 port->dev = dev; in audigyls_alloc_port()
523 if (ddi_dma_alloc_handle(dev->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL, in audigyls_alloc_port()
557 audigyls_del_controls(audigyls_dev_t *dev) in audigyls_del_controls() argument
560 if (dev->controls[i].ctrl) { in audigyls_del_controls()
561 audio_dev_del_control(dev->controls[i].ctrl); in audigyls_del_controls()
562 dev->controls[i].ctrl = NULL; in audigyls_del_controls()
568 audigyls_destroy(audigyls_dev_t *dev) in audigyls_destroy() argument
570 mutex_destroy(&dev->mutex); in audigyls_destroy()
571 mutex_destroy(&dev->low_mutex); in audigyls_destroy()
574 audigyls_port_t *port = dev->port[i]; in audigyls_destroy()
578 audio_dev_remove_engine(dev->adev, port->engine); in audigyls_destroy()
593 if (dev->ac97 != NULL) { in audigyls_destroy()
594 ac97_free(dev->ac97); in audigyls_destroy()
597 audigyls_del_controls(dev); in audigyls_destroy()
599 if (dev->adev != NULL) { in audigyls_destroy()
600 audio_dev_free(dev->adev); in audigyls_destroy()
602 if (dev->regsh != NULL) { in audigyls_destroy()
603 ddi_regs_map_free(&dev->regsh); in audigyls_destroy()
605 if (dev->pcih != NULL) { in audigyls_destroy()
606 pci_config_teardown(&dev->pcih); in audigyls_destroy()
608 kmem_free(dev, sizeof (*dev)); in audigyls_destroy()
612 audigyls_hwinit(audigyls_dev_t *dev) in audigyls_hwinit() argument
628 select_digital_enable(dev, dev->digital_enable); in audigyls_hwinit()
662 if (dev->ac97) in audigyls_hwinit()
663 OUTL(dev, GPIO, 0x005f03a3); in audigyls_hwinit()
666 OUTL(dev, GPIO, 0x005f4301); in audigyls_hwinit()
668 audigyls_i2c_write(dev, 0x15, 0x2); in audigyls_hwinit()
672 if (!audigyls_spi_write(dev, spi_dac[i]) && in audigyls_hwinit()
680 OUTL(dev, IER, 0); in audigyls_hwinit()
681 OUTL(dev, HC, 0x00000009); /* Enable audio, use 48 kHz */ in audigyls_hwinit()
683 tmp = read_chan(dev, SRCTL, 0); in audigyls_hwinit()
684 if (dev->ac97) in audigyls_hwinit()
689 write_chan(dev, SRCTL, 0, tmp); in audigyls_hwinit()
691 write_reg(dev, HMIXMAP_I2S, 0x76543210); /* Default out route */ in audigyls_hwinit()
692 write_reg(dev, AUDCTL, 0x0f0f003f); /* Enable all outputs */ in audigyls_hwinit()
695 write_reg(dev, SA, 0); in audigyls_hwinit()
702 write_chan(dev, PTBA, i, 0); in audigyls_hwinit()
703 write_chan(dev, PTBS, i, 0); in audigyls_hwinit()
704 write_chan(dev, PTCA, i, 0); in audigyls_hwinit()
706 write_chan(dev, CPFA, i, 0); in audigyls_hwinit()
707 write_chan(dev, PFEA, i, 0); in audigyls_hwinit()
708 write_chan(dev, CPCAV, i, 0); in audigyls_hwinit()
710 write_chan(dev, CRFA, i, 0); in audigyls_hwinit()
711 write_chan(dev, CRCAV, i, 0); in audigyls_hwinit()
718 port = dev->port[AUDIGYLS_PLAY_PORT]; in audigyls_hwinit()
721 write_chan(dev, PFBA, 0, paddr); in audigyls_hwinit()
722 write_chan(dev, PFBS, 0, chunksz << 16); in audigyls_hwinit()
724 write_chan(dev, PFBA, 1, paddr); in audigyls_hwinit()
725 write_chan(dev, PFBS, 1, chunksz << 16); in audigyls_hwinit()
727 write_chan(dev, PFBA, 3, paddr); in audigyls_hwinit()
728 write_chan(dev, PFBS, 3, chunksz << 16); in audigyls_hwinit()
731 port = dev->port[AUDIGYLS_REC_PORT]; in audigyls_hwinit()
734 write_chan(dev, RFBA, 2, paddr); in audigyls_hwinit()
735 write_chan(dev, RFBS, 2, chunksz << 16); in audigyls_hwinit()
738 tmp = read_chan(dev, SRCTL, 0) & ~0x0303c00f; in audigyls_hwinit()
739 write_chan(dev, SRCTL, 0, tmp); in audigyls_hwinit()
741 write_reg(dev, SCS0, 0x02108004); /* Audio */ in audigyls_hwinit()
742 write_reg(dev, SCS1, 0x02108004); /* Audio */ in audigyls_hwinit()
743 write_reg(dev, SCS2, 0x02108004); /* Audio */ in audigyls_hwinit()
744 write_reg(dev, SCS3, 0x02108004); /* Audio */ in audigyls_hwinit()
774 audigyls_configure_mixer(audigyls_dev_t *dev) in audigyls_configure_mixer() argument
780 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_FRONT].val, 8); in audigyls_configure_mixer()
782 write_chan(dev, MIXVOL_I2S, 0, r); in audigyls_configure_mixer()
785 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_SURROUND].val, 8); in audigyls_configure_mixer()
787 write_chan(dev, MIXVOL_I2S, 3, r); in audigyls_configure_mixer()
790 v1 = 255 - SCALE(dev->controls[CTL_CENTER].val, 8); in audigyls_configure_mixer()
791 v2 = 255 - SCALE(dev->controls[CTL_LFE].val, 8); in audigyls_configure_mixer()
794 write_chan(dev, MIXVOL_I2S, 1, r); in audigyls_configure_mixer()
797 r = dev->controls[CTL_SPREAD].val ? 0x10101010 : 0x76543210; in audigyls_configure_mixer()
798 write_reg(dev, HMIXMAP_I2S, r); in audigyls_configure_mixer()
803 v1 = dev->controls[CTL_RECORDVOL].val; in audigyls_configure_mixer()
804 if (dev->ac97_recgain && !dev->controls[CTL_LOOP].val) { in audigyls_configure_mixer()
809 (void) ac97_control_set(dev->ac97_recgain, v1); in audigyls_configure_mixer()
810 write_reg(dev, P17RECVOLL, 0x30303030); in audigyls_configure_mixer()
811 write_reg(dev, P17RECVOLH, 0x30303030); in audigyls_configure_mixer()
818 write_reg(dev, P17RECVOLL, r); in audigyls_configure_mixer()
819 write_reg(dev, P17RECVOLH, r); in audigyls_configure_mixer()
823 if (dev->ac97) { in audigyls_configure_mixer()
825 write_chan(dev, SRCTL, 1, 0x30303030); in audigyls_configure_mixer()
826 write_reg(dev, SMIXMAP_I2S, 0x10101076); in audigyls_configure_mixer()
829 r = 255 - SCALE(dev->controls[CTL_MONGAIN].val, 8); in audigyls_configure_mixer()
830 write_chan(dev, SRCTL, 1, 0xffff0000 | r << 8 | r); in audigyls_configure_mixer()
832 write_reg(dev, SMIXMAP_I2S, 0x10101076); in audigyls_configure_mixer()
834 write_reg(dev, SMIXMAP_I2S, 0x10101010); in audigyls_configure_mixer()
839 if (dev->ac97_recsrc != NULL) { in audigyls_configure_mixer()
840 (void) ac97_control_set(dev->ac97_recsrc, in audigyls_configure_mixer()
841 dev->controls[CTL_RECSRC].val); in audigyls_configure_mixer()
844 switch (dev->controls[CTL_RECSRC].val) { in audigyls_configure_mixer()
846 audigyls_i2c_write(dev, 0x15, 0x2); /* Mic */ in audigyls_configure_mixer()
847 OUTL(dev, GPIO, INL(dev, GPIO) | 0x400); in audigyls_configure_mixer()
851 audigyls_i2c_write(dev, 0x15, 0x4); /* Line */ in audigyls_configure_mixer()
852 OUTL(dev, GPIO, INL(dev, GPIO) & ~0x400); in audigyls_configure_mixer()
860 if (dev->controls[CTL_LOOP].val) { in audigyls_configure_mixer()
873 if (dev->ac97_recsrc != NULL) { in audigyls_configure_mixer()
883 write_reg(dev, P17RECSEL, r); in audigyls_configure_mixer()
890 audigyls_dev_t *dev = pc->dev; in audigyls_set_control() local
913 if (((1U << val) & (dev->recmask)) == 0) { in audigyls_set_control()
929 mutex_enter(&dev->mutex); in audigyls_set_control()
931 audigyls_configure_mixer(dev); in audigyls_set_control()
933 mutex_exit(&dev->mutex); in audigyls_set_control()
942 audigyls_dev_t *dev = pc->dev; in audigyls_get_control() local
944 mutex_enter(&dev->mutex); in audigyls_get_control()
946 mutex_exit(&dev->mutex); in audigyls_get_control()
951 audigyls_alloc_ctrl(audigyls_dev_t *dev, uint32_t num, uint64_t val) in audigyls_alloc_ctrl() argument
958 pc = &dev->controls[num]; in audigyls_alloc_ctrl()
960 pc->dev = dev; in audigyls_alloc_ctrl()
1014 if (dev->ac97_recsrc) { in audigyls_alloc_ctrl()
1019 adp = ac97_control_desc(dev->ac97_recsrc); in audigyls_alloc_ctrl()
1036 dev->recmask |= (1 << i); in audigyls_alloc_ctrl()
1039 desc.acd_minvalue = desc.acd_maxvalue = dev->recmask; in audigyls_alloc_ctrl()
1041 dev->recmask = 3; in audigyls_alloc_ctrl()
1050 ASSERT(!dev->ac97); in audigyls_alloc_ctrl()
1076 pc->ctrl = audio_dev_add_control(dev->adev, &desc, in audigyls_alloc_ctrl()
1081 audigyls_add_controls(audigyls_dev_t *dev) in audigyls_add_controls() argument
1083 audio_dev_add_soft_volume(dev->adev); in audigyls_add_controls()
1085 audigyls_alloc_ctrl(dev, CTL_FRONT, 75 | (75 << 8)); in audigyls_add_controls()
1086 audigyls_alloc_ctrl(dev, CTL_SURROUND, 75 | (75 << 8)); in audigyls_add_controls()
1087 audigyls_alloc_ctrl(dev, CTL_CENTER, 75); in audigyls_add_controls()
1088 audigyls_alloc_ctrl(dev, CTL_LFE, 75); in audigyls_add_controls()
1089 audigyls_alloc_ctrl(dev, CTL_RECORDVOL, 75 | (75 << 8)); in audigyls_add_controls()
1090 audigyls_alloc_ctrl(dev, CTL_RECSRC, 1); in audigyls_add_controls()
1091 audigyls_alloc_ctrl(dev, CTL_SPREAD, 0); in audigyls_add_controls()
1092 audigyls_alloc_ctrl(dev, CTL_LOOP, 0); in audigyls_add_controls()
1093 if (!dev->ac97) { in audigyls_add_controls()
1094 audigyls_alloc_ctrl(dev, CTL_MONGAIN, 0); in audigyls_add_controls()
1103 audigyls_dev_t *dev; in audigyls_attach() local
1108 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP); in audigyls_attach()
1109 dev->dip = dip; in audigyls_attach()
1110 ddi_set_driver_private(dip, dev); in audigyls_attach()
1111 mutex_init(&dev->mutex, NULL, MUTEX_DRIVER, NULL); in audigyls_attach()
1112 mutex_init(&dev->low_mutex, NULL, MUTEX_DRIVER, NULL); in audigyls_attach()
1114 if ((dev->adev = audio_dev_alloc(dip, 0)) == NULL) { in audigyls_attach()
1120 audio_dev_warn(dev->adev, "pci_config_setup failed"); in audigyls_attach()
1123 dev->pcih = pcih; in audigyls_attach()
1132 audio_dev_warn(dev->adev, "Hardware not recognized " in audigyls_attach()
1141 if ((ddi_regs_map_setup(dip, 1, &dev->base, 0, 0, &dev_attr, in audigyls_attach()
1142 &dev->regsh)) != DDI_SUCCESS) { in audigyls_attach()
1143 audio_dev_warn(dev->adev, "failed to map registers"); in audigyls_attach()
1148 dev->digital_enable = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip, in audigyls_attach()
1197 audio_dev_set_description(dev->adev, name); in audigyls_attach()
1199 audio_dev_set_version(dev->adev, version); in audigyls_attach()
1205 dev->ac97 = ac97_allocate(dev->adev, dip, in audigyls_attach()
1206 audigyls_read_ac97, audigyls_write_ac97, dev); in audigyls_attach()
1207 if (dev->ac97 == NULL) { in audigyls_attach()
1208 audio_dev_warn(dev->adev, in audigyls_attach()
1213 ac97_probe_controls(dev->ac97); in audigyls_attach()
1217 ctrl = ac97_control_find(dev->ac97, in audigyls_attach()
1224 dev->ac97_recgain = ac97_control_find(dev->ac97, in audigyls_attach()
1226 dev->ac97_recsrc = ac97_control_find(dev->ac97, in audigyls_attach()
1230 audigyls_add_controls(dev); in audigyls_attach()
1232 if (dev->ac97) { in audigyls_attach()
1233 ac97_register_controls(dev->ac97); in audigyls_attach()
1236 if (audigyls_alloc_port(dev, AUDIGYLS_PLAY_PORT) != DDI_SUCCESS) in audigyls_attach()
1238 if (audigyls_alloc_port(dev, AUDIGYLS_REC_PORT) != DDI_SUCCESS) in audigyls_attach()
1241 audigyls_hwinit(dev); in audigyls_attach()
1243 audigyls_configure_mixer(dev); in audigyls_attach()
1245 if (audio_dev_register(dev->adev) != DDI_SUCCESS) { in audigyls_attach()
1246 audio_dev_warn(dev->adev, "unable to register with framework"); in audigyls_attach()
1255 audigyls_destroy(dev); in audigyls_attach()
1262 audigyls_dev_t *dev; in audigyls_resume() local
1264 dev = ddi_get_driver_private(dip); in audigyls_resume()
1266 audigyls_hwinit(dev); in audigyls_resume()
1269 if (dev->ac97) in audigyls_resume()
1270 ac97_reset(dev->ac97); in audigyls_resume()
1272 audio_dev_resume(dev->adev); in audigyls_resume()
1278 audigyls_detach(audigyls_dev_t *dev) in audigyls_detach() argument
1280 if (audio_dev_unregister(dev->adev) != DDI_SUCCESS) in audigyls_detach()
1283 audigyls_destroy(dev); in audigyls_detach()
1288 audigyls_suspend(audigyls_dev_t *dev) in audigyls_suspend() argument
1290 audio_dev_suspend(dev->adev); in audigyls_suspend()
1372 audigyls_dev_t *dev; in audigyls_ddi_detach() local
1374 dev = ddi_get_driver_private(dip); in audigyls_ddi_detach()
1378 return (audigyls_detach(dev)); in audigyls_ddi_detach()
1381 return (audigyls_suspend(dev)); in audigyls_ddi_detach()
1391 audigyls_dev_t *dev; in audigyls_ddi_quiesce() local
1397 dev = ddi_get_driver_private(dip); in audigyls_ddi_quiesce()
1399 write_reg(dev, SA, 0); in audigyls_ddi_quiesce()
1400 OUTL(dev, IER, 0); /* Interrupt disable */ in audigyls_ddi_quiesce()
1401 write_reg(dev, AIE, 0); /* Disable audio interrupts */ in audigyls_ddi_quiesce()
1402 status = INL(dev, IPR); in audigyls_ddi_quiesce()
1403 OUTL(dev, IPR, status); /* Acknowledge */ in audigyls_ddi_quiesce()