Lines Matching refs:csr_handle
101 hci1394_csr_handle_t *csr_handle) in hci1394_csr_init() argument
108 ASSERT(csr_handle != NULL); in hci1394_csr_init()
114 *csr_handle = csr; in hci1394_csr_init()
130 hci1394_csr_fini(hci1394_csr_handle_t *csr_handle) in hci1394_csr_fini() argument
135 ASSERT(csr_handle != NULL); in hci1394_csr_fini()
137 csr = (hci1394_csr_t *)*csr_handle; in hci1394_csr_fini()
140 *csr_handle = NULL; in hci1394_csr_fini()
149 hci1394_csr_resume(hci1394_csr_handle_t csr_handle) in hci1394_csr_resume() argument
151 ASSERT(csr_handle != NULL); in hci1394_csr_resume()
152 hci1394_csr_state_init(csr_handle); in hci1394_csr_resume()
161 hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle, in hci1394_csr_node_capabilities() argument
164 ASSERT(csr_handle != NULL); in hci1394_csr_node_capabilities()
167 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_node_capabilities()
168 *capabilities = csr_handle->csr_capabilities; in hci1394_csr_node_capabilities()
169 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_node_capabilities()
180 hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state) in hci1394_csr_state_get() argument
182 ASSERT(csr_handle != NULL); in hci1394_csr_state_get()
185 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_state_get()
186 *state = csr_handle->csr_state; in hci1394_csr_state_get()
187 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_state_get()
199 hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state) in hci1394_csr_state_bset() argument
204 ASSERT(csr_handle != NULL); in hci1394_csr_state_bset()
206 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_state_bset()
217 (hci1394_ohci_root_check(csr_handle->csr_ohci))) { in hci1394_csr_state_bset()
218 hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci); in hci1394_csr_state_bset()
222 csr_handle->csr_state |= supported_state; in hci1394_csr_state_bset()
224 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_state_bset()
236 hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state) in hci1394_csr_state_bclr() argument
241 ASSERT(csr_handle != NULL); in hci1394_csr_state_bclr()
243 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_state_bclr()
254 (hci1394_ohci_root_check(csr_handle->csr_ohci))) { in hci1394_csr_state_bclr()
255 hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci); in hci1394_csr_state_bclr()
259 csr_handle->csr_state &= ~state; in hci1394_csr_state_bclr()
261 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_state_bclr()
270 hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle, in hci1394_csr_split_timeout_hi_get() argument
273 ASSERT(csr_handle != NULL); in hci1394_csr_split_timeout_hi_get()
276 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_hi_get()
277 *split_timeout_hi = csr_handle->csr_split_timeout_hi; in hci1394_csr_split_timeout_hi_get()
278 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_hi_get()
287 hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle, in hci1394_csr_split_timeout_lo_get() argument
290 ASSERT(csr_handle != NULL); in hci1394_csr_split_timeout_lo_get()
293 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_lo_get()
299 *split_timeout_lo = csr_handle->csr_split_timeout_lo << in hci1394_csr_split_timeout_lo_get()
302 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_lo_get()
315 hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle, in hci1394_csr_split_timeout_hi_set() argument
318 ASSERT(csr_handle != NULL); in hci1394_csr_split_timeout_hi_set()
320 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_hi_set()
326 csr_handle->csr_split_timeout_hi = split_timeout_hi & in hci1394_csr_split_timeout_hi_set()
328 csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT( in hci1394_csr_split_timeout_hi_set()
329 csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo); in hci1394_csr_split_timeout_hi_set()
331 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_hi_set()
344 hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle, in hci1394_csr_split_timeout_lo_set() argument
347 ASSERT(csr_handle != NULL); in hci1394_csr_split_timeout_lo_set()
349 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_lo_set()
356 csr_handle->csr_split_timeout_lo = split_timeout_lo >> in hci1394_csr_split_timeout_lo_set()
360 if (csr_handle->csr_split_timeout_lo < CSR_MIN_SPLIT_TIMEOUT_LO) { in hci1394_csr_split_timeout_lo_set()
361 csr_handle->csr_split_timeout_lo = CSR_MIN_SPLIT_TIMEOUT_LO; in hci1394_csr_split_timeout_lo_set()
362 } else if (csr_handle->csr_split_timeout_lo > in hci1394_csr_split_timeout_lo_set()
364 csr_handle->csr_split_timeout_lo = CSR_MAX_SPLIT_TIMEOUT_LO; in hci1394_csr_split_timeout_lo_set()
368 csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT( in hci1394_csr_split_timeout_lo_set()
369 csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo); in hci1394_csr_split_timeout_lo_set()
371 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_lo_set()
382 hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle) in hci1394_csr_split_timeout_get() argument
387 ASSERT(csr_handle != NULL); in hci1394_csr_split_timeout_get()
389 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_get()
392 split_timeout = csr_handle->csr_split_timeout; in hci1394_csr_split_timeout_get()
394 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_split_timeout_get()
409 hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle) in hci1394_csr_bus_reset() argument
411 ASSERT(csr_handle != NULL); in hci1394_csr_bus_reset()
413 mutex_enter(&csr_handle->csr_mutex); in hci1394_csr_bus_reset()
416 csr_handle->csr_state &= ~IEEE1394_CSR_STATE_ABDICATE; in hci1394_csr_bus_reset()
419 if (hci1394_ohci_root_check(csr_handle->csr_ohci) == B_FALSE) { in hci1394_csr_bus_reset()
424 csr_handle->csr_was_root = B_FALSE; in hci1394_csr_bus_reset()
431 csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR; in hci1394_csr_bus_reset()
437 } else if (csr_handle->csr_was_root == B_FALSE) { in hci1394_csr_bus_reset()
440 csr_handle->csr_was_root = B_TRUE; in hci1394_csr_bus_reset()
447 if (hci1394_ohci_cmc_check(csr_handle->csr_ohci)) { in hci1394_csr_bus_reset()
448 csr_handle->csr_state |= IEEE1394_CSR_STATE_CMSTR; in hci1394_csr_bus_reset()
449 hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci); in hci1394_csr_bus_reset()
457 csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR; in hci1394_csr_bus_reset()
458 hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci); in hci1394_csr_bus_reset()
467 mutex_exit(&csr_handle->csr_mutex); in hci1394_csr_bus_reset()