Lines Matching refs:r
35 #define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1) argument
46 #define VR0(r...) VR0_(r) argument
47 #define VR1(r...) VR1_(r) argument
48 #define VR2(r...) VR2_(r, 1) argument
49 #define VR3(r...) VR3_(r, 1, 2) argument
50 #define VR4(r...) VR4_(r, 1, 2) argument
51 #define VR5(r...) VR5_(r, 1, 2, 3) argument
52 #define VR6(r...) VR6_(r, 1, 2, 3, 4) argument
53 #define VR7(r...) VR7_(r, 1, 2, 3, 4, 5) argument
70 #define XOR_ACC(src, r...) \ argument
72 switch (REG_CNT(r)) { \
75 "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
76 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
77 "pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
78 "pxor 0x30(%[SRC]), %%" VR3(r) "\n" \
83 "pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
84 "pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
92 #define XOR(r...) \ argument
94 switch (REG_CNT(r)) { \
97 "pxor %" VR0(r) ", %" VR4(r) "\n" \
98 "pxor %" VR1(r) ", %" VR5(r) "\n" \
99 "pxor %" VR2(r) ", %" VR6(r) "\n" \
100 "pxor %" VR3(r) ", %" VR7(r)); \
104 "pxor %" VR0(r) ", %" VR2(r) "\n" \
105 "pxor %" VR1(r) ", %" VR3(r)); \
112 #define ZERO(r...) XOR(r, r) argument
114 #define COPY(r...) \ argument
116 switch (REG_CNT(r)) { \
119 "movdqa %" VR0(r) ", %" VR4(r) "\n" \
120 "movdqa %" VR1(r) ", %" VR5(r) "\n" \
121 "movdqa %" VR2(r) ", %" VR6(r) "\n" \
122 "movdqa %" VR3(r) ", %" VR7(r)); \
126 "movdqa %" VR0(r) ", %" VR2(r) "\n" \
127 "movdqa %" VR1(r) ", %" VR3(r)); \
134 #define LOAD(src, r...) \ argument
136 switch (REG_CNT(r)) { \
139 "movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
140 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
141 "movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
142 "movdqa 0x30(%[SRC]), %%" VR3(r) "\n" \
147 "movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
148 "movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
156 #define STORE(dst, r...) \ argument
158 switch (REG_CNT(r)) { \
161 "movdqa %%" VR0(r)", 0x00(%[DST])\n" \
162 "movdqa %%" VR1(r)", 0x10(%[DST])\n" \
163 "movdqa %%" VR2(r)", 0x20(%[DST])\n" \
164 "movdqa %%" VR3(r)", 0x30(%[DST])\n" \
169 "movdqa %%" VR0(r)", 0x00(%[DST])\n" \
170 "movdqa %%" VR1(r)", 0x10(%[DST])\n" \
186 #define _MUL2_x2(r...) \ argument
188 switch (REG_CNT(r)) { \
193 "pcmpgtb %" VR0(r)", %xmm14\n" \
194 "pcmpgtb %" VR1(r)", %xmm13\n" \
197 "paddb %" VR0(r)", %" VR0(r) "\n" \
198 "paddb %" VR1(r)", %" VR1(r) "\n" \
199 "pxor %xmm14, %" VR0(r) "\n" \
200 "pxor %xmm13, %" VR1(r)); \
207 #define MUL2(r...) \ argument
209 switch (REG_CNT(r)) { \
211 _MUL2_x2(R_01(r)); \
212 _MUL2_x2(R_23(r)); \
215 _MUL2_x2(r); \
222 #define MUL4(r...) \ argument
224 MUL2(r); \
225 MUL2(r); \
236 #define _MULx2(c, r...) \ argument
238 switch (REG_CNT(r)) { \
247 "movdqa %%" VR0(r) ", %%" _a_save "\n" \
248 "movdqa %%" VR1(r) ", %%" _b_save "\n" \
249 "psraw $0x4, %%" VR0(r) "\n" \
250 "psraw $0x4, %%" VR1(r) "\n" \
253 "pand %%" _0f ", %%" VR0(r) "\n" \
254 "pand %%" _0f ", %%" VR1(r) "\n" \
259 "pshufb %%" VR0(r) ",%%" _lt_mod_a "\n" \
260 "pshufb %%" VR1(r) ",%%" _lt_mod_b "\n" \
261 "pshufb %%" VR0(r) ",%%" _lt_clmul_a "\n" \
262 "pshufb %%" VR1(r) ",%%" _lt_clmul_b "\n" \
266 "movdqa %%" _lt_clmul_a ",%%" VR0(r) "\n" \
267 "movdqa %%" _lt_clmul_b ",%%" VR1(r) "\n" \
279 "pxor %%" _lt_mod_a ",%%" VR0(r) "\n" \
280 "pxor %%" _lt_mod_b ",%%" VR1(r) "\n" \
281 "pxor %%" _lt_clmul_a ",%%" VR0(r) "\n" \
282 "pxor %%" _lt_clmul_b ",%%" VR1(r) "\n" \
291 #define MUL(c, r...) \ argument
293 switch (REG_CNT(r)) { \
295 _MULx2(c, R_23(r)); \
296 _MULx2(c, R_01(r)); \
299 _MULx2(c, R_01(r)); \