Lines Matching refs:uint8_t
41 uint8_t spd_len; /* bytes written by manufacturer */
42 uint8_t spd_max_len; /* total available prom space */
43 uint8_t memory_type; /* e.g. SDRAM DDR = 0x07 */
44 uint8_t n_rows; /* row address bits */
45 uint8_t n_cols; /* column address bits */
46 uint8_t n_mod_rows; /* number of module rows */
47 uint8_t ls_data_width; /* e.g. 72 bits */
48 uint8_t ms_data_width;
49 uint8_t vddq_if; /* e.g. SSTL 2.5V = 0x04 */
50 uint8_t cycle_time25; /* cycle time at CAS latency 2.5 */
51 uint8_t access_time25;
52 uint8_t config; /* e.g. ECC = 0x02 */
53 uint8_t refresh; /* e.g. 7.8uS & self refresh = 0x82 */
54 uint8_t primary_width;
55 uint8_t err_chk_width;
56 uint8_t tCCD;
57 uint8_t burst_lengths; /* e.g. 2,4,8 = 0x0e */
58 uint8_t n_banks;
59 uint8_t cas_lat;
60 uint8_t cs_lat;
61 uint8_t we_lat;
62 uint8_t mod_attrs;
63 uint8_t dev_attrs;
64 uint8_t cycle_time20; /* cycle time at CAS latency 2.0 */
65 uint8_t access_time20;
66 uint8_t cycle_time15;
67 uint8_t access_time15;
68 uint8_t tRP;
69 uint8_t tRRD;
70 uint8_t tRCD;
71 uint8_t tRAS;
72 uint8_t mod_row_density;
73 uint8_t addr_ip_setup;
74 uint8_t addr_ip_hold;
75 uint8_t data_ip_setup;
76 uint8_t data_ip_hold;
77 uint8_t superset[62 - 36];
78 uint8_t spd_rev;
79 uint8_t chksum_0_62;
80 uint8_t jedec[8];
81 uint8_t manu_loc;
82 uint8_t manu_part_no[91 - 73];
83 uint8_t manu_rev_pcb;
84 uint8_t manu_rev_comp;
85 uint8_t manu_year;
86 uint8_t manu_week;
87 uint8_t asmb_serial_no[4];
88 uint8_t manu_specific[128 - 99];