Lines Matching defs:cpu_reg

422     struct cpu_reg *, struct fw_info *);
423 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
424 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
3991 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3998 bce_halt_cpu(sc, cpu_reg);
4001 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4011 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4021 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4031 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4041 offset = cpu_reg->spad_base +
4042 (fw->rodata_addr - cpu_reg->mips_view_base);
4052 REG_WR_IND(sc, cpu_reg->inst, 0);
4053 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4067 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4074 val = REG_RD_IND(sc, cpu_reg->mode);
4075 val &= ~cpu_reg->mode_value_halt;
4076 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4077 REG_WR_IND(sc, cpu_reg->mode, val);
4089 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4096 val = REG_RD_IND(sc, cpu_reg->mode);
4097 val |= cpu_reg->mode_value_halt;
4098 REG_WR_IND(sc, cpu_reg->mode, val);
4099 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4113 struct cpu_reg cpu_reg;
4117 cpu_reg.mode = BCE_RXP_CPU_MODE;
4118 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4119 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4120 cpu_reg.state = BCE_RXP_CPU_STATE;
4121 cpu_reg.state_value_clear = 0xffffff;
4122 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4123 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4124 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4125 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4126 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4127 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4128 cpu_reg.mips_view_base = 0x8000000;
4131 bce_start_cpu(sc, &cpu_reg);
4145 struct cpu_reg cpu_reg;
4150 cpu_reg.mode = BCE_RXP_CPU_MODE;
4151 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4152 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4153 cpu_reg.state = BCE_RXP_CPU_STATE;
4154 cpu_reg.state_value_clear = 0xffffff;
4155 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4156 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4157 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4158 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4159 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4160 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4161 cpu_reg.mips_view_base = 0x8000000;
4226 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4242 struct cpu_reg cpu_reg;
4247 cpu_reg.mode = BCE_TXP_CPU_MODE;
4248 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4249 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4250 cpu_reg.state = BCE_TXP_CPU_STATE;
4251 cpu_reg.state_value_clear = 0xffffff;
4252 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4253 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4254 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4255 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4256 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4257 cpu_reg.spad_base = BCE_TXP_SCRATCH;
4258 cpu_reg.mips_view_base = 0x8000000;
4323 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4324 bce_start_cpu(sc, &cpu_reg);
4338 struct cpu_reg cpu_reg;
4343 cpu_reg.mode = BCE_TPAT_CPU_MODE;
4344 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4345 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4346 cpu_reg.state = BCE_TPAT_CPU_STATE;
4347 cpu_reg.state_value_clear = 0xffffff;
4348 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4349 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4350 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4351 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4352 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4353 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4354 cpu_reg.mips_view_base = 0x8000000;
4419 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4420 bce_start_cpu(sc, &cpu_reg);
4434 struct cpu_reg cpu_reg;
4439 cpu_reg.mode = BCE_CP_CPU_MODE;
4440 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4441 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4442 cpu_reg.state = BCE_CP_CPU_STATE;
4443 cpu_reg.state_value_clear = 0xffffff;
4444 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4445 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4446 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4447 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4448 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4449 cpu_reg.spad_base = BCE_CP_SCRATCH;
4450 cpu_reg.mips_view_base = 0x8000000;
4515 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4516 bce_start_cpu(sc, &cpu_reg);
4530 struct cpu_reg cpu_reg;
4535 cpu_reg.mode = BCE_COM_CPU_MODE;
4536 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4537 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4538 cpu_reg.state = BCE_COM_CPU_STATE;
4539 cpu_reg.state_value_clear = 0xffffff;
4540 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4541 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4542 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4543 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4544 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4545 cpu_reg.spad_base = BCE_COM_SCRATCH;
4546 cpu_reg.mips_view_base = 0x8000000;
4611 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4612 bce_start_cpu(sc, &cpu_reg);