History log of /freebsd-head/sys/x86/x86/identcpu.c
Revision Date Author Comments
d897ed4bf5e2d3c101e51025f92b07171fbf3953 21-Feb-2020 kib <kib@FreeBSD.org> x86/identcpu.c whitespace cleanup.

Sponsored by: The FreeBSD Foundation
MFC after: 3 days
528641ee2bc312621a885d84127d868393d39367 21-Feb-2020 kib <kib@FreeBSD.org> print_svm_info: decode a CPUID 0x8000000a.edx bit 20.

This is SVM features word, the bit is defined in "PPR for AMD Family
17h Model 31h B0", document 55803 Rev 0.54.

N.B. GuesSpecCtl (no 't') is the spelling from the document.

Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after: 3 days
07706223ce3100937ef31d26023f5bd71eee0fb8 01-Feb-2020 dim <dim@FreeBSD.org> Merge ^/head r357368 through r357388.
495b57cd9b9ed106f33efe638f6cd5a267b40658 01-Feb-2020 cem <cem@FreeBSD.org> x86: Add/amend some power-management comments/macros

No functional change.
ce77fed4668120e77dc356abc20bcb10278f9913 28-Jan-2020 cem <cem@FreeBSD.org> x86: identcpu: Decode new Intel Structured Extended feature bits
e48969b30cb4745b9099c7cc0e4479f948222685 28-Jan-2020 cem <cem@FreeBSD.org> x86: identcpu: Decode new Zen2 AMD Feature2 bit
69f7c0ee631f179140895528cfea29e271e5186e 21-Jan-2020 kib <kib@FreeBSD.org> Add support for Hygon Dhyana Family 18h processor.

As a new x86 CPU vendor, Chengdu Haiguang IC Design Co., Ltd (Hygon)
is a joint venture between AMD and Haiguang Information Technology Co.,
Ltd., aims at providing x86 processors for China server market.

The first generation Hygon processor(Dhyana) shares most architecture
with AMD's family 17h, but with different CPU vendor ID("HygonGenuine")
and PCI vendor ID(0x1d94) and family series number 18h(Hygon negotiated
with AMD to confirm that only Hygon use family 18h).

To enable Hygon Dhyana support in FreeBSD, add new definitions
HYGON_VENDOR_ID("HygonGenuine") and X86_VENDOR_HYGON(0x1d94) to identify
Hygon Dhyana CPU.

Initialize the CPU features(topology, local APIC ext, MSI, TSC, hwpstate,
MCA, DEBUG_CTL, etc) for amd64 and i386 mode by sharing the code path of
AMD family 17h.

The changes have been applied on FreeBSD 13.0-CURRENT and tested
successfully on Hygon Dhyana processor.

References:
[1] Linux kernel patches for Hygon Dhyana, merged in 4.20:

https://git.kernel.org/tip/c9661c1e80b609cd038db7c908e061f0535804ef

[2] MSR and CPUID definition:

https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf

Submitted by: Pu Wen <puwen@hygon.cn>
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D23163
04cfdf0426f908b657821b4170d3714e786b0e08 12-Nov-2019 scottl <scottl@FreeBSD.org> Add new bit definitions for TSX, related to the TAA issue. The actual
mitigation will follow in a future commit.

Sponsored by: Intel
dfad9d3698aa397fbefc8a29711446da72d43b93 11-Nov-2019 scottl <scottl@FreeBSD.org> Add the text attribute for MDS_NO in the IA32_ARCH_CAP MSR.
4de94d53568bcfe65916f449bed753c80d532a8b 30-Oct-2019 cem <cem@FreeBSD.org> amd64: Define and decode new AMD64 feature bits

These are documented in revisions 3.32 of the public AMD64 Vol. 2 and
revision 3.28 of Vol. 3, published October and September 2019, respectively.
6487f370d24312e43cfc6e72592bfdf4035c2149 18-Oct-2019 cem <cem@FreeBSD.org> x86: Fetch and save standard CPUID leaf 6 in identcpu

Rather than a few scattered places in the tree. Organize flag names in a
contiguous region of specialreg.h.

While here, delete deprecated PCOMMIT from leaf 7.

No functional change.
7c575799c3c9dd8ea19b2493370f105677ddf5d2 14-Oct-2019 cem <cem@FreeBSD.org> x86: Use canonical spelling of MOVDIR64B feature/instruction

The former spelling probably confused MOVDIR64B with MOVDIRI64.

MOVDIR_64B is the 64-*byte* direct store instruction; MOVDIR_I64 is the
64-*bit* direct store instruction (underscores added here for clarity; they are
not part of the canonical instruction name).

No functional change.

Sponsored by: Dell EMC Isilon
0331abb6ef062b759cd0e0b7c7b3b305c8b7e57b 22-May-2019 cem <cem@FreeBSD.org> Decode and name additional x86 feature bits

These are all enumerated in Intel's ISA extension reference, 37th ed.

Sponsored by: Dell EMC Isilon
b5aa18864962affc0633e63444df6aaa59efbce9 21-May-2019 stevek <stevek@FreeBSD.org> The older detection methods (smbios.bios.vendor and smbios.system.product)
are able to determine some virtual machines, but the vm_guest variable was
still only being set to VM_GUEST_VM.

Since we do know what some of them specifically are, we can set vm_guest
appropriately.

Also, if we see the CPUID has the HV flag, but we were unable to find a
definitive vendor in the Hypervisor CPUID Information Leaf, fall back to
the older detection methods, as they may be able to determine a specific
HV type.

Add VM_GUEST_PARALLELS value to VM_GUEST for Parallels.

Approved by: cem
Differential Revision: https://reviews.freebsd.org/D20305
8b9a164441bb14ea61ac44b3fb966505b2c67e5f 19-May-2019 stevek <stevek@FreeBSD.org> Add missing setting of hv_base to the leaf that we used.
Correct setting hv_high to use regs[0], not leaf.
dd31a8ef39067d148388c965cf6a709cc3e905cc 17-May-2019 stevek <stevek@FreeBSD.org> Instead of individual conditional statements to look for each hypervisor
type, use a table to make it easier to add more in the future, if needed.

Add VirtualBox detection to the table ("VBoxVBoxVBox" is the hypervisor
vendor string to look for.) Also add VM_GUEST_VBOX to the VM_GUEST
enumeration to indicate VirtualBox.

Save the CPUID base for the hypervisor entry that we detected. Driver code
may need to know about it in order to obtain additional CPUID features.

Approved by: bryanv, jhb
Differential Revision: https://reviews.freebsd.org/D16305
ad030a4be03aba24c0be2dfc7065ecc3dc4dfd44 16-May-2019 cem <cem@FreeBSD.org> x86: Correctly identify bhyve hypervisor

Spotted after a similar report by Olivier Cochard-Labbé.

Sponsored by: Dell EMC Isilon
8f68635f8ea15068dd9b35526bbad0d2d0bb8776 15-May-2019 kib <kib@FreeBSD.org> Properly announce MD_CLEAR.

Submitted by: Petr Lampa <lampa@fit.vutbr.cz>
MFC after: 3 days
7beb5cb2e58aaed4726bc844c4f34d3fdb22dba0 12-Mar-2019 kib <kib@FreeBSD.org> Add register number, CPUID bits, and print identification for TSX
force abort errata.

Sponsored by: The FreeBSD Foundation
MFC after: 3 days
9c6508ad9d1567f761830d8a9b2f420b5964027f 05-Feb-2019 dim <dim@FreeBSD.org> Merge ^/head r343712 through r343806.
2a756b93166cec04a8dae61d725f0f1398c875e9 04-Feb-2019 kib <kib@FreeBSD.org> Update CPUID bits definitions and CPU identification based on changes
in SDM rev. 069.

Sponsored by: The FreeBSD Foundation
MFC after: 3 days
af881ec390ca378ac573d58251e8626623a6d1ed 30-Jan-2019 kib <kib@FreeBSD.org> i386: Merge PAE and non-PAE pmaps into same kernel.

Effectively all i386 kernels now have two pmaps compiled in: one
managing PAE pagetables, and another non-PAE. The implementation is
selected at cold time depending on the CPU features. The vm_paddr_t is
always 64bit now. As result, nx bit can be used on all capable CPUs.

Option PAE only affects the bus_addr_t: it is still 32bit for non-PAE
configs, for drivers compatibility. Kernel layout, esp. max kernel
address, low memory PDEs and max user address (same as trampoline
start) are now same for PAE and for non-PAE regardless of the type of
page tables used.

Non-PAE kernel (when using PAE pagetables) can handle physical memory
up to 24G now, larger memory requires re-tuning the KVA consumers and
instead the code caps the maximum at 24G. Unfortunately, a lot of
drivers do not use busdma(9) properly so by default even 4G barrier is
not easy. There are two tunables added: hw.above4g_allow and
hw.above24g_allow, the first one is kept enabled for now to evaluate
the status on HEAD, second is only for dev use.

i386 now creates three freelists if there is any memory above 4G, to
allow proper bounce pages allocation. Also, VM_KMEM_SIZE_SCALE changed
from 3 to 1.

The PAE_TABLES kernel config option is retired.

In collaboarion with: pho
Discussed with: emaste
Reviewed by: markj
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D18894
2425e5de5775eeaf6acb17c38944251ecfd0e2e4 17-Jan-2019 cem <cem@FreeBSD.org> Add definitions for AMD Spectre/Meltdown CPUID information

No functional change, aside from printing recognized bits in CPU
identification.

The bits are documented in 111006-B "Indirect Branch Control Extension"[1] and
124441 "Speculative Store Bypass Disable."[2]

Notably missing (left as future work):
* Integration with hw.spec_store_bypass_disable and hw_ssb_active flag,
which are currently Intel-specific
* Integration with hw_ibrs_active global flag, which are currently
Intel-specific
* SSB_NO integration in hw_ssb_recalculate()
* Bhyve integration (PR 235010)

[1]:
https://developer.amd.com/wp-content/resources/111006-B_AMD64TechnologyIndirectBranchControlExtenstion_WP_7-18Update_FNL.pdf

[2]:
https://developer.amd.com/wp-content/resources/124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

PR: 235010 (related, but does not fix)
MFC after: a week
3cd01680952f108ca8026e84c2fc6ebea5cca880 16-Nov-2018 kib <kib@FreeBSD.org> Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068.

SDM rev. 068 was released yesterday and it contains the description of
the MSR 0x10a IA32_ARCH_CAP. This change adds symbolic definitions for
all bits present in the document, and decode them in the CPU
identification lines printed on boot.

But also, the document defines SSB_NO as bit 4, while FreeBSD used but
2 to detect the need to work-around Speculative Store Bypass
issue. Change code to use the bit from SDM.

Similarly, the document describes bit 3 as an indicator that L1TF
issue is not present, in particular, no L1D flush is needed on
VMENTRY. We used RDCL_NO to avoid flushing, and again I changed the
code to follow new spec from SDM.

In fact my Apollo Lake machine with latest ucode shows this:
IA32_ARCH_CAPS=0x19<RDCL_NO,SKIP_L1DFL_VME,SSB_NO>

Reviewed by: bwidawsk
Sponsored by: The FreeBSD Foundation
MFC after: 3 days
Differential revision: https://reviews.freebsd.org/D18006
47d30bf79e5c48a25da1dc8cd8614a1389a36e01 12-Nov-2018 kib <kib@FreeBSD.org> Apply fix to un-cripple max cpu id on BSP earlier.

We need to know actual value for the standard extended features before
ifuncs are resolved.

Reported and tested by: madpilot
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
6fa97eaf1d34cd46dd67fc537e5bf6f671755b5f 18-Aug-2018 dim <dim@FreeBSD.org> Merge ^/head r338015 through r338025.
f8f60a2233ce11eb44ec694db5d10033ad4d0208 18-Aug-2018 kib <kib@FreeBSD.org> Print L1D FLUSH feature.

Sponsored by: The FreeBSD Foundation
MFC after: 3 days
3fe94097b6a499dd498cde778f38c5374d087136 21-May-2018 kib <kib@FreeBSD.org> Add definition for Intel Speculative Store Bypass Disable MSR bits

Security: CVE-2018-3639
Sponsored by: The FreeBSD Foundation
MFC after: 3 days
6746bdeb713c8f40dae612db002e526afe38e081 23-Mar-2018 jhb <jhb@FreeBSD.org> Add a workaround to the hypervisor detection for older versions of KVM.

Originally KVM set %eax to 0 in the cpuid leaf 0x4000000 rather than
to the highest supported leaf in the hypervisor "branch". Detect this
case and fixup the %eax value so that the hypervisor is still
detected.

Reported by: jpaetzel
Reviewed by: kib
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D14810
d03e4e760ff99689bd43e90930c3345e12a7bbd8 12-Mar-2018 avg <avg@FreeBSD.org> fix r297857, do not modify CPU extension bits under virtual machines

r297857 was meant for real hardware only.

PR: 213155
Submitted by: mainland@apeiron.net
MFC after: 1 week
9c0b8085dc4f0a1d13ed91847b1e500309ffe9ab 31-Jan-2018 kib <kib@FreeBSD.org> Do not enable PTI when IA32_ARCH_CAP_RDCL_NO bit is set.

Intel document 336996-001 claims that this will be the way to inform
about Meltdown correction.

Sponsored by: The FreeBSD Foundation
MFC after: 1 week
1cf1c6c06d2f9cc2a208d17d610064cbc621e01a 19-Jan-2018 emaste <emaste@FreeBSD.org> Enable KPTI by default on amd64 for non-AMD CPUs

Kernel Page Table Isolation (KPTI) was introduced in r328083 as a
mitigation for the 'Meltdown' vulnerability. AMD CPUs are not affected,
per https://www.amd.com/en/corporate/speculative-execution:

We believe AMD processors are not susceptible due to our use of
privilege level protections within paging architecture and no
mitigation is required.

Thus default KPTI to off for AMD CPUs, and to on for others. This may
be refined later as we obtain more specific information on the sets of
CPUs that are and are not affected.

Submitted by: Mitchell Horne
Reviewed by: cem
Relnotes: Yes
Security: CVE-2017-5754
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D13971
dcd37bb111024a9595fb6a3118dea09dc7b30f8f 14-Jan-2018 kib <kib@FreeBSD.org> Enumerate and print Intel CPU features for Speculative Execution Side
Channel Mitigations.

The definitions are taken from the document 336996-001.

Sponsored by: The FreeBSD Foundation
MFC after: 1 week
dc8d51112c9d764b95f310040aaf44e9b16a16c7 05-Jan-2018 kib <kib@FreeBSD.org> Make it possible to re-evaluate cpu_features.

Add cpuctl(4) ioctl CPUCTL_EVAL_CPU_FEATURES which forces re-read of
cpu_features, cpu_features2, cpu_stdext_features, and
std_stdext_features2.

The intent is to allow the kernel to see the changes in the CPU
features after micocode update. Of course, the update is not atomic
across variables and not synchronized with readers. See the man page
warning as well.

Reviewed by: imp (previous version), jilles
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D13770
6e13a02f219687e0de5961739bf818615c099d21 23-Dec-2017 kib <kib@FreeBSD.org> Add missed AVX512VL (128 and 256 bit vector length) extension
identification bit.

Sponsored by: The FreeBSD Foundation
MFC after: 3 days
b6dd74d7468769644d16c0bf6e1b3d3490310117 20-Sep-2017 cem <cem@FreeBSD.org> x86: Decode AMD "Extended Feature Extensions ID EBX" bits

In particular, this determines CPU support for the CLZERO instruction.

(No, I am not making this name up.)

Sponsored by: Dell EMC Isilon
42d7ded2213342774c9d69e0f26e71e69bddfb88 11-Sep-2017 cem <cem@FreeBSD.org> Decode new AMD SVM feature bits on family 17h

Sponsored by: Dell EMC Isilon
7b788c73488cb9ad2c2fbe1bef84630369e2ae9a 07-Sep-2017 cem <cem@FreeBSD.org> Store AMD RAS Capabilities cpuid value and name flags

Reviewed by: truckman
Sponsored by: Dell EMC Isilon
Differential Revision: https://reviews.freebsd.org/D12237
9180786e2c9977e1f883ccf964d55cb04aac0d68 24-Aug-2017 kib <kib@FreeBSD.org> Stop masking FSGSBASE and SMEP features under monitors.

Not enabling FSGSBASE in %cr4 does not prevent reporting of the
feature by the CPUID instruction (blame Int*l). As result, kernels
which were run under monitors pretended that usermode cannot modify
TLS base without the syscall, while libc noted right combination of
capable CPU and the new kernel version, trying to use the WRFSBASE
instruction.

Really old hypervisors that cannot handle enablement of these features
in %cr4 would require the manual configuration, by setting the loader
tunable hw.cpu_stdext_disable=0x81

Reported by: lwhsu, mjoras
Sponsored by: The FreeBSD Foundation
MFC after: 18 days
d871b34dbc932b6cf3cacfeb75e1bcceb0178926 09-Aug-2017 jkim <jkim@FreeBSD.org> Split identify_cpu() into two functions for amd64 as we do for i386. This
reduces diff between amd64 and i386. Also, it fixes a regression introduced
in r322076, i.e., identify_hypervisor() failed to identify some hypervisors.
This function assumes cpu_feature2 is already initialized.

Reported by: dexuan
Tested by: dexuan
0ac013123c784b8eca14bdaf2df688d9a595ebce 05-Aug-2017 jkim <jkim@FreeBSD.org> Detect hypervisors early. We used to set lower hz on hypervisors by default
but it was broken since r273800 (and r278522, its MFC to stable/10) because
identify_cpu() is called too late, i.e., after init_param1().

MFC after: 3 days
f12ef95704c0c172d9727b28059ad71858d416a5 08-Jun-2017 araujo <araujo@FreeBSD.org> Allow sysctl kern.vm_guest to return bhyve when running under bhyve.

Submitted by: Sean Fagan <sef@ixsystems.com>
Reviewed by: grehan
MFH: 4 weeks.
Sponsored by: iXsystems, Inc.
Differential Revision: https://reviews.freebsd.org/D11090
764f1c4cbe63b00c8a8719c0768fa64e98774b65 30-May-2017 dim <dim@FreeBSD.org> Merge ^/head r319165 through r319250.
fc233047aa921d2de3fc420b8ba212c73884352b 30-May-2017 avg <avg@FreeBSD.org> fix indentation

MFC after: 4 days
25c44aef1e4c5c173808a96d2cf4d6a69afd3cac 16-Mar-2017 grehan <grehan@FreeBSD.org> Add the AMD MONITORX/MWAITX feature definition introduced in
Bulldozer/Ryzen CPUs.

Reviewed by: kib
MFC after: 1 week
5cb41cd56e8e63d4d4d010cbb199dec18bb5568c 03-Feb-2017 kib <kib@FreeBSD.org> For i386, remove config options CPU_DISABLE_CMPXCHG, CPU_DISABLE_SSE
and device npx.

This means that FPU is always initialized and handled when available,
and SSE+ register file and exception are handled when available. This
makes the kernel FPU code much easier to maintain by the cost of
slight bloat for CPUs older than 25 years.

CPU_DISABLE_CMPXCHG outlived its usefulness, see the removed comment
explaining the original purpose.

Suggested by and discussed with: bde
Tested by: pho
Sponsored by: The FreeBSD Foundation
MFC after: 3 weeks
8f6db7095f6a7affc6a0b986117993e4965b49ee 19-Oct-2016 mjg <mjg@FreeBSD.org> Mark a bunch of mpsafe sysctls as such.

This gives me a sysctl Giant-free buildworld.
bc4a38459791f5d601f44dae196b1ec6323e85ef 15-Sep-2016 jhb <jhb@FreeBSD.org> Remove 'cpu' and 'cpu_class' on amd64.

The 'cpu' and 'cpu_class' variables were always set to the same value
on amd64 and are legacy holdovers from i386. Remove them entirely on
amd64.

Reviewed by: imp, kib (older version)
Differential Revision: https://reviews.freebsd.org/D7888
8628e8e91075a172055f3ae854d7f73481dd9d02 15-Sep-2016 kib <kib@FreeBSD.org> MFC r305744:
Fix typo in comment.
50c016ebe9c3f6e5a5226d4ff9eea701c99c9487 12-Sep-2016 kib <kib@FreeBSD.org> Fix typo in comment.

MFC after: 3 days
5908cb719ea51af7bed9d54bf3122c9d81e8ebc1 13-Jul-2016 badger <badger@FreeBSD.org> Add explicit detection of KVM hypervisor

Set vm_guest to a new enum value (VM_GUEST_KVM) when kvm is detected and use
vm_guest in conditionals testing for KVM.

Also, fix a conditional checking if we're running in a VM which caught only
the generic VM case, but not more specific VMs (KVM, VMWare, etc.). (Spotted
by: vangyzen).

Differential revision: https://reviews.freebsd.org/D7172
Sponsored by: Dell Inc.
Approved by: kib (mentor), vangyzen (mentor)
Reviewed by: alc
MFC after: 4 weeks
00d578928eca75be320b36d37543a7e2a4f9fbdb 27-May-2016 grehan <grehan@FreeBSD.org> Create branch for bhyve graphics import.
ecc2c61c9002a9159aba3f4c8215b793d08b91a4 04-May-2016 avg <avg@FreeBSD.org> MFC r297857: re-enable AMD Topology extension on certain models if
disabled by BIOS
c82ec6211c20f1a8235d1eb37d69e925f5040a13 23-Apr-2016 kib <kib@FreeBSD.org> MFC r298101:
Add x86 CPU features definitions published in the Intel SDM rev. 58.
be4082c832ab3e8ed4b2d4877eb549a54174bf85 19-Apr-2016 pfg <pfg@FreeBSD.org> X86: use our nitems() macro when it is avaliable through param.h.

No functional change, only trivial cases are done in this sweep,

Discussed in: freebsd-current
248c6f5874c29f723c33a5dfbd60e2f97f89edbc 16-Apr-2016 gjb <gjb@FreeBSD.org> MFH

This is the final merge from ^/head before merging this branch
back to head. It's time.

Sponsored by: The FreeBSD Foundation
cde0a91a263ab018c1610d04a0e965bb0ec08245 16-Apr-2016 kib <kib@FreeBSD.org> Add x86 CPU features definitions published in the Intel SDM rev. 58.

Sponsored by: The FreeBSD Foundation
MFC after: 1 week
2d6ac6ea572ca93a1ff4e32936214246cc9b2551 12-Apr-2016 gjb <gjb@FreeBSD.org> MFH

Sponsored by: The FreeBSD Foundation
f7d20d373434d068dcb6a6c509c1658cf683c026 12-Apr-2016 avg <avg@FreeBSD.org> re-enable AMD Topology extension on certain models if disabled by BIOS

Some BIOSes disable AMD Topology extension on AMD Family 15h notebook
processors. We re-enable the extension, so that we can properly discover
core and cache topology. Linux seems to do the same.

Reported by: Johannes Dieterich <dieterich.joh@gmail.com>
Reviewed by: jhb, kib
Tested by: Johannes Dieterich <dieterich.joh@gmail.com>
(earlier version)
MFC after: 3 weeks
Differential Revision: https://reviews.freebsd.org/D5883
427bb5d10fd29ef038c6a4f6df3160e9c77f1b24 19-Feb-2016 sephe <sephe@FreeBSD.org> MFC [Hyper-V]: r293719-r293722, r293869-r293871, r293873-r293875, r293877

r293719 hyperv/hn: Implement LRO
r293720 hyperv/hn: Implement SIOC[SG]IFMEDIA support
r293721 hyperv/hn: Avoid mbuf cluster allocation, if the packet is small.
r293722 hyperv/hn: Removed unused netvsc_init()
r293869 hyperv/hn: Unbreak LINT-NOIP
r293870 hyperv: use x86 generic code to do the hypervisor detection
r293871 hyperv: remove unused vmbus definitions
r293873 hyperv: implement an event timer
r293874 hyperv: add interrupt counters
r293875 hyperv: set receive buffer size according to NVSP protocol version
r293877 Unbreak `make depend` with sys/modules/hyperv/vmbus after r293870

Approved by: re (glebius), adrian (mentor)
Sponsored by: Microsoft OSTC
a3d3d84a95935e2c2fc259d5d825bd0768f8f2ef 14-Jan-2016 sephe <sephe@FreeBSD.org> hyperv: use x86 generic code to do the hypervisor detection

This is first step to move the generic part of HV code into kernel instead
of module, so that it is possible to use hypercall to implement some other
paravirtualization code in the kernel.

Submitted by: Howard Su <howard0su@gmail.com>
Reviewed by: royger, delphij, adrian
Approved by: adrian (mentor)
Sponsored by: Microsoft OSTC
Differential Revision: https://reviews.freebsd.org/D3072
2586c96893c94ddbe9ba0492eeda316f75ce4787 05-Jan-2016 kib <kib@FreeBSD.org> MFC r292890:
Add standard extended feature bit 6 from the Intel SDM rev. 57.
65cfa1c59dc578a57326c37542b1993012394bbb 29-Dec-2015 kib <kib@FreeBSD.org> Add standard extended feature bit 6 from the Intel SDM rev. 57, which
indicates that data-pointer in the saved x87 FPU state is only updated
on FPU exceptions.

Sponsored by: The FreeBSD Foundation
MFC after: 1 week
994c23f093ffc787a9df3aed34ac0192fd33b5cf 23-Dec-2015 jhb <jhb@FreeBSD.org> Move shared variables from {amd64,i386}/initcpu.c to x86/identcpu.c.
While here, move the common bits of <machine/cputypes.h> to
<x86/cputypes.h> as well.

Reviewed by: kib
Differential Revision: https://reviews.freebsd.org/D4670
9f113227f5e356d80ceea0bb026ef79e35279be1 20-Dec-2015 cem <cem@FreeBSD.org> x86: Detect feature flags "AVX512DQ", "AVX512IFMA", "AVX512BW", "AVX512VBMI"

Documented in Intel Architecture Set Extensions Programming Reference
(319433-023).

Sponsored by: EMC / Isilon Storage Division
37870ca8990e65ac8c52d7c7f4332d0b9e086f22 19-Dec-2015 cem <cem@FreeBSD.org> x86: Detect feature flags "CLWB" and "PCOMMIT"

"The availability of CLWB instruction is indicated by the presence of
the CPUID feature flag CLWB (bit 24 of the EBX register)."

CLWB is similar to CLFLUSHOPT, except that it is not required to discard
cacheline contents.

"On processors that supports PCOMMIT, PCOMMIT is enumerated through
CPUID (CPUID.7.0.EBX[22]) only when the feature is enabled by BIOS."

PCOMMIT is used to cause store-to-memory operations to become persistent
(protected from power failure).

Sponsored by: EMC / Isilon Storage Division
bb31d1f6dfdf60990144e6c0d90be5bd221cea69 27-Nov-2015 kib <kib@FreeBSD.org> MFC r291266:
Correct the number of DTLB entries reported for the CPUID Leaf 2
descriptor 0x6c.
e727053ab246b24cbcbdf3ceada2a0037ce79f54 24-Nov-2015 kib <kib@FreeBSD.org> Correct the number of DTLB entries reported for the CPUID Leaf 2
descriptor 0x6c.

Confirmed by: Intel
MFC after: 3 days
1d3471fc07a28d67df7856d05c0510a0b3ba8692 30-Oct-2015 kib <kib@FreeBSD.org> MFC r289823:
Decode new values for CPUID leaf 2 cache and TLB descriptors, from the
Intel SDM revision 56.
89907eb85ed4dd71ebc419a28a2bbff1690445da 23-Oct-2015 kib <kib@FreeBSD.org> Decode new values for CPUID leaf 2 cache and TLB descriptors, from the
Intel SDM revision 56.

Sponsored by: The FreeBSD Foundation
MFC after: 1 week
c3f28072a721507c668befdc47e94d5760893be5 04-Sep-2015 sbruno <sbruno@FreeBSD.org> MFC r276834

Update Features2 to display SDBG capability of processor. This is
showing up on Haswell-class CPUs

From the Intel SDM, "Table 3-20. Feature Information Returned in the
ECX Register"

11 | SDBG | A value of 1 indicates the processor supports
IA32_DEBUG_INTERFACE MSR for silicon debug.

Submitted by: jiashiun@gmail.com
70c41a2cb18dc2517295e70fd25b8fe5cbadcd4c 17-Aug-2015 kib <kib@FreeBSD.org> MFC r286228:
Clear the IA32_MISC_ENABLE MSR bit on APs.
b31c115daa6de83fc575d484bbd4f7114d62b234 03-Aug-2015 kib <kib@FreeBSD.org> Clear the IA32_MISC_ENABLE MSR bit, which limits the max CPUID
reported, on APs. We already did this on BSP.

Otherwise, the userspace software which depends on the features
reported by the high CPUID levels is misbehaving. In particular, AVX
detection is non-functional, depending on which CPU thread happens to
execute when doing CPUID. Another victim is the libthr signal
handlers interposer, which needs to save full FPU extended state.

Reported and tested by: Andre Meiser <ortadur@web.de>
Sponsored by: The FreeBSD Foundation
MFC after: 2 weeks
f014bfc33c51a646ad445d66106a905fa8293821 13-Jun-2015 kib <kib@FreeBSD.org> MFC r284104:
Updates from SDM rev. 55.
a1956e48c3811bb495369ba6221ef4d0930a78ef 06-Jun-2015 kib <kib@FreeBSD.org> Update print_INTEL_TLB() by the tag values from the Intel SDM
rev. 55. The modern CPUs cache and TLB descriptions looked quite
questionable without the update, e.g. Haswell i7 4770S reported:
Data TLB: 4 KB pages, 4-way set associative, 64 entries
L2 cache: 256 kbytes, 8-way associative, 64 bytes/line
After the update, the report is:
Data TLB: 1 GByte pages, 4-way set associative, 4 entries
Data TLB: 4 KB pages, 4-way set associative, 64 entries
Instruction TLB: 2M/4M pages, fully associative, 8 entries
Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
64-Byte prefetching
Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
L2 cache: 256 kbytes, 8-way associative, 64 bytes/line
Some tags were apparently removed from the table 3-21, Vol. 2A. Keep
them around, but add a comment stating the removal.

Update the format line for cpu_stdext_feature according to the bits
from the SDM rev.55. It appears that Haswells do not store %cs and
%ds values in the FPU save area.

Store content of the %ecx register from the CPUID leaf 0x7
subleaf 0 as cpu_stdext_feature2 and print defined bits from it,
again acording to SDM rev. 55.

Sponsored by: The FreeBSD Foundation
MFC after: 1 week
9c4c8b62fb9ee054b5166366915f1eb29e777c1e 30-Apr-2015 jhb <jhb@FreeBSD.org> Remove support for Xen PV domU kernels. Support for HVM domU kernels
remains. Xen is planning to phase out support for PV upstream since it
is harder to maintain and has more overhead. Modern x86 CPUs include
virtualization extensions that support HVM guests instead of PV guests.
In addition, the PV code was i386 only and not as well maintained recently
as the HVM code.
- Remove the i386-only NATIVE option that was used to disable certain
components for PV kernels. These components are now standard as they
are on amd64.
- Remove !XENHVM bits from PV drivers.
- Remove various shims required for XEN (e.g. PT_UPDATES_FLUSH, LOAD_CR3,
etc.)
- Remove duplicate copy of <xen/features.h>.
- Remove unused, i386-only xenstored.h.

Differential Revision: https://reviews.freebsd.org/D2362
Reviewed by: royger
Tested by: royger (i386/amd64 HVM domU and amd64 PVH dom0)
Relnotes: yes
9809511c44729704d6f683faf47bd9a7f506b8dc 10-Feb-2015 jhb <jhb@FreeBSD.org> MFC 273800:
Rework virtual machine hypervisor detection.
- Move the existing code to x86/x86/identcpu.c since it is x86-specific.
- If the CPUID2_HV flag is set, assume a hypervisor is present and query
the 0x40000000 leaf to determine the hypervisor vendor ID. Export the
vendor ID and the highest supported hypervisor CPUID leaf via
hv_vendor[] and hv_high variables, respectively. The hv_vendor[]
array is also exported via the hw.hv_vendor sysctl.
- Merge the VMWare detection code from tsc.c into the new probe in
identcpu.c. Add a VM_GUEST_VMWARE to identify vmware and use that in
the TSC code to identify VMWare.
da566e85be96a2ed618e86f2a0e67a61a8e61eef 19-Jan-2015 kib <kib@FreeBSD.org> MFC r277047:
For x86, read MAXPHYADDR into variable cpu_maxphyaddr.
11969484c857cbee84a402ce4109ef7ac3f1a2b5 12-Jan-2015 kib <kib@FreeBSD.org> For x86, read MAXPHYADDR, defined in SDM vol 3 4.1.4 Enumeration of Paging
Features by CPUID as CPUID.80000008H:EAX[7:0], into variable cpu_maxphyaddr.

Reviewed by: alc
Tested by: pho
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
8d4db71d65990fa9bdb3f2dcfa4e6fe820dbbdc0 08-Jan-2015 sbruno <sbruno@FreeBSD.org> Update Features2 to display SDBG capability of processor. This is
showing up on Haswell-class CPUs

From the Intel SDM, "Table 3-20. Feature Information Returned in the
ECX Register"

11 | SDBG | A value of 1 indicates the processor supports
IA32_DEBUG_INTERFACE MSR for silicon debug.

Submitted by: jiashiun@gmail.com
Reviewed by: jhb neel
MFC after: 2 weeks
649535f73cbb860495bc6d26c156d95935fcb6fd 31-Dec-2014 neel <neel@FreeBSD.org> MFC r273748

Output a summary of optional SVM features in dmesg similar to CPU features.
If bootverbose is enabled, a detailed list is provided; otherwise, a
single-line summary is displayed.

Requested by: jhb
5a03dd693d913ad7976ea26432589000f96f3dba 23-Dec-2014 kib <kib@FreeBSD.org> MFC r271197:
Add more bits for the XSAVE features from CPUID 0xd, sub-function 1
%eax report. Print the XSAVE features 0xd/1 in the boot banner.
71f9e38fa2d4dc13b36ced356445eea08f620127 22-Dec-2014 jhb <jhb@FreeBSD.org> MFC 271405,271408,271409,272658:
MFamd64: Use initializecpu() to set various model-specific registers on
AP startup and AP resume (it was already used for BSP startup and BSP
resume).
2b345a08edde7a77b1eccf22395f90aec2d3adac 22-Dec-2014 jhb <jhb@FreeBSD.org> MFC 260557,271076,271077,271082,271083,271098:
- Remove spaces from boot messages when we print the CPU ID/Family/Stepping
- Move prototypes for various functions into out of C files and into
<machine/md_var.h>.
- Reduce diffs between i386 and amd64 initcpu.c and identcpu.c files.
- Move blacklists of broken TSCs out of the printcpuinfo() function
and into the TSC probe routine.
- Merge the amd64 and i386 identcpu.c into a single x86 implementation.
d47eb7d2d46dabce3135bac7e98b771b40aff97d 28-Oct-2014 jhb <jhb@FreeBSD.org> Rework virtual machine hypervisor detection.
- Move the existing code to x86/x86/identcpu.c since it is x86-specific.
- If the CPUID2_HV flag is set, assume a hypervisor is present and query
the 0x40000000 leaf to determine the hypervisor vendor ID. Export the
vendor ID and the highest supported hypervisor CPUID leaf via
hv_vendor[] and hv_high variables, respectively. The hv_vendor[]
array is also exported via the hw.hv_vendor sysctl.
- Merge the VMWare detection code from tsc.c into the new probe in
identcpu.c. Add a VM_GUEST_VMWARE to identify vmware and use that in
the TSC code to identify VMWare.

Differential Revision: https://reviews.freebsd.org/D1010
Reviewed by: delphij, jkim, neel
1d26d798b2888e5e85d9d217862ee52530e514b4 27-Oct-2014 grehan <grehan@FreeBSD.org> Output a summary of optional SVM features in dmesg similar to CPU features.
If bootverbose is enabled, a detailed list is provided; otherwise, a
single-line summary is displayed.

Differential Revision: https://reviews.freebsd.org/D1008
Reviewed by: jhb, neel
MFC after: 1 week
2a48d5d52cd7eacbb9683744ec992a32832338ac 10-Sep-2014 jhb <jhb@FreeBSD.org> Move code to set various MSRs on AMD cpus out of printcpuinfo() and
into initalizecpu() instead.
51e3f3be5cd199bd551479feb6065cb920c185c4 06-Sep-2014 kib <kib@FreeBSD.org> Add more bits for the XSAVE features from CPUID 0xd, sub-function 1
%eax report.

Print the XSAVE features 0xd/1 in the boot banner. The printcpuinfo()
is executed late enough so that XSAVE is already enabled.

There is no known to me off the shelf hardware that implements any
feature bits except XSAVEOPT, the list is taken from SDM rev. 50. The
banner printing will allow us to note the hardware arrival.

Sponsored by: The FreeBSD Foundation
MFC after: 1 week
f7c94cc49724c1fba2f76fa87cc4c8363305e7ec 04-Sep-2014 jhb <jhb@FreeBSD.org> Merge the amd64 and i386 identcpu.c into a single x86 implementation.
This brings the structured extended features mask and VT-x reporting to
i386 and Intel cache and TLB info (under bootverbose) to amd64.