History log of /freebsd-head/sys/mips/include/asm.h
Revision Date Author Comments
d4fdf34d06e6e1fc20653c043d34537b5f7ff658 31-Jan-2018 jhb <jhb@FreeBSD.org> Consistently use 16-byte alignment for MIPS N32 and N64.

- Add a new <machine/abi.h> header to hold constants shared between C
and assembly such as CALLFRAME_SZ.
- Add a new STACK_ALIGN constant to <machine/abi.h> and use it to
replace hardcoded constants in the kernel and makecontext(). As a
result of this, ensure the stack pointer on N32 and N64 is 16-byte
aligned for N32 and N64 after exec(), after pthread_create(), and
when sending signals rather than 8-byte aligned.

Reviewed by: jmallett
Sponsored by: DARPA / AFRL
Differential Revision: https://reviews.freebsd.org/D13875
4736ccfd9c3411d50371d7f21f9450a47c19047e 20-Nov-2017 pfg <pfg@FreeBSD.org> sys: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 3-Clause license.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.
7e6cabd06e6caa6a02eeb86308dc0cb3f27e10da 28-Feb-2017 imp <imp@FreeBSD.org> Renumber copyright clause 4

Renumber cluase 4 to 3, per what everybody else did when BSD granted
them permission to remove clause 3. My insistance on keeping the same
numbering for legal reasons is too pedantic, so give up on that point.

Submitted by: Jan Schaumann <jschauma@stevens.edu>
Pull Request: https://github.com/freebsd/freebsd/pull/96
00d578928eca75be320b36d37543a7e2a4f9fbdb 27-May-2016 grehan <grehan@FreeBSD.org> Create branch for bhyve graphics import.
4fbe101595e65ea3b679a3d18bf897d5ac7038a7 02-Feb-2016 adrian <adrian@FreeBSD.org> Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx options

This revision does the following renames:
CPU_MIPS24KC -> CPU_MIPS24K
CPU_MIPS74KC -> CPU_MIPS74K
CPU_MIPS1004KC -> CPU_MIPS1004K

It also adds the following new CPU_MIPSxxx options:
CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV

CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the
MIPSxxxxK CPU has no FPU.
It would be better if the CPUs are named after their standard functionalities
only and the presence or absence of FPU can then be controlled via the
CPU_HAVEFPU option.

I will send out another dependent revision that moves MIPS 32 r2 and r3
CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP.

Submitted by: Stanislav Galabov <sgalabov@gmail.com>
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D5077
7481d4e82bfe476abd07fb792c0dd88364e99c35 28-Jan-2016 brooks <brooks@FreeBSD.org> MFC r294463:

Shift saved floating point registers up in jmp_buf.

sigmask_t is 128-bits so requires two slots.

Obtained from: CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc)
Sponsored by: DARPA, AFRL
e86fa364ca07e2714edcfb3790ae4ea2b1d460c9 20-Jan-2016 brooks <brooks@FreeBSD.org> Shift saved floating point registers up in jmp_buf.

sigmask_t is 128-bits so requires two slots.

Approved by: CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc)
MFC after: 1 week
Sponsored by: DARPA, AFRL
f4cd08de015fb504a60c3d1153891bd9390ed9d5 22-Jan-2015 brooks <brooks@FreeBSD.org> MFC r274816:

Add FPU support for MIPS setjmp(3)/longjmp(3).

This change saves/restores the callee-saved MIPS floating point
registers as documented by the o32/n32/n64 spec ("MIPSpro N32
ABI Handbook", Table 2-1) for the _setjmp(3), _longjmp(3),
setjmp(3) and longjmp(3) C library functions. This is only
included when the C library is built with hardware floating point
support (or when "SOFTFLOAT" is not defined).

Submitted by: sson
Sponsored by: DARPA, AFRL
b532057d45360838a1a3c71ee77b32fec6d971ba 21-Nov-2014 brooks <brooks@FreeBSD.org> Add FPU support for MIPS setjmp(3)/longjmp(3).

This change saves/restores the callee-saved MIPS floating point
registers as documented by the o32/n32/n64 spec ("MIPSpro N32
ABI Handbook", Table 2-1) for the _setjmp(3), _longjmp(3),
setjmp(3) and longjmp(3) C library functions. This is only
included when the C library is built with hardware floating point
support (or when "SOFTFLOAT" is not defined).

Submitted by: sson
MFC after: 1 month
Sponsored by: DARPA, AFRL
eb1a5f8de9f7ea602c373a710f531abbf81141c4 21-Feb-2014 gjb <gjb@FreeBSD.org> Move ^/user/gjb/hacking/release-embedded up one directory, and remove
^/user/gjb/hacking since this is likely to be merged to head/ soon.

Sponsored by: The FreeBSD Foundation
6b01bbf146ab195243a8e7d43bb11f8835c76af8 27-Dec-2013 gjb <gjb@FreeBSD.org> Copy head@r259933 -> user/gjb/hacking/release-embedded for initial
inclusion of (at least) arm builds with the release.

Sponsored by: The FreeBSD Foundation
296c494bdcbf3b8bbab2e0086c2fc5173240381b 15-Oct-2013 imp <imp@FreeBSD.org> Elminate NON_LEAF and use NESTED instead to unify our assembler
conventions.

Reviewed by: jmallet@
87b5f4698db491ac96ca095442d3efa95f6c87ed 15-Oct-2013 imp <imp@FreeBSD.org> Replace NLEAF with LEAF_NOPROFILE to unify the conventions we use in
our assembler files.

Reviewed by: jmallet@
0dd44faac75fb50d838778c538dcf8481d8bb398 15-Oct-2013 imp <imp@FreeBSD.org> Replace uses of the ALEAF macro with XLEAF and remove ALEAF macro to
try to unify the conventions used in our assembler.

Reviewed by: jmallet@
9a9fbbc1d012aaf3fc62d282c5dbe4915c8dbd86 15-Oct-2013 imp <imp@FreeBSD.org> Move DO_AST into pcb.h where it should have been all along. Move some
common macros for saving/restoring registers into pcb.h as well.
910e40a469b76eb7a0a7ab826835835a8e753047 09-Oct-2013 markm <markm@FreeBSD.org> MFC - tracking commit
2d83a106ef6be8c710efe1d9b7af3cd23e360ce6 09-Oct-2013 adrian <adrian@FreeBSD.org> Add "better" MIPS24k and MIPS74k barriers.

* the mips74k cores only need EHB (which is 'sll $0, $0, 3')
here; NOPs don't actually work.

* add EHB as the last NOP for the default barriers/hazards;
that is "better" behaviour and should work on a wider
variety of processors.

This allows the existing (icky) TLB code to work, allowing
the AR9344 SoC (mips74k) to actually get through kernel startup.

Tested:

* AR9344 SoC - (mips74k)
* AR9331 SoC - (mips24k)

TODO:

* test on mips4k CPUs, just to be sure.

* document that sll $0, $0, 3 is actually "EHB" and that it
falls back to being a NOP for pre-mips32r1.

* mips24k has an errata that we currently don't correctly explicitly
state - ie, that after DERET/ERET, the only valid instruction is
a NOP.

Reviewed by: imp@
Approved by: re@ (gjb)
9003746e9a613b1a0ca653027e0f881f52cd7027 01-May-2013 imp <imp@FreeBSD.org> Don't include asm.h in non-asm files.
Remove #define to get kludges that asm.h used to define
Move clever macros to access assembler instructions to trap.c
Remove __ASSEMBLER__ ifdefs in regdef.h: they aren't needed anymore.
ac880fa7c8eba95d2effa0a42b7c88775cdfe804 06-Mar-2012 jmallett <jmallett@FreeBSD.org> At the risk of reducing source compatibility with old NetBSD and Sprite:
o) Get rid of some unused macros related to features we don't intend to
provide.
o) Get rid of macro definitions for MIPS-I CPUs. We are not likely to
support anything that predartes MIPS-III.
o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being
used already.
o) Eliminate a duplicate and mostly-unused set of exception vector macros.

There's still considerable duplication and lots more obsolete in our headers,
but this reduces one of the larger files to a size where one could reckon
about the correctness of its contents with a mere few hours of contemplation.

There is, of course, a question of whether we need definitions for fields,
registers and configurations that we are unlikely to ever use or implement,
even if they're not obsolete since 1991. FreeBSD is not a processor
reference manual, and things that aren't used may be wrong, or may be
duplicated because nobody could possibly actually know whether they're
already defined.
ed098cf42083c6e4b4760129a932b9d19cf35a7e 18-Nov-2011 jchandra <jchandra@FreeBSD.org> Fix COP0 hazards for XLR and XLP

The XLR CPUs do not have any software visible hazards for COP0 operations.
On XLP the hazard is a ehb, since it is mips64r2.
09f9c897d33c41618ada06fbbcf1a9b3812dee53 19-Oct-2010 jamie <jamie@FreeBSD.org> A new jail(8) with a configuration file, to replace the work currently done
by /etc/rc.d/jail.
4b1b0132725cfd6fe5550c506752c4786797f311 16-Jul-2010 imp <imp@FreeBSD.org> Move common macros into asm.h. Replace MIPS_CPU_NOP_DELAY with
HAZARD_DELAY. Move HAZARD_DELAY and ITLBNOPFIX into asm.h, for
possible later optimization...

Reviewed by: jmallet, jchandra
a8f59ebcd27849df11e25d33f4832201d25f7808 24-Jun-2010 jchandra <jchandra@FreeBSD.org> Merge jmallett@'s n64 work into HEAD - changeset 7

Initial support for n32 and n64 ABIs from
http://svn.freebsd.org/base/user/jmallett/octeon

Changes are:
- syscall, exception and trap support for n32/n64 ABIs
- 64-bit address space defines
- _jmp_buf for n32/n64
- casts between registers and ptr/int updated to work on n32/n64

Approved by: rrs(mentor), jmallett
8b66012ecb8cc5ea8d8f0090d80875243b574826 25-May-2010 neel <neel@FreeBSD.org> Get rid of empty and unused KSEG0TEXT macros.
5605409291ac3900f8567c14cd145a54e8d40d4c 17-Apr-2010 jmallett <jmallett@FreeBSD.org> o) Use inline functions to access coprocessor 0 registers rather than external
ones implemented using assembly.
o) Use TRAPF_USERMODE() consistently rather than USERMODE(). Eliminate
<machine/psl.h> as a result.
o) Use intr_*() rather than *intr(), consistently.
o) Use register_t instead of u_int in some trap code.
o) Merge some more endian-related macros to machine/asm.h from NetBSD.
o) Add PTR_LI macro, which loads an address with the correct sign-extension for
a pointer.
o) Restore interrupts when bailing out due to an excessive IRQ in
nexus_setup_intr().
o) Remove unused functions from psraccess.S.
o) Enter temporary virtual entries for large memory access into the page tables
rather than simply hoping they stay resident in the TLB and we don't need to
do a refill for them.
o) Abstract out large memory mapping setup/teardown using some macros.
o) Do mips_dcache_wbinv_range() when using temporary virtual addresses just
like we do when we can use the direct map.
f1216d1f0ade038907195fc114b7e630623b402c 19-Mar-2010 delphij <delphij@FreeBSD.org> Create a custom branch where I will be able to do the merge.
090d85f3f59076a047985e5b6ecf975a1c2b4a26 02-Mar-2010 imp <imp@FreeBSD.org> Update macros for multiple ABI support from NetBSD.
Also update SZREG define in ucontext
91212ae23c60e92beb6a2bf31304fe0f44d84cee 09-Feb-2010 neel <neel@FreeBSD.org> SMP support for the mips port.

The platform that supports SMP currently is a SWARM with a dual-core Sibyte
processor. The kernel config file to use is SWARM_SMP.

Reviewed by: imp, rrs
6e3a5d426c5122a7b7d87af88b49b98148906b74 10-Jan-2010 imp <imp@FreeBSD.org> Merge from projects/mips to head by hand:

r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.

r200343 | imp | 2009-12-09 18:44:11 -0700 (Wed, 09 Dec 2009) | 4 lines
Get the sense of this right. We use uintpr_t for bus_addr_t when
we're building everything except octeon && 32-bit. As note before, we
need a clearner way, but at least now the hack is right.

r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines
Add in Cavium's CID. Report what the unknown CID is.

r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines
Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON.
Spell ld script name right.

r199599 | imp | 2009-11-20 09:32:26 -0700 (Fri, 20 Nov 2009) | 2 lines
Another kludge for 64-bit bus_addr_t with 32-bit pointers...

r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines
- Add cpu_init_interrupts function that is supposed to
prepeare stuff required for spinning out interrupts later
- Add API for managing intrcnt/intrnames arrays
- Some minor style(9) fixes

r198958 | rrs | 2009-11-05 11:15:47 -0700 (Thu, 05 Nov 2009) | 2 lines
For XLR adds extern for its bus space routines

r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)

r198666 | imp | 2009-10-29 18:37:50 -0600 (Thu, 29 Oct 2009) | 2 lines
Add some newer MIPS CO cores.

r198665 | imp | 2009-10-29 18:37:04 -0600 (Thu, 29 Oct 2009) | 4 lines
db_expr_t is really closer to a register_t.
Submitted by: bde@

r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines
- Remove bunch of declared but not defined cach-related variables
- Add mips_picache_linesize and mips_pdcache_linesize variables

r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines
Get rid of the hardcoded constants to define cacheable memory:
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE

Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.

r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines
- Commit missing part of "bt" fix: store PC register in pcb_context struct
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.

r198207 | imp | 2009-10-18 08:57:04 -0600 (Sun, 18 Oct 2009) | 2 lines
Undo spamage of last MFC.

r198206 | imp | 2009-10-18 08:56:33 -0600 (Sun, 18 Oct 2009) | 3 lines
_ALIGN has to return u_long, since pointers don't fit into u_int in
64-bit mips.

r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines
- Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe.
Context info could be obtained from other sources (see below) no only from
td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
structure as a source info for trace unwinding, but this structure
is filled only when exception occurs. Valid register values for sleeping
processes are in pcb_context array. For curthread use pc/sp/ra for current
frame

r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines
- Get rid of label_t. It came from NetBSD and was used only in one place

r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines

Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant
intr_machdep.c (which we will need for RMI) in the machine specific
directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.

r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines
- Move stack tracing function to db_trace.c
- Axe unused extern MipsXXX declarations
- Move all declarations for functions in exceptions.S/swtch.S
from trap.c to respective headers

r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines
- Sync caches properly when dealing with sf_buf

r196215 | imp | 2009-08-14 10:15:18 -0600 (Fri, 14 Aug 2009) | 6 lines
(u_int) is the wrong type here. Use unsigned long instead, even
though that's only less wrong...

r196199 | imp | 2009-08-13 13:47:13 -0600 (Thu, 13 Aug 2009) | 7 lines
Use unsigned long instead of unsigned for the integer casts here. The
former works for both ILP32 and LP64 programming models, while the
latter fails LP64.

r196089 | gonzo | 2009-08-09 19:49:59 -0600 (Sun, 09 Aug 2009) | 4 lines
- Make i/d cache size field 32-bit to prevent overflow
Submited by: Neelkanth Natu

r195582 | imp | 2009-07-10 13:07:07 -0600 (Fri, 10 Jul 2009) | 2 lines
fix prototype for MipsEmulateBranch.

r195581 | imp | 2009-07-10 13:06:43 -0600 (Fri, 10 Jul 2009) | 2 lines
Better definitions for a few types for n32/n64.

r195580 | imp | 2009-07-10 13:06:15 -0600 (Fri, 10 Jul 2009) | 5 lines
Fixed aligned macros...

r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines
- Port busdma code from FreeBSD/arm. This is more mature version
that takes into account all limitation to DMA memory (boundaries,
alignment) and implements bounce pages.
- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf

r195440 | imp | 2009-07-08 00:01:37 -0600 (Wed, 08 Jul 2009) | 2 lines
Fix atomic_store_64 prototype for 64-bit systems.

r195392 | imp | 2009-07-05 20:27:03 -0600 (Sun, 05 Jul 2009) | 3 lines
The MCOUNT macro isn't going to work in 64-bit mode. Add a note to
this effect.

r195391 | imp | 2009-07-05 20:22:51 -0600 (Sun, 05 Jul 2009) | 3 lines
Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32... Use PTR_ADDU in DO_AST macro.

r195390 | imp | 2009-07-05 20:22:06 -0600 (Sun, 05 Jul 2009) | 4 lines
Change the addu here to daddu.
addu paranoina prodded by: jmallet@

r195382 | imp | 2009-07-05 15:16:26 -0600 (Sun, 05 Jul 2009) | 5 lines
addu and subu are special. We need to use daddu and dsubu here to get
proper behavior.
Submitted by: jmallet@

r195370 | imp | 2009-07-05 09:20:16 -0600 (Sun, 05 Jul 2009) | 6 lines
The SB1 has cohernet memory, so add it.
Also, Maxmem is better as a long.
Submitted by: Neelkanth Natu

r195369 | imp | 2009-07-05 09:19:28 -0600 (Sun, 05 Jul 2009) | 4 lines
The SB1 needs a special value for the cache field of the pte.
Submitted by: Neelkanth Natu

r195368 | imp | 2009-07-05 09:18:06 -0600 (Sun, 05 Jul 2009) | 2 lines
compute the areas to save registers in for 64-bit access correctly.

r195367 | imp | 2009-07-05 09:17:11 -0600 (Sun, 05 Jul 2009) | 3 lines
First cut at 64-bit types. not 100% sure these are all correct for
N32 ABI.

r195366 | imp | 2009-07-05 09:16:27 -0600 (Sun, 05 Jul 2009) | 3 lines
Trim unreferenced goo. SDRAM likely should be next, but it is still
referenced.

r195365 | imp | 2009-07-05 09:13:24 -0600 (Sun, 05 Jul 2009) | 9 lines

First cut at atomics for 64-bit machines and SMP machines.
# Note: Cavium provided a port that has atomics similar to these, but
# that does a syncw; sync; atomic; sync; syncw where we just do the classic
# mips 'atomic' operation (eg ll; frob; sc). It is unclear to me why
# the extra is needed. Since my initial target is one core, I'll defer
# investigation until I bring up multiple cores. syncw is an octeon specific
# instruction.

r195359 | imp | 2009-07-05 02:14:00 -0600 (Sun, 05 Jul 2009) | 4 lines
Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from: NetBSD

r195358 | imp | 2009-07-05 02:13:19 -0600 (Sun, 05 Jul 2009) | 4 lines
Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.

r195357 | imp | 2009-07-05 01:01:34 -0600 (Sun, 05 Jul 2009) | 2 lines
Use uintptr_t rather than unsigned here for 64-bit correctness.

r195356 | imp | 2009-07-05 01:00:51 -0600 (Sun, 05 Jul 2009) | 6 lines
Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct. While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.

r195355 | imp | 2009-07-05 00:56:51 -0600 (Sun, 05 Jul 2009) | 7 lines
(1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.
(2) include a SB1 specific coherency mapping
Submitted by: Neelkanth Nath (2)

r195352 | imp | 2009-07-05 00:44:37 -0600 (Sun, 05 Jul 2009) | 3 lines
db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.

r195351 | imp | 2009-07-05 00:43:01 -0600 (Sun, 05 Jul 2009) | 4 lines
Define COP0_SYNC for SB1 CPU.
Submitted by: Neelkanth Natu

r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines
Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places. Provide n32/n64 register name defintions. This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).
Obtained from: NetBSD (for the regdef.h changes)

r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.

r195076 | gonzo | 2009-06-26 13:54:06 -0600 (Fri, 26 Jun 2009) | 2 lines
- Add guards to ensure that these files are included only once

r194469 | gonzo | 2009-06-18 22:43:49 -0600 (Thu, 18 Jun 2009) | 16 lines
- Mark temp variable as "earlyclobber" in assembler inline in
atomic_fetchadd_32. Without it gcc would use it as input
register for v and sometimes generate following code for
function call like atomic_fetchadd_32(&(fp)->f_count, -1):
801238b4: 2402ffff li v0,-1
801238b8: c2230018 ll v1,24(s1)
801238bc: 00431021 addu v0,v0,v1
801238c0: e2220018 sc v0,24(s1)
801238c4: 1040fffc beqz v0,801238b8 <dupfdopen+0x2e8>
801238c8: 00000000 nop
Which is definitly wrong because if sc fails v0 is set to 0
and previous value of -1 is overriden hence whole operation
turns to bogus

r194164 | imp | 2009-06-14 00:14:25 -0600 (Sun, 14 Jun 2009) | 3 lines
bye bye. This is no longer referenced, but much code from it will
resurface for a bus-space implementation.

r194160 | imp | 2009-06-14 00:10:36 -0600 (Sun, 14 Jun 2009) | 3 lines
Cavium-specific goo is no longer necessary here. Of course, I now
have to write a bus space for cavium, but that shouldn't be too hard.

r194157 | imp | 2009-06-14 00:01:46 -0600 (Sun, 14 Jun 2009) | 2 lines
Move this to a more approrpiate plae.

r194156 | imp | 2009-06-13 23:29:13 -0600 (Sat, 13 Jun 2009) | 2 lines
Bring this in from the cavium port.

r193487 | gonzo | 2009-06-05 02:37:11 -0600 (Fri, 05 Jun 2009) | 2 lines
- Use restoreintr instead of enableint while accessing pcpu in DO_AST

r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
we assume that there is no FPU, because majority of SoC does
not have it.

r192817 | gonzo | 2009-05-26 10:35:05 -0600 (Tue, 26 May 2009) | 2 lines
- Add type cast for atomic_cmpset_acq_ptr arguments

r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines
- Remove now unused NetBSDism intr.h

r192177 | gonzo | 2009-05-15 20:39:13 -0600 (Fri, 15 May 2009) | 4 lines
- Add MIPS_IS_KSEG0_ADDR, MIPS_IS_KSEG1_ADDR and MIPS_IS_VALID_PTR
macroses thet check if address belongs to KSEG0, KSEG1 or both
of them respectively.

r191589 | gonzo | 2009-04-27 13:18:55 -0600 (Mon, 27 Apr 2009) | 3 lines
- Cast argument to proper type in order to avoid warnings like
"shift value is too large for given type"

r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines
- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix
and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1
- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)

r191451 | gonzo | 2009-04-23 22:17:21 -0600 (Thu, 23 Apr 2009) | 4 lines
- Define accessor functions for CP0 Config(16) register selects 1, 2, 3.
Content of these registers is defined in MIPS spec and can be used
for obtaining info about CPU capabilities.

r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
struct bus_space and update all relevant places.

r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
50e8dc140d84434db96691f363786e7a7c3725de 06-Jul-2009 imp <imp@FreeBSD.org> Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32... Use PTR_ADDU in DO_AST macro.
e3ccf4129b169f18f1c6266d39cdabaff34280ce 05-Jul-2009 imp <imp@FreeBSD.org> Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
904ea08810a7b4e2a2842957120ecae227c58bf0 05-Jun-2009 gonzo <gonzo@FreeBSD.org> - Use restoreintr instead of enableint while accessing pcpu in DO_AST
cf5320822f93810742e3d4a1ac8202db8482e633 19-Oct-2008 lulf <lulf@FreeBSD.org> - Import the HEAD csup code which is the basis for the cvsmode work.
352e51d169c4877beae82a6316142f70d0742025 13-Apr-2008 imp <imp@FreeBSD.org> FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.

This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...

Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.

In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.