opteron_pcbe.c (9b0429a1) opteron_pcbe.c (281939df)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

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61 *
62 *
63 * This open source software license conforms to the BSD License template.
64 */
65
66/*
67 * Portions Copyright 2009 Advanced Micro Devices, Inc.
68 * Copyright 2019 Joyent, Inc.
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

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61 *
62 *
63 * This open source software license conforms to the BSD License template.
64 */
65
66/*
67 * Portions Copyright 2009 Advanced Micro Devices, Inc.
68 * Copyright 2019 Joyent, Inc.
69 * Copyright 2021 Oxide Computer Company
69 */
70
71/*
72 * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors.
73 */
74
75#include <sys/cpuvar.h>
76#include <sys/param.h>

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442
443static const amd_generic_event_t family_10h_generic_events[] = {
444 AMD_cmn_generic_events,
445 AMD_FAMILY_10h_generic_events,
446 GEN_EV_END
447};
448
449/*
70 */
71
72/*
73 * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors.
74 */
75
76#include <sys/cpuvar.h>
77#include <sys/param.h>

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443
444static const amd_generic_event_t family_10h_generic_events[] = {
445 AMD_cmn_generic_events,
446 AMD_FAMILY_10h_generic_events,
447 GEN_EV_END
448};
449
450/*
450 * For Family 17h, the cpcgen utility generates all of our events including ones
451 * that need specific unit codes, therefore we leave all unit codes out of
452 * these. Zen 1 and Zen 2 have different event sets that they support.
451 * For Family 17h and Family 19h, the cpcgen utility generates all of our events
452 * including ones that need specific unit codes, therefore we leave all unit
453 * codes out of these. Zen 1, Zen 2, and Zen 3 have different event sets that
454 * they support.
453 */
454static const amd_generic_event_t family_17h_zen1_papi_events[] = {
455 { "PAPI_br_cn", "ExRetCond" },
456 { "PAPI_br_ins", "ExRetBrn" },
457 { "PAPI_fpu_idl", "FpSchedEmpty" },
458 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
459 { "PAPI_tot_ins", "ExRetInstr" },
460 { "PAPI_tlb_dm", "LsL1DTlbMiss" },

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469 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
470 { "PAPI_tot_ins", "ExRetInstr" },
471 { "PAPI_tlb_dm", "LsL1DTlbMiss" },
472 { "PAPI_tlb_im", "BpL1TlbMissL2Miss" },
473 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
474 GEN_EV_END
475};
476
455 */
456static const amd_generic_event_t family_17h_zen1_papi_events[] = {
457 { "PAPI_br_cn", "ExRetCond" },
458 { "PAPI_br_ins", "ExRetBrn" },
459 { "PAPI_fpu_idl", "FpSchedEmpty" },
460 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
461 { "PAPI_tot_ins", "ExRetInstr" },
462 { "PAPI_tlb_dm", "LsL1DTlbMiss" },

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471 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
472 { "PAPI_tot_ins", "ExRetInstr" },
473 { "PAPI_tlb_dm", "LsL1DTlbMiss" },
474 { "PAPI_tlb_im", "BpL1TlbMissL2Miss" },
475 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
476 GEN_EV_END
477};
478
479static const amd_generic_event_t family_19h_zen3_papi_events[] = {
480 { "PAPI_br_cn", "ExRetCond" },
481 { "PAPI_br_ins", "ExRetBrn" },
482 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
483 { "PAPI_tot_ins", "ExRetInstr" },
484 { "PAPI_tlb_dm", "LsL1DTlbMiss" },
485 { "PAPI_tlb_im", "BpL1TlbMissL2TlbMiss" },
486 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
487 GEN_EV_END
488};
477
489
490
491
478static char *evlist;
479static size_t evlist_sz;
480static const amd_event_t *amd_events = NULL;
481static uint_t amd_family, amd_model;
482static const amd_generic_event_t *amd_generic_events = NULL;
483
484static char amd_fam_f_rev_ae_bkdg[] = "See \"BIOS and Kernel Developer's "
485"Guide for AMD Athlon 64 and AMD Opteron Processors\" (AMD publication 26094)";

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492static char amd_fam_17h_zen1_reg[] = "See \"Open-Source Register Reference For "
493"AMD Family 17h Processors Models 00h-2Fh\" (AMD publication 56255) and "
494"amd_f17h_zen1_events(3CPC)";
495static char amd_fam_17h_zen2_reg[] = "See \"Preliminary Processor Programming "
496"Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors\" "
497"(AMD publication 55803), \"Processor Programming Reference (PPR) for AMD "
498"Family 17h Model 71h, Revision B0 Processors\" (AMD publication 56176), and "
499"amd_f17h_zen2_events(3CPC)";
492static char *evlist;
493static size_t evlist_sz;
494static const amd_event_t *amd_events = NULL;
495static uint_t amd_family, amd_model;
496static const amd_generic_event_t *amd_generic_events = NULL;
497
498static char amd_fam_f_rev_ae_bkdg[] = "See \"BIOS and Kernel Developer's "
499"Guide for AMD Athlon 64 and AMD Opteron Processors\" (AMD publication 26094)";

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506static char amd_fam_17h_zen1_reg[] = "See \"Open-Source Register Reference For "
507"AMD Family 17h Processors Models 00h-2Fh\" (AMD publication 56255) and "
508"amd_f17h_zen1_events(3CPC)";
509static char amd_fam_17h_zen2_reg[] = "See \"Preliminary Processor Programming "
510"Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors\" "
511"(AMD publication 55803), \"Processor Programming Reference (PPR) for AMD "
512"Family 17h Model 71h, Revision B0 Processors\" (AMD publication 56176), and "
513"amd_f17h_zen2_events(3CPC)";
514static char amd_fam_19h_zen3_reg[] = "See \"Preliminary Processor Programming "
515"Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors Volume "
516"1 of 2 (AMD publication 55898) and amd_f17h_zen3_events(3CPC)";
500
501static char amd_pcbe_impl_name[64];
502static char *amd_pcbe_cpuref;
503
504
505#define BITS(v, u, l) \
506 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
507

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606 amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
607 amd_events = opteron_pcbe_f17h_zen1_events;
608 amd_generic_events = family_17h_zen1_papi_events;
609 } else if (amd_family == 0x17 && amd_model >= 0x30 &&
610 amd_model <= 0x7f) {
611 amd_pcbe_cpuref = amd_fam_17h_zen2_reg;
612 amd_events = opteron_pcbe_f17h_zen2_events;
613 amd_generic_events = family_17h_zen2_papi_events;
517
518static char amd_pcbe_impl_name[64];
519static char *amd_pcbe_cpuref;
520
521
522#define BITS(v, u, l) \
523 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
524

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623 amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
624 amd_events = opteron_pcbe_f17h_zen1_events;
625 amd_generic_events = family_17h_zen1_papi_events;
626 } else if (amd_family == 0x17 && amd_model >= 0x30 &&
627 amd_model <= 0x7f) {
628 amd_pcbe_cpuref = amd_fam_17h_zen2_reg;
629 amd_events = opteron_pcbe_f17h_zen2_events;
630 amd_generic_events = family_17h_zen2_papi_events;
631 } else if (amd_family == 0x19 && amd_model <= 0xf) {
632 amd_pcbe_cpuref = amd_fam_19h_zen3_reg;
633 amd_events = opteron_pcbe_f19h_zen3_events;
634 amd_generic_events = family_19h_zen3_papi_events;
614 } else {
615 /*
616 * Different families have different meanings on events and even
617 * worse (like family 15h), different constraints around
618 * programming these values.
619 */
620 return (-1);
621 }

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636 /*
637 * Different families have different meanings on events and even
638 * worse (like family 15h), different constraints around
639 * programming these values.
640 */
641 return (-1);
642 }

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