emlxs_sli3.c (1a5e258f) emlxs_sli3.c (8f23e9fa)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2010 Emulex. All rights reserved.
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
24 * Use is subject to license terms.
25 */
26
27
28#include <emlxs.h>
29
30/* Required for EMLXS_CONTEXT in EMLXS_MSGF calls */
31EMLXS_MSG_DEF(EMLXS_SLI3_C);
32
33static void emlxs_sli3_issue_iocb(emlxs_hba_t *hba, RING *rp, IOCBQ *iocbq);
34static void emlxs_sli3_handle_link_event(emlxs_hba_t *hba);
35static void emlxs_sli3_handle_ring_event(emlxs_hba_t *hba, int32_t ring_no,

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43static uint32_t emlxs_disable_traffic_cop = 1;
44
45static int emlxs_sli3_map_hdw(emlxs_hba_t *hba);
46
47static void emlxs_sli3_unmap_hdw(emlxs_hba_t *hba);
48
49static int32_t emlxs_sli3_online(emlxs_hba_t *hba);
50
27#include <emlxs.h>
28
29/* Required for EMLXS_CONTEXT in EMLXS_MSGF calls */
30EMLXS_MSG_DEF(EMLXS_SLI3_C);
31
32static void emlxs_sli3_issue_iocb(emlxs_hba_t *hba, RING *rp, IOCBQ *iocbq);
33static void emlxs_sli3_handle_link_event(emlxs_hba_t *hba);
34static void emlxs_sli3_handle_ring_event(emlxs_hba_t *hba, int32_t ring_no,

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42static uint32_t emlxs_disable_traffic_cop = 1;
43
44static int emlxs_sli3_map_hdw(emlxs_hba_t *hba);
45
46static void emlxs_sli3_unmap_hdw(emlxs_hba_t *hba);
47
48static int32_t emlxs_sli3_online(emlxs_hba_t *hba);
49
51static void emlxs_sli3_offline(emlxs_hba_t *hba);
50static void emlxs_sli3_offline(emlxs_hba_t *hba,
51 uint32_t reset_requested);
52
53static uint32_t emlxs_sli3_hba_reset(emlxs_hba_t *hba,
54 uint32_t restart, uint32_t skip_post,
55 uint32_t quiesce);
56
57static void emlxs_sli3_hba_kill(emlxs_hba_t *hba);
58static void emlxs_sli3_hba_kill4quiesce(emlxs_hba_t *hba);
59static uint32_t emlxs_sli3_hba_init(emlxs_hba_t *hba);

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92static uint32_t emlxs_sli3_prep_els_iocb(emlxs_port_t *port,
93 emlxs_buf_t *sbp);
94
95
96static uint32_t emlxs_sli3_prep_ct_iocb(emlxs_port_t *port,
97 emlxs_buf_t *sbp);
98
99
52
53static uint32_t emlxs_sli3_hba_reset(emlxs_hba_t *hba,
54 uint32_t restart, uint32_t skip_post,
55 uint32_t quiesce);
56
57static void emlxs_sli3_hba_kill(emlxs_hba_t *hba);
58static void emlxs_sli3_hba_kill4quiesce(emlxs_hba_t *hba);
59static uint32_t emlxs_sli3_hba_init(emlxs_hba_t *hba);

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92static uint32_t emlxs_sli3_prep_els_iocb(emlxs_port_t *port,
93 emlxs_buf_t *sbp);
94
95
96static uint32_t emlxs_sli3_prep_ct_iocb(emlxs_port_t *port,
97 emlxs_buf_t *sbp);
98
99
100static void emlxs_sli3_poll_intr(emlxs_hba_t *hba,
101 uint32_t att_bit);
100static void emlxs_sli3_poll_intr(emlxs_hba_t *hba);
102
103static int32_t emlxs_sli3_intx_intr(char *arg);
104#ifdef MSI_SUPPORT
105static uint32_t emlxs_sli3_msi_intr(char *arg1, char *arg2);
106#endif /* MSI_SUPPORT */
107
108static void emlxs_sli3_enable_intr(emlxs_hba_t *hba);
109

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131/* static int emlxs_handle_rcv_seq(emlxs_hba_t *hba, */
132 /* CHANNEL *cp, IOCBQ *iocbq); */
133/* static void emlxs_update_HBQ_index(emlxs_hba_t *hba, */
134 /* uint32_t hbq_id); */
135/* static void emlxs_hbq_free_all(emlxs_hba_t *hba, */
136 /* uint32_t hbq_id); */
137static uint32_t emlxs_hbq_setup(emlxs_hba_t *hba,
138 uint32_t hbq_id);
101
102static int32_t emlxs_sli3_intx_intr(char *arg);
103#ifdef MSI_SUPPORT
104static uint32_t emlxs_sli3_msi_intr(char *arg1, char *arg2);
105#endif /* MSI_SUPPORT */
106
107static void emlxs_sli3_enable_intr(emlxs_hba_t *hba);
108

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130/* static int emlxs_handle_rcv_seq(emlxs_hba_t *hba, */
131 /* CHANNEL *cp, IOCBQ *iocbq); */
132/* static void emlxs_update_HBQ_index(emlxs_hba_t *hba, */
133 /* uint32_t hbq_id); */
134/* static void emlxs_hbq_free_all(emlxs_hba_t *hba, */
135 /* uint32_t hbq_id); */
136static uint32_t emlxs_hbq_setup(emlxs_hba_t *hba,
137 uint32_t hbq_id);
139extern void emlxs_sli3_timer(emlxs_hba_t *hba);
138static void emlxs_sli3_timer(emlxs_hba_t *hba);
140
139
141extern void emlxs_sli3_poll_erratt(emlxs_hba_t *hba);
140static void emlxs_sli3_poll_erratt(emlxs_hba_t *hba);
142
141
142static uint32_t emlxs_sli3_reg_did(emlxs_port_t *port,
143 uint32_t did, SERV_PARM *param,
144 emlxs_buf_t *sbp, fc_unsol_buf_t *ubp,
145 IOCBQ *iocbq);
143
146
147static uint32_t emlxs_sli3_unreg_node(emlxs_port_t *port,
148 NODELIST *node, emlxs_buf_t *sbp,
149 fc_unsol_buf_t *ubp, IOCBQ *iocbq);
150
151
144/* Define SLI3 API functions */
145emlxs_sli_api_t emlxs_sli3_api = {
146 emlxs_sli3_map_hdw,
147 emlxs_sli3_unmap_hdw,
148 emlxs_sli3_online,
149 emlxs_sli3_offline,
150 emlxs_sli3_hba_reset,
151 emlxs_sli3_hba_kill,

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160 emlxs_sli3_prep_ip_iocb,
161 emlxs_sli3_prep_els_iocb,
162 emlxs_sli3_prep_ct_iocb,
163 emlxs_sli3_poll_intr,
164 emlxs_sli3_intx_intr,
165 emlxs_sli3_msi_intr,
166 emlxs_sli3_disable_intr,
167 emlxs_sli3_timer,
152/* Define SLI3 API functions */
153emlxs_sli_api_t emlxs_sli3_api = {
154 emlxs_sli3_map_hdw,
155 emlxs_sli3_unmap_hdw,
156 emlxs_sli3_online,
157 emlxs_sli3_offline,
158 emlxs_sli3_hba_reset,
159 emlxs_sli3_hba_kill,

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168 emlxs_sli3_prep_ip_iocb,
169 emlxs_sli3_prep_els_iocb,
170 emlxs_sli3_prep_ct_iocb,
171 emlxs_sli3_poll_intr,
172 emlxs_sli3_intx_intr,
173 emlxs_sli3_msi_intr,
174 emlxs_sli3_disable_intr,
175 emlxs_sli3_timer,
168 emlxs_sli3_poll_erratt
176 emlxs_sli3_poll_erratt,
177 emlxs_sli3_reg_did,
178 emlxs_sli3_unreg_node
169};
170
171
172/*
173 * emlxs_sli3_online()
174 *
175 * This routine will start initialization of the SLI2/3 HBA.
176 */

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231
232 /*
233 * Get a buffer which will be used repeatedly for mailbox commands
234 */
235 mbq = (MAILBOXQ *) kmem_zalloc((sizeof (MAILBOXQ)), KM_SLEEP);
236
237 mb = (MAILBOX *)mbq;
238
179};
180
181
182/*
183 * emlxs_sli3_online()
184 *
185 * This routine will start initialization of the SLI2/3 HBA.
186 */

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241
242 /*
243 * Get a buffer which will be used repeatedly for mailbox commands
244 */
245 mbq = (MAILBOXQ *) kmem_zalloc((sizeof (MAILBOXQ)), KM_SLEEP);
246
247 mb = (MAILBOX *)mbq;
248
239reset:
240 /* Initialize sli mode based on configuration parameter */
241 switch (cfg[CFG_SLI_MODE].current) {
242 case 2: /* SLI2 mode */
243 sli_mode = EMLXS_HBA_SLI2_MODE;
244 sli_mode_mask = EMLXS_SLI2_MASK;
245 break;
246
247 case 3: /* SLI3 mode */

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253 case 1: /* Best available */
254 default:
255 if (hba->model_info.sli_mask & EMLXS_SLI3_MASK) {
256 sli_mode = EMLXS_HBA_SLI3_MODE;
257 sli_mode_mask = EMLXS_SLI3_MASK;
258 } else if (hba->model_info.sli_mask & EMLXS_SLI2_MASK) {
259 sli_mode = EMLXS_HBA_SLI2_MODE;
260 sli_mode_mask = EMLXS_SLI2_MASK;
249 /* Initialize sli mode based on configuration parameter */
250 switch (cfg[CFG_SLI_MODE].current) {
251 case 2: /* SLI2 mode */
252 sli_mode = EMLXS_HBA_SLI2_MODE;
253 sli_mode_mask = EMLXS_SLI2_MASK;
254 break;
255
256 case 3: /* SLI3 mode */

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262 case 1: /* Best available */
263 default:
264 if (hba->model_info.sli_mask & EMLXS_SLI3_MASK) {
265 sli_mode = EMLXS_HBA_SLI3_MODE;
266 sli_mode_mask = EMLXS_SLI3_MASK;
267 } else if (hba->model_info.sli_mask & EMLXS_SLI2_MASK) {
268 sli_mode = EMLXS_HBA_SLI2_MODE;
269 sli_mode_mask = EMLXS_SLI2_MASK;
270 } else {
271 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
272 "No SLI mode available.");
273 rval = EIO;
274 goto failed;
261 }
275 }
276 break;
262 }
263 /* SBUS adapters only available in SLI2 */
264 if (hba->bus_type == SBUS_FC) {
265 sli_mode = EMLXS_HBA_SLI2_MODE;
266 sli_mode_mask = EMLXS_SLI2_MASK;
267 }
268
277 }
278 /* SBUS adapters only available in SLI2 */
279 if (hba->bus_type == SBUS_FC) {
280 sli_mode = EMLXS_HBA_SLI2_MODE;
281 sli_mode_mask = EMLXS_SLI2_MASK;
282 }
283
284reset:
269 /* Reset & Initialize the adapter */
270 if (emlxs_sli3_hba_init(hba)) {
271 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
272 "Unable to init hba.");
273
274 rval = EIO;
275 goto failed;
276 }

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286 EMLXS_MSGF(EMLXS_CONTEXT,
287 &emlxs_invalid_access_handle_msg, NULL);
288
289 rval = EIO;
290 goto failed;
291 }
292#endif /* FMA_SUPPORT */
293
285 /* Reset & Initialize the adapter */
286 if (emlxs_sli3_hba_init(hba)) {
287 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
288 "Unable to init hba.");
289
290 rval = EIO;
291 goto failed;
292 }

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302 EMLXS_MSGF(EMLXS_CONTEXT,
303 &emlxs_invalid_access_handle_msg, NULL);
304
305 rval = EIO;
306 goto failed;
307 }
308#endif /* FMA_SUPPORT */
309
294 /* Check for the LP9802 (This is a special case) */
310 /* Check for PEGASUS (This is a special case) */
295 /* We need to check for dual channel adapter */
311 /* We need to check for dual channel adapter */
296 if (hba->model_info.device_id == PCI_DEVICE_ID_LP9802) {
312 if (hba->model_info.device_id == PCI_DEVICE_ID_PEGASUS) {
297 /* Try to determine if this is a DC adapter */
298 if (emlxs_get_max_sram(hba, &MaxRbusSize, &MaxIbusSize) == 0) {
299 if (MaxRbusSize == REDUCED_SRAM_CFG) {
300 /* LP9802DC */
301 for (i = 1; i < emlxs_pci_model_count; i++) {
302 if (emlxs_pci_model[i].id == LP9802DC) {
303 bcopy(&emlxs_pci_model[i],
304 &hba->model_info,

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468 vpd->smFwRev = mb->un.varRdRev.un.smFwRev;
469 vpd->endecRev = mb->un.varRdRev.endecRev;
470 vpd->fcphHigh = mb->un.varRdRev.fcphHigh;
471 vpd->fcphLow = mb->un.varRdRev.fcphLow;
472 vpd->feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
473 vpd->feaLevelLow = mb->un.varRdRev.feaLevelLow;
474
475 /* Decode FW names */
313 /* Try to determine if this is a DC adapter */
314 if (emlxs_get_max_sram(hba, &MaxRbusSize, &MaxIbusSize) == 0) {
315 if (MaxRbusSize == REDUCED_SRAM_CFG) {
316 /* LP9802DC */
317 for (i = 1; i < emlxs_pci_model_count; i++) {
318 if (emlxs_pci_model[i].id == LP9802DC) {
319 bcopy(&emlxs_pci_model[i],
320 &hba->model_info,

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484 vpd->smFwRev = mb->un.varRdRev.un.smFwRev;
485 vpd->endecRev = mb->un.varRdRev.endecRev;
486 vpd->fcphHigh = mb->un.varRdRev.fcphHigh;
487 vpd->fcphLow = mb->un.varRdRev.fcphLow;
488 vpd->feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
489 vpd->feaLevelLow = mb->un.varRdRev.feaLevelLow;
490
491 /* Decode FW names */
476 emlxs_decode_version(vpd->postKernRev, vpd->postKernName);
477 emlxs_decode_version(vpd->opFwRev, vpd->opFwName);
478 emlxs_decode_version(vpd->sli1FwRev, vpd->sli1FwName);
479 emlxs_decode_version(vpd->sli2FwRev, vpd->sli2FwName);
480 emlxs_decode_version(vpd->sli3FwRev, vpd->sli3FwName);
481 emlxs_decode_version(vpd->sli4FwRev, vpd->sli4FwName);
492 emlxs_decode_version(vpd->postKernRev, vpd->postKernName,
493 sizeof (vpd->postKernName));
494 emlxs_decode_version(vpd->opFwRev, vpd->opFwName,
495 sizeof (vpd->opFwName));
496 emlxs_decode_version(vpd->sli1FwRev, vpd->sli1FwName,
497 sizeof (vpd->sli1FwName));
498 emlxs_decode_version(vpd->sli2FwRev, vpd->sli2FwName,
499 sizeof (vpd->sli2FwName));
500 emlxs_decode_version(vpd->sli3FwRev, vpd->sli3FwName,
501 sizeof (vpd->sli3FwName));
502 emlxs_decode_version(vpd->sli4FwRev, vpd->sli4FwName,
503 sizeof (vpd->sli4FwName));
482
483 /* Decode FW labels */
504
505 /* Decode FW labels */
484 emlxs_decode_label(vpd->opFwLabel, vpd->opFwLabel, 1);
485 emlxs_decode_label(vpd->sli1FwLabel, vpd->sli1FwLabel, 1);
486 emlxs_decode_label(vpd->sli2FwLabel, vpd->sli2FwLabel, 1);
487 emlxs_decode_label(vpd->sli3FwLabel, vpd->sli3FwLabel, 1);
488 emlxs_decode_label(vpd->sli4FwLabel, vpd->sli4FwLabel, 1);
506 emlxs_decode_label(vpd->opFwLabel, vpd->opFwLabel, 1,
507 sizeof (vpd->opFwLabel));
508 emlxs_decode_label(vpd->sli1FwLabel, vpd->sli1FwLabel, 1,
509 sizeof (vpd->sli1FwLabel));
510 emlxs_decode_label(vpd->sli2FwLabel, vpd->sli2FwLabel, 1,
511 sizeof (vpd->sli2FwLabel));
512 emlxs_decode_label(vpd->sli3FwLabel, vpd->sli3FwLabel, 1,
513 sizeof (vpd->sli3FwLabel));
514 emlxs_decode_label(vpd->sli4FwLabel, vpd->sli4FwLabel, 1,
515 sizeof (vpd->sli4FwLabel));
489
490 /* Reuse mbq from previous mbox */
491 bzero(mbq, sizeof (MAILBOXQ));
492
493 key = emlxs_get_key(hba, mbq);
494
495 /* Get adapter VPD information */
496 offset = 0;

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628 * Now lets update hba->model_info with the real
629 * VPD data, if any.
630 */
631
632 /*
633 * Replace the default model description with vpd data
634 */
635 if (vpd->model_desc[0] != 0) {
516
517 /* Reuse mbq from previous mbox */
518 bzero(mbq, sizeof (MAILBOXQ));
519
520 key = emlxs_get_key(hba, mbq);
521
522 /* Get adapter VPD information */
523 offset = 0;

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655 * Now lets update hba->model_info with the real
656 * VPD data, if any.
657 */
658
659 /*
660 * Replace the default model description with vpd data
661 */
662 if (vpd->model_desc[0] != 0) {
636 (void) strcpy(hba->model_info.model_desc,
637 vpd->model_desc);
663 (void) strncpy(hba->model_info.model_desc,
664 vpd->model_desc,
665 (sizeof (hba->model_info.model_desc)-1));
638 }
639
640 /* Replace the default model with vpd data */
641 if (vpd->model[0] != 0) {
666 }
667
668 /* Replace the default model with vpd data */
669 if (vpd->model[0] != 0) {
642 (void) strcpy(hba->model_info.model, vpd->model);
670 (void) strncpy(hba->model_info.model, vpd->model,
671 (sizeof (hba->model_info.model)-1));
643 }
644
645 /* Replace the default program types with vpd data */
646 if (vpd->prog_types[0] != 0) {
647 emlxs_parse_prog_types(hba, vpd->prog_types);
648 }
649 }
650

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661
662 rval = EIO;
663 goto failed;
664 }
665
666 /* Read the adapter's wakeup parms */
667 (void) emlxs_read_wakeup_parms(hba, &hba->wakeup_parms, 1);
668 emlxs_decode_version(hba->wakeup_parms.u0.boot_bios_wd[0],
672 }
673
674 /* Replace the default program types with vpd data */
675 if (vpd->prog_types[0] != 0) {
676 emlxs_parse_prog_types(hba, vpd->prog_types);
677 }
678 }
679

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690
691 rval = EIO;
692 goto failed;
693 }
694
695 /* Read the adapter's wakeup parms */
696 (void) emlxs_read_wakeup_parms(hba, &hba->wakeup_parms, 1);
697 emlxs_decode_version(hba->wakeup_parms.u0.boot_bios_wd[0],
669 vpd->boot_version);
698 vpd->boot_version, sizeof (vpd->boot_version));
670
671 /* Get fcode version property */
672 emlxs_get_fcode_version(hba);
673
674 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
675 "Firmware: kern=%08x stub=%08x sli1=%08x", vpd->postKernRev,
676 vpd->opFwRev, vpd->sli1FwRev);
677

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684
685 /*
686 * If firmware checking is enabled and the adapter model indicates
687 * a firmware image, then perform firmware version check
688 */
689 hba->fw_flag = 0;
690 hba->fw_timer = 0;
691
699
700 /* Get fcode version property */
701 emlxs_get_fcode_version(hba);
702
703 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
704 "Firmware: kern=%08x stub=%08x sli1=%08x", vpd->postKernRev,
705 vpd->opFwRev, vpd->sli1FwRev);
706

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713
714 /*
715 * If firmware checking is enabled and the adapter model indicates
716 * a firmware image, then perform firmware version check
717 */
718 hba->fw_flag = 0;
719 hba->fw_timer = 0;
720
692 if (((fw_check & 0x1) && (hba->model_info.flags & EMLXS_SUN_BRANDED) &&
721 if (((fw_check & 0x1) &&
722 (hba->model_info.flags & EMLXS_ORACLE_BRANDED) &&
693 hba->model_info.fwid) || ((fw_check & 0x2) &&
694 hba->model_info.fwid)) {
695 emlxs_firmware_t *fw;
696
697 /* Find firmware image indicated by adapter model */
698 fw = NULL;
699 for (i = 0; i < emlxs_fw_count; i++) {
700 if (emlxs_fw_table[i].id == hba->model_info.fwid) {

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732 * If MODFW_SUPPORT is not defined, the
733 * firmware image will already be defined
734 * in the emlxs_fw_table
735 */
736 emlxs_fw_load(hba, fw);
737#endif /* MODFW_SUPPORT */
738
739 if (fw->image && fw->size) {
723 hba->model_info.fwid) || ((fw_check & 0x2) &&
724 hba->model_info.fwid)) {
725 emlxs_firmware_t *fw;
726
727 /* Find firmware image indicated by adapter model */
728 fw = NULL;
729 for (i = 0; i < emlxs_fw_count; i++) {
730 if (emlxs_fw_table[i].id == hba->model_info.fwid) {

--- 31 unchanged lines hidden (view full) ---

762 * If MODFW_SUPPORT is not defined, the
763 * firmware image will already be defined
764 * in the emlxs_fw_table
765 */
766 emlxs_fw_load(hba, fw);
767#endif /* MODFW_SUPPORT */
768
769 if (fw->image && fw->size) {
740 if (emlxs_fw_download(hba,
741 (char *)fw->image, fw->size, 0)) {
770 uint32_t rc;
771
772 rc = emlxs_fw_download(hba,
773 (char *)fw->image, fw->size, 0);
774 if ((rc != FC_SUCCESS) &&
775 (rc != EMLXS_REBOOT_REQUIRED)) {
742 EMLXS_MSGF(EMLXS_CONTEXT,
743 &emlxs_init_msg,
744 "Firmware update failed.");
776 EMLXS_MSGF(EMLXS_CONTEXT,
777 &emlxs_init_msg,
778 "Firmware update failed.");
745
746 hba->fw_flag |=
747 FW_UPDATE_NEEDED;
748 }
749#ifdef MODFW_SUPPORT
750 /*
751 * Unload the firmware image from
752 * kernel memory
753 */
754 emlxs_fw_unload(hba, fw);
755#endif /* MODFW_SUPPORT */
756
757 fw_check = 0;
758
759 goto reset;
760 }
761
779 hba->fw_flag |=
780 FW_UPDATE_NEEDED;
781 }
782#ifdef MODFW_SUPPORT
783 /*
784 * Unload the firmware image from
785 * kernel memory
786 */
787 emlxs_fw_unload(hba, fw);
788#endif /* MODFW_SUPPORT */
789
790 fw_check = 0;
791
792 goto reset;
793 }
794
795 hba->fw_flag |= FW_UPDATE_NEEDED;
796
762 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_msg,
763 "Firmware image unavailable.");
764 } else {
765 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_msg,
766 "Firmware update not needed.");
767 }
768 } else {
769 /* This should not happen */

--- 85 unchanged lines hidden (view full) ---

855 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
856 "SLI3 mode: flag=%x vpi_max=%d", hba->flag, hba->vpi_max);
857 } else {
858 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
859 "SLI2 mode: flag=%x", hba->flag);
860 sli_mode = EMLXS_HBA_SLI2_MODE;
861 sli_mode_mask = EMLXS_SLI2_MASK;
862 hba->sli_mode = sli_mode;
797 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_msg,
798 "Firmware image unavailable.");
799 } else {
800 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_msg,
801 "Firmware update not needed.");
802 }
803 } else {
804 /* This should not happen */

--- 85 unchanged lines hidden (view full) ---

890 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
891 "SLI3 mode: flag=%x vpi_max=%d", hba->flag, hba->vpi_max);
892 } else {
893 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
894 "SLI2 mode: flag=%x", hba->flag);
895 sli_mode = EMLXS_HBA_SLI2_MODE;
896 sli_mode_mask = EMLXS_SLI2_MASK;
897 hba->sli_mode = sli_mode;
898#if (EMLXS_MODREV >= EMLXS_MODREV5)
899 hba->fca_tran->fca_num_npivports = 0;
900#endif /* >= EMLXS_MODREV5 */
901
863 }
864
865 /* Get and save the current firmware version (based on sli_mode) */
866 emlxs_decode_firmware_rev(hba, vpd);
867
868 emlxs_pcix_mxr_update(hba, 0);
869
870 /* Reuse mbq from previous mbox */

--- 19 unchanged lines hidden (view full) ---

890 min(cfg[CFG_NUM_NODES].current,
891 mb->un.varRdConfig.max_rpi);
892 } else {
893 hba->max_nodes = mb->un.varRdConfig.max_rpi;
894 }
895
896 /* Set the io throttle */
897 hba->io_throttle = mb->un.varRdConfig.max_xri - IO_THROTTLE_RESERVE;
902 }
903
904 /* Get and save the current firmware version (based on sli_mode) */
905 emlxs_decode_firmware_rev(hba, vpd);
906
907 emlxs_pcix_mxr_update(hba, 0);
908
909 /* Reuse mbq from previous mbox */

--- 19 unchanged lines hidden (view full) ---

929 min(cfg[CFG_NUM_NODES].current,
930 mb->un.varRdConfig.max_rpi);
931 } else {
932 hba->max_nodes = mb->un.varRdConfig.max_rpi;
933 }
934
935 /* Set the io throttle */
936 hba->io_throttle = mb->un.varRdConfig.max_xri - IO_THROTTLE_RESERVE;
898 hba->max_iotag = mb->un.varRdConfig.max_xri;
899
937
938 /* Set max_iotag */
939 if (cfg[CFG_NUM_IOTAGS].current) {
940 hba->max_iotag = (uint16_t)cfg[CFG_NUM_IOTAGS].current;
941 } else {
942 hba->max_iotag = mb->un.varRdConfig.max_xri;
943 }
944
945 /* Set out-of-range iotag base */
946 hba->fc_oor_iotag = hba->max_iotag;
947
900 /*
901 * Allocate some memory for buffers
902 */
903 if (emlxs_mem_alloc_buffer(hba) == 0) {
904 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
905 "Unable to allocate memory buffers.");
906
907 EMLXS_STATE_CHANGE(hba, FC_ERROR);
908 return (ENOMEM);
909 }
910
911 /*
912 * Setup and issue mailbox RUN BIU DIAG command Setup test buffers
913 */
948 /*
949 * Allocate some memory for buffers
950 */
951 if (emlxs_mem_alloc_buffer(hba) == 0) {
952 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
953 "Unable to allocate memory buffers.");
954
955 EMLXS_STATE_CHANGE(hba, FC_ERROR);
956 return (ENOMEM);
957 }
958
959 /*
960 * Setup and issue mailbox RUN BIU DIAG command Setup test buffers
961 */
914 if (((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF, 1)) == 0) ||
915 ((mp1 = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF, 1)) == 0)) {
962 if (((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF)) == 0) ||
963 ((mp1 = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF)) == 0)) {
916 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
917 "Unable to allocate diag buffers.");
918
919 rval = ENOMEM;
920 goto failed;
921 }
922
923 bcopy((caddr_t)&emlxs_diag_pattern[0], (caddr_t)mp->virt,

--- 23 unchanged lines hidden (view full) ---

947 DDI_DMA_SYNC_FORKERNEL);
948
949#ifdef FMA_SUPPORT
950 if (mp->dma_handle) {
951 if (emlxs_fm_check_dma_handle(hba, mp->dma_handle)
952 != DDI_FM_OK) {
953 EMLXS_MSGF(EMLXS_CONTEXT,
954 &emlxs_invalid_dma_handle_msg,
964 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
965 "Unable to allocate diag buffers.");
966
967 rval = ENOMEM;
968 goto failed;
969 }
970
971 bcopy((caddr_t)&emlxs_diag_pattern[0], (caddr_t)mp->virt,

--- 23 unchanged lines hidden (view full) ---

995 DDI_DMA_SYNC_FORKERNEL);
996
997#ifdef FMA_SUPPORT
998 if (mp->dma_handle) {
999 if (emlxs_fm_check_dma_handle(hba, mp->dma_handle)
1000 != DDI_FM_OK) {
1001 EMLXS_MSGF(EMLXS_CONTEXT,
1002 &emlxs_invalid_dma_handle_msg,
955 "emlxs_sli3_online: hdl=%p",
1003 "sli3_online: hdl=%p",
956 mp->dma_handle);
957 rval = EIO;
958 goto failed;
959 }
960 }
961
962 if (mp1->dma_handle) {
963 if (emlxs_fm_check_dma_handle(hba, mp1->dma_handle)
964 != DDI_FM_OK) {
965 EMLXS_MSGF(EMLXS_CONTEXT,
966 &emlxs_invalid_dma_handle_msg,
1004 mp->dma_handle);
1005 rval = EIO;
1006 goto failed;
1007 }
1008 }
1009
1010 if (mp1->dma_handle) {
1011 if (emlxs_fm_check_dma_handle(hba, mp1->dma_handle)
1012 != DDI_FM_OK) {
1013 EMLXS_MSGF(EMLXS_CONTEXT,
1014 &emlxs_invalid_dma_handle_msg,
967 "emlxs_sli3_online: hdl=%p",
1015 "sli3_online: hdl=%p",
968 mp1->dma_handle);
969 rval = EIO;
970 goto failed;
971 }
972 }
973#endif /* FMA_SUPPORT */
974
975 outptr = mp->virt;

--- 25 unchanged lines hidden (view full) ---

1001 hba->channel_ip = FC_IP_RING;
1002 hba->channel_ct = FC_CT_RING;
1003 hba->sli.sli3.ring_count = MAX_RINGS;
1004
1005 hba->channel_tx_count = 0;
1006 hba->io_count = 0;
1007 hba->fc_iotag = 1;
1008
1016 mp1->dma_handle);
1017 rval = EIO;
1018 goto failed;
1019 }
1020 }
1021#endif /* FMA_SUPPORT */
1022
1023 outptr = mp->virt;

--- 25 unchanged lines hidden (view full) ---

1049 hba->channel_ip = FC_IP_RING;
1050 hba->channel_ct = FC_CT_RING;
1051 hba->sli.sli3.ring_count = MAX_RINGS;
1052
1053 hba->channel_tx_count = 0;
1054 hba->io_count = 0;
1055 hba->fc_iotag = 1;
1056
1009 /*
1010 * OutOfRange (oor) iotags are used for abort or
1011 * close XRI commands
1012 */
1013 hba->fc_oor_iotag = hba->max_iotag;
1014
1015 for (i = 0; i < hba->chan_count; i++) {
1016 cp = &hba->chan[i];
1017
1018 /* 1 to 1 mapping between ring and channel */
1019 cp->iopath = (void *)&hba->sli.sli3.ring[i];
1020
1021 cp->hba = hba;
1022 cp->channelno = i;

--- 174 unchanged lines hidden (view full) ---

1197 vpd->port_index = 0;
1198 while (c_dip && (hba->dip != c_dip)) {
1199 c_dip = ddi_get_next_sibling(c_dip);
1200 vpd->port_index++;
1201 }
1202 }
1203
1204 if (vpd->port_num[0] == 0) {
1057 for (i = 0; i < hba->chan_count; i++) {
1058 cp = &hba->chan[i];
1059
1060 /* 1 to 1 mapping between ring and channel */
1061 cp->iopath = (void *)&hba->sli.sli3.ring[i];
1062
1063 cp->hba = hba;
1064 cp->channelno = i;

--- 174 unchanged lines hidden (view full) ---

1239 vpd->port_index = 0;
1240 while (c_dip && (hba->dip != c_dip)) {
1241 c_dip = ddi_get_next_sibling(c_dip);
1242 vpd->port_index++;
1243 }
1244 }
1245
1246 if (vpd->port_num[0] == 0) {
1205 if (hba->model_info.channels > 1) {
1206 (void) sprintf(vpd->port_num, "%d", vpd->port_index);
1247 if (hba->model_info.channels == EMLXS_MULTI_CHANNEL) {
1248 (void) snprintf(vpd->port_num,
1249 (sizeof (vpd->port_num)-1),
1250 "%d", vpd->port_index);
1207 }
1208 }
1209
1210 if (vpd->id[0] == 0) {
1251 }
1252 }
1253
1254 if (vpd->id[0] == 0) {
1211 (void) strcpy(vpd->id, hba->model_info.model_desc);
1255 (void) strncpy(vpd->id, hba->model_info.model_desc,
1256 (sizeof (vpd->id)-1));
1212 }
1213
1214 if (vpd->manufacturer[0] == 0) {
1257 }
1258
1259 if (vpd->manufacturer[0] == 0) {
1215 (void) strcpy(vpd->manufacturer, hba->model_info.manufacturer);
1260 (void) strncpy(vpd->manufacturer, hba->model_info.manufacturer,
1261 (sizeof (vpd->manufacturer)-1));
1216 }
1217
1218 if (vpd->part_num[0] == 0) {
1262 }
1263
1264 if (vpd->part_num[0] == 0) {
1219 (void) strcpy(vpd->part_num, hba->model_info.model);
1265 (void) strncpy(vpd->part_num, hba->model_info.model,
1266 (sizeof (vpd->part_num)-1));
1220 }
1221
1222 if (vpd->model_desc[0] == 0) {
1267 }
1268
1269 if (vpd->model_desc[0] == 0) {
1223 (void) strcpy(vpd->model_desc, hba->model_info.model_desc);
1270 (void) strncpy(vpd->model_desc, hba->model_info.model_desc,
1271 (sizeof (vpd->model_desc)-1));
1224 }
1225
1226 if (vpd->model[0] == 0) {
1272 }
1273
1274 if (vpd->model[0] == 0) {
1227 (void) strcpy(vpd->model, hba->model_info.model);
1275 (void) strncpy(vpd->model, hba->model_info.model,
1276 (sizeof (vpd->model)-1));
1228 }
1229
1230 if (vpd->prog_types[0] == 0) {
1277 }
1278
1279 if (vpd->prog_types[0] == 0) {
1231 emlxs_build_prog_types(hba, vpd->prog_types);
1280 emlxs_build_prog_types(hba, vpd);
1232 }
1233
1234 /* Create the symbolic names */
1281 }
1282
1283 /* Create the symbolic names */
1235 (void) sprintf(hba->snn, "Emulex %s FV%s DV%s %s",
1284 (void) snprintf(hba->snn, (sizeof (hba->snn)-1),
1285 "Emulex %s FV%s DV%s %s",
1236 hba->model_info.model, hba->vpd.fw_version, emlxs_version,
1237 (char *)utsname.nodename);
1238
1286 hba->model_info.model, hba->vpd.fw_version, emlxs_version,
1287 (char *)utsname.nodename);
1288
1239 (void) sprintf(hba->spn,
1289 (void) snprintf(hba->spn, (sizeof (hba->spn)-1),
1240 "Emulex PPN-%01x%01x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
1241 hba->wwpn.nameType, hba->wwpn.IEEEextMsn, hba->wwpn.IEEEextLsb,
1242 hba->wwpn.IEEE[0], hba->wwpn.IEEE[1], hba->wwpn.IEEE[2],
1243 hba->wwpn.IEEE[3], hba->wwpn.IEEE[4], hba->wwpn.IEEE[5]);
1244
1245 if (cfg[CFG_NETWORK_ON].current) {
1246 if ((hba->sparam.portName.nameType != NAME_IEEE) ||
1247 (hba->sparam.portName.IEEEextMsn != 0) ||
1248 (hba->sparam.portName.IEEEextLsb != 0)) {
1249
1290 "Emulex PPN-%01x%01x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
1291 hba->wwpn.nameType, hba->wwpn.IEEEextMsn, hba->wwpn.IEEEextLsb,
1292 hba->wwpn.IEEE[0], hba->wwpn.IEEE[1], hba->wwpn.IEEE[2],
1293 hba->wwpn.IEEE[3], hba->wwpn.IEEE[4], hba->wwpn.IEEE[5]);
1294
1295 if (cfg[CFG_NETWORK_ON].current) {
1296 if ((hba->sparam.portName.nameType != NAME_IEEE) ||
1297 (hba->sparam.portName.IEEEextMsn != 0) ||
1298 (hba->sparam.portName.IEEEextLsb != 0)) {
1299
1250 cfg[CFG_NETWORK_ON].current = 0;
1251
1252 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_msg,
1300 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_msg,
1253 "WWPN doesn't conform to IP profile: nameType=%x",
1301 "WWPN doesn't conform to IP profile: "
1302 "nameType=%x. Disabling networking.",
1254 hba->sparam.portName.nameType);
1303 hba->sparam.portName.nameType);
1304
1305 cfg[CFG_NETWORK_ON].current = 0;
1255 }
1306 }
1307 }
1256
1308
1309 if (cfg[CFG_NETWORK_ON].current) {
1257 /* Reuse mbq from previous mbox */
1258 bzero(mbq, sizeof (MAILBOXQ));
1259
1260 /* Issue CONFIG FARP */
1261 emlxs_mb_config_farp(hba, mbq);
1262 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) !=
1263 MBX_SUCCESS) {
1264 /*

--- 123 unchanged lines hidden (view full) ---

1388 hba->flag |= FC_ASYNC_EVENTS;
1389 }
1390
1391 EMLXS_STATE_CHANGE(hba, FC_LINK_DOWN);
1392
1393 emlxs_sli3_enable_intr(hba);
1394
1395 if (hba->flag & FC_HBQ_ENABLED) {
1310 /* Reuse mbq from previous mbox */
1311 bzero(mbq, sizeof (MAILBOXQ));
1312
1313 /* Issue CONFIG FARP */
1314 emlxs_mb_config_farp(hba, mbq);
1315 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) !=
1316 MBX_SUCCESS) {
1317 /*

--- 123 unchanged lines hidden (view full) ---

1441 hba->flag |= FC_ASYNC_EVENTS;
1442 }
1443
1444 EMLXS_STATE_CHANGE(hba, FC_LINK_DOWN);
1445
1446 emlxs_sli3_enable_intr(hba);
1447
1448 if (hba->flag & FC_HBQ_ENABLED) {
1396 if (hba->tgt_mode) {
1449 if (port->flag & EMLXS_TGT_ENABLED) {
1397 if (emlxs_hbq_setup(hba, EMLXS_FCT_HBQ_ID)) {
1398 EMLXS_MSGF(EMLXS_CONTEXT,
1399 &emlxs_init_failed_msg,
1400 "Unable to setup FCT HBQ.");
1401
1402 rval = ENOMEM;
1450 if (emlxs_hbq_setup(hba, EMLXS_FCT_HBQ_ID)) {
1451 EMLXS_MSGF(EMLXS_CONTEXT,
1452 &emlxs_init_failed_msg,
1453 "Unable to setup FCT HBQ.");
1454
1455 rval = ENOMEM;
1456
1457#ifdef SFCT_SUPPORT
1458 /* Check if we can fall back to just */
1459 /* initiator mode */
1460 if ((hba->pm_state == EMLXS_PM_IN_ATTACH) &&
1461 (port->flag & EMLXS_INI_ENABLED) &&
1462 (cfg[CFG_DTM_ENABLE].current == 1) &&
1463 (cfg[CFG_TARGET_MODE].current == 0)) {
1464
1465 cfg[CFG_DTM_ENABLE].current = 0;
1466
1467 EMLXS_MSGF(EMLXS_CONTEXT,
1468 &emlxs_init_failed_msg,
1469 "Disabling dynamic target mode. "
1470 "Enabling initiator mode only.");
1471
1472 /* This will trigger the driver to */
1473 /* reattach */
1474 rval = EAGAIN;
1475 }
1476#endif /* SFCT_SUPPORT */
1403 goto failed;
1404 }
1405 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1406 "FCT Ring: Posted %d buffers.", MEM_FCTBUF_COUNT);
1407 }
1408
1409 if (cfg[CFG_NETWORK_ON].current) {
1410 if (emlxs_hbq_setup(hba, EMLXS_IP_HBQ_ID)) {

--- 22 unchanged lines hidden (view full) ---

1433 "Unable to setup CT HBQ.");
1434
1435 rval = ENOMEM;
1436 goto failed;
1437 }
1438 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1439 "CT Ring: Posted %d buffers.", MEM_CTBUF_COUNT);
1440 } else {
1477 goto failed;
1478 }
1479 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1480 "FCT Ring: Posted %d buffers.", MEM_FCTBUF_COUNT);
1481 }
1482
1483 if (cfg[CFG_NETWORK_ON].current) {
1484 if (emlxs_hbq_setup(hba, EMLXS_IP_HBQ_ID)) {

--- 22 unchanged lines hidden (view full) ---

1507 "Unable to setup CT HBQ.");
1508
1509 rval = ENOMEM;
1510 goto failed;
1511 }
1512 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1513 "CT Ring: Posted %d buffers.", MEM_CTBUF_COUNT);
1514 } else {
1441 if (hba->tgt_mode) {
1515 if (port->flag & EMLXS_TGT_ENABLED) {
1442 /* Post the FCT unsol buffers */
1443 rp = &hba->sli.sli3.ring[FC_FCT_RING];
1444 for (j = 0; j < MEM_FCTBUF_COUNT; j += 2) {
1445 (void) emlxs_post_buffer(hba, rp, 2);
1446 }
1447 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1448 "FCP Ring: Posted %d buffers.", MEM_FCTBUF_COUNT);
1449 }

--- 23 unchanged lines hidden (view full) ---

1473 (void) emlxs_post_buffer(hba, rp, 2);
1474 }
1475 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1476 "CT Ring: Posted %d buffers.", MEM_CTBUF_COUNT);
1477 }
1478
1479 (void) kmem_free((uint8_t *)mbq, sizeof (MAILBOXQ));
1480
1516 /* Post the FCT unsol buffers */
1517 rp = &hba->sli.sli3.ring[FC_FCT_RING];
1518 for (j = 0; j < MEM_FCTBUF_COUNT; j += 2) {
1519 (void) emlxs_post_buffer(hba, rp, 2);
1520 }
1521 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1522 "FCP Ring: Posted %d buffers.", MEM_FCTBUF_COUNT);
1523 }

--- 23 unchanged lines hidden (view full) ---

1547 (void) emlxs_post_buffer(hba, rp, 2);
1548 }
1549 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
1550 "CT Ring: Posted %d buffers.", MEM_CTBUF_COUNT);
1551 }
1552
1553 (void) kmem_free((uint8_t *)mbq, sizeof (MAILBOXQ));
1554
1555 /* Check persist-linkdown */
1556 if (cfg[CFG_PERSIST_LINKDOWN].current) {
1557 EMLXS_STATE_CHANGE(hba, FC_LINK_DOWN_PERSIST);
1558 return (0);
1559 }
1560
1561#ifdef SFCT_SUPPORT
1562 if ((port->mode == MODE_TARGET) &&
1563 !(port->fct_flags & FCT_STATE_PORT_ONLINE)) {
1564 emlxs_enable_latt(hba);
1565 return (0);
1566 }
1567#endif /* SFCT_SUPPORT */
1568
1481 /*
1482 * Setup and issue mailbox INITIALIZE LINK command
1483 * At this point, the interrupt will be generated by the HW
1569 /*
1570 * Setup and issue mailbox INITIALIZE LINK command
1571 * At this point, the interrupt will be generated by the HW
1484 * Do this only if persist-linkdown is not set
1485 */
1572 */
1486 if (cfg[CFG_PERSIST_LINKDOWN].current == 0) {
1487 mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1);
1488 if (mbq == NULL) {
1489 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1490 "Unable to allocate mailbox buffer.");
1573 mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX);
1574 if (mbq == NULL) {
1575 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1576 "Unable to allocate mailbox buffer.");
1491
1577
1492 rval = EIO;
1493 goto failed;
1494 }
1578 rval = EIO;
1579 goto failed;
1580 }
1581 mb = (MAILBOX *)mbq;
1495
1582
1496 emlxs_mb_init_link(hba, mbq, cfg[CFG_TOPOLOGY].current,
1497 cfg[CFG_LINK_SPEED].current);
1583 emlxs_mb_init_link(hba, mbq, cfg[CFG_TOPOLOGY].current,
1584 cfg[CFG_LINK_SPEED].current);
1498
1585
1499 rval = emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_NOWAIT, 0);
1500 if ((rval != MBX_SUCCESS) && (rval != MBX_BUSY)) {
1501 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1502 "Unable to initialize link. " \
1503 "Mailbox cmd=%x status=%x",
1504 mb->mbxCommand, mb->mbxStatus);
1586 rval = emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_NOWAIT, 0);
1587 if ((rval != MBX_SUCCESS) && (rval != MBX_BUSY)) {
1588 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg,
1589 "Unable to initialize link. " \
1590 "Mailbox cmd=%x status=%x",
1591 mb->mbxCommand, mb->mbxStatus);
1505
1592
1506 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
1593 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
1594 mbq = NULL;
1595 rval = EIO;
1596 goto failed;
1597 }
1598
1599 /*
1600 * Enable link attention interrupt
1601 */
1602 emlxs_enable_latt(hba);
1603
1604 /* Wait for link to come up */
1605 i = cfg[CFG_LINKUP_DELAY].current;
1606 while (i && (hba->state < FC_LINK_UP)) {
1607 /* Check for hardware error */
1608 if (hba->state == FC_ERROR) {
1609 EMLXS_MSGF(EMLXS_CONTEXT,
1610 &emlxs_init_failed_msg,
1611 "Adapter error.");
1612
1507 mbq = NULL;
1508 rval = EIO;
1509 goto failed;
1510 }
1511
1613 mbq = NULL;
1614 rval = EIO;
1615 goto failed;
1616 }
1617
1512 /*
1513 * Enable link attention interrupt
1514 */
1515 emlxs_enable_latt(hba);
1516
1517 /* Wait for link to come up */
1518 i = cfg[CFG_LINKUP_DELAY].current;
1519 while (i && (hba->state < FC_LINK_UP)) {
1520 /* Check for hardware error */
1521 if (hba->state == FC_ERROR) {
1522 EMLXS_MSGF(EMLXS_CONTEXT,
1523 &emlxs_init_failed_msg,
1524 "Adapter error.");
1525
1526 mbq = NULL;
1527 rval = EIO;
1528 goto failed;
1529 }
1530
1531 DELAYMS(1000);
1532 i--;
1533 }
1534 } else {
1535 EMLXS_STATE_CHANGE(hba, FC_LINK_DOWN_PERSIST);
1618 BUSYWAIT_MS(1000);
1619 i--;
1536 }
1537
1538 /*
1539 * The leadvile driver will now handle the FLOGI at the driver level
1540 */
1541
1542 return (0);
1543

--- 27 unchanged lines hidden (view full) ---

1571 rval = EIO;
1572 }
1573
1574 return (rval);
1575
1576} /* emlxs_sli3_online() */
1577
1578
1620 }
1621
1622 /*
1623 * The leadvile driver will now handle the FLOGI at the driver level
1624 */
1625
1626 return (0);
1627

--- 27 unchanged lines hidden (view full) ---

1655 rval = EIO;
1656 }
1657
1658 return (rval);
1659
1660} /* emlxs_sli3_online() */
1661
1662
1663/*ARGSUSED*/
1579static void
1664static void
1580emlxs_sli3_offline(emlxs_hba_t *hba)
1665emlxs_sli3_offline(emlxs_hba_t *hba, uint32_t reset_requested)
1581{
1582 /* Reverse emlxs_sli3_online */
1583
1584 /* Kill the adapter */
1585 emlxs_sli3_hba_kill(hba);
1586
1587 /* Free driver shared memory */
1588 (void) emlxs_mem_free_buffer(hba);

--- 231 unchanged lines hidden (view full) ---

1820
1821static uint32_t
1822emlxs_sli3_hba_init(emlxs_hba_t *hba)
1823{
1824 emlxs_port_t *port = &PPORT;
1825 emlxs_port_t *vport;
1826 emlxs_config_t *cfg;
1827 uint16_t i;
1666{
1667 /* Reverse emlxs_sli3_online */
1668
1669 /* Kill the adapter */
1670 emlxs_sli3_hba_kill(hba);
1671
1672 /* Free driver shared memory */
1673 (void) emlxs_mem_free_buffer(hba);

--- 231 unchanged lines hidden (view full) ---

1905
1906static uint32_t
1907emlxs_sli3_hba_init(emlxs_hba_t *hba)
1908{
1909 emlxs_port_t *port = &PPORT;
1910 emlxs_port_t *vport;
1911 emlxs_config_t *cfg;
1912 uint16_t i;
1913 VPIobj_t *vpip;
1828
1829 cfg = &CFG;
1830 i = 0;
1831
1832 /* Restart the adapter */
1833 if (emlxs_sli3_hba_reset(hba, 1, 0, 0)) {
1834 return (1);
1835 }

--- 4 unchanged lines hidden (view full) ---

1840 hba->channel_ct = FC_CT_RING;
1841 hba->chan_count = MAX_RINGS;
1842 hba->sli.sli3.ring_count = MAX_RINGS;
1843
1844 /*
1845 * WARNING: There is a max of 6 ring masks allowed
1846 */
1847 /* RING 0 - FCP */
1914
1915 cfg = &CFG;
1916 i = 0;
1917
1918 /* Restart the adapter */
1919 if (emlxs_sli3_hba_reset(hba, 1, 0, 0)) {
1920 return (1);
1921 }

--- 4 unchanged lines hidden (view full) ---

1926 hba->channel_ct = FC_CT_RING;
1927 hba->chan_count = MAX_RINGS;
1928 hba->sli.sli3.ring_count = MAX_RINGS;
1929
1930 /*
1931 * WARNING: There is a max of 6 ring masks allowed
1932 */
1933 /* RING 0 - FCP */
1848 if (hba->tgt_mode) {
1934 if (port->flag & EMLXS_TGT_ENABLED) {
1849 hba->sli.sli3.ring_masks[FC_FCP_RING] = 1;
1850 hba->sli.sli3.ring_rval[i] = FC_FCP_CMND;
1851 hba->sli.sli3.ring_rmask[i] = 0;
1935 hba->sli.sli3.ring_masks[FC_FCP_RING] = 1;
1936 hba->sli.sli3.ring_rval[i] = FC_FCP_CMND;
1937 hba->sli.sli3.ring_rmask[i] = 0;
1852 hba->sli.sli3.ring_tval[i] = FC_FCP_DATA;
1938 hba->sli.sli3.ring_tval[i] = FC_TYPE_SCSI_FCP;
1853 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1854 } else {
1855 hba->sli.sli3.ring_masks[FC_FCP_RING] = 0;
1856 }
1857
1858 hba->sli.sli3.ring[FC_FCP_RING].fc_numCiocb = SLIM_IOCB_CMD_R0_ENTRIES;
1859 hba->sli.sli3.ring[FC_FCP_RING].fc_numRiocb = SLIM_IOCB_RSP_R0_ENTRIES;
1860
1861 /* RING 1 - IP */
1862 if (cfg[CFG_NETWORK_ON].current) {
1863 hba->sli.sli3.ring_masks[FC_IP_RING] = 1;
1864 hba->sli.sli3.ring_rval[i] = FC_UNSOL_DATA; /* Unsol Data */
1865 hba->sli.sli3.ring_rmask[i] = 0xFF;
1939 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1940 } else {
1941 hba->sli.sli3.ring_masks[FC_FCP_RING] = 0;
1942 }
1943
1944 hba->sli.sli3.ring[FC_FCP_RING].fc_numCiocb = SLIM_IOCB_CMD_R0_ENTRIES;
1945 hba->sli.sli3.ring[FC_FCP_RING].fc_numRiocb = SLIM_IOCB_RSP_R0_ENTRIES;
1946
1947 /* RING 1 - IP */
1948 if (cfg[CFG_NETWORK_ON].current) {
1949 hba->sli.sli3.ring_masks[FC_IP_RING] = 1;
1950 hba->sli.sli3.ring_rval[i] = FC_UNSOL_DATA; /* Unsol Data */
1951 hba->sli.sli3.ring_rmask[i] = 0xFF;
1866 hba->sli.sli3.ring_tval[i] = FC_LLC_SNAP; /* LLC/SNAP */
1952 hba->sli.sli3.ring_tval[i] = FC_TYPE_IS8802_SNAP; /* LLC/SNAP */
1867 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1868 } else {
1869 hba->sli.sli3.ring_masks[FC_IP_RING] = 0;
1870 }
1871
1872 hba->sli.sli3.ring[FC_IP_RING].fc_numCiocb = SLIM_IOCB_CMD_R1_ENTRIES;
1873 hba->sli.sli3.ring[FC_IP_RING].fc_numRiocb = SLIM_IOCB_RSP_R1_ENTRIES;
1874
1875 /* RING 2 - ELS */
1876 hba->sli.sli3.ring_masks[FC_ELS_RING] = 1;
1877 hba->sli.sli3.ring_rval[i] = FC_ELS_REQ; /* ELS request/rsp */
1878 hba->sli.sli3.ring_rmask[i] = 0xFE;
1953 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1954 } else {
1955 hba->sli.sli3.ring_masks[FC_IP_RING] = 0;
1956 }
1957
1958 hba->sli.sli3.ring[FC_IP_RING].fc_numCiocb = SLIM_IOCB_CMD_R1_ENTRIES;
1959 hba->sli.sli3.ring[FC_IP_RING].fc_numRiocb = SLIM_IOCB_RSP_R1_ENTRIES;
1960
1961 /* RING 2 - ELS */
1962 hba->sli.sli3.ring_masks[FC_ELS_RING] = 1;
1963 hba->sli.sli3.ring_rval[i] = FC_ELS_REQ; /* ELS request/rsp */
1964 hba->sli.sli3.ring_rmask[i] = 0xFE;
1879 hba->sli.sli3.ring_tval[i] = FC_ELS_DATA; /* ELS */
1965 hba->sli.sli3.ring_tval[i] = FC_TYPE_EXTENDED_LS; /* ELS */
1880 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1881
1882 hba->sli.sli3.ring[FC_ELS_RING].fc_numCiocb = SLIM_IOCB_CMD_R2_ENTRIES;
1883 hba->sli.sli3.ring[FC_ELS_RING].fc_numRiocb = SLIM_IOCB_RSP_R2_ENTRIES;
1884
1885 /* RING 3 - CT */
1886 hba->sli.sli3.ring_masks[FC_CT_RING] = 1;
1887 hba->sli.sli3.ring_rval[i] = FC_UNSOL_CTL; /* CT request/rsp */
1888 hba->sli.sli3.ring_rmask[i] = 0xFE;
1966 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1967
1968 hba->sli.sli3.ring[FC_ELS_RING].fc_numCiocb = SLIM_IOCB_CMD_R2_ENTRIES;
1969 hba->sli.sli3.ring[FC_ELS_RING].fc_numRiocb = SLIM_IOCB_RSP_R2_ENTRIES;
1970
1971 /* RING 3 - CT */
1972 hba->sli.sli3.ring_masks[FC_CT_RING] = 1;
1973 hba->sli.sli3.ring_rval[i] = FC_UNSOL_CTL; /* CT request/rsp */
1974 hba->sli.sli3.ring_rmask[i] = 0xFE;
1889 hba->sli.sli3.ring_tval[i] = FC_CT_TYPE; /* CT */
1975 hba->sli.sli3.ring_tval[i] = FC_TYPE_FC_SERVICES; /* CT */
1890 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1891
1892 hba->sli.sli3.ring[FC_CT_RING].fc_numCiocb = SLIM_IOCB_CMD_R3_ENTRIES;
1893 hba->sli.sli3.ring[FC_CT_RING].fc_numRiocb = SLIM_IOCB_RSP_R3_ENTRIES;
1894
1895 if (i > 6) {
1896 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_attach_failed_msg,
1976 hba->sli.sli3.ring_tmask[i++] = 0xFF;
1977
1978 hba->sli.sli3.ring[FC_CT_RING].fc_numCiocb = SLIM_IOCB_CMD_R3_ENTRIES;
1979 hba->sli.sli3.ring[FC_CT_RING].fc_numRiocb = SLIM_IOCB_RSP_R3_ENTRIES;
1980
1981 if (i > 6) {
1982 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_attach_failed_msg,
1897 "emlxs_hba_init: Too many ring masks defined. cnt=%d", i);
1983 "hba_init: Too many ring masks defined. cnt=%d", i);
1898 return (1);
1899 }
1900
1901 /* Initialize all the port objects */
1984 return (1);
1985 }
1986
1987 /* Initialize all the port objects */
1902 hba->vpi_base = 0;
1903 hba->vpi_max = 0;
1904 for (i = 0; i < MAX_VPORTS; i++) {
1905 vport = &VPORT(i);
1906 vport->hba = hba;
1907 vport->vpi = i;
1988 hba->vpi_max = 0;
1989 for (i = 0; i < MAX_VPORTS; i++) {
1990 vport = &VPORT(i);
1991 vport->hba = hba;
1992 vport->vpi = i;
1908 vport->VPIobj.index = i;
1909 vport->VPIobj.VPI = i;
1910 vport->VPIobj.port = vport;
1911 vport->VPIobj.state = VPI_STATE_OFFLINE;
1993
1994 vpip = &vport->VPIobj;
1995 vpip->index = i;
1996 vpip->VPI = i;
1997 vpip->port = vport;
1998 vpip->state = VPI_STATE_OFFLINE;
1999 vport->vpip = vpip;
1912 }
1913
1914 /*
1915 * Initialize the max_node count to a default value if needed
1916 * This determines how many node objects we preallocate in the pool
1917 * The actual max_nodes will be set later based on adapter info
1918 */
1919 if (hba->max_nodes == 0) {

--- 19 unchanged lines hidden (view full) ---

1939emlxs_sli3_hba_reset(emlxs_hba_t *hba, uint32_t restart, uint32_t skip_post,
1940 uint32_t quiesce)
1941{
1942 emlxs_port_t *port = &PPORT;
1943 MAILBOX *swpmb;
1944 MAILBOX *mb;
1945 uint32_t word0;
1946 uint16_t cfg_value;
2000 }
2001
2002 /*
2003 * Initialize the max_node count to a default value if needed
2004 * This determines how many node objects we preallocate in the pool
2005 * The actual max_nodes will be set later based on adapter info
2006 */
2007 if (hba->max_nodes == 0) {

--- 19 unchanged lines hidden (view full) ---

2027emlxs_sli3_hba_reset(emlxs_hba_t *hba, uint32_t restart, uint32_t skip_post,
2028 uint32_t quiesce)
2029{
2030 emlxs_port_t *port = &PPORT;
2031 MAILBOX *swpmb;
2032 MAILBOX *mb;
2033 uint32_t word0;
2034 uint16_t cfg_value;
1947 uint32_t status;
2035 uint32_t status = 0;
1948 uint32_t status1;
1949 uint32_t status2;
1950 uint32_t i;
1951 uint32_t ready;
1952 emlxs_port_t *vport;
1953 RING *rp;
1954 emlxs_config_t *cfg = &CFG;
1955
2036 uint32_t status1;
2037 uint32_t status2;
2038 uint32_t i;
2039 uint32_t ready;
2040 emlxs_port_t *vport;
2041 RING *rp;
2042 emlxs_config_t *cfg = &CFG;
2043
1956 i = 0;
1957
1958 if (!cfg[CFG_RESET_ENABLE].current) {
1959 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_reset_failed_msg,
1960 "Adapter reset disabled.");
1961 EMLXS_STATE_CHANGE(hba, FC_ERROR);
1962
1963 return (1);
1964 }
1965

--- 20 unchanged lines hidden (view full) ---

1986
1987 hba->flag &= ~(FC_SLIM2_MODE | FC_HARDWARE_ERROR);
1988
1989 mb = FC_SLIM1_MAILBOX(hba);
1990 swpmb = (MAILBOX *)&word0;
1991
1992reset:
1993
2044 if (!cfg[CFG_RESET_ENABLE].current) {
2045 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_reset_failed_msg,
2046 "Adapter reset disabled.");
2047 EMLXS_STATE_CHANGE(hba, FC_ERROR);
2048
2049 return (1);
2050 }
2051

--- 20 unchanged lines hidden (view full) ---

2072
2073 hba->flag &= ~(FC_SLIM2_MODE | FC_HARDWARE_ERROR);
2074
2075 mb = FC_SLIM1_MAILBOX(hba);
2076 swpmb = (MAILBOX *)&word0;
2077
2078reset:
2079
2080 i = 0;
2081
1994 /* Save reset time */
1995 HBASTATS.ResetTime = hba->timer_tics;
1996
1997 if (restart) {
1998 /* First put restart command in mailbox */
1999 word0 = 0;
2000 swpmb->mbxCommand = MBX_RESTART;
2001 swpmb->mbxHc = 1;

--- 19 unchanged lines hidden (view full) ---

2021 ddi_put16(hba->pci_acc_handle,
2022 (uint16_t *)(hba->pci_addr + PCI_COMMAND_REGISTER),
2023 (uint16_t)(cfg_value & ~(CMD_PARITY_CHK | CMD_SERR_ENBL)));
2024
2025 hba->sli.sli3.hc_copy = HC_INITFF;
2026 WRITE_CSR_REG(hba, FC_HC_REG(hba), hba->sli.sli3.hc_copy);
2027
2028 /* Wait 1 msec before restoring PCI config */
2082 /* Save reset time */
2083 HBASTATS.ResetTime = hba->timer_tics;
2084
2085 if (restart) {
2086 /* First put restart command in mailbox */
2087 word0 = 0;
2088 swpmb->mbxCommand = MBX_RESTART;
2089 swpmb->mbxHc = 1;

--- 19 unchanged lines hidden (view full) ---

2109 ddi_put16(hba->pci_acc_handle,
2110 (uint16_t *)(hba->pci_addr + PCI_COMMAND_REGISTER),
2111 (uint16_t)(cfg_value & ~(CMD_PARITY_CHK | CMD_SERR_ENBL)));
2112
2113 hba->sli.sli3.hc_copy = HC_INITFF;
2114 WRITE_CSR_REG(hba, FC_HC_REG(hba), hba->sli.sli3.hc_copy);
2115
2116 /* Wait 1 msec before restoring PCI config */
2029 DELAYMS(1);
2117 BUSYWAIT_MS(1);
2030
2031 /* Restore PCI cmd register */
2032 ddi_put16(hba->pci_acc_handle,
2033 (uint16_t *)(hba->pci_addr + PCI_COMMAND_REGISTER),
2034 (uint16_t)cfg_value);
2035
2036 /* Wait 3 seconds before checking */
2118
2119 /* Restore PCI cmd register */
2120 ddi_put16(hba->pci_acc_handle,
2121 (uint16_t *)(hba->pci_addr + PCI_COMMAND_REGISTER),
2122 (uint16_t)cfg_value);
2123
2124 /* Wait 3 seconds before checking */
2037 DELAYMS(3000);
2125 BUSYWAIT_MS(3000);
2038 i += 3;
2039
2040 /* Wait for reset completion */
2041 while (i < 30) {
2042 /* Check status register to see what current state is */
2043 status = READ_CSR_REG(hba, FC_HS_REG(hba));
2044
2045 /* Check to see if any errors occurred during init */

--- 15 unchanged lines hidden (view full) ---

2061 /* Reset Done !! */
2062 goto done;
2063 }
2064
2065 /*
2066 * Check every 1 second for 15 seconds, then reset board
2067 * again (w/post), then check every 1 second for 15 * seconds.
2068 */
2126 i += 3;
2127
2128 /* Wait for reset completion */
2129 while (i < 30) {
2130 /* Check status register to see what current state is */
2131 status = READ_CSR_REG(hba, FC_HS_REG(hba));
2132
2133 /* Check to see if any errors occurred during init */

--- 15 unchanged lines hidden (view full) ---

2149 /* Reset Done !! */
2150 goto done;
2151 }
2152
2153 /*
2154 * Check every 1 second for 15 seconds, then reset board
2155 * again (w/post), then check every 1 second for 15 * seconds.
2156 */
2069 DELAYMS(1000);
2157 BUSYWAIT_MS(1000);
2070 i++;
2071
2072 /* Reset again (w/post) at 15 seconds */
2073 if (i == 15) {
2074 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
2075 "Reset failed. Retrying...");
2076
2077 goto reset;

--- 40 unchanged lines hidden (view full) ---

2118 hba->iodone_count = 0;
2119 hba->topology = 0;
2120 hba->linkspeed = 0;
2121 hba->heartbeat_active = 0;
2122 hba->discovery_timer = 0;
2123 hba->linkup_timer = 0;
2124 hba->loopback_tics = 0;
2125
2158 i++;
2159
2160 /* Reset again (w/post) at 15 seconds */
2161 if (i == 15) {
2162 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
2163 "Reset failed. Retrying...");
2164
2165 goto reset;

--- 40 unchanged lines hidden (view full) ---

2206 hba->iodone_count = 0;
2207 hba->topology = 0;
2208 hba->linkspeed = 0;
2209 hba->heartbeat_active = 0;
2210 hba->discovery_timer = 0;
2211 hba->linkup_timer = 0;
2212 hba->loopback_tics = 0;
2213
2126
2127 /* Reset the ring objects */
2128 for (i = 0; i < MAX_RINGS; i++) {
2129 rp = &hba->sli.sli3.ring[i];
2130 rp->fc_mpon = 0;
2131 rp->fc_mpoff = 0;
2132 }
2133
2134 /* Reset the port objects */

--- 25 unchanged lines hidden (view full) ---

2160} /* emlxs_sli3_hba_reset */
2161
2162
2163#define BPL_CMD 0
2164#define BPL_RESP 1
2165#define BPL_DATA 2
2166
2167static ULP_BDE64 *
2214 /* Reset the ring objects */
2215 for (i = 0; i < MAX_RINGS; i++) {
2216 rp = &hba->sli.sli3.ring[i];
2217 rp->fc_mpon = 0;
2218 rp->fc_mpoff = 0;
2219 }
2220
2221 /* Reset the port objects */

--- 25 unchanged lines hidden (view full) ---

2247} /* emlxs_sli3_hba_reset */
2248
2249
2250#define BPL_CMD 0
2251#define BPL_RESP 1
2252#define BPL_DATA 2
2253
2254static ULP_BDE64 *
2168emlxs_pkt_to_bpl(ULP_BDE64 *bpl, fc_packet_t *pkt, uint32_t bpl_type,
2169 uint8_t bdeFlags)
2255emlxs_pkt_to_bpl(fc_packet_t *pkt, ULP_BDE64 *bpl, uint32_t bpl_type)
2170{
2171 ddi_dma_cookie_t *cp;
2172 uint_t i;
2173 int32_t size;
2174 uint_t cookie_cnt;
2256{
2257 ddi_dma_cookie_t *cp;
2258 uint_t i;
2259 int32_t size;
2260 uint_t cookie_cnt;
2261 uint8_t bdeFlags;
2175
2176#if (EMLXS_MODREV >= EMLXS_MODREV3)
2177 switch (bpl_type) {
2178 case BPL_CMD:
2179 cp = pkt->pkt_cmd_cookie;
2180 cookie_cnt = pkt->pkt_cmd_cookie_cnt;
2181 size = (int32_t)pkt->pkt_cmdlen;
2262
2263#if (EMLXS_MODREV >= EMLXS_MODREV3)
2264 switch (bpl_type) {
2265 case BPL_CMD:
2266 cp = pkt->pkt_cmd_cookie;
2267 cookie_cnt = pkt->pkt_cmd_cookie_cnt;
2268 size = (int32_t)pkt->pkt_cmdlen;
2269 bdeFlags = 0;
2182 break;
2183
2184 case BPL_RESP:
2185 cp = pkt->pkt_resp_cookie;
2186 cookie_cnt = pkt->pkt_resp_cookie_cnt;
2187 size = (int32_t)pkt->pkt_rsplen;
2270 break;
2271
2272 case BPL_RESP:
2273 cp = pkt->pkt_resp_cookie;
2274 cookie_cnt = pkt->pkt_resp_cookie_cnt;
2275 size = (int32_t)pkt->pkt_rsplen;
2276 bdeFlags = BUFF_USE_RCV;
2188 break;
2189
2190
2191 case BPL_DATA:
2192 cp = pkt->pkt_data_cookie;
2193 cookie_cnt = pkt->pkt_data_cookie_cnt;
2194 size = (int32_t)pkt->pkt_datalen;
2277 break;
2278
2279
2280 case BPL_DATA:
2281 cp = pkt->pkt_data_cookie;
2282 cookie_cnt = pkt->pkt_data_cookie_cnt;
2283 size = (int32_t)pkt->pkt_datalen;
2284 bdeFlags = (pkt->pkt_tran_type == FC_PKT_FCP_READ) ?
2285 BUFF_USE_RCV : 0;
2195 break;
2286 break;
2287
2288 default:
2289 return (NULL);
2196 }
2197
2198#else
2199 switch (bpl_type) {
2200 case BPL_CMD:
2201 cp = &pkt->pkt_cmd_cookie;
2202 cookie_cnt = 1;
2203 size = (int32_t)pkt->pkt_cmdlen;
2290 }
2291
2292#else
2293 switch (bpl_type) {
2294 case BPL_CMD:
2295 cp = &pkt->pkt_cmd_cookie;
2296 cookie_cnt = 1;
2297 size = (int32_t)pkt->pkt_cmdlen;
2298 bdeFlags = 0;
2204 break;
2205
2206 case BPL_RESP:
2207 cp = &pkt->pkt_resp_cookie;
2208 cookie_cnt = 1;
2209 size = (int32_t)pkt->pkt_rsplen;
2299 break;
2300
2301 case BPL_RESP:
2302 cp = &pkt->pkt_resp_cookie;
2303 cookie_cnt = 1;
2304 size = (int32_t)pkt->pkt_rsplen;
2305 bdeFlags = BUFF_USE_RCV;
2210 break;
2211
2212
2213 case BPL_DATA:
2214 cp = &pkt->pkt_data_cookie;
2215 cookie_cnt = 1;
2216 size = (int32_t)pkt->pkt_datalen;
2306 break;
2307
2308
2309 case BPL_DATA:
2310 cp = &pkt->pkt_data_cookie;
2311 cookie_cnt = 1;
2312 size = (int32_t)pkt->pkt_datalen;
2313 bdeFlags = (pkt->pkt_tran_type == FC_PKT_FCP_READ) ?
2314 BUFF_USE_RCV : 0;
2217 break;
2315 break;
2316
2317 default:
2318 return (NULL);
2218 }
2219#endif /* >= EMLXS_MODREV3 */
2220
2221 for (i = 0; i < cookie_cnt && size > 0; i++, cp++) {
2222 bpl->addrHigh =
2223 BE_SWAP32(PADDR_HI(cp->dmac_laddress));
2224 bpl->addrLow =
2225 BE_SWAP32(PADDR_LO(cp->dmac_laddress));

--- 13 unchanged lines hidden (view full) ---

2239static uint32_t
2240emlxs_sli2_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
2241{
2242 emlxs_hba_t *hba = HBA;
2243 fc_packet_t *pkt;
2244 MATCHMAP *bmp;
2245 ULP_BDE64 *bpl;
2246 uint64_t bp;
2319 }
2320#endif /* >= EMLXS_MODREV3 */
2321
2322 for (i = 0; i < cookie_cnt && size > 0; i++, cp++) {
2323 bpl->addrHigh =
2324 BE_SWAP32(PADDR_HI(cp->dmac_laddress));
2325 bpl->addrLow =
2326 BE_SWAP32(PADDR_LO(cp->dmac_laddress));

--- 13 unchanged lines hidden (view full) ---

2340static uint32_t
2341emlxs_sli2_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
2342{
2343 emlxs_hba_t *hba = HBA;
2344 fc_packet_t *pkt;
2345 MATCHMAP *bmp;
2346 ULP_BDE64 *bpl;
2347 uint64_t bp;
2247 uint8_t bdeFlag;
2248 IOCB *iocb;
2249 IOCBQ *iocbq;
2250 CHANNEL *cp;
2348 IOCB *iocb;
2349 IOCBQ *iocbq;
2350 CHANNEL *cp;
2251 uint32_t cmd_cookie_cnt;
2252 uint32_t resp_cookie_cnt;
2253 uint32_t data_cookie_cnt;
2351 uint32_t data_cookie_cnt;
2254 uint32_t cookie_cnt;
2352 uint32_t channelno;
2255
2256 cp = sbp->channel;
2257 iocb = (IOCB *) & sbp->iocbq;
2258 pkt = PRIV2PKT(sbp);
2259
2353
2354 cp = sbp->channel;
2355 iocb = (IOCB *) & sbp->iocbq;
2356 pkt = PRIV2PKT(sbp);
2357
2260#ifdef EMLXS_SPARC
2261 /* Use FCP MEM_BPL table to get BPL buffer */
2262 bmp = hba->sli.sli3.fcp_bpl_table[sbp->iotag];
2263#else
2264 /* Use MEM_BPL pool to get BPL buffer */
2265 bmp = (MATCHMAP *) emlxs_mem_get(hba, MEM_BPL, 0);
2358 if (hba->sli.sli3.bpl_table) {
2359 bmp = hba->sli.sli3.bpl_table[sbp->iotag];
2360 } else {
2361 bmp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BPL);
2362 }
2266
2363
2267#endif
2268
2269 if (!bmp) {
2270 return (1);
2271 }
2272
2273 sbp->bmp = bmp;
2274 bpl = (ULP_BDE64 *)bmp->virt;
2275 bp = bmp->phys;
2364 if (!bmp) {
2365 return (1);
2366 }
2367
2368 sbp->bmp = bmp;
2369 bpl = (ULP_BDE64 *)bmp->virt;
2370 bp = bmp->phys;
2276 cookie_cnt = 0;
2277
2278#if (EMLXS_MODREV >= EMLXS_MODREV3)
2371
2372#if (EMLXS_MODREV >= EMLXS_MODREV3)
2279 cmd_cookie_cnt = pkt->pkt_cmd_cookie_cnt;
2280 resp_cookie_cnt = pkt->pkt_resp_cookie_cnt;
2281 data_cookie_cnt = pkt->pkt_data_cookie_cnt;
2282#else
2373 data_cookie_cnt = pkt->pkt_data_cookie_cnt;
2374#else
2283 cmd_cookie_cnt = 1;
2284 resp_cookie_cnt = 1;
2285 data_cookie_cnt = 1;
2286#endif /* >= EMLXS_MODREV3 */
2287
2288 iocbq = &sbp->iocbq;
2375 data_cookie_cnt = 1;
2376#endif /* >= EMLXS_MODREV3 */
2377
2378 iocbq = &sbp->iocbq;
2289 if (iocbq->flag & IOCB_FCP_CMD)
2290 goto fcpcmd;
2291
2379
2292 switch (cp->channelno) {
2293 case FC_FCP_RING:
2294fcpcmd:
2380 channelno = (iocbq->flag & IOCB_FCP_CMD)? FC_FCP_RING:cp->channelno;
2381 switch (channelno) {
2382 case FC_FCP_RING:
2383
2295 /* CMD payload */
2384 /* CMD payload */
2296 bpl = emlxs_pkt_to_bpl(bpl, pkt, BPL_CMD, 0);
2297 cookie_cnt = cmd_cookie_cnt;
2385 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_CMD);
2386 if (! bpl) {
2387 return (1);
2388 }
2298
2389
2299 if (pkt->pkt_tran_type != FC_PKT_OUTBOUND) {
2300 /* RSP payload */
2301 bpl =
2302 emlxs_pkt_to_bpl(bpl, pkt, BPL_RESP,
2303 BUFF_USE_RCV);
2304 cookie_cnt += resp_cookie_cnt;
2390 /* Check if response & data payloads are needed */
2391 if (pkt->pkt_tran_type == FC_PKT_OUTBOUND) {
2392 break;
2393 }
2305
2394
2306 /* DATA payload */
2307 if (pkt->pkt_datalen != 0) {
2308 bdeFlag =
2309 (pkt->pkt_tran_type ==
2310 FC_PKT_FCP_READ) ? BUFF_USE_RCV : 0;
2311 bpl =
2312 emlxs_pkt_to_bpl(bpl, pkt, BPL_DATA,
2313 bdeFlag);
2314 cookie_cnt += data_cookie_cnt;
2315 }
2395 /* RSP payload */
2396 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_RESP);
2397 if (! bpl) {
2398 return (1);
2316 }
2399 }
2317 /*
2318 * else
2319 * {
2320 * Target mode FCP status. Do nothing more.
2321 * }
2322 */
2323
2400
2401 /* Check if data payload is needed */
2402 if ((pkt->pkt_datalen == 0) ||
2403 (data_cookie_cnt == 0)) {
2404 break;
2405 }
2406
2407 /* DATA payload */
2408 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_DATA);
2409 if (! bpl) {
2410 return (1);
2411 }
2324 break;
2325
2326 case FC_IP_RING:
2327
2328 /* CMD payload */
2412 break;
2413
2414 case FC_IP_RING:
2415
2416 /* CMD payload */
2329 bpl = emlxs_pkt_to_bpl(bpl, pkt, BPL_CMD, 0);
2330 cookie_cnt = cmd_cookie_cnt;
2331
2417 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_CMD);
2418 if (! bpl) {
2419 return (1);
2420 }
2332 break;
2333
2334 case FC_ELS_RING:
2335
2336 /* CMD payload */
2421 break;
2422
2423 case FC_ELS_RING:
2424
2425 /* CMD payload */
2337 bpl = emlxs_pkt_to_bpl(bpl, pkt, BPL_CMD, 0);
2338 cookie_cnt = cmd_cookie_cnt;
2426 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_CMD);
2427 if (! bpl) {
2428 return (1);
2429 }
2339
2430
2340 /* RSP payload */
2341 if (pkt->pkt_tran_type != FC_PKT_OUTBOUND) {
2342 bpl =
2343 emlxs_pkt_to_bpl(bpl, pkt, BPL_RESP,
2344 BUFF_USE_RCV);
2345 cookie_cnt += resp_cookie_cnt;
2431 /* Check if response payload is needed */
2432 if (pkt->pkt_tran_type == FC_PKT_OUTBOUND) {
2433 break;
2346 }
2347
2434 }
2435
2436 /* RSP payload */
2437 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_RESP);
2438 if (! bpl) {
2439 return (1);
2440 }
2348 break;
2349
2441 break;
2442
2350
2351 case FC_CT_RING:
2352
2353 /* CMD payload */
2443 case FC_CT_RING:
2444
2445 /* CMD payload */
2354 bpl = emlxs_pkt_to_bpl(bpl, pkt, BPL_CMD, 0);
2355 cookie_cnt = cmd_cookie_cnt;
2446 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_CMD);
2447 if (! bpl) {
2448 return (1);
2449 }
2356
2450
2357 if ((pkt->pkt_tran_type != FC_PKT_OUTBOUND) ||
2358 (pkt->pkt_cmd_fhdr.type == EMLXS_MENLO_TYPE)) {
2359 /* RSP payload */
2360 bpl =
2361 emlxs_pkt_to_bpl(bpl, pkt, BPL_RESP,
2362 BUFF_USE_RCV);
2363 cookie_cnt += resp_cookie_cnt;
2451 /* Check if response payload is needed */
2452 if ((pkt->pkt_tran_type == FC_PKT_OUTBOUND) &&
2453 (pkt->pkt_cmd_fhdr.type != EMLXS_MENLO_TYPE)) {
2454 break;
2364 }
2365
2455 }
2456
2457 /* RSP payload */
2458 bpl = emlxs_pkt_to_bpl(pkt, bpl, BPL_RESP);
2459 if (! bpl) {
2460 return (1);
2461 }
2366 break;
2367
2368 }
2369
2370 iocb->un.genreq64.bdl.bdeFlags = BUFF_TYPE_BDL;
2371 iocb->un.genreq64.bdl.addrHigh = PADDR_HI(bp);
2372 iocb->un.genreq64.bdl.addrLow = PADDR_LO(bp);
2462 break;
2463
2464 }
2465
2466 iocb->un.genreq64.bdl.bdeFlags = BUFF_TYPE_BDL;
2467 iocb->un.genreq64.bdl.addrHigh = PADDR_HI(bp);
2468 iocb->un.genreq64.bdl.addrLow = PADDR_LO(bp);
2373 iocb->un.genreq64.bdl.bdeSize = cookie_cnt * sizeof (ULP_BDE64);
2374
2469 iocb->un.genreq64.bdl.bdeSize =
2470 (uint32_t)(((uintptr_t)bpl - (uintptr_t)bmp->virt) & 0xFFFFFFFF);
2375 iocb->ULPBDECOUNT = 1;
2376 iocb->ULPLE = 1;
2377
2378 return (0);
2379
2380} /* emlxs_sli2_bde_setup */
2381
2382
2383static uint32_t
2384emlxs_sli3_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
2385{
2386 ddi_dma_cookie_t *cp_cmd;
2387 ddi_dma_cookie_t *cp_resp;
2388 ddi_dma_cookie_t *cp_data;
2389 fc_packet_t *pkt;
2390 ULP_BDE64 *bde;
2391 int data_cookie_cnt;
2392 uint32_t i;
2471 iocb->ULPBDECOUNT = 1;
2472 iocb->ULPLE = 1;
2473
2474 return (0);
2475
2476} /* emlxs_sli2_bde_setup */
2477
2478
2479static uint32_t
2480emlxs_sli3_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
2481{
2482 ddi_dma_cookie_t *cp_cmd;
2483 ddi_dma_cookie_t *cp_resp;
2484 ddi_dma_cookie_t *cp_data;
2485 fc_packet_t *pkt;
2486 ULP_BDE64 *bde;
2487 int data_cookie_cnt;
2488 uint32_t i;
2489 uint32_t channelno;
2393 IOCB *iocb;
2394 IOCBQ *iocbq;
2395 CHANNEL *cp;
2396
2490 IOCB *iocb;
2491 IOCBQ *iocbq;
2492 CHANNEL *cp;
2493
2397 cp = sbp->channel;
2398 iocb = (IOCB *) & sbp->iocbq;
2399 pkt = PRIV2PKT(sbp);
2400#if (EMLXS_MODREV >= EMLXS_MODREV3)
2401 if ((pkt->pkt_cmd_cookie_cnt > 1) ||
2402 (pkt->pkt_resp_cookie_cnt > 1) ||
2403 ((pkt->pkt_cmd_cookie_cnt + pkt->pkt_resp_cookie_cnt +
2404 pkt->pkt_data_cookie_cnt) > SLI3_MAX_BDE)) {
2405 i = emlxs_sli2_bde_setup(port, sbp);
2406 return (i);
2407 }
2408
2494 pkt = PRIV2PKT(sbp);
2495#if (EMLXS_MODREV >= EMLXS_MODREV3)
2496 if ((pkt->pkt_cmd_cookie_cnt > 1) ||
2497 (pkt->pkt_resp_cookie_cnt > 1) ||
2498 ((pkt->pkt_cmd_cookie_cnt + pkt->pkt_resp_cookie_cnt +
2499 pkt->pkt_data_cookie_cnt) > SLI3_MAX_BDE)) {
2500 i = emlxs_sli2_bde_setup(port, sbp);
2501 return (i);
2502 }
2503
2409#endif /* >= EMLXS_MODREV3 */
2410
2411#if (EMLXS_MODREV >= EMLXS_MODREV3)
2412 cp_cmd = pkt->pkt_cmd_cookie;
2413 cp_resp = pkt->pkt_resp_cookie;
2414 cp_data = pkt->pkt_data_cookie;
2415 data_cookie_cnt = pkt->pkt_data_cookie_cnt;
2416#else
2417 cp_cmd = &pkt->pkt_cmd_cookie;
2418 cp_resp = &pkt->pkt_resp_cookie;
2419 cp_data = &pkt->pkt_data_cookie;
2420 data_cookie_cnt = 1;
2421#endif /* >= EMLXS_MODREV3 */
2422
2504 cp_cmd = pkt->pkt_cmd_cookie;
2505 cp_resp = pkt->pkt_resp_cookie;
2506 cp_data = pkt->pkt_data_cookie;
2507 data_cookie_cnt = pkt->pkt_data_cookie_cnt;
2508#else
2509 cp_cmd = &pkt->pkt_cmd_cookie;
2510 cp_resp = &pkt->pkt_resp_cookie;
2511 cp_data = &pkt->pkt_data_cookie;
2512 data_cookie_cnt = 1;
2513#endif /* >= EMLXS_MODREV3 */
2514
2515 cp = sbp->channel;
2516 iocbq = &sbp->iocbq;
2517 iocb = (IOCB *)iocbq;
2423 iocb->unsli3.ext_iocb.ebde_count = 0;
2424
2518 iocb->unsli3.ext_iocb.ebde_count = 0;
2519
2425 iocbq = &sbp->iocbq;
2426 if (iocbq->flag & IOCB_FCP_CMD)
2427 goto fcpcmd;
2428
2429 switch (cp->channelno) {
2520 channelno = (iocbq->flag & IOCB_FCP_CMD)? FC_FCP_RING:cp->channelno;
2521 switch (channelno) {
2430 case FC_FCP_RING:
2522 case FC_FCP_RING:
2431fcpcmd:
2432 /* CMD payload */
2433 iocb->un.fcpi64.bdl.addrHigh =
2434 PADDR_HI(cp_cmd->dmac_laddress);
2435 iocb->un.fcpi64.bdl.addrLow =
2436 PADDR_LO(cp_cmd->dmac_laddress);
2437 iocb->un.fcpi64.bdl.bdeSize = pkt->pkt_cmdlen;
2438 iocb->un.fcpi64.bdl.bdeFlags = 0;
2439
2523 /* CMD payload */
2524 iocb->un.fcpi64.bdl.addrHigh =
2525 PADDR_HI(cp_cmd->dmac_laddress);
2526 iocb->un.fcpi64.bdl.addrLow =
2527 PADDR_LO(cp_cmd->dmac_laddress);
2528 iocb->un.fcpi64.bdl.bdeSize = pkt->pkt_cmdlen;
2529 iocb->un.fcpi64.bdl.bdeFlags = 0;
2530
2440 if (pkt->pkt_tran_type != FC_PKT_OUTBOUND) {
2441 /* RSP payload */
2442 iocb->unsli3.ext_iocb.ebde1.addrHigh =
2443 PADDR_HI(cp_resp->dmac_laddress);
2444 iocb->unsli3.ext_iocb.ebde1.addrLow =
2445 PADDR_LO(cp_resp->dmac_laddress);
2446 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeSize =
2447 pkt->pkt_rsplen;
2448 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeFlags = 0;
2449 iocb->unsli3.ext_iocb.ebde_count = 1;
2531 /* Check if a response & data payload are needed */
2532 if (pkt->pkt_tran_type == FC_PKT_OUTBOUND) {
2533 break;
2534 }
2450
2535
2451 /* DATA payload */
2452 if (pkt->pkt_datalen != 0) {
2453 bde =
2454 (ULP_BDE64 *)&iocb->unsli3.ext_iocb.
2455 ebde2;
2456 for (i = 0; i < data_cookie_cnt; i++) {
2457 bde->addrHigh =
2458 PADDR_HI(cp_data->
2459 dmac_laddress);
2460 bde->addrLow =
2461 PADDR_LO(cp_data->
2462 dmac_laddress);
2463 bde->tus.f.bdeSize =
2464 cp_data->dmac_size;
2465 bde->tus.f.bdeFlags = 0;
2466 cp_data++;
2467 bde++;
2468 }
2469 iocb->unsli3.ext_iocb.ebde_count +=
2470 data_cookie_cnt;
2471 }
2536 /* RSP payload */
2537 iocb->unsli3.ext_iocb.ebde1.addrHigh =
2538 PADDR_HI(cp_resp->dmac_laddress);
2539 iocb->unsli3.ext_iocb.ebde1.addrLow =
2540 PADDR_LO(cp_resp->dmac_laddress);
2541 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeSize = pkt->pkt_rsplen;
2542 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeFlags = 0;
2543 iocb->unsli3.ext_iocb.ebde_count = 1;
2544
2545 /* Check if a data payload is needed */
2546 if ((pkt->pkt_datalen == 0) ||
2547 (data_cookie_cnt == 0)) {
2548 break;
2472 }
2549 }
2473 /*
2474 * else
2475 * {
2476 * Target mode FCP status. Do nothing more.
2477 * }
2478 */
2479
2550
2551 /* DATA payload */
2552 bde = (ULP_BDE64 *)&iocb->unsli3.ext_iocb.ebde2;
2553 for (i = 0; i < data_cookie_cnt; i++) {
2554 bde->addrHigh = PADDR_HI(cp_data->dmac_laddress);
2555 bde->addrLow = PADDR_LO(cp_data->dmac_laddress);
2556 bde->tus.f.bdeSize = cp_data->dmac_size;
2557 bde->tus.f.bdeFlags = 0;
2558 cp_data++;
2559 bde++;
2560 }
2561 iocb->unsli3.ext_iocb.ebde_count += data_cookie_cnt;
2562
2480 break;
2481
2482 case FC_IP_RING:
2563 break;
2564
2565 case FC_IP_RING:
2483
2484 /* CMD payload */
2485 iocb->un.xseq64.bdl.addrHigh =
2486 PADDR_HI(cp_cmd->dmac_laddress);
2487 iocb->un.xseq64.bdl.addrLow =
2488 PADDR_LO(cp_cmd->dmac_laddress);
2489 iocb->un.xseq64.bdl.bdeSize = pkt->pkt_cmdlen;
2490 iocb->un.xseq64.bdl.bdeFlags = 0;
2491

--- 4 unchanged lines hidden (view full) ---

2496 /* CMD payload */
2497 iocb->un.elsreq64.bdl.addrHigh =
2498 PADDR_HI(cp_cmd->dmac_laddress);
2499 iocb->un.elsreq64.bdl.addrLow =
2500 PADDR_LO(cp_cmd->dmac_laddress);
2501 iocb->un.elsreq64.bdl.bdeSize = pkt->pkt_cmdlen;
2502 iocb->un.elsreq64.bdl.bdeFlags = 0;
2503
2566 /* CMD payload */
2567 iocb->un.xseq64.bdl.addrHigh =
2568 PADDR_HI(cp_cmd->dmac_laddress);
2569 iocb->un.xseq64.bdl.addrLow =
2570 PADDR_LO(cp_cmd->dmac_laddress);
2571 iocb->un.xseq64.bdl.bdeSize = pkt->pkt_cmdlen;
2572 iocb->un.xseq64.bdl.bdeFlags = 0;
2573

--- 4 unchanged lines hidden (view full) ---

2578 /* CMD payload */
2579 iocb->un.elsreq64.bdl.addrHigh =
2580 PADDR_HI(cp_cmd->dmac_laddress);
2581 iocb->un.elsreq64.bdl.addrLow =
2582 PADDR_LO(cp_cmd->dmac_laddress);
2583 iocb->un.elsreq64.bdl.bdeSize = pkt->pkt_cmdlen;
2584 iocb->un.elsreq64.bdl.bdeFlags = 0;
2585
2504 /* RSP payload */
2505 if (pkt->pkt_tran_type != FC_PKT_OUTBOUND) {
2506 iocb->unsli3.ext_iocb.ebde1.addrHigh =
2507 PADDR_HI(cp_resp->dmac_laddress);
2508 iocb->unsli3.ext_iocb.ebde1.addrLow =
2509 PADDR_LO(cp_resp->dmac_laddress);
2510 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeSize =
2511 pkt->pkt_rsplen;
2512 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeFlags =
2513 BUFF_USE_RCV;
2514 iocb->unsli3.ext_iocb.ebde_count = 1;
2586 /* Check if a response payload is needed */
2587 if (pkt->pkt_tran_type == FC_PKT_OUTBOUND) {
2588 break;
2515 }
2516
2589 }
2590
2591 /* RSP payload */
2592 iocb->unsli3.ext_iocb.ebde1.addrHigh =
2593 PADDR_HI(cp_resp->dmac_laddress);
2594 iocb->unsli3.ext_iocb.ebde1.addrLow =
2595 PADDR_LO(cp_resp->dmac_laddress);
2596 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeSize = pkt->pkt_rsplen;
2597 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeFlags = BUFF_USE_RCV;
2598 iocb->unsli3.ext_iocb.ebde_count = 1;
2517 break;
2518
2519 case FC_CT_RING:
2520
2521 /* CMD payload */
2522 iocb->un.genreq64.bdl.addrHigh =
2523 PADDR_HI(cp_cmd->dmac_laddress);
2524 iocb->un.genreq64.bdl.addrLow =
2525 PADDR_LO(cp_cmd->dmac_laddress);
2526 iocb->un.genreq64.bdl.bdeSize = pkt->pkt_cmdlen;
2527 iocb->un.genreq64.bdl.bdeFlags = 0;
2528
2599 break;
2600
2601 case FC_CT_RING:
2602
2603 /* CMD payload */
2604 iocb->un.genreq64.bdl.addrHigh =
2605 PADDR_HI(cp_cmd->dmac_laddress);
2606 iocb->un.genreq64.bdl.addrLow =
2607 PADDR_LO(cp_cmd->dmac_laddress);
2608 iocb->un.genreq64.bdl.bdeSize = pkt->pkt_cmdlen;
2609 iocb->un.genreq64.bdl.bdeFlags = 0;
2610
2529 if ((pkt->pkt_tran_type != FC_PKT_OUTBOUND) ||
2530 (pkt->pkt_cmd_fhdr.type == EMLXS_MENLO_TYPE)) {
2531 /* RSP payload */
2532 iocb->unsli3.ext_iocb.ebde1.addrHigh =
2533 PADDR_HI(cp_resp->dmac_laddress);
2534 iocb->unsli3.ext_iocb.ebde1.addrLow =
2535 PADDR_LO(cp_resp->dmac_laddress);
2536 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeSize =
2537 pkt->pkt_rsplen;
2538 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeFlags =
2539 BUFF_USE_RCV;
2540 iocb->unsli3.ext_iocb.ebde_count = 1;
2611 /* Check if a response payload is needed */
2612 if ((pkt->pkt_tran_type == FC_PKT_OUTBOUND) &&
2613 (pkt->pkt_cmd_fhdr.type != EMLXS_MENLO_TYPE)) {
2614 break;
2541 }
2542
2615 }
2616
2617 /* RSP payload */
2618 iocb->unsli3.ext_iocb.ebde1.addrHigh =
2619 PADDR_HI(cp_resp->dmac_laddress);
2620 iocb->unsli3.ext_iocb.ebde1.addrLow =
2621 PADDR_LO(cp_resp->dmac_laddress);
2622 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeSize = pkt->pkt_rsplen;
2623 iocb->unsli3.ext_iocb.ebde1.tus.f.bdeFlags = BUFF_USE_RCV;
2624 iocb->unsli3.ext_iocb.ebde_count = 1;
2543 break;
2544 }
2545
2546 iocb->ULPBDECOUNT = 0;
2547 iocb->ULPLE = 0;
2548
2549 return (0);
2550

--- 8 unchanged lines hidden (view full) ---

2559{
2560 emlxs_hba_t *hba = HBA;
2561 scsi_task_t *fct_task;
2562 MATCHMAP *bmp;
2563 ULP_BDE64 *bpl;
2564 uint64_t bp;
2565 uint8_t bdeFlags;
2566 IOCB *iocb;
2625 break;
2626 }
2627
2628 iocb->ULPBDECOUNT = 0;
2629 iocb->ULPLE = 0;
2630
2631 return (0);
2632

--- 8 unchanged lines hidden (view full) ---

2641{
2642 emlxs_hba_t *hba = HBA;
2643 scsi_task_t *fct_task;
2644 MATCHMAP *bmp;
2645 ULP_BDE64 *bpl;
2646 uint64_t bp;
2647 uint8_t bdeFlags;
2648 IOCB *iocb;
2567 uint32_t resid;
2568 uint32_t count;
2569 uint32_t size;
2649 uint32_t size;
2570 uint32_t sgllen;
2571 struct stmf_sglist_ent *sgl;
2572 emlxs_fct_dmem_bctl_t *bctl;
2650 MATCHMAP *mp;
2573
2651
2574
2575 iocb = (IOCB *)&sbp->iocbq;
2652 iocb = (IOCB *)&sbp->iocbq.iocb;
2576 sbp->bmp = NULL;
2577
2578 if (!sbp->fct_buf) {
2579 iocb->un.fcpt64.bdl.addrHigh = 0;
2580 iocb->un.fcpt64.bdl.addrLow = 0;
2581 iocb->un.fcpt64.bdl.bdeSize = 0;
2582 iocb->un.fcpt64.bdl.bdeFlags = 0;
2583 iocb->un.fcpt64.fcpt_Offset = 0;
2584 iocb->un.fcpt64.fcpt_Length = 0;
2585 iocb->ULPBDECOUNT = 0;
2586 iocb->ULPLE = 1;
2587 return (0);
2588 }
2653 sbp->bmp = NULL;
2654
2655 if (!sbp->fct_buf) {
2656 iocb->un.fcpt64.bdl.addrHigh = 0;
2657 iocb->un.fcpt64.bdl.addrLow = 0;
2658 iocb->un.fcpt64.bdl.bdeSize = 0;
2659 iocb->un.fcpt64.bdl.bdeFlags = 0;
2660 iocb->un.fcpt64.fcpt_Offset = 0;
2661 iocb->un.fcpt64.fcpt_Length = 0;
2662 iocb->ULPBDECOUNT = 0;
2663 iocb->ULPLE = 1;
2664 return (0);
2665 }
2589#ifdef EMLXS_SPARC
2590 /* Use FCP MEM_BPL table to get BPL buffer */
2591 bmp = hba->sli.sli3.fcp_bpl_table[sbp->iotag];
2592#else
2593 /* Use MEM_BPL pool to get BPL buffer */
2594 bmp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BPL, 0);
2595#endif /* EMLXS_SPARC */
2596
2666
2667 if (hba->sli.sli3.bpl_table) {
2668 bmp = hba->sli.sli3.bpl_table[sbp->iotag];
2669 } else {
2670 bmp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BPL);
2671 }
2672
2597 if (!bmp) {
2598 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_error_msg,
2673 if (!bmp) {
2674 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_error_msg,
2599 "emlxs_fct_sli2_bde_setup: Unable to BPL buffer. iotag=%x",
2675 "fct_sli2_bde_setup: Unable to BPL buffer. iotag=%d",
2600 sbp->iotag);
2601
2602 iocb->un.fcpt64.bdl.addrHigh = 0;
2603 iocb->un.fcpt64.bdl.addrLow = 0;
2604 iocb->un.fcpt64.bdl.bdeSize = 0;
2605 iocb->un.fcpt64.bdl.bdeFlags = 0;
2606 iocb->un.fcpt64.fcpt_Offset = 0;
2607 iocb->un.fcpt64.fcpt_Length = 0;
2608 iocb->ULPBDECOUNT = 0;
2609 iocb->ULPLE = 1;
2610 return (1);
2611 }
2612
2613 bpl = (ULP_BDE64 *)bmp->virt;
2614 bp = bmp->phys;
2615
2676 sbp->iotag);
2677
2678 iocb->un.fcpt64.bdl.addrHigh = 0;
2679 iocb->un.fcpt64.bdl.addrLow = 0;
2680 iocb->un.fcpt64.bdl.bdeSize = 0;
2681 iocb->un.fcpt64.bdl.bdeFlags = 0;
2682 iocb->un.fcpt64.fcpt_Offset = 0;
2683 iocb->un.fcpt64.fcpt_Length = 0;
2684 iocb->ULPBDECOUNT = 0;
2685 iocb->ULPLE = 1;
2686 return (1);
2687 }
2688
2689 bpl = (ULP_BDE64 *)bmp->virt;
2690 bp = bmp->phys;
2691
2616
2617 fct_task = (scsi_task_t *)sbp->fct_cmd->cmd_specific;
2618
2619 size = sbp->fct_buf->db_data_size;
2692 fct_task = (scsi_task_t *)sbp->fct_cmd->cmd_specific;
2693
2694 size = sbp->fct_buf->db_data_size;
2620 count = sbp->fct_buf->db_sglist_length;
2621 bctl = (emlxs_fct_dmem_bctl_t *)sbp->fct_buf->db_port_private;
2695 mp = (MATCHMAP *)sbp->fct_buf->db_port_private;
2622
2623 bdeFlags = (fct_task->task_flags & TF_WRITE_DATA) ? BUFF_USE_RCV : 0;
2696
2697 bdeFlags = (fct_task->task_flags & TF_WRITE_DATA) ? BUFF_USE_RCV : 0;
2624 sgl = sbp->fct_buf->db_sglist;
2625 resid = size;
2626
2627 /* Init the buffer list */
2698
2699 /* Init the buffer list */
2628 for (sgllen = 0; sgllen < count && resid > 0; sgllen++) {
2629 bpl->addrHigh =
2630 BE_SWAP32(PADDR_HI(bctl->bctl_dev_addr));
2631 bpl->addrLow =
2632 BE_SWAP32(PADDR_LO(bctl->bctl_dev_addr));
2633 bpl->tus.f.bdeSize = MIN(resid, sgl->seg_length);
2634 bpl->tus.f.bdeFlags = bdeFlags;
2635 bpl->tus.w = BE_SWAP32(bpl->tus.w);
2636 bpl++;
2700 bpl->addrHigh = BE_SWAP32(PADDR_HI(mp->phys));
2701 bpl->addrLow = BE_SWAP32(PADDR_LO(mp->phys));
2702 bpl->tus.f.bdeSize = size;
2703 bpl->tus.f.bdeFlags = bdeFlags;
2704 bpl->tus.w = BE_SWAP32(bpl->tus.w);
2637
2705
2638 resid -= MIN(resid, sgl->seg_length);
2639 sgl++;
2640 }
2641
2642 /* Init the IOCB */
2643 iocb->un.fcpt64.bdl.addrHigh = PADDR_HI(bp);
2644 iocb->un.fcpt64.bdl.addrLow = PADDR_LO(bp);
2706 /* Init the IOCB */
2707 iocb->un.fcpt64.bdl.addrHigh = PADDR_HI(bp);
2708 iocb->un.fcpt64.bdl.addrLow = PADDR_LO(bp);
2645 iocb->un.fcpt64.bdl.bdeSize = sgllen * sizeof (ULP_BDE64);
2709 iocb->un.fcpt64.bdl.bdeSize = sizeof (ULP_BDE64);
2646 iocb->un.fcpt64.bdl.bdeFlags = BUFF_TYPE_BDL;
2647
2648 iocb->un.fcpt64.fcpt_Length =
2649 (fct_task->task_flags & TF_WRITE_DATA) ? size : 0;
2650 iocb->un.fcpt64.fcpt_Offset = 0;
2651
2652 iocb->ULPBDECOUNT = 1;
2653 iocb->ULPLE = 1;

--- 6 unchanged lines hidden (view full) ---

2660
2661
2662#ifdef SFCT_SUPPORT
2663/*ARGSUSED*/
2664static uint32_t
2665emlxs_sli3_fct_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
2666{
2667 scsi_task_t *fct_task;
2710 iocb->un.fcpt64.bdl.bdeFlags = BUFF_TYPE_BDL;
2711
2712 iocb->un.fcpt64.fcpt_Length =
2713 (fct_task->task_flags & TF_WRITE_DATA) ? size : 0;
2714 iocb->un.fcpt64.fcpt_Offset = 0;
2715
2716 iocb->ULPBDECOUNT = 1;
2717 iocb->ULPLE = 1;

--- 6 unchanged lines hidden (view full) ---

2724
2725
2726#ifdef SFCT_SUPPORT
2727/*ARGSUSED*/
2728static uint32_t
2729emlxs_sli3_fct_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
2730{
2731 scsi_task_t *fct_task;
2668 ULP_BDE64 *bde;
2669 IOCB *iocb;
2732 IOCB *iocb;
2670 uint32_t size;
2671 uint32_t count;
2672 uint32_t sgllen;
2673 int32_t resid;
2674 struct stmf_sglist_ent *sgl;
2733 MATCHMAP *mp;
2675 uint32_t bdeFlags;
2734 uint32_t bdeFlags;
2676 emlxs_fct_dmem_bctl_t *bctl;
2735 uint32_t size;
2677
2678 iocb = (IOCB *)&sbp->iocbq;
2679
2680 if (!sbp->fct_buf) {
2681 iocb->un.fcpt64.bdl.addrHigh = 0;
2682 iocb->un.fcpt64.bdl.addrLow = 0;
2683 iocb->un.fcpt64.bdl.bdeSize = 0;
2684 iocb->un.fcpt64.bdl.bdeFlags = 0;
2685 iocb->un.fcpt64.fcpt_Offset = 0;
2686 iocb->un.fcpt64.fcpt_Length = 0;
2687 iocb->ULPBDECOUNT = 0;
2688 iocb->ULPLE = 0;
2689 iocb->unsli3.ext_iocb.ebde_count = 0;
2690 return (0);
2691 }
2692
2693 fct_task = (scsi_task_t *)sbp->fct_cmd->cmd_specific;
2694
2695 size = sbp->fct_buf->db_data_size;
2736
2737 iocb = (IOCB *)&sbp->iocbq;
2738
2739 if (!sbp->fct_buf) {
2740 iocb->un.fcpt64.bdl.addrHigh = 0;
2741 iocb->un.fcpt64.bdl.addrLow = 0;
2742 iocb->un.fcpt64.bdl.bdeSize = 0;
2743 iocb->un.fcpt64.bdl.bdeFlags = 0;
2744 iocb->un.fcpt64.fcpt_Offset = 0;
2745 iocb->un.fcpt64.fcpt_Length = 0;
2746 iocb->ULPBDECOUNT = 0;
2747 iocb->ULPLE = 0;
2748 iocb->unsli3.ext_iocb.ebde_count = 0;
2749 return (0);
2750 }
2751
2752 fct_task = (scsi_task_t *)sbp->fct_cmd->cmd_specific;
2753
2754 size = sbp->fct_buf->db_data_size;
2696 count = sbp->fct_buf->db_sglist_length;
2697 bctl = (emlxs_fct_dmem_bctl_t *)sbp->fct_buf->db_port_private;
2755 mp = (MATCHMAP *)sbp->fct_buf->db_port_private;
2698
2699 bdeFlags = (fct_task->task_flags & TF_WRITE_DATA) ? BUFF_USE_RCV : 0;
2756
2757 bdeFlags = (fct_task->task_flags & TF_WRITE_DATA) ? BUFF_USE_RCV : 0;
2700 sgl = sbp->fct_buf->db_sglist;
2701 resid = size;
2702
2703 /* Init first BDE */
2758
2759 /* Init first BDE */
2704 iocb->un.fcpt64.bdl.addrHigh = PADDR_HI(bctl->bctl_dev_addr);
2705 iocb->un.fcpt64.bdl.addrLow = PADDR_LO(bctl->bctl_dev_addr);
2706 iocb->un.fcpt64.bdl.bdeSize = MIN(resid, sgl->seg_length);
2760 iocb->un.fcpt64.bdl.addrHigh = PADDR_HI(mp->phys);
2761 iocb->un.fcpt64.bdl.addrLow = PADDR_LO(mp->phys);
2762 iocb->un.fcpt64.bdl.bdeSize = size;
2707 iocb->un.fcpt64.bdl.bdeFlags = bdeFlags;
2763 iocb->un.fcpt64.bdl.bdeFlags = bdeFlags;
2708 resid -= MIN(resid, sgl->seg_length);
2709 sgl++;
2710
2764
2711 /* Init remaining BDE's */
2712 bde = (ULP_BDE64 *)&iocb->unsli3.ext_iocb.ebde1;
2713 for (sgllen = 1; sgllen < count && resid > 0; sgllen++) {
2714 bde->addrHigh = PADDR_HI(bctl->bctl_dev_addr);
2715 bde->addrLow = PADDR_LO(bctl->bctl_dev_addr);
2716 bde->tus.f.bdeSize = MIN(resid, sgl->seg_length);
2717 bde->tus.f.bdeFlags = bdeFlags;
2718 bde++;
2719
2720 resid -= MIN(resid, sgl->seg_length);
2721 sgl++;
2722 }
2723
2724 iocb->unsli3.ext_iocb.ebde_count = sgllen - 1;
2765 iocb->unsli3.ext_iocb.ebde_count = 0;
2725 iocb->un.fcpt64.fcpt_Length =
2726 (fct_task->task_flags & TF_WRITE_DATA) ? size : 0;
2727 iocb->un.fcpt64.fcpt_Offset = 0;
2728
2729 iocb->ULPBDECOUNT = 0;
2730 iocb->ULPLE = 0;
2731
2732 return (0);

--- 15 unchanged lines hidden (view full) ---

2748 uint32_t nextIdx;
2749 uint32_t status;
2750 void *ioa2;
2751 off_t offset;
2752 uint32_t count = 0;
2753 uint32_t flag;
2754 uint32_t channelno;
2755 int32_t throttle;
2766 iocb->un.fcpt64.fcpt_Length =
2767 (fct_task->task_flags & TF_WRITE_DATA) ? size : 0;
2768 iocb->un.fcpt64.fcpt_Offset = 0;
2769
2770 iocb->ULPBDECOUNT = 0;
2771 iocb->ULPLE = 0;
2772
2773 return (0);

--- 15 unchanged lines hidden (view full) ---

2789 uint32_t nextIdx;
2790 uint32_t status;
2791 void *ioa2;
2792 off_t offset;
2793 uint32_t count = 0;
2794 uint32_t flag;
2795 uint32_t channelno;
2796 int32_t throttle;
2797#ifdef NODE_THROTTLE_SUPPORT
2798 int32_t node_throttle;
2799 NODELIST *marked_node = NULL;
2800#endif /* NODE_THROTTLE_SUPPORT */
2756
2757 channelno = cp->channelno;
2758 rp = (RING *)cp->iopath;
2759
2760 throttle = 0;
2761
2762 /* Check if FCP ring and adapter is not ready */
2763 /* We may use any ring for FCP_CMD */
2764 if (iocbq && (iocbq->flag & IOCB_FCP_CMD) && (hba->state != FC_READY)) {
2765 if (!(iocbq->flag & IOCB_SPECIAL) || !iocbq->port ||
2801
2802 channelno = cp->channelno;
2803 rp = (RING *)cp->iopath;
2804
2805 throttle = 0;
2806
2807 /* Check if FCP ring and adapter is not ready */
2808 /* We may use any ring for FCP_CMD */
2809 if (iocbq && (iocbq->flag & IOCB_FCP_CMD) && (hba->state != FC_READY)) {
2810 if (!(iocbq->flag & IOCB_SPECIAL) || !iocbq->port ||
2766 !(((emlxs_port_t *)iocbq->port)->tgt_mode)) {
2811 (((emlxs_port_t *)iocbq->port)->mode == MODE_INITIATOR)) {
2767 emlxs_tx_put(iocbq, 1);
2768 return;
2769 }
2770 }
2771
2772 /* Attempt to acquire CMD_RING lock */
2773 if (mutex_tryenter(&EMLXS_CMD_RING_LOCK(channelno)) == 0) {
2774 /* Queue it for later */

--- 93 unchanged lines hidden (view full) ---

2868 iocbq = emlxs_tx_get(cp, 1);
2869 }
2870
2871sendit:
2872 count = 0;
2873
2874 /* Process each iocbq */
2875 while (iocbq) {
2812 emlxs_tx_put(iocbq, 1);
2813 return;
2814 }
2815 }
2816
2817 /* Attempt to acquire CMD_RING lock */
2818 if (mutex_tryenter(&EMLXS_CMD_RING_LOCK(channelno)) == 0) {
2819 /* Queue it for later */

--- 93 unchanged lines hidden (view full) ---

2913 iocbq = emlxs_tx_get(cp, 1);
2914 }
2915
2916sendit:
2917 count = 0;
2918
2919 /* Process each iocbq */
2920 while (iocbq) {
2876
2877 sbp = iocbq->sbp;
2921 sbp = iocbq->sbp;
2922
2923#ifdef NODE_THROTTLE_SUPPORT
2924 if (sbp && sbp->node && sbp->node->io_throttle) {
2925 node_throttle = sbp->node->io_throttle -
2926 sbp->node->io_active;
2927 if (node_throttle <= 0) {
2928 /* Node is busy */
2929 /* Queue this iocb and get next iocb from */
2930 /* channel */
2931
2932 if (!marked_node) {
2933 marked_node = sbp->node;
2934 }
2935
2936 mutex_enter(&EMLXS_TX_CHANNEL_LOCK);
2937 emlxs_tx_put(iocbq, 0);
2938
2939 if (cp->nodeq.q_first == marked_node) {
2940 mutex_exit(&EMLXS_TX_CHANNEL_LOCK);
2941 goto busy;
2942 }
2943
2944 iocbq = emlxs_tx_get(cp, 0);
2945 mutex_exit(&EMLXS_TX_CHANNEL_LOCK);
2946 continue;
2947 }
2948 }
2949 marked_node = 0;
2950#endif /* NODE_THROTTLE_SUPPORT */
2951
2878 if (sbp && (sbp->pkt_flags & PACKET_DELAY_REQUIRED)) {
2879 /*
2880 * Update adapter if needed, since we are about to
2881 * delay here
2882 */
2883 if (count) {
2884 count = 0;
2885

--- 189 unchanged lines hidden (view full) ---

3075 uint32_t tmo)
3076{
3077 emlxs_port_t *port;
3078 SLIM2 *slim2p = (SLIM2 *)hba->sli.sli3.slim2.virt;
3079 MAILBOX *mbox;
3080 MAILBOX *mb;
3081 volatile uint32_t word0;
3082 volatile uint32_t ldata;
2952 if (sbp && (sbp->pkt_flags & PACKET_DELAY_REQUIRED)) {
2953 /*
2954 * Update adapter if needed, since we are about to
2955 * delay here
2956 */
2957 if (count) {
2958 count = 0;
2959

--- 189 unchanged lines hidden (view full) ---

3149 uint32_t tmo)
3150{
3151 emlxs_port_t *port;
3152 SLIM2 *slim2p = (SLIM2 *)hba->sli.sli3.slim2.virt;
3153 MAILBOX *mbox;
3154 MAILBOX *mb;
3155 volatile uint32_t word0;
3156 volatile uint32_t ldata;
3083 uint32_t ha_copy;
3084 off_t offset;
3085 MATCHMAP *mbox_bp;
3086 uint32_t tmo_local;
3087 MAILBOX *swpmb;
3088
3089 if (!mbq->port) {
3090 mbq->port = &PPORT;
3091 }

--- 47 unchanged lines hidden (view full) ---

3139 if (hba->flag & FC_HARDWARE_ERROR) {
3140 mb->mbxStatus = (hba->flag & FC_OVERTEMP_EVENT) ?
3141 MBX_OVERTEMP_ERROR : MBX_HARDWARE_ERROR;
3142
3143 mutex_exit(&EMLXS_PORT_LOCK);
3144
3145 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_detail_msg,
3146 "Hardware error reported. %s failed. status=%x mb=%p",
3157 off_t offset;
3158 MATCHMAP *mbox_bp;
3159 uint32_t tmo_local;
3160 MAILBOX *swpmb;
3161
3162 if (!mbq->port) {
3163 mbq->port = &PPORT;
3164 }

--- 47 unchanged lines hidden (view full) ---

3212 if (hba->flag & FC_HARDWARE_ERROR) {
3213 mb->mbxStatus = (hba->flag & FC_OVERTEMP_EVENT) ?
3214 MBX_OVERTEMP_ERROR : MBX_HARDWARE_ERROR;
3215
3216 mutex_exit(&EMLXS_PORT_LOCK);
3217
3218 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_detail_msg,
3219 "Hardware error reported. %s failed. status=%x mb=%p",
3147 emlxs_mb_cmd_xlate(mb->mbxCommand), mb->mbxStatus, mb);
3220 emlxs_mb_cmd_xlate(mb->mbxCommand), mb->mbxStatus, mb);
3148
3149 return (MBX_HARDWARE_ERROR);
3150 }
3151
3152 if (hba->mbox_queue_flag) {
3153 /* If we are not polling, then queue it for later */
3154 if (flag == MBX_NOWAIT) {
3155 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_detail_msg,

--- 20 unchanged lines hidden (view full) ---

3176 tmo);
3177
3178 /* Non-lethalStatus mailbox timeout */
3179 /* Does not indicate a hardware error */
3180 mb->mbxStatus = MBX_TIMEOUT;
3181 return (MBX_TIMEOUT);
3182 }
3183
3221
3222 return (MBX_HARDWARE_ERROR);
3223 }
3224
3225 if (hba->mbox_queue_flag) {
3226 /* If we are not polling, then queue it for later */
3227 if (flag == MBX_NOWAIT) {
3228 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_detail_msg,

--- 20 unchanged lines hidden (view full) ---

3249 tmo);
3250
3251 /* Non-lethalStatus mailbox timeout */
3252 /* Does not indicate a hardware error */
3253 mb->mbxStatus = MBX_TIMEOUT;
3254 return (MBX_TIMEOUT);
3255 }
3256
3184 DELAYMS(10);
3257 BUSYWAIT_MS(10);
3185 mutex_enter(&EMLXS_PORT_LOCK);
3258 mutex_enter(&EMLXS_PORT_LOCK);
3259
3260 /* Check for hardware error */
3261 if (hba->flag & FC_HARDWARE_ERROR) {
3262 mb->mbxStatus =
3263 (hba->flag & FC_OVERTEMP_EVENT) ?
3264 MBX_OVERTEMP_ERROR : MBX_HARDWARE_ERROR;
3265
3266 mutex_exit(&EMLXS_PORT_LOCK);
3267
3268 EMLXS_MSGF(EMLXS_CONTEXT,
3269 &emlxs_mbox_detail_msg,
3270 "Hardware error reported. %s failed. "
3271 "status=%x mb=%p",
3272 emlxs_mb_cmd_xlate(mb->mbxCommand),
3273 mb->mbxStatus, mb);
3274
3275 return (MBX_HARDWARE_ERROR);
3276 }
3186 }
3187 }
3188
3189 /* Initialize mailbox area */
3190 emlxs_mb_init(hba, mbq, flag, tmo);
3191
3192 switch (flag) {
3193 case MBX_NOWAIT:

--- 58 unchanged lines hidden (view full) ---

3252 }
3253#endif /* MBOX_EXT_SUPPORT */
3254
3255 BE_SWAP32_BCOPY((uint8_t *)mb, (uint8_t *)mbox,
3256 MAILBOX_CMD_BSIZE);
3257
3258 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset,
3259 MAILBOX_CMD_BSIZE, DDI_DMA_SYNC_FORDEV);
3277 }
3278 }
3279
3280 /* Initialize mailbox area */
3281 emlxs_mb_init(hba, mbq, flag, tmo);
3282
3283 switch (flag) {
3284 case MBX_NOWAIT:

--- 58 unchanged lines hidden (view full) ---

3343 }
3344#endif /* MBOX_EXT_SUPPORT */
3345
3346 BE_SWAP32_BCOPY((uint8_t *)mb, (uint8_t *)mbox,
3347 MAILBOX_CMD_BSIZE);
3348
3349 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset,
3350 MAILBOX_CMD_BSIZE, DDI_DMA_SYNC_FORDEV);
3260 }
3261 /* Check for config port command */
3262 else if (mb->mbxCommand == MBX_CONFIG_PORT) {
3263 /* copy command data into host mbox for cmpl */
3264 mbox = FC_SLIM2_MAILBOX(hba);
3265 offset = (off_t)((uint64_t)((unsigned long)mbox)
3266 - (uint64_t)((unsigned long)slim2p));
3267
3268 BE_SWAP32_BCOPY((uint8_t *)mb, (uint8_t *)mbox,
3269 MAILBOX_CMD_BSIZE);
3270
3271 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle, offset,
3272 MAILBOX_CMD_BSIZE, DDI_DMA_SYNC_FORDEV);
3273
3274 /* First copy command data */
3275 mbox = FC_SLIM1_MAILBOX(hba);
3276 WRITE_SLIM_COPY(hba, &mb->un.varWords, &mbox->un.varWords,
3277 (MAILBOX_CMD_WSIZE - 1));
3278
3279 /* copy over last word, with mbxOwner set */
3280 ldata = *((volatile uint32_t *)mb);
3281 WRITE_SLIM_ADDR(hba, ((volatile uint32_t *)mbox), ldata);
3282
3283 /* switch over to host mailbox */
3284 hba->flag |= FC_SLIM2_MODE;
3285 } else { /* SLIM 1 */
3286
3287 mbox = FC_SLIM1_MAILBOX(hba);
3288
3289#ifdef MBOX_EXT_SUPPORT
3290 if (mbq->extbuf) {
3291 uint32_t *mbox_ext =
3292 (uint32_t *)((uint8_t *)mbox +

--- 62 unchanged lines hidden (view full) ---

3355
3356 break;
3357
3358 case MBX_POLL:
3359
3360 /* Convert tmo seconds to 500 usec tics */
3361 tmo_local = tmo * 2000;
3362
3351 } else { /* SLIM 1 */
3352
3353 mbox = FC_SLIM1_MAILBOX(hba);
3354
3355#ifdef MBOX_EXT_SUPPORT
3356 if (mbq->extbuf) {
3357 uint32_t *mbox_ext =
3358 (uint32_t *)((uint8_t *)mbox +

--- 62 unchanged lines hidden (view full) ---

3421
3422 break;
3423
3424 case MBX_POLL:
3425
3426 /* Convert tmo seconds to 500 usec tics */
3427 tmo_local = tmo * 2000;
3428
3363 if (hba->state >= FC_INIT_START) {
3364 ha_copy =
3365 READ_CSR_REG(hba, FC_HA_REG(hba));
3366
3367 /* Wait for command to complete */
3368 while (!(ha_copy & HA_MBATT) &&
3369 !(mbq->flag & MBQ_COMPLETED)) {
3370 if (!hba->timer_id && (tmo_local-- == 0)) {
3371 /* self time */
3372 EMLXS_MSGF(EMLXS_CONTEXT,
3373 &emlxs_mbox_timeout_msg,
3374 "%s: mb=%p Polled.",
3375 emlxs_mb_cmd_xlate(mb->
3376 mbxCommand), mb);
3377
3378 hba->flag |= FC_MBOX_TIMEOUT;
3379 EMLXS_STATE_CHANGE(hba, FC_ERROR);
3380 emlxs_mb_fini(hba, NULL, MBX_TIMEOUT);
3381
3382 break;
3383 }
3384
3385 DELAYUS(500);
3386 ha_copy = READ_CSR_REG(hba, FC_HA_REG(hba));
3387 }
3388
3389 if (mb->mbxStatus == MBX_TIMEOUT) {
3390 EMLXS_MSGF(EMLXS_CONTEXT,
3391 &emlxs_mbox_event_msg,
3392 "Timeout. %s: mb=%p tmo=%d. Polled.",
3393 emlxs_mb_cmd_xlate(mb->mbxCommand), mb,
3394 tmo);
3395
3396 break;
3397 }
3398 }
3399
3400 /* Get first word of mailbox */
3401 if (hba->flag & FC_SLIM2_MODE) {
3402 mbox = FC_SLIM2_MAILBOX(hba);
3403 offset = (off_t)((uint64_t)((unsigned long)mbox) -
3404 (uint64_t)((unsigned long)slim2p));
3405
3406 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle,
3407 offset, sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);

--- 7 unchanged lines hidden (view full) ---

3415
3416 /* Wait for command to complete */
3417 while ((swpmb->mbxOwner == OWN_CHIP) &&
3418 !(mbq->flag & MBQ_COMPLETED)) {
3419 if (!hba->timer_id && (tmo_local-- == 0)) {
3420 /* self time */
3421 EMLXS_MSGF(EMLXS_CONTEXT,
3422 &emlxs_mbox_timeout_msg,
3429 /* Get first word of mailbox */
3430 if (hba->flag & FC_SLIM2_MODE) {
3431 mbox = FC_SLIM2_MAILBOX(hba);
3432 offset = (off_t)((uint64_t)((unsigned long)mbox) -
3433 (uint64_t)((unsigned long)slim2p));
3434
3435 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle,
3436 offset, sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);

--- 7 unchanged lines hidden (view full) ---

3444
3445 /* Wait for command to complete */
3446 while ((swpmb->mbxOwner == OWN_CHIP) &&
3447 !(mbq->flag & MBQ_COMPLETED)) {
3448 if (!hba->timer_id && (tmo_local-- == 0)) {
3449 /* self time */
3450 EMLXS_MSGF(EMLXS_CONTEXT,
3451 &emlxs_mbox_timeout_msg,
3423 "%s: mb=%p Polled.",
3424 emlxs_mb_cmd_xlate(mb->mbxCommand), mb);
3452 "%s: mb=%p tmo=%d Polled.",
3453 emlxs_mb_cmd_xlate(mb->mbxCommand),
3454 mb, tmo);
3425
3426 hba->flag |= FC_MBOX_TIMEOUT;
3427 EMLXS_STATE_CHANGE(hba, FC_ERROR);
3428 emlxs_mb_fini(hba, NULL, MBX_TIMEOUT);
3429
3430 break;
3431 }
3432
3455
3456 hba->flag |= FC_MBOX_TIMEOUT;
3457 EMLXS_STATE_CHANGE(hba, FC_ERROR);
3458 emlxs_mb_fini(hba, NULL, MBX_TIMEOUT);
3459
3460 break;
3461 }
3462
3433 DELAYUS(500);
3463 BUSYWAIT_US(500);
3434
3435 /* Get first word of mailbox */
3436 if (hba->flag & FC_SLIM2_MODE) {
3437 EMLXS_MPDATA_SYNC(
3438 hba->sli.sli3.slim2.dma_handle, offset,
3439 sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);
3440 word0 = *((volatile uint32_t *)mbox);
3441 word0 = BE_SWAP32(word0);

--- 8 unchanged lines hidden (view full) ---

3450 if (mb->mbxStatus == MBX_TIMEOUT) {
3451 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_event_msg,
3452 "Timeout. %s: mb=%p tmo=%d. Polled.",
3453 emlxs_mb_cmd_xlate(mb->mbxCommand), mb, tmo);
3454
3455 break;
3456 }
3457
3464
3465 /* Get first word of mailbox */
3466 if (hba->flag & FC_SLIM2_MODE) {
3467 EMLXS_MPDATA_SYNC(
3468 hba->sli.sli3.slim2.dma_handle, offset,
3469 sizeof (uint32_t), DDI_DMA_SYNC_FORKERNEL);
3470 word0 = *((volatile uint32_t *)mbox);
3471 word0 = BE_SWAP32(word0);

--- 8 unchanged lines hidden (view full) ---

3480 if (mb->mbxStatus == MBX_TIMEOUT) {
3481 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mbox_event_msg,
3482 "Timeout. %s: mb=%p tmo=%d. Polled.",
3483 emlxs_mb_cmd_xlate(mb->mbxCommand), mb, tmo);
3484
3485 break;
3486 }
3487
3488 /* Check for config port command */
3489 if ((swpmb->mbxCommand == MBX_CONFIG_PORT) &&
3490 (swpmb->mbxStatus == MBX_SUCCESS)) {
3491 /* Setup host mbox for cmpl */
3492 mbox = FC_SLIM2_MAILBOX(hba);
3493 offset = (off_t)((uint64_t)((unsigned long)mbox)
3494 - (uint64_t)((unsigned long)slim2p));
3495
3496 hba->flag |= FC_SLIM2_MODE;
3497 }
3498
3458 /* copy results back to user */
3459 if (hba->flag & FC_SLIM2_MODE) {
3460 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle,
3461 offset, MAILBOX_CMD_BSIZE, DDI_DMA_SYNC_FORKERNEL);
3462
3463 BE_SWAP32_BCOPY((uint8_t *)mbox, (uint8_t *)mb,
3464 MAILBOX_CMD_BSIZE);
3465 } else {

--- 56 unchanged lines hidden (view full) ---

3522 } /* switch (flag) */
3523
3524 return (mb->mbxStatus);
3525
3526} /* emlxs_sli3_issue_mbox_cmd() */
3527
3528
3529#ifdef SFCT_SUPPORT
3499 /* copy results back to user */
3500 if (hba->flag & FC_SLIM2_MODE) {
3501 EMLXS_MPDATA_SYNC(hba->sli.sli3.slim2.dma_handle,
3502 offset, MAILBOX_CMD_BSIZE, DDI_DMA_SYNC_FORKERNEL);
3503
3504 BE_SWAP32_BCOPY((uint8_t *)mbox, (uint8_t *)mb,
3505 MAILBOX_CMD_BSIZE);
3506 } else {

--- 56 unchanged lines hidden (view full) ---

3563 } /* switch (flag) */
3564
3565 return (mb->mbxStatus);
3566
3567} /* emlxs_sli3_issue_mbox_cmd() */
3568
3569
3570#ifdef SFCT_SUPPORT
3571/*ARGSUSED*/
3530static uint32_t
3531emlxs_sli3_prep_fct_iocb(emlxs_port_t *port, emlxs_buf_t *cmd_sbp,
3532 int channel)
3533{
3534 emlxs_hba_t *hba = HBA;
3535 emlxs_config_t *cfg = &CFG;
3536 fct_cmd_t *fct_cmd;
3537 stmf_data_buf_t *dbuf;
3538 scsi_task_t *fct_task;
3572static uint32_t
3573emlxs_sli3_prep_fct_iocb(emlxs_port_t *port, emlxs_buf_t *cmd_sbp,
3574 int channel)
3575{
3576 emlxs_hba_t *hba = HBA;
3577 emlxs_config_t *cfg = &CFG;
3578 fct_cmd_t *fct_cmd;
3579 stmf_data_buf_t *dbuf;
3580 scsi_task_t *fct_task;
3581 fc_packet_t *pkt;
3539 uint32_t did;
3540 IOCBQ *iocbq;
3541 IOCB *iocb;
3542 uint32_t timeout;
3543 uint32_t iotag;
3544 emlxs_node_t *ndlp;
3545 CHANNEL *cp;
3582 uint32_t did;
3583 IOCBQ *iocbq;
3584 IOCB *iocb;
3585 uint32_t timeout;
3586 uint32_t iotag;
3587 emlxs_node_t *ndlp;
3588 CHANNEL *cp;
3589 ddi_dma_cookie_t *cp_cmd;
3546
3590
3547 dbuf = cmd_sbp->fct_buf;
3548 fct_cmd = cmd_sbp->fct_cmd;
3549 fct_task = (scsi_task_t *)fct_cmd->cmd_specific;
3550 ndlp = *(emlxs_node_t **)fct_cmd->cmd_rp->rp_fca_private;
3551 did = fct_cmd->cmd_rportid;
3591 pkt = PRIV2PKT(cmd_sbp);
3552
3553 cp = (CHANNEL *)cmd_sbp->channel;
3554
3592
3593 cp = (CHANNEL *)cmd_sbp->channel;
3594
3555 channel = channel;
3556 iocbq = &cmd_sbp->iocbq;
3557 iocb = &iocbq->iocb;
3558
3595 iocbq = &cmd_sbp->iocbq;
3596 iocb = &iocbq->iocb;
3597
3559 if (cfg[CFG_TIMEOUT_ENABLE].current) {
3560 timeout =
3561 ((2 * hba->fc_ratov) < 60) ? 60 : (2 * hba->fc_ratov);
3562 } else {
3563 timeout = 0x80000000;
3564 }
3565
3598
3566#ifdef FCT_API_TRACE
3567 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_api_msg,
3568 "emlxs_fct_send_fcp_data %p: flgs=%x ioflags=%x dl=%d,%d,%d,%d,%d",
3569 fct_cmd, dbuf->db_flags, ioflags, fct_task->task_cmd_xfer_length,
3570 fct_task->task_nbytes_transferred, dbuf->db_data_size,
3571 fct_task->task_expected_xfer_length, channel);
3572#endif /* FCT_API_TRACE */
3573
3574
3575 /* Get the iotag by registering the packet */
3576 iotag = emlxs_register_pkt(cp, cmd_sbp);
3577
3578 if (!iotag) {
3579 /* No more command slots available, retry later */
3580 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_pkt_trans_msg,
3599 /* Get the iotag by registering the packet */
3600 iotag = emlxs_register_pkt(cp, cmd_sbp);
3601
3602 if (!iotag) {
3603 /* No more command slots available, retry later */
3604 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_pkt_trans_msg,
3581 "Adapter Busy. Unable to allocate iotag. did=0x%x", did);
3605 "Adapter Busy. Unable to allocate iotag. did=0x%x",
3606 cmd_sbp->did);
3582
3583 return (IOERR_NO_RESOURCES);
3584 }
3585
3607
3608 return (IOERR_NO_RESOURCES);
3609 }
3610
3586 cmd_sbp->ticks =
3587 hba->timer_tics + timeout + ((timeout > 0xff) ? 0 : 10);
3588
3611
3589 /* Initalize iocbq */
3590 iocbq->port = (void *)port;
3591 iocbq->node = (void *)ndlp;
3612 /* Point of no return */
3592
3613
3614 if (iocb->ULPCOMMAND == CMD_ABORT_XRI_CX) {
3593
3615
3616 ndlp = cmd_sbp->node;
3617 cp->ulpSendCmd++;
3618
3619 /* Initalize iocbq */
3620 iocbq->port = (void *)port;
3621 iocbq->node = (void *)ndlp;
3622 iocbq->channel = (void *)cp;
3623
3624 /*
3625 * Don't give the abort priority, we want the IOCB
3626 * we are aborting to be processed first.
3627 */
3628 iocbq->flag |= IOCB_SPECIAL;
3629
3630 iocb->ULPCONTEXT = pkt->pkt_cmd_fhdr.rx_id;
3631 iocb->ULPIOTAG = (uint16_t)iotag;
3632 iocb->ULPLE = 1;
3633 iocb->ULPCLASS = cmd_sbp->class;
3634 iocb->ULPOWNER = OWN_CHIP;
3635
3636 if (hba->state >= FC_LINK_UP) {
3637 /* Create the abort IOCB */
3638 iocb->un.acxri.abortType = ABORT_TYPE_ABTS;
3639 iocb->ULPCOMMAND = CMD_ABORT_XRI_CX;
3640
3641 } else {
3642 /* Create the close IOCB */
3643 iocb->ULPCOMMAND = CMD_CLOSE_XRI_CX;
3644
3645 }
3646
3647 iocb->ULPRSVDBYTE =
3648 ((pkt->pkt_timeout > 0xff) ? 0 : pkt->pkt_timeout);
3649 /* Set the pkt timer */
3650 cmd_sbp->ticks = hba->timer_tics + pkt->pkt_timeout +
3651 ((pkt->pkt_timeout > 0xff) ? 0 : 10);
3652
3653 return (IOERR_SUCCESS);
3654
3655 } else if (iocb->ULPCOMMAND == CMD_FCP_TRSP64_CX) {
3656
3657 ndlp = cmd_sbp->node;
3658 cp->ulpSendCmd++;
3659
3660 /* Initalize iocbq */
3661 iocbq->port = (void *)port;
3662 iocbq->node = (void *)ndlp;
3663 iocbq->channel = (void *)cp;
3664
3665#if (EMLXS_MODREV >= EMLXS_MODREV3)
3666 cp_cmd = pkt->pkt_cmd_cookie;
3667#else
3668 cp_cmd = &pkt->pkt_cmd_cookie;
3669#endif /* >= EMLXS_MODREV3 */
3670
3671 iocb->un.fcpt64.bdl.addrHigh = PADDR_HI(cp_cmd->dmac_laddress);
3672 iocb->un.fcpt64.bdl.addrLow = PADDR_LO(cp_cmd->dmac_laddress);
3673 iocb->un.fcpt64.bdl.bdeSize = pkt->pkt_cmdlen;
3674 iocb->un.fcpt64.bdl.bdeFlags = 0;
3675
3676 if (hba->sli_mode < 3) {
3677 iocb->ULPBDECOUNT = 1;
3678 iocb->ULPLE = 1;
3679 } else { /* SLI3 */
3680
3681 iocb->ULPBDECOUNT = 0;
3682 iocb->ULPLE = 0;
3683 iocb->unsli3.ext_iocb.ebde_count = 0;
3684 }
3685
3686 /* Initalize iocb */
3687 iocb->ULPCONTEXT = (uint16_t)pkt->pkt_cmd_fhdr.rx_id;
3688 iocb->ULPIOTAG = (uint16_t)iotag;
3689 iocb->ULPRSVDBYTE =
3690 ((pkt->pkt_timeout > 0xff) ? 0 : pkt->pkt_timeout);
3691 iocb->ULPOWNER = OWN_CHIP;
3692 iocb->ULPCLASS = cmd_sbp->class;
3693 iocb->ULPCOMMAND = CMD_FCP_TRSP64_CX;
3694
3695 /* Set the pkt timer */
3696 cmd_sbp->ticks = hba->timer_tics + pkt->pkt_timeout +
3697 ((pkt->pkt_timeout > 0xff) ? 0 : 10);
3698
3699 if (pkt->pkt_cmdlen) {
3700 EMLXS_MPDATA_SYNC(pkt->pkt_cmd_dma, 0, pkt->pkt_cmdlen,
3701 DDI_DMA_SYNC_FORDEV);
3702 }
3703
3704 return (IOERR_SUCCESS);
3705 }
3706
3707 dbuf = cmd_sbp->fct_buf;
3708 fct_cmd = cmd_sbp->fct_cmd;
3709 fct_task = (scsi_task_t *)fct_cmd->cmd_specific;
3710 ndlp = *(emlxs_node_t **)fct_cmd->cmd_rp->rp_fca_private;
3711 did = fct_cmd->cmd_rportid;
3712
3594 iocbq->channel = (void *)cmd_sbp->channel;
3595
3596 if (emlxs_fct_bde_setup(port, cmd_sbp)) {
3597 /* Unregister the packet */
3598 (void) emlxs_unregister_pkt(cmd_sbp->channel, iotag, 0);
3599
3600 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_pkt_trans_msg,
3601 "Adapter Busy. Unable to setup buffer list. did=%x", did);
3602
3603 return (IOERR_INTERNAL_ERROR);
3604 }
3713 iocbq->channel = (void *)cmd_sbp->channel;
3714
3715 if (emlxs_fct_bde_setup(port, cmd_sbp)) {
3716 /* Unregister the packet */
3717 (void) emlxs_unregister_pkt(cmd_sbp->channel, iotag, 0);
3718
3719 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_pkt_trans_msg,
3720 "Adapter Busy. Unable to setup buffer list. did=%x", did);
3721
3722 return (IOERR_INTERNAL_ERROR);
3723 }
3605 /* Point of no return */
3606
3724
3725 if (cfg[CFG_TIMEOUT_ENABLE].current) {
3726 timeout =
3727 ((2 * hba->fc_ratov) < 60) ? 60 : (2 * hba->fc_ratov);
3728 } else {
3729 timeout = 0x80000000;
3730 }
3731
3732 cmd_sbp->ticks =
3733 hba->timer_tics + timeout + ((timeout > 0xff) ? 0 : 10);
3734
3735 /* Initalize iocbq */
3736 iocbq->port = (void *)port;
3737 iocbq->node = (void *)ndlp;
3738
3607 /* Initalize iocb */
3608 iocb->ULPCONTEXT = (uint16_t)fct_cmd->cmd_rxid;
3609 iocb->ULPIOTAG = (uint16_t)iotag;
3610 iocb->ULPRSVDBYTE = ((timeout > 0xff) ? 0 : timeout);
3611 iocb->ULPOWNER = OWN_CHIP;
3612 iocb->ULPCLASS = cmd_sbp->class;
3613
3614 iocb->ULPPU = 1; /* Wd4 is relative offset */
3615 iocb->un.fcpt64.fcpt_Offset = dbuf->db_relative_offset;
3616
3617 if (fct_task->task_flags & TF_WRITE_DATA) {
3618 iocb->ULPCOMMAND = CMD_FCP_TRECEIVE64_CX;
3619 } else { /* TF_READ_DATA */
3620
3621 iocb->ULPCOMMAND = CMD_FCP_TSEND64_CX;
3622
3623 if ((hba->sli_mode == EMLXS_HBA_SLI3_MODE) &&
3739 /* Initalize iocb */
3740 iocb->ULPCONTEXT = (uint16_t)fct_cmd->cmd_rxid;
3741 iocb->ULPIOTAG = (uint16_t)iotag;
3742 iocb->ULPRSVDBYTE = ((timeout > 0xff) ? 0 : timeout);
3743 iocb->ULPOWNER = OWN_CHIP;
3744 iocb->ULPCLASS = cmd_sbp->class;
3745
3746 iocb->ULPPU = 1; /* Wd4 is relative offset */
3747 iocb->un.fcpt64.fcpt_Offset = dbuf->db_relative_offset;
3748
3749 if (fct_task->task_flags & TF_WRITE_DATA) {
3750 iocb->ULPCOMMAND = CMD_FCP_TRECEIVE64_CX;
3751 } else { /* TF_READ_DATA */
3752
3753 iocb->ULPCOMMAND = CMD_FCP_TSEND64_CX;
3754
3755 if ((hba->sli_mode == EMLXS_HBA_SLI3_MODE) &&
3624 (dbuf->db_data_size ==
3756 (dbuf->db_data_size >=
3625 fct_task->task_expected_xfer_length)) {
3626 iocb->ULPCT = 0x1;
3627 /* enable auto-rsp AP feature */
3628 }
3629 }
3630
3631 return (IOERR_SUCCESS);
3632

--- 80 unchanged lines hidden (view full) ---

3713 if (ndlp->nlp_fcp_info & NLP_FCP_2_DEVICE) {
3714 iocb->ULPFCP2RCVY = 1;
3715 }
3716
3717 if (pkt->pkt_datalen == 0) {
3718 iocb->ULPCOMMAND = CMD_FCP_ICMND64_CR;
3719 } else if (pkt->pkt_tran_type == FC_PKT_FCP_READ) {
3720 iocb->ULPCOMMAND = CMD_FCP_IREAD64_CR;
3757 fct_task->task_expected_xfer_length)) {
3758 iocb->ULPCT = 0x1;
3759 /* enable auto-rsp AP feature */
3760 }
3761 }
3762
3763 return (IOERR_SUCCESS);
3764

--- 80 unchanged lines hidden (view full) ---

3845 if (ndlp->nlp_fcp_info & NLP_FCP_2_DEVICE) {
3846 iocb->ULPFCP2RCVY = 1;
3847 }
3848
3849 if (pkt->pkt_datalen == 0) {
3850 iocb->ULPCOMMAND = CMD_FCP_ICMND64_CR;
3851 } else if (pkt->pkt_tran_type == FC_PKT_FCP_READ) {
3852 iocb->ULPCOMMAND = CMD_FCP_IREAD64_CR;
3721 iocb->ULPPU = PARM_READ_CHECK;
3853 iocb->ULPPU = PARM_XFER_CHECK;
3722 iocb->un.fcpi64.fcpi_parm = pkt->pkt_datalen;
3723 } else {
3724 iocb->ULPCOMMAND = CMD_FCP_IWRITE64_CR;
3725 }
3726
3727 return (FC_SUCCESS);
3728
3729} /* emlxs_sli3_prep_fcp_iocb() */

--- 300 unchanged lines hidden (view full) ---

4030} /* emlxs_sli3_prep_ct_iocb() */
4031
4032
4033#ifdef SFCT_SUPPORT
4034static uint32_t
4035emlxs_fct_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
4036{
4037 emlxs_hba_t *hba = HBA;
3854 iocb->un.fcpi64.fcpi_parm = pkt->pkt_datalen;
3855 } else {
3856 iocb->ULPCOMMAND = CMD_FCP_IWRITE64_CR;
3857 }
3858
3859 return (FC_SUCCESS);
3860
3861} /* emlxs_sli3_prep_fcp_iocb() */

--- 300 unchanged lines hidden (view full) ---

4162} /* emlxs_sli3_prep_ct_iocb() */
4163
4164
4165#ifdef SFCT_SUPPORT
4166static uint32_t
4167emlxs_fct_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
4168{
4169 emlxs_hba_t *hba = HBA;
4038 uint32_t sgllen = 1;
4039 uint32_t rval;
4170 uint32_t rval;
4040 uint32_t size;
4041 uint32_t count;
4042 uint32_t resid;
4043 struct stmf_sglist_ent *sgl;
4044
4171
4045 size = sbp->fct_buf->db_data_size;
4046 count = sbp->fct_buf->db_sglist_length;
4047 sgl = sbp->fct_buf->db_sglist;
4048 resid = size;
4049
4050 for (sgllen = 0; sgllen < count && resid > 0; sgllen++) {
4051 resid -= MIN(resid, sgl->seg_length);
4052 sgl++;
4053 }
4054
4055 if (resid > 0) {
4172 if (sbp->fct_buf->db_sglist_length != 1) {
4056 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_error_msg,
4173 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_error_msg,
4057 "emlxs_fct_bde_setup: Not enough scatter gather buffers "
4058 " size=%d resid=%d count=%d",
4059 size, resid, count);
4174 "fct_bde_setup: Only 1 sglist entry supported: %d",
4175 sbp->fct_buf->db_sglist_length);
4060 return (1);
4061 }
4062
4176 return (1);
4177 }
4178
4063 if ((hba->sli_mode < EMLXS_HBA_SLI3_MODE) ||
4064 (sgllen > SLI3_MAX_BDE)) {
4179 if (hba->sli_mode < EMLXS_HBA_SLI3_MODE) {
4065 rval = emlxs_sli2_fct_bde_setup(port, sbp);
4066 } else {
4067 rval = emlxs_sli3_fct_bde_setup(port, sbp);
4068 }
4069
4070 return (rval);
4071
4072} /* emlxs_fct_bde_setup() */
4073#endif /* SFCT_SUPPORT */
4074
4180 rval = emlxs_sli2_fct_bde_setup(port, sbp);
4181 } else {
4182 rval = emlxs_sli3_fct_bde_setup(port, sbp);
4183 }
4184
4185 return (rval);
4186
4187} /* emlxs_fct_bde_setup() */
4188#endif /* SFCT_SUPPORT */
4189
4190
4075static uint32_t
4076emlxs_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
4077{
4078 uint32_t rval;
4079 emlxs_hba_t *hba = HBA;
4080
4081 if (hba->sli_mode < EMLXS_HBA_SLI3_MODE) {
4082 rval = emlxs_sli2_bde_setup(port, sbp);
4083 } else {
4084 rval = emlxs_sli3_bde_setup(port, sbp);
4085 }
4086
4087 return (rval);
4088
4089} /* emlxs_bde_setup() */
4090
4091
4092static void
4191static uint32_t
4192emlxs_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp)
4193{
4194 uint32_t rval;
4195 emlxs_hba_t *hba = HBA;
4196
4197 if (hba->sli_mode < EMLXS_HBA_SLI3_MODE) {
4198 rval = emlxs_sli2_bde_setup(port, sbp);
4199 } else {
4200 rval = emlxs_sli3_bde_setup(port, sbp);
4201 }
4202
4203 return (rval);
4204
4205} /* emlxs_bde_setup() */
4206
4207
4208static void
4093emlxs_sli3_poll_intr(emlxs_hba_t *hba, uint32_t att_bit)
4209emlxs_sli3_poll_intr(emlxs_hba_t *hba)
4094{
4095 uint32_t ha_copy;
4096
4210{
4211 uint32_t ha_copy;
4212
4097 /*
4098 * Polling a specific attention bit.
4099 */
4100 for (;;) {
4101 ha_copy = emlxs_check_attention(hba);
4213 /* Check attention bits once and process if required */
4102
4214
4103 if (ha_copy & att_bit) {
4104 break;
4105 }
4215 ha_copy = emlxs_check_attention(hba);
4106
4216
4217 if (ha_copy == 0) {
4218 return;
4107 }
4108
4109 mutex_enter(&EMLXS_PORT_LOCK);
4110 ha_copy = emlxs_get_attention(hba, -1);
4111 mutex_exit(&EMLXS_PORT_LOCK);
4112
4219 }
4220
4221 mutex_enter(&EMLXS_PORT_LOCK);
4222 ha_copy = emlxs_get_attention(hba, -1);
4223 mutex_exit(&EMLXS_PORT_LOCK);
4224
4113 /* Process the attentions */
4114 emlxs_proc_attention(hba, ha_copy);
4115
4116 return;
4117
4118} /* emlxs_sli3_poll_intr() */
4119
4225 emlxs_proc_attention(hba, ha_copy);
4226
4227 return;
4228
4229} /* emlxs_sli3_poll_intr() */
4230
4231
4120#ifdef MSI_SUPPORT
4121static uint32_t
4122emlxs_sli3_msi_intr(char *arg1, char *arg2)
4123{
4124 emlxs_hba_t *hba = (emlxs_hba_t *)arg1;
4125#ifdef FMA_SUPPORT
4126 emlxs_port_t *port = &PPORT;
4127#endif /* FMA_SUPPORT */
4128 uint16_t msgid;
4129 uint32_t hc_copy;
4130 uint32_t ha_copy;
4131 uint32_t restore = 0;
4132
4133 /*
4134 * EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
4232#ifdef MSI_SUPPORT
4233static uint32_t
4234emlxs_sli3_msi_intr(char *arg1, char *arg2)
4235{
4236 emlxs_hba_t *hba = (emlxs_hba_t *)arg1;
4237#ifdef FMA_SUPPORT
4238 emlxs_port_t *port = &PPORT;
4239#endif /* FMA_SUPPORT */
4240 uint16_t msgid;
4241 uint32_t hc_copy;
4242 uint32_t ha_copy;
4243 uint32_t restore = 0;
4244
4245 /*
4246 * EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
4135 * "emlxs_sli3_msi_intr: arg1=%p arg2=%p", arg1, arg2);
4247 * "sli3_msi_intr: arg1=%p arg2=%p", arg1, arg2);
4136 */
4137
4138 /* Check for legacy interrupt handling */
4139 if (hba->intr_type == DDI_INTR_TYPE_FIXED) {
4140 mutex_enter(&EMLXS_PORT_LOCK);
4141
4142 if (hba->flag & FC_OFFLINE_MODE) {
4143 mutex_exit(&EMLXS_PORT_LOCK);

--- 231 unchanged lines hidden (view full) ---

4375#ifdef FMA_SUPPORT
4376 emlxs_port_t *port = &PPORT;
4377#endif /* FMA_SUPPORT */
4378
4379 /* ha_copy should be pre-filtered */
4380
4381 /*
4382 * EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
4248 */
4249
4250 /* Check for legacy interrupt handling */
4251 if (hba->intr_type == DDI_INTR_TYPE_FIXED) {
4252 mutex_enter(&EMLXS_PORT_LOCK);
4253
4254 if (hba->flag & FC_OFFLINE_MODE) {
4255 mutex_exit(&EMLXS_PORT_LOCK);

--- 231 unchanged lines hidden (view full) ---

4487#ifdef FMA_SUPPORT
4488 emlxs_port_t *port = &PPORT;
4489#endif /* FMA_SUPPORT */
4490
4491 /* ha_copy should be pre-filtered */
4492
4493 /*
4494 * EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
4383 * "emlxs_proc_attention: ha_copy=%x", ha_copy);
4495 * "proc_attention: ha_copy=%x", ha_copy);
4384 */
4385
4386 if (hba->state < FC_WARM_START) {
4387 return;
4388 }
4389
4390 if (!ha_copy) {
4391 return;

--- 87 unchanged lines hidden (view full) ---

4479 WRITE_CSR_REG(hba, FC_HA_REG(hba), HA_ERATT);
4480
4481 /* If HS_FFER1 is set, then wait until the HS_FFER1 bit clears */
4482 if (status & HS_FFER1) {
4483
4484 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_hardware_error_msg,
4485 "HS_FFER1 received");
4486 EMLXS_STATE_CHANGE(hba, FC_ERROR);
4496 */
4497
4498 if (hba->state < FC_WARM_START) {
4499 return;
4500 }
4501
4502 if (!ha_copy) {
4503 return;

--- 87 unchanged lines hidden (view full) ---

4591 WRITE_CSR_REG(hba, FC_HA_REG(hba), HA_ERATT);
4592
4593 /* If HS_FFER1 is set, then wait until the HS_FFER1 bit clears */
4594 if (status & HS_FFER1) {
4595
4596 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_hardware_error_msg,
4597 "HS_FFER1 received");
4598 EMLXS_STATE_CHANGE(hba, FC_ERROR);
4487 (void) emlxs_offline(hba);
4599 (void) emlxs_offline(hba, 1);
4488 while ((status & HS_FFER1) && (i < 300)) {
4489 status =
4490 READ_CSR_REG(hba, FC_HS_REG(hba));
4600 while ((status & HS_FFER1) && (i < 300)) {
4601 status =
4602 READ_CSR_REG(hba, FC_HS_REG(hba));
4491 DELAYMS(1000);
4603 BUSYWAIT_MS(1000);
4492 i++;
4493 }
4494 }
4495
4496 if (i == 300) {
4497 /* 5 minutes is up, shutdown HBA */
4498 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_hardware_error_msg,
4499 "HS_FFER1 clear timeout");

--- 73 unchanged lines hidden (view full) ---

4573 HBASTATS.LinkEvent++;
4574
4575 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_link_event_msg, "event=%x",
4576 HBASTATS.LinkEvent);
4577
4578 /* Make sure link is declared down */
4579 emlxs_linkdown(hba);
4580
4604 i++;
4605 }
4606 }
4607
4608 if (i == 300) {
4609 /* 5 minutes is up, shutdown HBA */
4610 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_hardware_error_msg,
4611 "HS_FFER1 clear timeout");

--- 73 unchanged lines hidden (view full) ---

4685 HBASTATS.LinkEvent++;
4686
4687 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_link_event_msg, "event=%x",
4688 HBASTATS.LinkEvent);
4689
4690 /* Make sure link is declared down */
4691 emlxs_linkdown(hba);
4692
4581
4582 /* Get a buffer which will be used for mailbox commands */
4693 /* Get a buffer which will be used for mailbox commands */
4583 if ((mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1))) {
4694 if ((mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX))) {
4584 /* Get link attention message */
4585 if (emlxs_mb_read_la(hba, mbq) == 0) {
4586 rc = emlxs_sli3_issue_mbox_cmd(hba, mbq,
4587 MBX_NOWAIT, 0);
4588 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
4589 emlxs_mem_put(hba, MEM_MBOX,
4590 (void *)mbq);
4591 }
4592
4593 mutex_enter(&EMLXS_PORT_LOCK);
4594
4695 /* Get link attention message */
4696 if (emlxs_mb_read_la(hba, mbq) == 0) {
4697 rc = emlxs_sli3_issue_mbox_cmd(hba, mbq,
4698 MBX_NOWAIT, 0);
4699 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
4700 emlxs_mem_put(hba, MEM_MBOX,
4701 (void *)mbq);
4702 }
4703
4704 mutex_enter(&EMLXS_PORT_LOCK);
4705
4595
4596 /*
4597 * Clear Link Attention in HA REG
4598 */
4599 WRITE_CSR_REG(hba, FC_HA_REG(hba), HA_LATT);
4600
4601#ifdef FMA_SUPPORT
4602 /* Access handle validation */
4603 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);

--- 83 unchanged lines hidden (view full) ---

4687 (uint8_t *)iocbq + (sizeof (uint32_t) * 6),
4688 (sizeof (uint32_t) * 2));
4689
4690 /* when LE is not set, entire Command has not been received */
4691 if (!iocbq->iocb.ULPLE) {
4692 /* This should never happen */
4693 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_ring_error_msg,
4694 "ulpLE is not set. "
4706 /*
4707 * Clear Link Attention in HA REG
4708 */
4709 WRITE_CSR_REG(hba, FC_HA_REG(hba), HA_LATT);
4710
4711#ifdef FMA_SUPPORT
4712 /* Access handle validation */
4713 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);

--- 83 unchanged lines hidden (view full) ---

4797 (uint8_t *)iocbq + (sizeof (uint32_t) * 6),
4798 (sizeof (uint32_t) * 2));
4799
4800 /* when LE is not set, entire Command has not been received */
4801 if (!iocbq->iocb.ULPLE) {
4802 /* This should never happen */
4803 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_ring_error_msg,
4804 "ulpLE is not set. "
4695 "ring=%d iotag=%x cmd=%x status=%x",
4805 "ring=%d iotag=%d cmd=%x status=%x",
4696 channel_no, iocbq->iocb.ULPIOTAG,
4697 iocbq->iocb.ULPCOMMAND, iocbq->iocb.ULPSTATUS);
4698
4699 goto next;
4700 }
4701
4806 channel_no, iocbq->iocb.ULPIOTAG,
4807 iocbq->iocb.ULPCOMMAND, iocbq->iocb.ULPSTATUS);
4808
4809 goto next;
4810 }
4811
4812 sbp = NULL;
4702 switch (iocbq->iocb.ULPCOMMAND) {
4703#ifdef SFCT_SUPPORT
4704 case CMD_CLOSE_XRI_CX:
4705 case CMD_CLOSE_XRI_CN:
4706 case CMD_ABORT_XRI_CX:
4813 switch (iocbq->iocb.ULPCOMMAND) {
4814#ifdef SFCT_SUPPORT
4815 case CMD_CLOSE_XRI_CX:
4816 case CMD_CLOSE_XRI_CN:
4817 case CMD_ABORT_XRI_CX:
4707 if (!port->tgt_mode) {
4708 sbp = NULL;
4709 break;
4818 if (port->mode == MODE_TARGET) {
4819 sbp = emlxs_unregister_pkt(cp,
4820 iocbq->iocb.ULPIOTAG, 0);
4710 }
4821 }
4711
4712 sbp =
4713 emlxs_unregister_pkt(cp, iocbq->iocb.ULPIOTAG, 0);
4714 break;
4715#endif /* SFCT_SUPPORT */
4716
4717 /* Ring 0 registered commands */
4718 case CMD_FCP_ICMND_CR:
4719 case CMD_FCP_ICMND_CX:
4720 case CMD_FCP_IREAD_CR:
4721 case CMD_FCP_IREAD_CX:

--- 36 unchanged lines hidden (view full) ---

4758
4759 /* Ring 3 registered commands */
4760 case CMD_GEN_REQUEST64_CR:
4761 case CMD_GEN_REQUEST64_CX:
4762
4763 sbp =
4764 emlxs_unregister_pkt(cp, iocbq->iocb.ULPIOTAG, 0);
4765 break;
4822 break;
4823#endif /* SFCT_SUPPORT */
4824
4825 /* Ring 0 registered commands */
4826 case CMD_FCP_ICMND_CR:
4827 case CMD_FCP_ICMND_CX:
4828 case CMD_FCP_IREAD_CR:
4829 case CMD_FCP_IREAD_CX:

--- 36 unchanged lines hidden (view full) ---

4866
4867 /* Ring 3 registered commands */
4868 case CMD_GEN_REQUEST64_CR:
4869 case CMD_GEN_REQUEST64_CX:
4870
4871 sbp =
4872 emlxs_unregister_pkt(cp, iocbq->iocb.ULPIOTAG, 0);
4873 break;
4766
4767 default:
4768 sbp = NULL;
4769 }
4770
4771 /* If packet is stale, then drop it. */
4772 if (sbp == STALE_PACKET) {
4773 cp->hbaCmplCmd_sbp++;
4774 /* Copy entry to the local iocbq */
4775 BE_SWAP32_BCOPY((uint8_t *)entry,
4776 (uint8_t *)iocbq, hba->sli.sli3.iocb_rsp_size);
4777
4778 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_iocb_stale_msg,
4779 "channelno=%d iocb=%p cmd=%x status=%x "
4874 }
4875
4876 /* If packet is stale, then drop it. */
4877 if (sbp == STALE_PACKET) {
4878 cp->hbaCmplCmd_sbp++;
4879 /* Copy entry to the local iocbq */
4880 BE_SWAP32_BCOPY((uint8_t *)entry,
4881 (uint8_t *)iocbq, hba->sli.sli3.iocb_rsp_size);
4882
4883 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_iocb_stale_msg,
4884 "channelno=%d iocb=%p cmd=%x status=%x "
4780 "error=%x iotag=%x context=%x info=%x",
4885 "error=%x iotag=%d context=%x info=%x",
4781 channel_no, iocbq, (uint8_t)iocbq->iocb.ULPCOMMAND,
4782 iocbq->iocb.ULPSTATUS,
4783 (uint8_t)iocbq->iocb.un.grsp.perr.statLocalError,
4784 (uint16_t)iocbq->iocb.ULPIOTAG,
4785 (uint16_t)iocbq->iocb.ULPCONTEXT,
4786 (uint8_t)iocbq->iocb.ULPRSVDBYTE);
4787
4788 goto next;

--- 15 unchanged lines hidden (view full) ---

4804 mutex_enter(&cmd_sbp->fct_mtx);
4805 EMLXS_FCT_STATE_CHG(fct_cmd, cmd_sbp,
4806 EMLXS_FCT_IOCB_COMPLETE);
4807 mutex_exit(&cmd_sbp->fct_mtx);
4808 }
4809#endif /* SFCT_SUPPORT */
4810 cp->hbaCmplCmd_sbp++;
4811 atomic_dec_32(&hba->io_active);
4886 channel_no, iocbq, (uint8_t)iocbq->iocb.ULPCOMMAND,
4887 iocbq->iocb.ULPSTATUS,
4888 (uint8_t)iocbq->iocb.un.grsp.perr.statLocalError,
4889 (uint16_t)iocbq->iocb.ULPIOTAG,
4890 (uint16_t)iocbq->iocb.ULPCONTEXT,
4891 (uint8_t)iocbq->iocb.ULPRSVDBYTE);
4892
4893 goto next;

--- 15 unchanged lines hidden (view full) ---

4909 mutex_enter(&cmd_sbp->fct_mtx);
4910 EMLXS_FCT_STATE_CHG(fct_cmd, cmd_sbp,
4911 EMLXS_FCT_IOCB_COMPLETE);
4912 mutex_exit(&cmd_sbp->fct_mtx);
4913 }
4914#endif /* SFCT_SUPPORT */
4915 cp->hbaCmplCmd_sbp++;
4916 atomic_dec_32(&hba->io_active);
4917#ifdef NODE_THROTTLE_SUPPORT
4918 if (sbp->node) {
4919 atomic_dec_32(&sbp->node->io_active);
4920 }
4921#endif /* NODE_THROTTLE_SUPPORT */
4812
4813 /* Copy entry to sbp's iocbq */
4814 iocbq = &sbp->iocbq;
4815 BE_SWAP32_BCOPY((uint8_t *)entry,
4816 (uint8_t *)iocbq, hba->sli.sli3.iocb_rsp_size);
4817
4818 iocbq->next = NULL;
4819

--- 129 unchanged lines hidden (view full) ---

4949 uint32_t size = 0;
4950 uint32_t *RcvError;
4951 uint32_t *RcvDropped;
4952 uint32_t *UbPosted;
4953 emlxs_msg_t *dropped_msg;
4954 char error_str[64];
4955 uint32_t buf_type;
4956 uint32_t *word;
4922
4923 /* Copy entry to sbp's iocbq */
4924 iocbq = &sbp->iocbq;
4925 BE_SWAP32_BCOPY((uint8_t *)entry,
4926 (uint8_t *)iocbq, hba->sli.sli3.iocb_rsp_size);
4927
4928 iocbq->next = NULL;
4929

--- 129 unchanged lines hidden (view full) ---

5059 uint32_t size = 0;
5060 uint32_t *RcvError;
5061 uint32_t *RcvDropped;
5062 uint32_t *UbPosted;
5063 emlxs_msg_t *dropped_msg;
5064 char error_str[64];
5065 uint32_t buf_type;
5066 uint32_t *word;
4957 uint32_t hbq_id;
4958
4959 channelno = cp->channelno;
4960 rp = &hba->sli.sli3.ring[channelno];
4961
4962 iocb = &iocbq->iocb;
4963 word = (uint32_t *)iocb;
4964
4965 switch (channelno) {

--- 43 unchanged lines hidden (view full) ---

5009 word[6], word[7]);
5010 return (1);
5011 }
5012
5013 if (iocb->ULPSTATUS) {
5014 if ((iocb->ULPSTATUS == IOSTAT_LOCAL_REJECT) &&
5015 (iocb->un.grsp.perr.statLocalError ==
5016 IOERR_RCV_BUFFER_TIMEOUT)) {
5067
5068 channelno = cp->channelno;
5069 rp = &hba->sli.sli3.ring[channelno];
5070
5071 iocb = &iocbq->iocb;
5072 word = (uint32_t *)iocb;
5073
5074 switch (channelno) {

--- 43 unchanged lines hidden (view full) ---

5118 word[6], word[7]);
5119 return (1);
5120 }
5121
5122 if (iocb->ULPSTATUS) {
5123 if ((iocb->ULPSTATUS == IOSTAT_LOCAL_REJECT) &&
5124 (iocb->un.grsp.perr.statLocalError ==
5125 IOERR_RCV_BUFFER_TIMEOUT)) {
5017 (void) strcpy(error_str, "Out of posted buffers:");
5126 (void) strlcpy(error_str, "Out of posted buffers:",
5127 sizeof (error_str));
5128 iocb->ULPBDECOUNT = 0;
5018 } else if ((iocb->ULPSTATUS == IOSTAT_LOCAL_REJECT) &&
5019 (iocb->un.grsp.perr.statLocalError ==
5020 IOERR_RCV_BUFFER_WAITING)) {
5129 } else if ((iocb->ULPSTATUS == IOSTAT_LOCAL_REJECT) &&
5130 (iocb->un.grsp.perr.statLocalError ==
5131 IOERR_RCV_BUFFER_WAITING)) {
5021 (void) strcpy(error_str, "Buffer waiting:");
5132 (void) strlcpy(error_str, "Buffer waiting:",
5133 sizeof (error_str));
5134 iocb->ULPBDECOUNT = 0;
5022 goto done;
5023 } else if (iocb->ULPSTATUS == IOSTAT_NEED_BUFF_ENTRY) {
5135 goto done;
5136 } else if (iocb->ULPSTATUS == IOSTAT_NEED_BUFF_ENTRY) {
5024 (void) strcpy(error_str, "Need Buffer Entry:");
5137 (void) strlcpy(error_str, "Need Buffer Entry:",
5138 sizeof (error_str));
5139 iocb->ULPBDECOUNT = 0;
5025 goto done;
5026 } else {
5140 goto done;
5141 } else {
5027 (void) strcpy(error_str, "General error:");
5142 (void) strlcpy(error_str, "General error:",
5143 sizeof (error_str));
5028 }
5029
5030 goto failed;
5031 }
5032
5033 if (hba->flag & FC_HBQ_ENABLED) {
5034 HBQ_INIT_t *hbq;
5035 HBQE_t *hbqE;
5036 uint32_t hbqe_tag;
5144 }
5145
5146 goto failed;
5147 }
5148
5149 if (hba->flag & FC_HBQ_ENABLED) {
5150 HBQ_INIT_t *hbq;
5151 HBQE_t *hbqE;
5152 uint32_t hbqe_tag;
5153 uint32_t hbq_id;
5037
5038 (*UbPosted)--;
5039
5040 hbqE = (HBQE_t *)iocb;
5041 hbq_id = hbqE->unt.ext.HBQ_tag;
5042 hbqe_tag = hbqE->unt.ext.HBQE_tag;
5043
5044 hbq = &hba->sli.sli3.hbq_table[hbq_id];
5045
5046 if (hbqe_tag >= hbq->HBQ_numEntries) {
5154
5155 (*UbPosted)--;
5156
5157 hbqE = (HBQE_t *)iocb;
5158 hbq_id = hbqE->unt.ext.HBQ_tag;
5159 hbqe_tag = hbqE->unt.ext.HBQE_tag;
5160
5161 hbq = &hba->sli.sli3.hbq_table[hbq_id];
5162
5163 if (hbqe_tag >= hbq->HBQ_numEntries) {
5047 (void) sprintf(error_str, "Invalid HBQE tag=%x:",
5048 hbqe_tag);
5164 (void) snprintf(error_str, sizeof (error_str),
5165 "Invalid HBQE iotag=%d:", hbqe_tag);
5049 goto dropped;
5050 }
5051
5052 mp = hba->sli.sli3.hbq_table[hbq_id].HBQ_PostBufs[hbqe_tag];
5053
5054 size = iocb->unsli3.ext_rcv.seq_len;
5055 } else {
5056 bdeAddr =
5057 PADDR(iocb->un.cont64[0].addrHigh,
5058 iocb->un.cont64[0].addrLow);
5059
5060 /* Check for invalid buffer */
5061 if (iocb->un.cont64[0].tus.f.bdeFlags & BUFF_TYPE_INVALID) {
5166 goto dropped;
5167 }
5168
5169 mp = hba->sli.sli3.hbq_table[hbq_id].HBQ_PostBufs[hbqe_tag];
5170
5171 size = iocb->unsli3.ext_rcv.seq_len;
5172 } else {
5173 bdeAddr =
5174 PADDR(iocb->un.cont64[0].addrHigh,
5175 iocb->un.cont64[0].addrLow);
5176
5177 /* Check for invalid buffer */
5178 if (iocb->un.cont64[0].tus.f.bdeFlags & BUFF_TYPE_INVALID) {
5062 (void) strcpy(error_str, "Invalid buffer:");
5179 (void) strlcpy(error_str, "Invalid buffer:",
5180 sizeof (error_str));
5063 goto dropped;
5064 }
5065
5066 mp = emlxs_mem_get_vaddr(hba, rp, bdeAddr);
5067
5068 size = iocb->un.rcvseq64.rcvBde.tus.f.bdeSize;
5069 }
5070
5071 if (!mp) {
5181 goto dropped;
5182 }
5183
5184 mp = emlxs_mem_get_vaddr(hba, rp, bdeAddr);
5185
5186 size = iocb->un.rcvseq64.rcvBde.tus.f.bdeSize;
5187 }
5188
5189 if (!mp) {
5072 (void) strcpy(error_str, "Buffer not mapped:");
5190 (void) strlcpy(error_str, "Buffer not mapped:",
5191 sizeof (error_str));
5073 goto dropped;
5074 }
5075
5076#ifdef FMA_SUPPORT
5077 if (mp->dma_handle) {
5078 if (emlxs_fm_check_dma_handle(hba, mp->dma_handle)
5079 != DDI_FM_OK) {
5080 EMLXS_MSGF(EMLXS_CONTEXT,
5081 &emlxs_invalid_dma_handle_msg,
5192 goto dropped;
5193 }
5194
5195#ifdef FMA_SUPPORT
5196 if (mp->dma_handle) {
5197 if (emlxs_fm_check_dma_handle(hba, mp->dma_handle)
5198 != DDI_FM_OK) {
5199 EMLXS_MSGF(EMLXS_CONTEXT,
5200 &emlxs_invalid_dma_handle_msg,
5082 "emlxs_handle_rcv_seq: hdl=%p",
5201 "handle_rcv_seq: hdl=%p",
5083 mp->dma_handle);
5084 goto dropped;
5085 }
5086 }
5087#endif /* FMA_SUPPORT */
5088
5089 if (!size) {
5202 mp->dma_handle);
5203 goto dropped;
5204 }
5205 }
5206#endif /* FMA_SUPPORT */
5207
5208 if (!size) {
5090 (void) strcpy(error_str, "Buffer empty:");
5209 (void) strlcpy(error_str, "Buffer empty:", sizeof (error_str));
5091 goto dropped;
5092 }
5093
5094 /* To avoid we drop the broadcast packets */
5095 if (channelno != FC_IP_RING) {
5096 /* Get virtual port */
5097 if (hba->flag & FC_NPIV_ENABLED) {
5098 vpi = iocb->unsli3.ext_rcv.vpi;
5099 if (vpi >= hba->vpi_max) {
5210 goto dropped;
5211 }
5212
5213 /* To avoid we drop the broadcast packets */
5214 if (channelno != FC_IP_RING) {
5215 /* Get virtual port */
5216 if (hba->flag & FC_NPIV_ENABLED) {
5217 vpi = iocb->unsli3.ext_rcv.vpi;
5218 if (vpi >= hba->vpi_max) {
5100 (void) sprintf(error_str,
5219 (void) snprintf(error_str, sizeof (error_str),
5101 "Invalid VPI=%d:", vpi);
5102 goto dropped;
5103 }
5104
5105 port = &VPORT(vpi);
5106 }
5107 }
5108
5109 /* Process request */
5110 switch (channelno) {
5220 "Invalid VPI=%d:", vpi);
5221 goto dropped;
5222 }
5223
5224 port = &VPORT(vpi);
5225 }
5226 }
5227
5228 /* Process request */
5229 switch (channelno) {
5111#ifdef SFCT_SUPPORT
5112 case FC_FCT_RING:
5230 case FC_FCT_RING:
5113 (void) emlxs_fct_handle_unsol_req(port, cp, iocbq, mp, size);
5114 break;
5231 if (port->mode == MODE_INITIATOR) {
5232 (void) strlcpy(error_str, "Target mode disabled:",
5233 sizeof (error_str));
5234 goto dropped;
5235#ifdef SFCT_SUPPORT
5236 } else if (port->mode == MODE_TARGET) {
5237 (void) emlxs_fct_handle_unsol_req(port, cp, iocbq, mp,
5238 size);
5115#endif /* SFCT_SUPPORT */
5239#endif /* SFCT_SUPPORT */
5240 } else {
5241 (void) snprintf(error_str, sizeof (error_str),
5242 "Invalid mode=%x:", port->mode);
5243 goto dropped;
5244 }
5245 break;
5116
5117 case FC_IP_RING:
5246
5247 case FC_IP_RING:
5118 (void) emlxs_ip_handle_unsol_req(port, cp, iocbq, mp, size);
5248 if (port->mode == MODE_INITIATOR) {
5249 (void) emlxs_ip_handle_unsol_req(port, cp, iocbq,
5250 mp, size);
5251#ifdef SFCT_SUPPORT
5252 } else if (port->mode == MODE_TARGET) {
5253 (void) strlcpy(error_str, "Initiator mode disabled:",
5254 sizeof (error_str));
5255 goto dropped;
5256#endif /* SFCT_SUPPORT */
5257 } else {
5258 (void) snprintf(error_str, sizeof (error_str),
5259 "Invalid mode=%x:", port->mode);
5260 goto dropped;
5261 }
5119 break;
5120
5121 case FC_ELS_RING:
5262 break;
5263
5264 case FC_ELS_RING:
5122 /* If this is a target port, then let fct handle this */
5123 if (port->ini_mode) {
5265 if (port->mode == MODE_INITIATOR) {
5124 (void) emlxs_els_handle_unsol_req(port, cp, iocbq, mp,
5125 size);
5266 (void) emlxs_els_handle_unsol_req(port, cp, iocbq, mp,
5267 size);
5126 }
5127#ifdef SFCT_SUPPORT
5268#ifdef SFCT_SUPPORT
5128 else if (port->tgt_mode) {
5269 } else if (port->mode == MODE_TARGET) {
5129 (void) emlxs_fct_handle_unsol_els(port, cp, iocbq, mp,
5130 size);
5270 (void) emlxs_fct_handle_unsol_els(port, cp, iocbq, mp,
5271 size);
5131 }
5132#endif /* SFCT_SUPPORT */
5272#endif /* SFCT_SUPPORT */
5273 } else {
5274 (void) snprintf(error_str, sizeof (error_str),
5275 "Invalid mode=%x:", port->mode);
5276 goto dropped;
5277 }
5133 break;
5134
5135 case FC_CT_RING:
5136 (void) emlxs_ct_handle_unsol_req(port, cp, iocbq, mp, size);
5137 break;
5138 }
5139
5140 goto done;

--- 4 unchanged lines hidden (view full) ---

5145 EMLXS_MSGF(EMLXS_CONTEXT, dropped_msg,
5146 "%s: cmd=%x %s %x %x %x %x",
5147 error_str, iocb->ULPCOMMAND, emlxs_state_xlate(iocb->ULPSTATUS),
5148 word[4], word[5], word[6], word[7]);
5149
5150 if (channelno == FC_FCT_RING) {
5151 uint32_t sid;
5152
5278 break;
5279
5280 case FC_CT_RING:
5281 (void) emlxs_ct_handle_unsol_req(port, cp, iocbq, mp, size);
5282 break;
5283 }
5284
5285 goto done;

--- 4 unchanged lines hidden (view full) ---

5290 EMLXS_MSGF(EMLXS_CONTEXT, dropped_msg,
5291 "%s: cmd=%x %s %x %x %x %x",
5292 error_str, iocb->ULPCOMMAND, emlxs_state_xlate(iocb->ULPSTATUS),
5293 word[4], word[5], word[6], word[7]);
5294
5295 if (channelno == FC_FCT_RING) {
5296 uint32_t sid;
5297
5153 if (hba->sli_mode >= EMLXS_HBA_SLI3_MODE) {
5298 if (hba->sli_mode == EMLXS_HBA_SLI3_MODE) {
5154 emlxs_node_t *ndlp;
5155 ndlp = emlxs_node_find_rpi(port, iocb->ULPIOTAG);
5299 emlxs_node_t *ndlp;
5300 ndlp = emlxs_node_find_rpi(port, iocb->ULPIOTAG);
5301 if (! ndlp) {
5302 goto done;
5303 }
5156 sid = ndlp->nlp_DID;
5157 } else {
5158 sid = iocb->un.ulpWord[4] & 0xFFFFFF;
5159 }
5160
5161 emlxs_send_logo(port, sid);
5162 }
5163

--- 5 unchanged lines hidden (view full) ---

5169 EMLXS_MSGF(EMLXS_CONTEXT, dropped_msg,
5170 "%s: cmd=%x %s %x %x %x %x hba:%x %x",
5171 error_str, iocb->ULPCOMMAND, emlxs_state_xlate(iocb->ULPSTATUS),
5172 word[4], word[5], word[6], word[7], hba->state, hba->flag);
5173
5174done:
5175
5176 if (hba->flag & FC_HBQ_ENABLED) {
5304 sid = ndlp->nlp_DID;
5305 } else {
5306 sid = iocb->un.ulpWord[4] & 0xFFFFFF;
5307 }
5308
5309 emlxs_send_logo(port, sid);
5310 }
5311

--- 5 unchanged lines hidden (view full) ---

5317 EMLXS_MSGF(EMLXS_CONTEXT, dropped_msg,
5318 "%s: cmd=%x %s %x %x %x %x hba:%x %x",
5319 error_str, iocb->ULPCOMMAND, emlxs_state_xlate(iocb->ULPSTATUS),
5320 word[4], word[5], word[6], word[7], hba->state, hba->flag);
5321
5322done:
5323
5324 if (hba->flag & FC_HBQ_ENABLED) {
5177 emlxs_update_HBQ_index(hba, hbq_id);
5325 if (iocb->ULPBDECOUNT) {
5326 HBQE_t *hbqE;
5327 uint32_t hbq_id;
5328
5329 hbqE = (HBQE_t *)iocb;
5330 hbq_id = hbqE->unt.ext.HBQ_tag;
5331
5332 emlxs_update_HBQ_index(hba, hbq_id);
5333 }
5178 } else {
5179 if (mp) {
5180 emlxs_mem_put(hba, buf_type, (void *)mp);
5181 }
5334 } else {
5335 if (mp) {
5336 emlxs_mem_put(hba, buf_type, (void *)mp);
5337 }
5182 (void) emlxs_post_buffer(hba, rp, 1);
5338
5339 if (iocb->ULPBDECOUNT) {
5340 (void) emlxs_post_buffer(hba, rp, 1);
5341 }
5183 }
5184
5185 return (0);
5186
5187} /* emlxs_handle_rcv_seq() */
5188
5189
5190/* EMLXS_CMD_RING_LOCK must be held when calling this function */

--- 23 unchanged lines hidden (view full) ---

5214 iocbq->node = (void *)&port->node_base;
5215 sbp->node = (void *)&port->node_base;
5216 }
5217
5218 sbp->pkt_flags |= PACKET_IN_CHIPQ;
5219 mutex_exit(&sbp->mtx);
5220
5221 atomic_inc_32(&hba->io_active);
5342 }
5343
5344 return (0);
5345
5346} /* emlxs_handle_rcv_seq() */
5347
5348
5349/* EMLXS_CMD_RING_LOCK must be held when calling this function */

--- 23 unchanged lines hidden (view full) ---

5373 iocbq->node = (void *)&port->node_base;
5374 sbp->node = (void *)&port->node_base;
5375 }
5376
5377 sbp->pkt_flags |= PACKET_IN_CHIPQ;
5378 mutex_exit(&sbp->mtx);
5379
5380 atomic_inc_32(&hba->io_active);
5381#ifdef NODE_THROTTLE_SUPPORT
5382 if (sbp->node) {
5383 atomic_inc_32(&sbp->node->io_active);
5384 }
5385#endif /* NODE_THROTTLE_SUPPORT */
5222
5223#ifdef SFCT_SUPPORT
5224#ifdef FCT_IO_TRACE
5225 if (sbp->fct_cmd) {
5226 emlxs_fct_io_trace(port, sbp->fct_cmd,
5227 EMLXS_FCT_IOCB_ISSUED);
5228 emlxs_fct_io_trace(port, sbp->fct_cmd,
5229 icmd->ULPCOMMAND);

--- 71 unchanged lines hidden (view full) ---

5301
5302 j = 0;
5303 while (j++ < 10000) {
5304 if (hba->mbox_queue_flag == 0) {
5305 break;
5306 }
5307
5308 mutex_exit(&EMLXS_PORT_LOCK);
5386
5387#ifdef SFCT_SUPPORT
5388#ifdef FCT_IO_TRACE
5389 if (sbp->fct_cmd) {
5390 emlxs_fct_io_trace(port, sbp->fct_cmd,
5391 EMLXS_FCT_IOCB_ISSUED);
5392 emlxs_fct_io_trace(port, sbp->fct_cmd,
5393 icmd->ULPCOMMAND);

--- 71 unchanged lines hidden (view full) ---

5465
5466 j = 0;
5467 while (j++ < 10000) {
5468 if (hba->mbox_queue_flag == 0) {
5469 break;
5470 }
5471
5472 mutex_exit(&EMLXS_PORT_LOCK);
5309 DELAYUS(100);
5473 BUSYWAIT_US(100);
5310 mutex_enter(&EMLXS_PORT_LOCK);
5311 }
5312
5313 if (hba->mbox_queue_flag != 0) {
5314 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5315 "Interlock failed. Mailbox busy.");
5316 mutex_exit(&EMLXS_PORT_LOCK);
5317 return;

--- 53 unchanged lines hidden (view full) ---

5371 j = 0;
5372 while (j++ < 1000) {
5373 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5374
5375 if (value == 0xAAAAAAAA) {
5376 break;
5377 }
5378
5474 mutex_enter(&EMLXS_PORT_LOCK);
5475 }
5476
5477 if (hba->mbox_queue_flag != 0) {
5478 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5479 "Interlock failed. Mailbox busy.");
5480 mutex_exit(&EMLXS_PORT_LOCK);
5481 return;

--- 53 unchanged lines hidden (view full) ---

5535 j = 0;
5536 while (j++ < 1000) {
5537 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5538
5539 if (value == 0xAAAAAAAA) {
5540 break;
5541 }
5542
5379 DELAYUS(50);
5543 BUSYWAIT_US(50);
5380 }
5381
5382 if (value == 0xAAAAAAAA) {
5383 /* Now wait for mailbox ownership to clear */
5384 while (j++ < 10000) {
5385 word0 =
5386 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5387
5388 if (swpmb->mbxOwner == 0) {
5389 break;
5390 }
5391
5544 }
5545
5546 if (value == 0xAAAAAAAA) {
5547 /* Now wait for mailbox ownership to clear */
5548 while (j++ < 10000) {
5549 word0 =
5550 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5551
5552 if (swpmb->mbxOwner == 0) {
5553 break;
5554 }
5555
5392 DELAYUS(50);
5556 BUSYWAIT_US(50);
5393 }
5394
5395 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5396 "Interlock succeeded.");
5397
5398 goto done;
5399 }
5400

--- 25 unchanged lines hidden (view full) ---

5426 j = 0;
5427 while (j++ < 1000) {
5428 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5429
5430 if (value == 0xAAAAAAAA) {
5431 break;
5432 }
5433
5557 }
5558
5559 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5560 "Interlock succeeded.");
5561
5562 goto done;
5563 }
5564

--- 25 unchanged lines hidden (view full) ---

5590 j = 0;
5591 while (j++ < 1000) {
5592 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5593
5594 if (value == 0xAAAAAAAA) {
5595 break;
5596 }
5597
5434 DELAYUS(50);
5598 BUSYWAIT_US(50);
5435 }
5436
5437 if (value == 0xAAAAAAAA) {
5438 /* Now wait for mailbox ownership to clear */
5439 while (j++ < 10000) {
5440 word0 =
5441 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5442
5443 if (swpmb->mbxOwner == 0) {
5444 break;
5445 }
5446
5599 }
5600
5601 if (value == 0xAAAAAAAA) {
5602 /* Now wait for mailbox ownership to clear */
5603 while (j++ < 10000) {
5604 word0 =
5605 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5606
5607 if (swpmb->mbxOwner == 0) {
5608 break;
5609 }
5610
5447 DELAYUS(50);
5611 BUSYWAIT_US(50);
5448 }
5449
5450 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5451 "Interlock succeeded.");
5452
5453 goto done;
5454 }
5455

--- 16 unchanged lines hidden (view full) ---

5472 j = 0;
5473 while (j++ < 10000) {
5474 ha_copy = READ_CSR_REG(hba, FC_HA_REG(hba));
5475
5476 if (ha_copy & HA_ERATT) {
5477 break;
5478 }
5479
5612 }
5613
5614 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5615 "Interlock succeeded.");
5616
5617 goto done;
5618 }
5619

--- 16 unchanged lines hidden (view full) ---

5636 j = 0;
5637 while (j++ < 10000) {
5638 ha_copy = READ_CSR_REG(hba, FC_HA_REG(hba));
5639
5640 if (ha_copy & HA_ERATT) {
5641 break;
5642 }
5643
5480 DELAYUS(50);
5644 BUSYWAIT_US(50);
5481 }
5482
5483 if (ha_copy & HA_ERATT) {
5484 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5485 "Interlock failed. Board killed.");
5486 } else {
5487 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5488 "Interlock failed. Board not killed.");

--- 70 unchanged lines hidden (view full) ---

5559 /* First wait for command acceptence */
5560 j = 0;
5561 while (j++ < 1000) {
5562 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5563
5564 if (value == 0xAAAAAAAA) {
5565 break;
5566 }
5645 }
5646
5647 if (ha_copy & HA_ERATT) {
5648 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5649 "Interlock failed. Board killed.");
5650 } else {
5651 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
5652 "Interlock failed. Board not killed.");

--- 70 unchanged lines hidden (view full) ---

5723 /* First wait for command acceptence */
5724 j = 0;
5725 while (j++ < 1000) {
5726 value = READ_SLIM_ADDR(hba, (((volatile uint32_t *)mb1) + 1));
5727
5728 if (value == 0xAAAAAAAA) {
5729 break;
5730 }
5567 DELAYUS(50);
5731 BUSYWAIT_US(50);
5568 }
5569 if (value == 0xAAAAAAAA) {
5570 /* Now wait for mailbox ownership to clear */
5571 while (j++ < 10000) {
5572 word0 =
5573 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5574 if (swpmb->mbxOwner == 0) {
5575 break;
5576 }
5732 }
5733 if (value == 0xAAAAAAAA) {
5734 /* Now wait for mailbox ownership to clear */
5735 while (j++ < 10000) {
5736 word0 =
5737 READ_SLIM_ADDR(hba, ((volatile uint32_t *)mb1));
5738 if (swpmb->mbxOwner == 0) {
5739 break;
5740 }
5577 DELAYUS(50);
5741 BUSYWAIT_US(50);
5578 }
5579 goto done;
5580 }
5581
5582done:
5583 EMLXS_STATE_CHANGE_LOCKED(hba, FC_KILLED);
5584
5585#ifdef FMA_SUPPORT

--- 237 unchanged lines hidden (view full) ---

5823 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
5824 }
5825 }
5826 return (0);
5827
5828} /* emlxs_handle_mb_event() */
5829
5830
5742 }
5743 goto done;
5744 }
5745
5746done:
5747 EMLXS_STATE_CHANGE_LOCKED(hba, FC_KILLED);
5748
5749#ifdef FMA_SUPPORT

--- 237 unchanged lines hidden (view full) ---

5987 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
5988 }
5989 }
5990 return (0);
5991
5992} /* emlxs_handle_mb_event() */
5993
5994
5831extern void
5995static void
5832emlxs_sli3_timer(emlxs_hba_t *hba)
5833{
5834 /* Perform SLI3 level timer checks */
5835
5836 emlxs_sli3_timer_check_mbox(hba);
5837
5838} /* emlxs_sli3_timer() */
5839

--- 389 unchanged lines hidden (view full) ---

6229 ringno = FC_FCT_RING;
6230 seg = MEM_FCTBUF;
6231 HBASTATS.FctUbPosted = count;
6232 break;
6233#endif /* SFCT_SUPPORT */
6234
6235 default:
6236 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
5996emlxs_sli3_timer(emlxs_hba_t *hba)
5997{
5998 /* Perform SLI3 level timer checks */
5999
6000 emlxs_sli3_timer_check_mbox(hba);
6001
6002} /* emlxs_sli3_timer() */
6003

--- 389 unchanged lines hidden (view full) ---

6393 ringno = FC_FCT_RING;
6394 seg = MEM_FCTBUF;
6395 HBASTATS.FctUbPosted = count;
6396 break;
6397#endif /* SFCT_SUPPORT */
6398
6399 default:
6400 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6237 "emlxs_hbq_setup: Invalid HBQ id. (%x)", hbq_id);
6401 "hbq_setup: Invalid HBQ id. (%x)", hbq_id);
6238 return (1);
6239 }
6240
6241 /* Configure HBQ */
6242 hbq = &hba->sli.sli3.hbq_table[hbq_id];
6243 hbq->HBQ_numEntries = count;
6244
6245 /* Get a Mailbox buffer to setup mailbox commands for CONFIG_HBQ */
6402 return (1);
6403 }
6404
6405 /* Configure HBQ */
6406 hbq = &hba->sli.sli3.hbq_table[hbq_id];
6407 hbq->HBQ_numEntries = count;
6408
6409 /* Get a Mailbox buffer to setup mailbox commands for CONFIG_HBQ */
6246 if ((mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1)) == 0) {
6410 if ((mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX)) == 0) {
6247 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6411 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6248 "emlxs_hbq_setup: Unable to get mailbox.");
6412 "hbq_setup: Unable to get mailbox.");
6249 return (1);
6250 }
6251 mb = (MAILBOX *)mbq;
6252
6253 /* Allocate HBQ Host buffer and Initialize the HBQEs */
6254 if (emlxs_hbq_alloc(hba, hbq_id)) {
6255 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6413 return (1);
6414 }
6415 mb = (MAILBOX *)mbq;
6416
6417 /* Allocate HBQ Host buffer and Initialize the HBQEs */
6418 if (emlxs_hbq_alloc(hba, hbq_id)) {
6419 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6256 "emlxs_hbq_setup: Unable to allocate HBQ.");
6420 "hbq_setup: Unable to allocate HBQ.");
6257 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6258 return (1);
6259 }
6260
6261 hbq->HBQ_recvNotify = 1;
6262 hbq->HBQ_num_mask = 0; /* Bind to ring */
6263 hbq->HBQ_profile = 0; /* Selection profile */
6264 /* 0=all, 7=logentry */

--- 11 unchanged lines hidden (view full) ---

6276 hbq->HBQ_PostBufCnt = hbq->HBQ_numEntries;
6277 bzero(hbq->HBQ_PostBufs, sizeof (hbq->HBQ_PostBufs));
6278
6279 /* Fill in POST BUFFERs in HBQE */
6280 hbqE = (HBQE_t *)hbq->HBQ_host_buf.virt;
6281 for (j = 0; j < hbq->HBQ_numEntries; j++, hbqE++) {
6282 /* Allocate buffer to post */
6283 if ((mp = (MATCHMAP *)emlxs_mem_get(hba,
6421 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6422 return (1);
6423 }
6424
6425 hbq->HBQ_recvNotify = 1;
6426 hbq->HBQ_num_mask = 0; /* Bind to ring */
6427 hbq->HBQ_profile = 0; /* Selection profile */
6428 /* 0=all, 7=logentry */

--- 11 unchanged lines hidden (view full) ---

6440 hbq->HBQ_PostBufCnt = hbq->HBQ_numEntries;
6441 bzero(hbq->HBQ_PostBufs, sizeof (hbq->HBQ_PostBufs));
6442
6443 /* Fill in POST BUFFERs in HBQE */
6444 hbqE = (HBQE_t *)hbq->HBQ_host_buf.virt;
6445 for (j = 0; j < hbq->HBQ_numEntries; j++, hbqE++) {
6446 /* Allocate buffer to post */
6447 if ((mp = (MATCHMAP *)emlxs_mem_get(hba,
6284 seg, 1)) == 0) {
6448 seg)) == 0) {
6285 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6449 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_mem_alloc_msg,
6286 "emlxs_hbq_setup: Unable to allocate HBQ buffer. "
6450 "hbq_setup: Unable to allocate HBQ buffer. "
6287 "cnt=%d", j);
6288 emlxs_hbq_free_all(hba, hbq_id);
6289 return (1);
6290 }
6291
6292 hbq->HBQ_PostBufs[j] = mp;
6293
6294 hbqE->unt.ext.HBQ_tag = hbq_id;

--- 7 unchanged lines hidden (view full) ---

6302 hbqE->bde.addrHigh =
6303 BE_SWAP32(PADDR_HI(mp->phys));
6304 }
6305
6306 /* Issue CONFIG_HBQ */
6307 emlxs_mb_config_hbq(hba, mbq, hbq_id);
6308 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) != MBX_SUCCESS) {
6309 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
6451 "cnt=%d", j);
6452 emlxs_hbq_free_all(hba, hbq_id);
6453 return (1);
6454 }
6455
6456 hbq->HBQ_PostBufs[j] = mp;
6457
6458 hbqE->unt.ext.HBQ_tag = hbq_id;

--- 7 unchanged lines hidden (view full) ---

6466 hbqE->bde.addrHigh =
6467 BE_SWAP32(PADDR_HI(mp->phys));
6468 }
6469
6470 /* Issue CONFIG_HBQ */
6471 emlxs_mb_config_hbq(hba, mbq, hbq_id);
6472 if (emlxs_sli3_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0) != MBX_SUCCESS) {
6473 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg,
6310 "emlxs_hbq_setup: Unable to config HBQ. cmd=%x status=%x",
6474 "hbq_setup: Unable to config HBQ. cmd=%x status=%x",
6311 mb->mbxCommand, mb->mbxStatus);
6312
6313 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6314 emlxs_hbq_free_all(hba, hbq_id);
6315 return (1);
6316 }
6317
6318 /* Setup HBQ Get/Put indexes */

--- 239 unchanged lines hidden (view full) ---

6558#ifdef FMA_SUPPORT
6559 /* Access handle validation */
6560 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);
6561#endif /* FMA_SUPPORT */
6562 return (ha_copy);
6563
6564} /* emlxs_check_attention() */
6565
6475 mb->mbxCommand, mb->mbxStatus);
6476
6477 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6478 emlxs_hbq_free_all(hba, hbq_id);
6479 return (1);
6480 }
6481
6482 /* Setup HBQ Get/Put indexes */

--- 239 unchanged lines hidden (view full) ---

6722#ifdef FMA_SUPPORT
6723 /* Access handle validation */
6724 EMLXS_CHK_ACC_HANDLE(hba, hba->sli.sli3.csr_acc_handle);
6725#endif /* FMA_SUPPORT */
6726 return (ha_copy);
6727
6728} /* emlxs_check_attention() */
6729
6566void
6730
6731static void
6567emlxs_sli3_poll_erratt(emlxs_hba_t *hba)
6568{
6569 uint32_t ha_copy;
6570
6571 ha_copy = emlxs_check_attention(hba);
6572
6573 /* Adapter error */
6574 if (ha_copy & HA_ERATT) {
6575 HBASTATS.IntrEvent[6]++;
6576 emlxs_handle_ff_error(hba);
6577 }
6732emlxs_sli3_poll_erratt(emlxs_hba_t *hba)
6733{
6734 uint32_t ha_copy;
6735
6736 ha_copy = emlxs_check_attention(hba);
6737
6738 /* Adapter error */
6739 if (ha_copy & HA_ERATT) {
6740 HBASTATS.IntrEvent[6]++;
6741 emlxs_handle_ff_error(hba);
6742 }
6578}
6743
6744} /* emlxs_sli3_poll_erratt() */
6745
6746
6747static uint32_t
6748emlxs_sli3_reg_did_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq)
6749{
6750 emlxs_port_t *port = (emlxs_port_t *)mbq->port;
6751 MAILBOXQ *mboxq;
6752 MAILBOX *mb;
6753 MATCHMAP *mp;
6754 NODELIST *ndlp;
6755 emlxs_port_t *vport;
6756 SERV_PARM *sp;
6757 int32_t i;
6758 uint32_t control;
6759 uint32_t ldata;
6760 uint32_t ldid;
6761 uint16_t lrpi;
6762 uint16_t lvpi;
6763 uint32_t rval;
6764
6765 mb = (MAILBOX *)mbq;
6766
6767 if (mb->mbxStatus) {
6768 if (mb->mbxStatus == MBXERR_NO_RESOURCES) {
6769 control = mb->un.varRegLogin.un.sp.bdeSize;
6770 if (control == 0) {
6771 /* Special handle for vport PLOGI */
6772 if (mbq->iocbq == (uint8_t *)1) {
6773 mbq->iocbq = NULL;
6774 }
6775 return (0);
6776 }
6777 emlxs_mb_retry(hba, mbq);
6778 return (1);
6779 }
6780 if (mb->mbxStatus == MBXERR_RPI_FULL) {
6781 EMLXS_MSGF(EMLXS_CONTEXT,
6782 &emlxs_node_create_failed_msg,
6783 "Limit reached. count=%d", port->node_count);
6784 }
6785
6786 /* Special handle for vport PLOGI */
6787 if (mbq->iocbq == (uint8_t *)1) {
6788 mbq->iocbq = NULL;
6789 }
6790
6791 return (0);
6792 }
6793
6794 mp = (MATCHMAP *)mbq->bp;
6795 if (!mp) {
6796 return (0);
6797 }
6798
6799 ldata = mb->un.varWords[5];
6800 lvpi = (ldata & 0xffff);
6801 port = &VPORT(lvpi);
6802
6803 /* First copy command data */
6804 ldata = mb->un.varWords[0]; /* get rpi */
6805 lrpi = ldata & 0xffff;
6806
6807 ldata = mb->un.varWords[1]; /* get did */
6808 ldid = ldata & MASK_DID;
6809
6810 sp = (SERV_PARM *)mp->virt;
6811
6812 /* Create or update the node */
6813 ndlp = emlxs_node_create(port, ldid, lrpi, sp);
6814
6815 if (ndlp == NULL) {
6816 emlxs_ub_priv_t *ub_priv;
6817
6818 /*
6819 * Fake a mailbox error, so the mbox_fini
6820 * can take appropriate action
6821 */
6822 mb->mbxStatus = MBXERR_RPI_FULL;
6823 if (mbq->ubp) {
6824 ub_priv = ((fc_unsol_buf_t *)mbq->ubp)->ub_fca_private;
6825 ub_priv->flags |= EMLXS_UB_REPLY;
6826 }
6827
6828 /* This must be (0xFFFFFE) which was registered by vport */
6829 if (lrpi == 0) {
6830 return (0);
6831 }
6832
6833 if (!(mboxq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX))) {
6834 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
6835 "reg_did_mbcmpl:failed. Unable to allocate mbox");
6836 return (0);
6837 }
6838
6839 mb = (MAILBOX *)mboxq->mbox;
6840 mb->un.varUnregLogin.rpi = lrpi;
6841 mb->un.varUnregLogin.vpi = lvpi;
6842
6843 mb->mbxCommand = MBX_UNREG_LOGIN;
6844 mb->mbxOwner = OWN_HOST;
6845 mboxq->sbp = NULL;
6846 mboxq->ubp = NULL;
6847 mboxq->iocbq = NULL;
6848 mboxq->mbox_cmpl = NULL;
6849 mboxq->context = NULL;
6850 mboxq->port = (void *)port;
6851
6852 rval = EMLXS_SLI_ISSUE_MBOX_CMD(hba, mboxq, MBX_NOWAIT, 0);
6853 if ((rval != MBX_BUSY) && (rval != MBX_SUCCESS)) {
6854 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
6855 "reg_did_mbcmpl:failed. Unable to send request.");
6856
6857 emlxs_mem_put(hba, MEM_MBOX, (void *)mboxq);
6858 return (0);
6859 }
6860
6861 return (0);
6862 }
6863
6864 if (ndlp->nlp_DID == FABRIC_DID) {
6865 /* FLOGI/FDISC successfully completed on this port */
6866 mutex_enter(&EMLXS_PORT_LOCK);
6867 port->flag |= EMLXS_PORT_FLOGI_CMPL;
6868 mutex_exit(&EMLXS_PORT_LOCK);
6869
6870 /* If CLEAR_LA has been sent, then attempt to */
6871 /* register the vpi now */
6872 if (hba->state == FC_READY) {
6873 (void) emlxs_mb_reg_vpi(port, NULL);
6874 }
6875
6876 /*
6877 * If NPIV Fabric support has just been established on
6878 * the physical port, then notify the vports of the
6879 * link up
6880 */
6881 if ((lvpi == 0) &&
6882 (hba->flag & FC_NPIV_ENABLED) &&
6883 (hba->flag & FC_NPIV_SUPPORTED)) {
6884 /* Skip the physical port */
6885 for (i = 1; i < MAX_VPORTS; i++) {
6886 vport = &VPORT(i);
6887
6888 if (!(vport->flag & EMLXS_PORT_BOUND) ||
6889 !(vport->flag &
6890 EMLXS_PORT_ENABLED)) {
6891 continue;
6892 }
6893
6894 emlxs_port_online(vport);
6895 }
6896 }
6897 }
6898
6899 /* Check for special restricted login flag */
6900 if (mbq->iocbq == (uint8_t *)1) {
6901 mbq->iocbq = NULL;
6902 (void) EMLXS_SLI_UNREG_NODE(port, ndlp, NULL, NULL, NULL);
6903 return (0);
6904 }
6905
6906 /* Needed for FCT trigger in emlxs_mb_deferred_cmpl */
6907 if (mbq->sbp) {
6908 ((emlxs_buf_t *)mbq->sbp)->node = ndlp;
6909 }
6910
6911#ifdef DHCHAP_SUPPORT
6912 if (mbq->sbp || mbq->ubp) {
6913 if (emlxs_dhc_auth_start(port, ndlp, mbq->sbp,
6914 mbq->ubp) == 0) {
6915 /* Auth started - auth completion will */
6916 /* handle sbp and ubp now */
6917 mbq->sbp = NULL;
6918 mbq->ubp = NULL;
6919 }
6920 }
6921#endif /* DHCHAP_SUPPORT */
6922
6923 return (0);
6924
6925} /* emlxs_sli3_reg_did_mbcmpl() */
6926
6927
6928static uint32_t
6929emlxs_sli3_reg_did(emlxs_port_t *port, uint32_t did, SERV_PARM *param,
6930 emlxs_buf_t *sbp, fc_unsol_buf_t *ubp, IOCBQ *iocbq)
6931{
6932 emlxs_hba_t *hba = HBA;
6933 MATCHMAP *mp;
6934 MAILBOXQ *mbq;
6935 MAILBOX *mb;
6936 uint32_t rval;
6937
6938 /* Check for invalid node ids to register */
6939 if ((did == 0) && (!(hba->flag & FC_LOOPBACK_MODE))) {
6940 return (1);
6941 }
6942
6943 if (did & 0xff000000) {
6944 return (1);
6945 }
6946
6947 if ((rval = emlxs_mb_check_sparm(hba, param))) {
6948 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
6949 "Invalid service parameters. did=%06x rval=%d", did,
6950 rval);
6951
6952 return (1);
6953 }
6954
6955 /* Check if the node limit has been reached */
6956 if (port->node_count >= hba->max_nodes) {
6957 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
6958 "Limit reached. did=%06x count=%d", did,
6959 port->node_count);
6960
6961 return (1);
6962 }
6963
6964 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX))) {
6965 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
6966 "Unable to allocate mailbox. did=%x", did);
6967
6968 return (1);
6969 }
6970 mb = (MAILBOX *)mbq->mbox;
6971 bzero((void *)mb, MAILBOX_CMD_BSIZE);
6972
6973 /* Build login request */
6974 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF)) == 0) {
6975 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
6976
6977 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
6978 "Unable to allocate buffer. did=%x", did);
6979 return (1);
6980 }
6981 bcopy((void *)param, (void *)mp->virt, sizeof (SERV_PARM));
6982
6983 mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (SERV_PARM);
6984 mb->un.varRegLogin.un.sp64.addrHigh = PADDR_HI(mp->phys);
6985 mb->un.varRegLogin.un.sp64.addrLow = PADDR_LO(mp->phys);
6986 mb->un.varRegLogin.did = did;
6987 mb->un.varWords[30] = 0; /* flags */
6988 mb->mbxCommand = MBX_REG_LOGIN64;
6989 mb->mbxOwner = OWN_HOST;
6990 mb->un.varRegLogin.vpi = port->vpi;
6991 mb->un.varRegLogin.rpi = 0;
6992
6993 mbq->sbp = (void *)sbp;
6994 mbq->ubp = (void *)ubp;
6995 mbq->iocbq = (void *)iocbq;
6996 mbq->bp = (void *)mp;
6997 mbq->mbox_cmpl = emlxs_sli3_reg_did_mbcmpl;
6998 mbq->context = NULL;
6999 mbq->port = (void *)port;
7000
7001 rval = EMLXS_SLI_ISSUE_MBOX_CMD(hba, mbq, MBX_NOWAIT, 0);
7002 if ((rval != MBX_BUSY) && (rval != MBX_SUCCESS)) {
7003 emlxs_mem_put(hba, MEM_BUF, (void *)mp);
7004 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
7005
7006 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
7007 "Unable to send mbox. did=%x", did);
7008 return (1);
7009 }
7010
7011 return (0);
7012
7013} /* emlxs_sli3_reg_did() */
7014
7015
7016/*ARGSUSED*/
7017static uint32_t
7018emlxs_sli3_unreg_node_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq)
7019{
7020 emlxs_port_t *port = (emlxs_port_t *)mbq->port;
7021 MAILBOX *mb;
7022 NODELIST *node;
7023 uint16_t rpi;
7024
7025 node = (NODELIST *)mbq->context;
7026 mb = (MAILBOX *)mbq;
7027 rpi = (node)? node->nlp_Rpi:0xffff;
7028
7029 if (mb->mbxStatus) {
7030 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
7031 "unreg_node_mbcmpl:failed. node=%p rpi=%d status=%x",
7032 node, rpi, mb->mbxStatus);
7033
7034 return (0);
7035 }
7036
7037 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
7038 "unreg_node_mbcmpl: node=%p rpi=%d",
7039 node, rpi);
7040
7041 if (node) {
7042 emlxs_node_rm(port, node);
7043
7044 } else { /* All nodes */
7045 emlxs_node_destroy_all(port);
7046 }
7047
7048 return (0);
7049
7050} /* emlxs_sli3_unreg_node_mbcmpl */
7051
7052
7053static uint32_t
7054emlxs_sli3_unreg_node(emlxs_port_t *port, NODELIST *node, emlxs_buf_t *sbp,
7055 fc_unsol_buf_t *ubp, IOCBQ *iocbq)
7056{
7057 emlxs_hba_t *hba = HBA;
7058 MAILBOXQ *mbq;
7059 MAILBOX *mb;
7060 uint16_t rpi;
7061 uint32_t rval;
7062
7063 if (node) {
7064 /* Check for base node */
7065 if (node == &port->node_base) {
7066 /* just flush base node */
7067 (void) emlxs_tx_node_flush(port, &port->node_base,
7068 0, 0, 0);
7069 (void) emlxs_chipq_node_flush(port, 0,
7070 &port->node_base, 0);
7071
7072 port->did = 0;
7073
7074 /* Return now */
7075 return (1);
7076 }
7077
7078 rpi = (uint16_t)node->nlp_Rpi;
7079
7080 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
7081 "unreg_node:%p rpi=%d", node, rpi);
7082
7083 /* This node must be (0xFFFFFE) which registered by vport */
7084 if (rpi == 0) {
7085 emlxs_node_rm(port, node);
7086 return (0);
7087 }
7088
7089 } else { /* Unreg all nodes */
7090 rpi = 0xffff;
7091
7092 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
7093 "unreg_node: All");
7094 }
7095
7096 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX))) {
7097 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
7098 "unreg_node:failed. Unable to allocate mbox");
7099 return (1);
7100 }
7101
7102 mb = (MAILBOX *)mbq->mbox;
7103 mb->un.varUnregLogin.rpi = rpi;
7104 mb->un.varUnregLogin.vpi = port->vpip->VPI;
7105
7106 mb->mbxCommand = MBX_UNREG_LOGIN;
7107 mb->mbxOwner = OWN_HOST;
7108 mbq->sbp = (void *)sbp;
7109 mbq->ubp = (void *)ubp;
7110 mbq->iocbq = (void *)iocbq;
7111 mbq->mbox_cmpl = emlxs_sli3_unreg_node_mbcmpl;
7112 mbq->context = (void *)node;
7113 mbq->port = (void *)port;
7114
7115 rval = EMLXS_SLI_ISSUE_MBOX_CMD(hba, mbq, MBX_NOWAIT, 0);
7116 if ((rval != MBX_BUSY) && (rval != MBX_SUCCESS)) {
7117 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
7118 "unreg_node:failed. Unable to send request.");
7119
7120 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
7121 return (1);
7122 }
7123
7124 return (0);
7125
7126} /* emlxs_sli3_unreg_node() */