emlxs_mbox.c (a9800beb) emlxs_mbox.c (8f23e9fa)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
8 * You can obtain a copy of the license at
9 * http://www.opensource.org/licenses/cddl1.txt.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2010 Emulex. All rights reserved.
23 * Copyright (c) 2004-2012 Emulex. All rights reserved.
24 * Use is subject to license terms.
25 */
26
24 * Use is subject to license terms.
25 */
26
27
28#include <emlxs.h>
29
30/* Required for EMLXS_CONTEXT in EMLXS_MSGF calls */
31EMLXS_MSG_DEF(EMLXS_MBOX_C);
32
33
27#include <emlxs.h>
28
29/* Required for EMLXS_CONTEXT in EMLXS_MSGF calls */
30EMLXS_MSG_DEF(EMLXS_MBOX_C);
31
32
33emlxs_table_t emlxs_mb_status_table[] = {
34 {MBX_SUCCESS, "SUCCESS"},
35 {MBX_FAILURE, "FAILURE"},
36 {MBXERR_NUM_IOCBS, "NUM_IOCBS"},
37 {MBXERR_IOCBS_EXCEEDED, "IOCBS_EXCEEDED"},
38 {MBXERR_BAD_RING_NUMBER, "BAD_RING_NUMBER"},
39 {MBXERR_MASK_ENTRIES_RANGE, "MASK_ENTRIES_RANGE"},
40 {MBXERR_MASKS_EXCEEDED, "MASKS_EXCEEDED"},
41 {MBXERR_BAD_PROFILE, "BAD_PROFILE"},
42 {MBXERR_BAD_DEF_CLASS, "BAD_DEF_CLASS"},
43 {MBXERR_BAD_MAX_RESPONDER, "BAD_MAX_RESPONDER"},
44 {MBXERR_BAD_MAX_ORIGINATOR, "BAD_MAX_ORIGINATOR"},
45 {MBXERR_RPI_REGISTERED, "RPI_REGISTERED"},
46 {MBXERR_RPI_FULL, "RPI_FULL"},
47 {MBXERR_NO_RESOURCES, "NO_RESOURCES"},
48 {MBXERR_BAD_RCV_LENGTH, "BAD_RCV_LENGTH"},
49 {MBXERR_DMA_ERROR, "DMA_ERROR"},
50 {MBXERR_NOT_SUPPORTED, "NOT_SUPPORTED"},
51 {MBXERR_UNSUPPORTED_FEATURE, "UNSUPPORTED_FEATURE"},
52 {MBXERR_UNKNOWN_COMMAND, "UNKNOWN_COMMAND"},
53 {MBXERR_BAD_IP_BIT, "BAD_IP_BIT"},
54 {MBXERR_BAD_PCB_ALIGN, "BAD_PCB_ALIGN"},
55 {MBXERR_BAD_HBQ_ID, "BAD_HBQ_ID"},
56 {MBXERR_BAD_HBQ_STATE, "BAD_HBQ_STATE"},
57 {MBXERR_BAD_HBQ_MASK_NUM, "BAD_HBQ_MASK_NUM"},
58 {MBXERR_BAD_HBQ_MASK_SUBSET, "BAD_HBQ_MASK_SUBSET"},
59 {MBXERR_HBQ_CREATE_FAIL, "HBQ_CREATE_FAIL"},
60 {MBXERR_HBQ_EXISTING, "HBQ_EXISTING"},
61 {MBXERR_HBQ_RSPRING_FULL, "HBQ_RSPRING_FULL"},
62 {MBXERR_HBQ_DUP_MASK, "HBQ_DUP_MASK"},
63 {MBXERR_HBQ_INVAL_GET_PTR, "HBQ_INVAL_GET_PTR"},
64 {MBXERR_BAD_HBQ_SIZE, "BAD_HBQ_SIZE"},
65 {MBXERR_BAD_HBQ_ORDER, "BAD_HBQ_ORDER"},
66 {MBXERR_INVALID_ID, "INVALID_ID"},
67 {MBXERR_INVALID_VFI, "INVALID_VFI"},
68 {MBXERR_FLASH_WRITE_FAILED, "FLASH_WRITE_FAILED"},
69 {MBXERR_INVALID_LINKSPEED, "INVALID_LINKSPEED"},
70 {MBXERR_BAD_REDIRECT, "BAD_REDIRECT"},
71 {MBXERR_RING_ALREADY_CONFIG, "RING_ALREADY_CONFIG"},
72 {MBXERR_RING_INACTIVE, "RING_INACTIVE"},
73 {MBXERR_RPI_INACTIVE, "RPI_INACTIVE"},
74 {MBXERR_NO_ACTIVE_XRI, "NO_ACTIVE_XRI"},
75 {MBXERR_XRI_NOT_ACTIVE, "XRI_NOT_ACTIVE"},
76 {MBXERR_RPI_INUSE, "RPI_INUSE"},
77 {MBXERR_NO_LINK_ATTENTION, "NO_LINK_ATTENTION"},
78 {MBXERR_INVALID_SLI_MODE, "INVALID_SLI_MODE"},
79 {MBXERR_INVALID_HOST_PTR, "INVALID_HOST_PTR"},
80 {MBXERR_CANT_CFG_SLI_MODE, "CANT_CFG_SLI_MODE"},
81 {MBXERR_BAD_OVERLAY, "BAD_OVERLAY"},
82 {MBXERR_INVALID_FEAT_REQ, "INVALID_FEAT_REQ"},
83 {MBXERR_CONFIG_CANT_COMPLETE, "CONFIG_CANT_COMPLETE"},
84 {MBXERR_DID_ALREADY_REGISTERED, "DID_ALREADY_REGISTERED"},
85 {MBXERR_DID_INCONSISTENT, "DID_INCONSISTENT"},
86 {MBXERR_VPI_TOO_LARGE, "VPI_TOO_LARGE"},
87 {MBXERR_STILL_ASSOCIATED, "STILL_ASSOCIATED"},
88 {MBXERR_INVALID_VF_STATE, "INVALID_VF_STATE"},
89 {MBXERR_VFI_ALREADY_REGISTERED, "VFI_ALREADY_REGISTERED"},
90 {MBXERR_VFI_TOO_LARGE, "VFI_TOO_LARGE"},
91 {MBXERR_LOAD_FW_FAILED, "LOAD_FW_FAILED"},
92 {MBXERR_FIND_FW_FAILED, "FIND_FW_FAILED"},
93};
34
35emlxs_table_t emlxs_mb_cmd_table[] = {
36 {MBX_SHUTDOWN, "SHUTDOWN"},
37 {MBX_LOAD_SM, "LOAD_SM"},
38 {MBX_READ_NV, "READ_NV"},
39 {MBX_WRITE_NV, "WRITE_NV"},
40 {MBX_RUN_BIU_DIAG, "RUN_BIU_DIAG"},
41 {MBX_INIT_LINK, "INIT_LINK"},

--- 56 unchanged lines hidden (view full) ---

98 {MBX_SLI_CONFIG, "SLI_CONFIG"},
99 {MBX_REQUEST_FEATURES, "REQUEST_FEATURES"},
100 {MBX_RESUME_RPI, "RESUME_RPI"},
101 {MBX_REG_VFI, "REG_VFI"},
102 {MBX_REG_FCFI, "REG_FCFI"},
103 {MBX_UNREG_VFI, "UNREG_VFI"},
104 {MBX_UNREG_FCFI, "UNREG_FCFI"},
105 {MBX_INIT_VFI, "INIT_VFI"},
94
95emlxs_table_t emlxs_mb_cmd_table[] = {
96 {MBX_SHUTDOWN, "SHUTDOWN"},
97 {MBX_LOAD_SM, "LOAD_SM"},
98 {MBX_READ_NV, "READ_NV"},
99 {MBX_WRITE_NV, "WRITE_NV"},
100 {MBX_RUN_BIU_DIAG, "RUN_BIU_DIAG"},
101 {MBX_INIT_LINK, "INIT_LINK"},

--- 56 unchanged lines hidden (view full) ---

158 {MBX_SLI_CONFIG, "SLI_CONFIG"},
159 {MBX_REQUEST_FEATURES, "REQUEST_FEATURES"},
160 {MBX_RESUME_RPI, "RESUME_RPI"},
161 {MBX_REG_VFI, "REG_VFI"},
162 {MBX_REG_FCFI, "REG_FCFI"},
163 {MBX_UNREG_VFI, "UNREG_VFI"},
164 {MBX_UNREG_FCFI, "UNREG_FCFI"},
165 {MBX_INIT_VFI, "INIT_VFI"},
106 {MBX_INIT_VPI, "INIT_VPI"}
166 {MBX_INIT_VPI, "INIT_VPI"},
167 {MBX_WRITE_VPARMS, "WRITE_VPARMS"},
168 {MBX_ACCESS_VDATA, "ACCESS_VDATA"}
107}; /* emlxs_mb_cmd_table */
108
109
169}; /* emlxs_mb_cmd_table */
170
171
172emlxs_table_t emlxs_request_feature_table[] = {
173 {SLI4_FEATURE_INHIBIT_AUTO_ABTS, "IAA "}, /* Bit 0 */
174 {SLI4_FEATURE_NPIV, "NPIV "}, /* Bit 1 */
175 {SLI4_FEATURE_DIF, "DIF "}, /* Bit 2 */
176 {SLI4_FEATURE_VIRTUAL_FABRICS, "VF "}, /* Bit 3 */
177 {SLI4_FEATURE_FCP_INITIATOR, "FCPI "}, /* Bit 4 */
178 {SLI4_FEATURE_FCP_TARGET, "FCPT "}, /* Bit 5 */
179 {SLI4_FEATURE_FCP_COMBO, "FCPC "}, /* Bit 6 */
180 {SLI4_FEATURE_RSVD1, "RSVD1 "}, /* Bit 7 */
181 {SLI4_FEATURE_RQD, "RQD "}, /* Bit 8 */
182 {SLI4_FEATURE_INHIBIT_AUTO_ABTS_R, "IAAR "}, /* Bit 9 */
183 {SLI4_FEATURE_HIGH_LOGIN_MODE, "HLM "}, /* Bit 10 */
184 {SLI4_FEATURE_PERF_HINT, "PERFH "} /* Bit 11 */
185}; /* emlxs_request_feature_table */
186
187
188extern char *
189emlxs_mb_xlate_status(uint32_t status)
190{
191 static char buffer[32];
192 uint32_t i;
193 uint32_t count;
194
195 count = sizeof (emlxs_mb_status_table) / sizeof (emlxs_table_t);
196 for (i = 0; i < count; i++) {
197 if (status == emlxs_mb_status_table[i].code) {
198 return (emlxs_mb_status_table[i].string);
199 }
200 }
201
202 (void) snprintf(buffer, sizeof (buffer), "status=%x", status);
203 return (buffer);
204
205} /* emlxs_mb_xlate_status() */
206
207
110/* SLI4 */
111/*ARGSUSED*/
112extern void
113emlxs_mb_resetport(emlxs_hba_t *hba, MAILBOXQ *mbq)
114{
115 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
116
117 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);

--- 18 unchanged lines hidden (view full) ---

136 return;
137
138} /* emlxs_mb_resetport() */
139
140
141/* SLI4 */
142/*ARGSUSED*/
143extern void
208/* SLI4 */
209/*ARGSUSED*/
210extern void
211emlxs_mb_resetport(emlxs_hba_t *hba, MAILBOXQ *mbq)
212{
213 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
214
215 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);

--- 18 unchanged lines hidden (view full) ---

234 return;
235
236} /* emlxs_mb_resetport() */
237
238
239/* SLI4 */
240/*ARGSUSED*/
241extern void
144emlxs_mb_request_features(emlxs_hba_t *hba, MAILBOXQ *mbq)
242emlxs_mb_request_features(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t mask)
145{
243{
146 emlxs_config_t *cfg = &CFG;
147 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
148
149 hba->flag &= ~FC_NPIV_ENABLED;
244 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
245
246 hba->flag &= ~FC_NPIV_ENABLED;
247 hba->sli.sli4.flag &= ~(EMLXS_SLI4_PHON | EMLXS_SLI4_PHWQ);
150
151 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
152 mbq->nonembed = NULL;
153 mbq->mbox_cmpl = NULL; /* no cmpl needed */
154 mbq->port = (void *)&PPORT;
155
156 mb4->mbxCommand = MBX_REQUEST_FEATURES;
157 mb4->mbxOwner = OWN_HOST;
248
249 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
250 mbq->nonembed = NULL;
251 mbq->mbox_cmpl = NULL; /* no cmpl needed */
252 mbq->port = (void *)&PPORT;
253
254 mb4->mbxCommand = MBX_REQUEST_FEATURES;
255 mb4->mbxOwner = OWN_HOST;
158 mb4->un.varReqFeatures.featuresRequested |=
159 SLI4_FEATURE_FCP_INITIATOR;
160
256
161 if (cfg[CFG_NPIV_ENABLE].current) {
162 mb4->un.varReqFeatures.featuresRequested |=
163 SLI4_FEATURE_NPIV;
164 }
257 mb4->un.varReqFeatures.featuresRequested = mask;
258 return;
165
166} /* emlxs_mb_request_features() */
167
168
169/* SLI4 */
170/*ARGSUSED*/
171extern void
172emlxs_mb_noop(emlxs_hba_t *hba, MAILBOXQ *mbq)

--- 36 unchanged lines hidden (view full) ---

209{
210 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
211 IOCTL_COMMON_NOP *nop;
212 MATCHMAP *mp;
213 mbox_req_hdr_t *hdr_req;
214
215 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
216
259
260} /* emlxs_mb_request_features() */
261
262
263/* SLI4 */
264/*ARGSUSED*/
265extern void
266emlxs_mb_noop(emlxs_hba_t *hba, MAILBOXQ *mbq)

--- 36 unchanged lines hidden (view full) ---

303{
304 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
305 IOCTL_COMMON_NOP *nop;
306 MATCHMAP *mp;
307 mbox_req_hdr_t *hdr_req;
308
309 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
310
217 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF, 1)) == 0) {
311 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF)) == 0) {
218 return (1);
219 }
220 /*
221 * Save address for completion
222 * Signifies a non-embedded command
223 */
224 mb4->un.varSLIConfig.be.embedded = 0;
225 mbq->nonembed = (void *)mp;

--- 40 unchanged lines hidden (view full) ---

266 mb4->un.varSLIConfig.be.payload_length =
267 sizeof (IOCTL_COMMON_EQ_CREATE) + IOCTL_HEADER_SZ;
268 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
269 IOCTL_SUBSYSTEM_COMMON;
270 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = COMMON_OPCODE_EQ_CREATE;
271 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
272 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
273 sizeof (IOCTL_COMMON_EQ_CREATE);
312 return (1);
313 }
314 /*
315 * Save address for completion
316 * Signifies a non-embedded command
317 */
318 mb4->un.varSLIConfig.be.embedded = 0;
319 mbq->nonembed = (void *)mp;

--- 40 unchanged lines hidden (view full) ---

360 mb4->un.varSLIConfig.be.payload_length =
361 sizeof (IOCTL_COMMON_EQ_CREATE) + IOCTL_HEADER_SZ;
362 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
363 IOCTL_SUBSYSTEM_COMMON;
364 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = COMMON_OPCODE_EQ_CREATE;
365 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
366 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
367 sizeof (IOCTL_COMMON_EQ_CREATE);
368 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0;
369
274 qp = (IOCTL_COMMON_EQ_CREATE *)&mb4->un.varSLIConfig.payload;
275
276 /* 1024 * 4 bytes = 4K */
277 qp->params.request.EQContext.Count = EQ_ELEMENT_COUNT_1024;
278 qp->params.request.EQContext.Valid = 1;
370 qp = (IOCTL_COMMON_EQ_CREATE *)&mb4->un.varSLIConfig.payload;
371
372 /* 1024 * 4 bytes = 4K */
373 qp->params.request.EQContext.Count = EQ_ELEMENT_COUNT_1024;
374 qp->params.request.EQContext.Valid = 1;
279 qp->params.request.EQContext.NoDelay = 0;
280 qp->params.request.EQContext.DelayMult = EQ_DELAY_MULT;
281
282 addr = hba->sli.sli4.eq[num].addr.phys;
283 qp->params.request.NumPages = 1;
284 qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
285 qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);
286
287 return;
288
289} /* emlxs_mb_eq_create() */
290
291
292/* SLI4 */
293/*ARGSUSED*/
294extern void
295emlxs_mb_cq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
296{
297 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
298 IOCTL_COMMON_CQ_CREATE *qp;
375 qp->params.request.EQContext.DelayMult = EQ_DELAY_MULT;
376
377 addr = hba->sli.sli4.eq[num].addr.phys;
378 qp->params.request.NumPages = 1;
379 qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
380 qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);
381
382 return;
383
384} /* emlxs_mb_eq_create() */
385
386
387/* SLI4 */
388/*ARGSUSED*/
389extern void
390emlxs_mb_cq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
391{
392 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
393 IOCTL_COMMON_CQ_CREATE *qp;
394 IOCTL_COMMON_CQ_CREATE_V2 *qp2;
299 uint64_t addr;
395 uint64_t addr;
396 uint32_t i;
300
301 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
302 mbq->nonembed = NULL;
303 mbq->mbox_cmpl = NULL; /* no cmpl needed */
304 mbq->port = (void *)&PPORT;
305
306 /*
307 * Signifies an embedded command
308 */
309 mb4->un.varSLIConfig.be.embedded = 1;
310
311 mb4->mbxCommand = MBX_SLI_CONFIG;
312 mb4->mbxOwner = OWN_HOST;
397
398 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
399 mbq->nonembed = NULL;
400 mbq->mbox_cmpl = NULL; /* no cmpl needed */
401 mbq->port = (void *)&PPORT;
402
403 /*
404 * Signifies an embedded command
405 */
406 mb4->un.varSLIConfig.be.embedded = 1;
407
408 mb4->mbxCommand = MBX_SLI_CONFIG;
409 mb4->mbxOwner = OWN_HOST;
313 mb4->un.varSLIConfig.be.payload_length =
314 sizeof (IOCTL_COMMON_CQ_CREATE) + IOCTL_HEADER_SZ;
410
411 switch (hba->sli.sli4.param.CQV) {
412 case 0:
413 mb4->un.varSLIConfig.be.payload_length =
414 sizeof (IOCTL_COMMON_CQ_CREATE) + IOCTL_HEADER_SZ;
415 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
416 IOCTL_SUBSYSTEM_COMMON;
417 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
418 COMMON_OPCODE_CQ_CREATE;
419 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
420 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
421 sizeof (IOCTL_COMMON_CQ_CREATE);
422 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0;
423
424 qp = (IOCTL_COMMON_CQ_CREATE *)
425 &mb4->un.varSLIConfig.payload;
426
427 /* 256 * 16 bytes = 4K */
428 qp->params.request.CQContext.Count = CQ_ELEMENT_COUNT_256;
429 qp->params.request.CQContext.EQId =
430 (uint8_t)hba->sli.sli4.cq[num].eqid;
431 qp->params.request.CQContext.Valid = 1;
432 qp->params.request.CQContext.Eventable = 1;
433 qp->params.request.CQContext.NoDelay = 0;
434 qp->params.request.CQContext.CoalesceWM = 0;
435
436 addr = hba->sli.sli4.cq[num].addr.phys;
437 qp->params.request.NumPages = 1;
438 qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
439 qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);
440
441 break;
442
443 case 2:
444 default:
445 mb4->un.varSLIConfig.be.payload_length =
446 sizeof (IOCTL_COMMON_CQ_CREATE_V2) + IOCTL_HEADER_SZ;
447 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
448 IOCTL_SUBSYSTEM_COMMON;
449 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
450 COMMON_OPCODE_CQ_CREATE;
451 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
452 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
453 sizeof (IOCTL_COMMON_CQ_CREATE_V2);
454 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 2;
455
456 qp2 = (IOCTL_COMMON_CQ_CREATE_V2 *)
457 &mb4->un.varSLIConfig.payload;
458
459 qp2->params.request.CQContext.CqeCnt = CQ_ELEMENT_COUNT_1024;
460 qp2->params.request.CQContext.CqeSize = CQE_SIZE_16_BYTES;
461 qp2->params.request.CQContext.EQId = hba->sli.sli4.cq[num].eqid;
462 qp2->params.request.CQContext.Valid = 1;
463 qp2->params.request.CQContext.AutoValid = 0;
464 qp2->params.request.CQContext.Eventable = 1;
465 qp2->params.request.CQContext.NoDelay = 0;
466 qp2->params.request.CQContext.Count1 = 0;
467 qp2->params.request.CQContext.CoalesceWM = 0;
468
469 addr = hba->sli.sli4.cq[num].addr.phys;
470 qp2->params.request.PageSize = CQ_PAGE_SIZE_4K;
471 qp2->params.request.NumPages = EMLXS_NUM_CQ_PAGES_V2;
472
473 for (i = 0; i < EMLXS_NUM_CQ_PAGES_V2; i++) {
474 qp2->params.request.Pages[i].addrLow = PADDR_LO(addr);
475 qp2->params.request.Pages[i].addrHigh = PADDR_HI(addr);
476 addr += 4096;
477 }
478
479 break;
480 }
481 return;
482
483} /* emlxs_mb_cq_create() */
484
485
486/* SLI4 */
487/*ARGSUSED*/
488extern void
489emlxs_mb_get_port_name(emlxs_hba_t *hba, MAILBOXQ *mbq)
490{
491 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
492
493 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
494 mbq->nonembed = NULL;
495 mbq->mbox_cmpl = NULL; /* no cmpl needed */
496 mbq->port = (void *)&PPORT;
497
498 mb4->un.varSLIConfig.be.embedded = 1;
499 mb4->mbxCommand = MBX_SLI_CONFIG;
500 mb4->mbxOwner = OWN_HOST;
501
502 mb4->un.varSLIConfig.be.payload_length = IOCTL_HEADER_SZ;
315 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
316 IOCTL_SUBSYSTEM_COMMON;
503 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
504 IOCTL_SUBSYSTEM_COMMON;
317 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = COMMON_OPCODE_CQ_CREATE;
505 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
506 COMMON_OPCODE_GET_PORT_NAME;
318 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
507 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
319 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
320 sizeof (IOCTL_COMMON_CQ_CREATE);
321 qp = (IOCTL_COMMON_CQ_CREATE *)&mb4->un.varSLIConfig.payload;
508 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length = 0;
322
509
323 /* 256 * 16 bytes = 4K */
324 qp->params.request.CQContext.Count = CQ_ELEMENT_COUNT_256;
325 qp->params.request.CQContext.EQId = hba->sli.sli4.cq[num].eqid;
326 qp->params.request.CQContext.Valid = 1;
327 qp->params.request.CQContext.Eventable = 1;
328 qp->params.request.CQContext.NoDelay = 0;
510 if (hba->model_info.chip & EMLXS_BE_CHIPS) {
511 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0; /* V0 */
512 } else {
513 IOCTL_COMMON_GET_PORT_NAME_V1 *pn;
329
514
330 addr = hba->sli.sli4.cq[num].addr.phys;
331 qp->params.request.NumPages = 1;
332 qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
333 qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);
515 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 1; /* V1 */
334
516
517 pn = (IOCTL_COMMON_GET_PORT_NAME_V1 *)
518 &mb4->un.varSLIConfig.payload;
519 pn->params.request.pt = PORT_TYPE_FC;
520 }
521
335 return;
336
522 return;
523
337} /* emlxs_mb_cq_create() */
524} /* emlxs_mb_get_port_name() */
338
339
340/* SLI4 */
341/*ARGSUSED*/
342extern void
525
526
527/* SLI4 */
528/*ARGSUSED*/
529extern void
530emlxs_mb_get_sli4_params(emlxs_hba_t *hba, MAILBOXQ *mbq)
531{
532 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
533
534 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
535 mbq->nonembed = NULL;
536 mbq->mbox_cmpl = NULL; /* no cmpl needed */
537 mbq->port = (void *)&PPORT;
538
539 mb4->un.varSLIConfig.be.embedded = 1;
540 mb4->mbxCommand = MBX_SLI_CONFIG;
541 mb4->mbxOwner = OWN_HOST;
542
543 mb4->un.varSLIConfig.be.payload_length = IOCTL_HEADER_SZ;
544 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
545 IOCTL_SUBSYSTEM_COMMON;
546 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
547 COMMON_OPCODE_GET_SLI4_PARAMS;
548 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
549 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length = 0;
550 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0; /* V0 */
551
552 return;
553
554} /* emlxs_mb_get_sli4_params() */
555
556
557/* SLI4 */
558/*ARGSUSED*/
559extern void
560emlxs_mb_get_extents_info(emlxs_hba_t *hba, MAILBOXQ *mbq, uint16_t type)
561{
562 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
563 IOCTL_COMMON_EXTENTS *ep;
564
565 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
566 mbq->nonembed = NULL;
567 mbq->mbox_cmpl = NULL; /* no cmpl needed */
568 mbq->port = (void *)&PPORT;
569
570 mb4->un.varSLIConfig.be.embedded = 1;
571 mb4->mbxCommand = MBX_SLI_CONFIG;
572 mb4->mbxOwner = OWN_HOST;
573
574 mb4->un.varSLIConfig.be.payload_length = IOCTL_HEADER_SZ;
575 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.subsystem =
576 IOCTL_SUBSYSTEM_COMMON;
577 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.opcode =
578 COMMON_OPCODE_GET_EXTENTS_INFO;
579 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.timeout = 0;
580 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.req_length =
581 sizeof (IOCTL_COMMON_EXTENTS);
582 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
583 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vh_number = 0;
584 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.pf_number = 0;
585
586 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.version = 0; /* V0 */
587
588 ep = (IOCTL_COMMON_EXTENTS *)&mb4->un.varSLIConfig.payload;
589 ep->params.request.RscType = type;
590
591 return;
592
593} /* emlxs_mb_get_extents_info() */
594
595
596/* SLI4 */
597/*ARGSUSED*/
598extern void
599emlxs_mb_get_extents(emlxs_hba_t *hba, MAILBOXQ *mbq, uint16_t type)
600{
601 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
602 IOCTL_COMMON_EXTENTS *ep;
603
604 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
605 mbq->nonembed = NULL;
606 mbq->mbox_cmpl = NULL; /* no cmpl needed */
607 mbq->port = (void *)&PPORT;
608
609 mb4->un.varSLIConfig.be.embedded = 1;
610 mb4->mbxCommand = MBX_SLI_CONFIG;
611 mb4->mbxOwner = OWN_HOST;
612
613 mb4->un.varSLIConfig.be.payload_length = IOCTL_HEADER_SZ;
614 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.subsystem =
615 IOCTL_SUBSYSTEM_COMMON;
616 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.opcode =
617 COMMON_OPCODE_GET_EXTENTS;
618 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.timeout = 0;
619 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.req_length =
620 sizeof (IOCTL_COMMON_EXTENTS);
621 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
622 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vh_number = 0;
623 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.pf_number = 0;
624
625 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.version = 0; /* V0 */
626
627 ep = (IOCTL_COMMON_EXTENTS *)&mb4->un.varSLIConfig.payload;
628 ep->params.request.RscType = type;
629
630 return;
631
632} /* emlxs_mb_get_extents() */
633
634
635/* SLI4 */
636/*ARGSUSED*/
637extern void
638emlxs_mb_alloc_extents(emlxs_hba_t *hba, MAILBOXQ *mbq, uint16_t type,
639 uint16_t count)
640{
641 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
642 IOCTL_COMMON_EXTENTS *ep;
643
644 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
645 mbq->nonembed = NULL;
646 mbq->mbox_cmpl = NULL; /* no cmpl needed */
647 mbq->port = (void *)&PPORT;
648
649 mb4->un.varSLIConfig.be.embedded = 1;
650 mb4->mbxCommand = MBX_SLI_CONFIG;
651 mb4->mbxOwner = OWN_HOST;
652
653 mb4->un.varSLIConfig.be.payload_length = IOCTL_HEADER_SZ;
654 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.subsystem =
655 IOCTL_SUBSYSTEM_COMMON;
656 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.opcode =
657 COMMON_OPCODE_ALLOC_EXTENTS;
658 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.timeout = 0;
659 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.req_length =
660 sizeof (IOCTL_COMMON_EXTENTS);
661 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
662 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vh_number = 0;
663 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.pf_number = 0;
664
665 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.version = 0; /* V0 */
666
667 ep = (IOCTL_COMMON_EXTENTS *)&mb4->un.varSLIConfig.payload;
668 ep->params.request.RscType = type;
669
670 count = min(count, MAX_EXTENTS);
671 ep->params.request.RscCnt = count;
672
673 return;
674
675} /* emlxs_mb_alloc_extents() */
676
677
678/* SLI4 */
679/*ARGSUSED*/
680extern void
681emlxs_mb_dealloc_extents(emlxs_hba_t *hba, MAILBOXQ *mbq, uint16_t type)
682{
683 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
684 IOCTL_COMMON_EXTENTS *ep;
685
686 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
687 mbq->nonembed = NULL;
688 mbq->mbox_cmpl = NULL; /* no cmpl needed */
689 mbq->port = (void *)&PPORT;
690
691 mb4->un.varSLIConfig.be.embedded = 1;
692 mb4->mbxCommand = MBX_SLI_CONFIG;
693 mb4->mbxOwner = OWN_HOST;
694
695 mb4->un.varSLIConfig.be.payload_length = IOCTL_HEADER_SZ;
696 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.subsystem =
697 IOCTL_SUBSYSTEM_COMMON;
698 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.opcode =
699 COMMON_OPCODE_DEALLOC_EXTENTS;
700 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.timeout = 0;
701 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.req_length =
702 sizeof (IOCTL_COMMON_EXTENTS);
703 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vf_number = 0;
704 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.vh_number = 0;
705 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.pf_number = 0;
706
707 mb4->un.varSLIConfig.be.un_hdr.hdr_req2.version = 0; /* V0 */
708
709 ep = (IOCTL_COMMON_EXTENTS *)&mb4->un.varSLIConfig.payload;
710 ep->params.request.RscType = type;
711
712 return;
713
714} /* emlxs_mb_dealloc_extents() */
715
716
717/* SLI4 */
718/*ARGSUSED*/
719extern void
343emlxs_mb_wq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
344{
345 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
346 IOCTL_FCOE_WQ_CREATE *qp;
720emlxs_mb_wq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
721{
722 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
723 IOCTL_FCOE_WQ_CREATE *qp;
724 IOCTL_FCOE_WQ_CREATE_V1 *qp1;
347 uint64_t addr;
348 int i;
349
350 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
351 mbq->nonembed = NULL;
352 mbq->mbox_cmpl = NULL; /* no cmpl needed */
353 mbq->port = (void *)&PPORT;
354
355 /*
356 * Signifies an embedded command
357 */
358 mb4->un.varSLIConfig.be.embedded = 1;
359
360 mb4->mbxCommand = MBX_SLI_CONFIG;
361 mb4->mbxOwner = OWN_HOST;
725 uint64_t addr;
726 int i;
727
728 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
729 mbq->nonembed = NULL;
730 mbq->mbox_cmpl = NULL; /* no cmpl needed */
731 mbq->port = (void *)&PPORT;
732
733 /*
734 * Signifies an embedded command
735 */
736 mb4->un.varSLIConfig.be.embedded = 1;
737
738 mb4->mbxCommand = MBX_SLI_CONFIG;
739 mb4->mbxOwner = OWN_HOST;
362 mb4->un.varSLIConfig.be.payload_length =
363 sizeof (IOCTL_FCOE_WQ_CREATE) + IOCTL_HEADER_SZ;
364 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
365 IOCTL_SUBSYSTEM_FCOE;
366 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = FCOE_OPCODE_WQ_CREATE;
367 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
368 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
369 sizeof (IOCTL_FCOE_WQ_CREATE);
370
740
371 addr = hba->sli.sli4.wq[num].addr.phys;
372 qp = (IOCTL_FCOE_WQ_CREATE *)&mb4->un.varSLIConfig.payload;
741 switch (hba->sli.sli4.param.WQV) {
742 case 0:
743 mb4->un.varSLIConfig.be.payload_length =
744 sizeof (IOCTL_FCOE_WQ_CREATE) + IOCTL_HEADER_SZ;
745 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
746 IOCTL_SUBSYSTEM_FCOE;
747 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
748 FCOE_OPCODE_WQ_CREATE;
749 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
750 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
751 sizeof (IOCTL_FCOE_WQ_CREATE);
752 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0;
373
753
374 qp->params.request.CQId = hba->sli.sli4.wq[num].cqid;
754 addr = hba->sli.sli4.wq[num].addr.phys;
755 qp = (IOCTL_FCOE_WQ_CREATE *)&mb4->un.varSLIConfig.payload;
375
756
376 qp->params.request.NumPages = EMLXS_NUM_WQ_PAGES;
377 for (i = 0; i < EMLXS_NUM_WQ_PAGES; i++) {
378 qp->params.request.Pages[i].addrLow = PADDR_LO(addr);
379 qp->params.request.Pages[i].addrHigh = PADDR_HI(addr);
380 addr += 4096;
757 qp->params.request.CQId = hba->sli.sli4.wq[num].cqid;
758
759 qp->params.request.NumPages = EMLXS_NUM_WQ_PAGES;
760 for (i = 0; i < EMLXS_NUM_WQ_PAGES; i++) {
761 qp->params.request.Pages[i].addrLow = PADDR_LO(addr);
762 qp->params.request.Pages[i].addrHigh = PADDR_HI(addr);
763 addr += 4096;
764 }
765
766 break;
767
768 case 1:
769 default:
770 mb4->un.varSLIConfig.be.payload_length =
771 sizeof (IOCTL_FCOE_WQ_CREATE_V1) + IOCTL_HEADER_SZ;
772 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
773 IOCTL_SUBSYSTEM_FCOE;
774 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
775 FCOE_OPCODE_WQ_CREATE;
776 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
777 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
778 sizeof (IOCTL_FCOE_WQ_CREATE_V1);
779 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 1;
780
781 addr = hba->sli.sli4.wq[num].addr.phys;
782 qp1 = (IOCTL_FCOE_WQ_CREATE_V1 *)&mb4->un.varSLIConfig.payload;
783
784 qp1->params.request.CQId = hba->sli.sli4.wq[num].cqid;
785 qp1->params.request.NumPages = EMLXS_NUM_WQ_PAGES;
786
787 qp1->params.request.WqeCnt = WQ_DEPTH;
788 qp1->params.request.WqeSize = WQE_SIZE_64_BYTES;
789 qp1->params.request.PageSize = WQ_PAGE_SIZE_4K;
790
791 for (i = 0; i < EMLXS_NUM_WQ_PAGES; i++) {
792 qp1->params.request.Pages[i].addrLow = PADDR_LO(addr);
793 qp1->params.request.Pages[i].addrHigh = PADDR_HI(addr);
794 addr += 4096;
795 }
796
797 break;
381 }
382
383 return;
384
385} /* emlxs_mb_wq_create() */
386
387
388/* SLI4 */
389/*ARGSUSED*/
390extern void
391emlxs_mb_rq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
392{
393 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
394 IOCTL_FCOE_RQ_CREATE *qp;
798 }
799
800 return;
801
802} /* emlxs_mb_wq_create() */
803
804
805/* SLI4 */
806/*ARGSUSED*/
807extern void
808emlxs_mb_rq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
809{
810 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
811 IOCTL_FCOE_RQ_CREATE *qp;
812 IOCTL_FCOE_RQ_CREATE_V1 *qp1;
395 uint64_t addr;
396
397 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
398 mbq->nonembed = NULL;
399 mbq->mbox_cmpl = NULL; /* no cmpl needed */
400 mbq->port = (void *)&PPORT;
401
402 /*
403 * Signifies an embedded command
404 */
405 mb4->un.varSLIConfig.be.embedded = 1;
406
407 mb4->mbxCommand = MBX_SLI_CONFIG;
408 mb4->mbxOwner = OWN_HOST;
813 uint64_t addr;
814
815 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
816 mbq->nonembed = NULL;
817 mbq->mbox_cmpl = NULL; /* no cmpl needed */
818 mbq->port = (void *)&PPORT;
819
820 /*
821 * Signifies an embedded command
822 */
823 mb4->un.varSLIConfig.be.embedded = 1;
824
825 mb4->mbxCommand = MBX_SLI_CONFIG;
826 mb4->mbxOwner = OWN_HOST;
409 mb4->un.varSLIConfig.be.payload_length =
410 sizeof (IOCTL_FCOE_RQ_CREATE) + IOCTL_HEADER_SZ;
411 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
412 IOCTL_SUBSYSTEM_FCOE;
413 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = FCOE_OPCODE_RQ_CREATE;
414 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
415 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
416 sizeof (IOCTL_FCOE_RQ_CREATE);
417 addr = hba->sli.sli4.rq[num].addr.phys;
418
827
419 qp = (IOCTL_FCOE_RQ_CREATE *)&mb4->un.varSLIConfig.payload;
828 switch (hba->sli.sli4.param.RQV) {
829 case 0:
830 mb4->un.varSLIConfig.be.payload_length =
831 sizeof (IOCTL_FCOE_RQ_CREATE) + IOCTL_HEADER_SZ;
832 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
833 IOCTL_SUBSYSTEM_FCOE;
834 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
835 FCOE_OPCODE_RQ_CREATE;
836 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
837 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
838 sizeof (IOCTL_FCOE_RQ_CREATE);
839 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0;
420
840
421 qp->params.request.RQContext.RQSize = RQ_DEPTH_EXPONENT;
422 qp->params.request.RQContext.BufferSize = RQB_DATA_SIZE;
423 qp->params.request.RQContext.CQIdRecv = hba->sli.sli4.rq[num].cqid;
841 addr = hba->sli.sli4.rq[num].addr.phys;
424
842
425 qp->params.request.NumPages = 1;
426 qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
427 qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);
843 qp = (IOCTL_FCOE_RQ_CREATE *)&mb4->un.varSLIConfig.payload;
428
844
845 qp->params.request.RQContext.RqeCnt = RQ_DEPTH_EXPONENT;
846 qp->params.request.RQContext.BufferSize = RQB_DATA_SIZE;
847 qp->params.request.RQContext.CQId =
848 hba->sli.sli4.rq[num].cqid;
849
850 qp->params.request.NumPages = 1;
851 qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
852 qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);
853
854 break;
855
856 case 1:
857 default:
858 mb4->un.varSLIConfig.be.payload_length =
859 sizeof (IOCTL_FCOE_RQ_CREATE_V1) + IOCTL_HEADER_SZ;
860 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
861 IOCTL_SUBSYSTEM_FCOE;
862 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
863 FCOE_OPCODE_RQ_CREATE;
864 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
865 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
866 sizeof (IOCTL_FCOE_RQ_CREATE_V1);
867 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 1;
868
869 addr = hba->sli.sli4.rq[num].addr.phys;
870
871 qp1 = (IOCTL_FCOE_RQ_CREATE_V1 *)&mb4->un.varSLIConfig.payload;
872
873 qp1->params.request.RQContext.RqeCnt = RQ_DEPTH;
874 qp1->params.request.RQContext.RqeSize = RQE_SIZE_8_BYTES;
875 qp1->params.request.RQContext.PageSize = RQ_PAGE_SIZE_4K;
876
877 qp1->params.request.RQContext.BufferSize = RQB_DATA_SIZE;
878 qp1->params.request.RQContext.CQId =
879 hba->sli.sli4.rq[num].cqid;
880
881 qp1->params.request.NumPages = 1;
882 qp1->params.request.Pages[0].addrLow = PADDR_LO(addr);
883 qp1->params.request.Pages[0].addrHigh = PADDR_HI(addr);
884
885 break;
886 }
887
429 return;
430
431} /* emlxs_mb_rq_create() */
432
433
434/* SLI4 */
435/*ARGSUSED*/
436extern void

--- 38 unchanged lines hidden (view full) ---

475 return;
476
477} /* emlxs_mb_mq_create() */
478
479
480/* SLI4 */
481/*ARGSUSED*/
482extern void
888 return;
889
890} /* emlxs_mb_rq_create() */
891
892
893/* SLI4 */
894/*ARGSUSED*/
895extern void

--- 38 unchanged lines hidden (view full) ---

934 return;
935
936} /* emlxs_mb_mq_create() */
937
938
939/* SLI4 */
940/*ARGSUSED*/
941extern void
483emlxs_mb_mcc_create_ext(emlxs_hba_t *hba, MAILBOXQ *mbq)
942emlxs_mb_mq_create_ext(emlxs_hba_t *hba, MAILBOXQ *mbq)
484{
485 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
943{
944 MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
486 IOCTL_COMMON_MCC_CREATE_EXT *qp;
945 IOCTL_COMMON_MQ_CREATE_EXT *qp;
946 IOCTL_COMMON_MQ_CREATE_EXT_V1 *qp1;
487 uint64_t addr;
488
489 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
490 mbq->nonembed = NULL;
491 mbq->mbox_cmpl = NULL; /* no cmpl needed */
492 mbq->port = (void *)&PPORT;
493
494 /*
495 * Signifies an embedded command
496 */
497 mb4->un.varSLIConfig.be.embedded = 1;
498
499 mb4->mbxCommand = MBX_SLI_CONFIG;
500 mb4->mbxOwner = OWN_HOST;
947 uint64_t addr;
948
949 bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
950 mbq->nonembed = NULL;
951 mbq->mbox_cmpl = NULL; /* no cmpl needed */
952 mbq->port = (void *)&PPORT;
953
954 /*
955 * Signifies an embedded command
956 */
957 mb4->un.varSLIConfig.be.embedded = 1;
958
959 mb4->mbxCommand = MBX_SLI_CONFIG;
960 mb4->mbxOwner = OWN_HOST;
501 mb4->un.varSLIConfig.be.payload_length =
502 sizeof (IOCTL_COMMON_MQ_CREATE) + IOCTL_HEADER_SZ;
503 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
504 IOCTL_SUBSYSTEM_COMMON;
505 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
506 COMMON_OPCODE_MCC_CREATE_EXT;
507 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
508 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
509 sizeof (IOCTL_COMMON_MCC_CREATE_EXT);
510
961
511 addr = hba->sli.sli4.mq.addr.phys;
512 qp = (IOCTL_COMMON_MCC_CREATE_EXT *)&mb4->un.varSLIConfig.payload;
962 switch (hba->sli.sli4.param.MQV) {
963 case 0:
964 mb4->un.varSLIConfig.be.payload_length =
965 sizeof (IOCTL_COMMON_MQ_CREATE_EXT) + IOCTL_HEADER_SZ;
966 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
967 IOCTL_SUBSYSTEM_COMMON;
968 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
969 COMMON_OPCODE_MQ_CREATE_EXT;
970 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
971 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
972 sizeof (IOCTL_COMMON_MQ_CREATE_EXT);
973 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0;
513
974
514 qp->params.request.num_pages = 1;
515 qp->params.request.async_event_bitmap =
516 ASYNC_LINK_EVENT | ASYNC_FCF_EVENT | ASYNC_GROUP5_EVENT;
517 qp->params.request.context.Size = MQ_ELEMENT_COUNT_16;
518 qp->params.request.context.Valid = 1;
519 qp->params.request.context.CQId = hba->sli.sli4.mq.cqid;
975 addr = hba->sli.sli4.mq.addr.phys;
976 qp = (IOCTL_COMMON_MQ_CREATE_EXT *)
977 &mb4->un.varSLIConfig.payload;
520
978
521 qp->params.request.pages[0].addrLow = PADDR_LO(addr);
522 qp->params.request.pages[0].addrHigh = PADDR_HI(addr);
979 qp->params.request.num_pages = 1;
980 qp->params.request.async_event_bitmap =
981 ASYNC_LINK_EVENT | ASYNC_FCF_EVENT | ASYNC_GROUP5_EVENT;
982 qp->params.request.context.Size = MQ_ELEMENT_COUNT_16;
983 qp->params.request.context.Valid = 1;
984 qp->params.request.context.CQId = hba->sli.sli4.mq.cqid;
523
985
986 qp->params.request.pages[0].addrLow = PADDR_LO(addr);
987 qp->params.request.pages[0].addrHigh = PADDR_HI(addr);
988
989 break;
990
991 case 1:
992 default:
993 mb4->un.varSLIConfig.be.payload_length =
994 sizeof (IOCTL_COMMON_MQ_CREATE) + IOCTL_HEADER_SZ;
995 mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
996 IOCTL_SUBSYSTEM_COMMON;
997 mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
998 COMMON_OPCODE_MQ_CREATE_EXT;
999 mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
1000 mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
1001 sizeof (IOCTL_COMMON_MQ_CREATE_EXT_V1);
1002 mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 1;
1003
1004 addr = hba->sli.sli4.mq.addr.phys;
1005 qp1 = (IOCTL_COMMON_MQ_CREATE_EXT_V1 *)
1006 &mb4->un.varSLIConfig.payload;
1007
1008 qp1->params.request.num_pages = 1;
1009 qp1->params.request.async_event_bitmap =
1010 ASYNC_LINK_EVENT | ASYNC_FCF_EVENT | ASYNC_GROUP5_EVENT |
1011 ASYNC_FC_EVENT | ASYNC_PORT_EVENT;
1012 qp1->params.request.context.Size = MQ_ELEMENT_COUNT_16;
1013 qp1->params.request.context.Valid = 1;
1014 qp1->params.request.CQId = hba->sli.sli4.mq.cqid;
1015
1016 qp1->params.request.pages[0].addrLow = PADDR_LO(addr);
1017 qp1->params.request.pages[0].addrHigh = PADDR_HI(addr);
1018
1019 break;
1020 }
1021
524 return;
525
1022 return;
1023
526} /* emlxs_mb_mcc_create_ext() */
1024} /* emlxs_mb_mq_create_ext() */
527
528
529/*ARGSUSED*/
530extern void
531emlxs_mb_async_event(emlxs_hba_t *hba, MAILBOXQ *mbq)
532{
533 MAILBOX *mb = (MAILBOX *)mbq;
534

--- 436 unchanged lines hidden (view full) ---

971/* This should only be called with active MBX_NOWAIT mailboxes */
972void
973emlxs_mb_retry(emlxs_hba_t *hba, MAILBOXQ *mbq)
974{
975 MAILBOX *mb;
976 MAILBOX *mbox;
977 int rc;
978
1025
1026
1027/*ARGSUSED*/
1028extern void
1029emlxs_mb_async_event(emlxs_hba_t *hba, MAILBOXQ *mbq)
1030{
1031 MAILBOX *mb = (MAILBOX *)mbq;
1032

--- 436 unchanged lines hidden (view full) ---

1469/* This should only be called with active MBX_NOWAIT mailboxes */
1470void
1471emlxs_mb_retry(emlxs_hba_t *hba, MAILBOXQ *mbq)
1472{
1473 MAILBOX *mb;
1474 MAILBOX *mbox;
1475 int rc;
1476
979 mbox = (MAILBOX *)emlxs_mem_get(hba, MEM_MBOX, 1);
1477 mbox = (MAILBOX *)emlxs_mem_get(hba, MEM_MBOX);
980 if (!mbox) {
981 return;
982 }
983 mb = (MAILBOX *)mbq;
984 bcopy((uint8_t *)mb, (uint8_t *)mbox, MAILBOX_CMD_BSIZE);
985 mbox->mbxOwner = OWN_HOST;
986 mbox->mbxStatus = 0;
987

--- 100 unchanged lines hidden (view full) ---

1088
1089 hba->link_event_tag = la.eventTag;
1090 port->lip_type = 0;
1091
1092 /* If link not already up then declare it up now */
1093 if ((la.attType == AT_LINK_UP) && (hba->state < FC_LINK_UP)) {
1094
1095#ifdef MENLO_SUPPORT
1478 if (!mbox) {
1479 return;
1480 }
1481 mb = (MAILBOX *)mbq;
1482 bcopy((uint8_t *)mb, (uint8_t *)mbox, MAILBOX_CMD_BSIZE);
1483 mbox->mbxOwner = OWN_HOST;
1484 mbox->mbxStatus = 0;
1485

--- 100 unchanged lines hidden (view full) ---

1586
1587 hba->link_event_tag = la.eventTag;
1588 port->lip_type = 0;
1589
1590 /* If link not already up then declare it up now */
1591 if ((la.attType == AT_LINK_UP) && (hba->state < FC_LINK_UP)) {
1592
1593#ifdef MENLO_SUPPORT
1096 if ((hba->model_info.device_id == PCI_DEVICE_ID_LP21000_M) &&
1594 if ((hba->model_info.device_id == PCI_DEVICE_ID_HORNET) &&
1097 (hba->flag & (FC_ILB_MODE | FC_ELB_MODE))) {
1098 la.topology = TOPOLOGY_LOOP;
1099 la.granted_AL_PA = 0;
1100 port->alpa_map[0] = 1;
1101 port->alpa_map[1] = 0;
1102 la.lipType = LT_PORT_INIT;
1103 }
1104#endif /* MENLO_SUPPORT */
1105 /* Save the linkspeed */
1106 hba->linkspeed = la.UlnkSpeed;
1107
1108 /* Check for old model adapters that only */
1109 /* supported 1Gb */
1110 if ((hba->linkspeed == 0) &&
1111 (hba->model_info.chip & EMLXS_DRAGONFLY_CHIP)) {
1112 hba->linkspeed = LA_1GHZ_LINK;
1113 }
1114
1115 if ((hba->topology = la.topology) == TOPOLOGY_LOOP) {
1595 (hba->flag & (FC_ILB_MODE | FC_ELB_MODE))) {
1596 la.topology = TOPOLOGY_LOOP;
1597 la.granted_AL_PA = 0;
1598 port->alpa_map[0] = 1;
1599 port->alpa_map[1] = 0;
1600 la.lipType = LT_PORT_INIT;
1601 }
1602#endif /* MENLO_SUPPORT */
1603 /* Save the linkspeed */
1604 hba->linkspeed = la.UlnkSpeed;
1605
1606 /* Check for old model adapters that only */
1607 /* supported 1Gb */
1608 if ((hba->linkspeed == 0) &&
1609 (hba->model_info.chip & EMLXS_DRAGONFLY_CHIP)) {
1610 hba->linkspeed = LA_1GHZ_LINK;
1611 }
1612
1613 if ((hba->topology = la.topology) == TOPOLOGY_LOOP) {
1116 port->did = la.granted_AL_PA;
1614 port->granted_alpa = la.granted_AL_PA;
1615 port->did = port->granted_alpa;
1117 port->lip_type = la.lipType;
1118 if (hba->flag & FC_SLIM2_MODE) {
1119 i = la.un.lilpBde64.tus.f.bdeSize;
1120 } else {
1121 i = la.un.lilpBde.bdeSize;
1122 }
1123
1124 if (i == 0) {

--- 33 unchanged lines hidden (view full) ---

1158 alpa_map[j + 6],
1159 alpa_map[j + 7]);
1160 }
1161 }
1162 }
1163#ifdef MENLO_SUPPORT
1164 /* Check if Menlo maintenance mode is enabled */
1165 if (hba->model_info.device_id ==
1616 port->lip_type = la.lipType;
1617 if (hba->flag & FC_SLIM2_MODE) {
1618 i = la.un.lilpBde64.tus.f.bdeSize;
1619 } else {
1620 i = la.un.lilpBde.bdeSize;
1621 }
1622
1623 if (i == 0) {

--- 33 unchanged lines hidden (view full) ---

1657 alpa_map[j + 6],
1658 alpa_map[j + 7]);
1659 }
1660 }
1661 }
1662#ifdef MENLO_SUPPORT
1663 /* Check if Menlo maintenance mode is enabled */
1664 if (hba->model_info.device_id ==
1166 PCI_DEVICE_ID_LP21000_M) {
1665 PCI_DEVICE_ID_HORNET) {
1167 if (la.mm == 1) {
1168 EMLXS_MSGF(EMLXS_CONTEXT,
1169 &emlxs_link_atten_msg,
1170 "Maintenance Mode enabled.");
1171
1172 mutex_enter(&EMLXS_PORT_LOCK);
1173 hba->flag |= FC_MENLO_MODE;
1174 mutex_exit(&EMLXS_PORT_LOCK);

--- 12 unchanged lines hidden (view full) ---

1187 emlxs_thread_spawn(hba,
1188 emlxs_fcoe_attention_thread,
1189 0, 0);
1190 }
1191 }
1192#endif /* MENLO_SUPPORT */
1193
1194 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1666 if (la.mm == 1) {
1667 EMLXS_MSGF(EMLXS_CONTEXT,
1668 &emlxs_link_atten_msg,
1669 "Maintenance Mode enabled.");
1670
1671 mutex_enter(&EMLXS_PORT_LOCK);
1672 hba->flag |= FC_MENLO_MODE;
1673 mutex_exit(&EMLXS_PORT_LOCK);

--- 12 unchanged lines hidden (view full) ---

1686 emlxs_thread_spawn(hba,
1687 emlxs_fcoe_attention_thread,
1688 0, 0);
1689 }
1690 }
1691#endif /* MENLO_SUPPORT */
1692
1693 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1195 MEM_MBOX, 1))) {
1694 MEM_MBOX))) {
1196 /* This should turn on DELAYED ABTS for */
1197 /* ELS timeouts */
1198 emlxs_mb_set_var(hba, mbox, 0x00052198, 0x1);
1199
1200 emlxs_mb_put(hba, mbox);
1201 }
1202
1203 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1695 /* This should turn on DELAYED ABTS for */
1696 /* ELS timeouts */
1697 emlxs_mb_set_var(hba, mbox, 0x00052198, 0x1);
1698
1699 emlxs_mb_put(hba, mbox);
1700 }
1701
1702 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1204 MEM_MBOX, 1))) {
1703 MEM_MBOX))) {
1205 /* If link not already down then */
1206 /* declare it down now */
1207 if (emlxs_mb_read_sparam(hba, mbox) == 0) {
1208 emlxs_mb_put(hba, mbox);
1209 } else {
1210 emlxs_mem_put(hba, MEM_MBOX,
1211 (void *)mbox);
1212 }
1213 }
1214
1215 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1704 /* If link not already down then */
1705 /* declare it down now */
1706 if (emlxs_mb_read_sparam(hba, mbox) == 0) {
1707 emlxs_mb_put(hba, mbox);
1708 } else {
1709 emlxs_mem_put(hba, MEM_MBOX,
1710 (void *)mbox);
1711 }
1712 }
1713
1714 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1216 MEM_MBOX, 1))) {
1715 MEM_MBOX))) {
1217 emlxs_mb_config_link(hba, mbox);
1218
1219 emlxs_mb_put(hba, mbox);
1220 }
1221
1222 /* Declare the linkup here */
1223 emlxs_linkup(hba);
1224 }

--- 18 unchanged lines hidden (view full) ---

1243
1244 mutex_exit(&EMLXS_PORT_LOCK);
1245
1246 return (0);
1247
1248} /* emlxs_read_la_mbcmpl() */
1249
1250
1716 emlxs_mb_config_link(hba, mbox);
1717
1718 emlxs_mb_put(hba, mbox);
1719 }
1720
1721 /* Declare the linkup here */
1722 emlxs_linkup(hba);
1723 }

--- 18 unchanged lines hidden (view full) ---

1742
1743 mutex_exit(&EMLXS_PORT_LOCK);
1744
1745 return (0);
1746
1747} /* emlxs_read_la_mbcmpl() */
1748
1749
1251/* SLI3 */
1252extern uint32_t
1253emlxs_mb_read_la(emlxs_hba_t *hba, MAILBOXQ *mbq)
1254{
1255 MAILBOX *mb = (MAILBOX *)mbq;
1256 MATCHMAP *mp;
1257
1258 bzero((void *)mb, MAILBOX_CMD_BSIZE);
1259
1750extern uint32_t
1751emlxs_mb_read_la(emlxs_hba_t *hba, MAILBOXQ *mbq)
1752{
1753 MAILBOX *mb = (MAILBOX *)mbq;
1754 MATCHMAP *mp;
1755
1756 bzero((void *)mb, MAILBOX_CMD_BSIZE);
1757
1260 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF, 1)) == 0) {
1758 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF)) == 0) {
1261 mb->mbxCommand = MBX_READ_LA64;
1262
1263 return (1);
1264 }
1265
1266 mb->mbxCommand = MBX_READ_LA64;
1267 mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128;
1268 mb->un.varReadLA.un.lilpBde64.addrHigh = PADDR_HI(mp->phys);

--- 26 unchanged lines hidden (view full) ---

1295 mb = (MAILBOX *)mbq;
1296 if (mb->mbxStatus) {
1297 la_enable = 1;
1298
1299 if (mb->mbxStatus == 0x1601) {
1300 /* Get a buffer which will be used for */
1301 /* mailbox commands */
1302 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1759 mb->mbxCommand = MBX_READ_LA64;
1760
1761 return (1);
1762 }
1763
1764 mb->mbxCommand = MBX_READ_LA64;
1765 mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128;
1766 mb->un.varReadLA.un.lilpBde64.addrHigh = PADDR_HI(mp->phys);

--- 26 unchanged lines hidden (view full) ---

1793 mb = (MAILBOX *)mbq;
1794 if (mb->mbxStatus) {
1795 la_enable = 1;
1796
1797 if (mb->mbxStatus == 0x1601) {
1798 /* Get a buffer which will be used for */
1799 /* mailbox commands */
1800 if ((mbox = (MAILBOXQ *)emlxs_mem_get(hba,
1303 MEM_MBOX, 1))) {
1801 MEM_MBOX))) {
1304 /* Get link attention message */
1305 if (emlxs_mb_read_la(hba, mbox) == 0) {
1306 rc = EMLXS_SLI_ISSUE_MBOX_CMD(hba,
1307 (MAILBOX *)mbox, MBX_NOWAIT, 0);
1308 if ((rc != MBX_BUSY) &&
1309 (rc != MBX_SUCCESS)) {
1310 emlxs_mem_put(hba,
1311 MEM_MBOX, (void *)mbox);

--- 207 unchanged lines hidden (view full) ---

1519 */
1520 if (cfg[CFG_CR_DELAY].current) {
1521 mb->un.varCfgLnk.cr = 1;
1522 mb->un.varCfgLnk.ci = 1;
1523 mb->un.varCfgLnk.cr_delay = cfg[CFG_CR_DELAY].current;
1524 mb->un.varCfgLnk.cr_count = cfg[CFG_CR_COUNT].current;
1525 }
1526
1802 /* Get link attention message */
1803 if (emlxs_mb_read_la(hba, mbox) == 0) {
1804 rc = EMLXS_SLI_ISSUE_MBOX_CMD(hba,
1805 (MAILBOX *)mbox, MBX_NOWAIT, 0);
1806 if ((rc != MBX_BUSY) &&
1807 (rc != MBX_SUCCESS)) {
1808 emlxs_mem_put(hba,
1809 MEM_MBOX, (void *)mbox);

--- 207 unchanged lines hidden (view full) ---

2017 */
2018 if (cfg[CFG_CR_DELAY].current) {
2019 mb->un.varCfgLnk.cr = 1;
2020 mb->un.varCfgLnk.ci = 1;
2021 mb->un.varCfgLnk.cr_delay = cfg[CFG_CR_DELAY].current;
2022 mb->un.varCfgLnk.cr_count = cfg[CFG_CR_COUNT].current;
2023 }
2024
1527 if (cfg[CFG_ACK0].current)
2025 if (cfg[CFG_ACK0].current) {
1528 mb->un.varCfgLnk.ack0_enable = 1;
2026 mb->un.varCfgLnk.ack0_enable = 1;
2027 }
1529
1530 mb->un.varCfgLnk.myId = port->did;
1531 mb->un.varCfgLnk.edtov = hba->fc_edtov;
1532 mb->un.varCfgLnk.arbtov = hba->fc_arbtov;
1533 mb->un.varCfgLnk.ratov = hba->fc_ratov;
1534 mb->un.varCfgLnk.rttov = hba->fc_rttov;
1535 mb->un.varCfgLnk.altov = hba->fc_altov;
1536 mb->un.varCfgLnk.crtov = hba->fc_crtov;

--- 51 unchanged lines hidden (view full) ---

1588extern void
1589emlxs_mb_init_link(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t topology,
1590 uint32_t linkspeed)
1591{
1592 MAILBOX *mb = (MAILBOX *)mbq;
1593 emlxs_vpd_t *vpd = &VPD;
1594 emlxs_config_t *cfg = &CFG;
1595
2028
2029 mb->un.varCfgLnk.myId = port->did;
2030 mb->un.varCfgLnk.edtov = hba->fc_edtov;
2031 mb->un.varCfgLnk.arbtov = hba->fc_arbtov;
2032 mb->un.varCfgLnk.ratov = hba->fc_ratov;
2033 mb->un.varCfgLnk.rttov = hba->fc_rttov;
2034 mb->un.varCfgLnk.altov = hba->fc_altov;
2035 mb->un.varCfgLnk.crtov = hba->fc_crtov;

--- 51 unchanged lines hidden (view full) ---

2087extern void
2088emlxs_mb_init_link(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t topology,
2089 uint32_t linkspeed)
2090{
2091 MAILBOX *mb = (MAILBOX *)mbq;
2092 emlxs_vpd_t *vpd = &VPD;
2093 emlxs_config_t *cfg = &CFG;
2094
1596 if (hba->sli_mode == EMLXS_HBA_SLI4_MODE) {
2095 if ((hba->sli_mode == EMLXS_HBA_SLI4_MODE) &&
2096 (SLI4_FCOE_MODE)) {
1597 bzero((void *) mb, MAILBOX_CMD_SLI4_BSIZE);
1598 mbq->nonembed = NULL;
1599 mbq->mbox_cmpl = NULL; /* no cmpl needed */
1600 mbq->port = (void *)&PPORT;
1601
1602 mb->mbxCommand = (volatile uint8_t) MBX_INIT_LINK;
1603 mb->mbxOwner = OWN_HOST;
1604 return;

--- 59 unchanged lines hidden (view full) ---

1664 break;
1665
1666 case 10:
1667 if (!(vpd->link_speed & LMT_10GB_CAPABLE)) {
1668 linkspeed = 0;
1669 }
1670 break;
1671
2097 bzero((void *) mb, MAILBOX_CMD_SLI4_BSIZE);
2098 mbq->nonembed = NULL;
2099 mbq->mbox_cmpl = NULL; /* no cmpl needed */
2100 mbq->port = (void *)&PPORT;
2101
2102 mb->mbxCommand = (volatile uint8_t) MBX_INIT_LINK;
2103 mb->mbxOwner = OWN_HOST;
2104 return;

--- 59 unchanged lines hidden (view full) ---

2164 break;
2165
2166 case 10:
2167 if (!(vpd->link_speed & LMT_10GB_CAPABLE)) {
2168 linkspeed = 0;
2169 }
2170 break;
2171
2172 case 16:
2173 if (!(vpd->link_speed & LMT_16GB_CAPABLE)) {
2174 linkspeed = 0;
2175 }
2176 break;
2177
1672 default:
1673 linkspeed = 0;
1674 break;
1675
1676 }
1677
1678 if ((linkspeed > 0) && (vpd->feaLevelHigh >= 0x02)) {
1679 mb->un.varInitLnk.link_flags |= FLAGS_LINK_SPEED;

--- 34 unchanged lines hidden (view full) ---

1714 return;
1715
1716} /* emlxs_mb_down_link() */
1717
1718
1719static uint32_t
1720emlxs_read_sparam_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq)
1721{
2178 default:
2179 linkspeed = 0;
2180 break;
2181
2182 }
2183
2184 if ((linkspeed > 0) && (vpd->feaLevelHigh >= 0x02)) {
2185 mb->un.varInitLnk.link_flags |= FLAGS_LINK_SPEED;

--- 34 unchanged lines hidden (view full) ---

2220 return;
2221
2222} /* emlxs_mb_down_link() */
2223
2224
2225static uint32_t
2226emlxs_read_sparam_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq)
2227{
1722 emlxs_port_t *port = (emlxs_port_t *)mbq->port;
2228 emlxs_port_t *port = &PPORT;
1723 MAILBOX *mb;
1724 MATCHMAP *mp;
1725 emlxs_port_t *vport;
1726 int32_t i;
1727 uint32_t control;
1728 uint8_t null_wwn[8];
1729
1730 mb = (MAILBOX *)mbq;

--- 32 unchanged lines hidden (view full) ---

1763 (caddr_t)&hba->sparam.portName, sizeof (NAME_TYPE));
1764 }
1765
1766 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
1767 "SPARAM: EDTOV hba=%x mbox_csp=%x BBC=%x",
1768 hba->fc_edtov, hba->sparam.cmn.e_d_tov,
1769 hba->sparam.cmn.bbCreditlsb);
1770
2229 MAILBOX *mb;
2230 MATCHMAP *mp;
2231 emlxs_port_t *vport;
2232 int32_t i;
2233 uint32_t control;
2234 uint8_t null_wwn[8];
2235
2236 mb = (MAILBOX *)mbq;

--- 32 unchanged lines hidden (view full) ---

2269 (caddr_t)&hba->sparam.portName, sizeof (NAME_TYPE));
2270 }
2271
2272 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2273 "SPARAM: EDTOV hba=%x mbox_csp=%x BBC=%x",
2274 hba->fc_edtov, hba->sparam.cmn.e_d_tov,
2275 hba->sparam.cmn.bbCreditlsb);
2276
1771 hba->sparam.cmn.e_d_tov = hba->fc_edtov;
1772
1773 /* Initialize the physical port */
2277 /* Initialize the physical port */
1774 bcopy((caddr_t)&hba->sparam,
1775 (caddr_t)&port->sparam, sizeof (SERV_PARM));
2278 bcopy((caddr_t)&hba->sparam, (caddr_t)&port->sparam,
2279 sizeof (SERV_PARM));
1776 bcopy((caddr_t)&hba->wwpn, (caddr_t)&port->wwpn,
1777 sizeof (NAME_TYPE));
1778 bcopy((caddr_t)&hba->wwnn, (caddr_t)&port->wwnn,
1779 sizeof (NAME_TYPE));
1780
1781 /* Initialize the virtual ports */
1782 for (i = 1; i < MAX_VPORTS; i++) {
1783 vport = &VPORT(i);
2280 bcopy((caddr_t)&hba->wwpn, (caddr_t)&port->wwpn,
2281 sizeof (NAME_TYPE));
2282 bcopy((caddr_t)&hba->wwnn, (caddr_t)&port->wwnn,
2283 sizeof (NAME_TYPE));
2284
2285 /* Initialize the virtual ports */
2286 for (i = 1; i < MAX_VPORTS; i++) {
2287 vport = &VPORT(i);
1784 if (vport->flag & EMLXS_PORT_BOUND) {
2288 if (! (vport->flag & EMLXS_PORT_BOUND)) {
1785 continue;
1786 }
1787
1788 bcopy((caddr_t)&hba->sparam,
1789 (caddr_t)&vport->sparam,
1790 sizeof (SERV_PARM));
1791
1792 bcopy((caddr_t)&vport->wwnn,

--- 16 unchanged lines hidden (view full) ---

1809extern uint32_t
1810emlxs_mb_read_sparam(emlxs_hba_t *hba, MAILBOXQ *mbq)
1811{
1812 MAILBOX *mb = (MAILBOX *)mbq;
1813 MATCHMAP *mp;
1814
1815 bzero((void *)mb, MAILBOX_CMD_BSIZE);
1816
2289 continue;
2290 }
2291
2292 bcopy((caddr_t)&hba->sparam,
2293 (caddr_t)&vport->sparam,
2294 sizeof (SERV_PARM));
2295
2296 bcopy((caddr_t)&vport->wwnn,

--- 16 unchanged lines hidden (view full) ---

2313extern uint32_t
2314emlxs_mb_read_sparam(emlxs_hba_t *hba, MAILBOXQ *mbq)
2315{
2316 MAILBOX *mb = (MAILBOX *)mbq;
2317 MATCHMAP *mp;
2318
2319 bzero((void *)mb, MAILBOX_CMD_BSIZE);
2320
1817 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF, 1)) == 0) {
2321 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF)) == 0) {
1818 mb->mbxCommand = MBX_READ_SPARM64;
1819
1820 return (1);
1821 }
1822
1823 mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (SERV_PARM);
1824 mb->un.varRdSparm.un.sp64.addrHigh = PADDR_HI(mp->phys);
1825 mb->un.varRdSparm.un.sp64.addrLow = PADDR_LO(mp->phys);

--- 114 unchanged lines hidden (view full) ---

1940 }
1941 }
1942
1943 return (0);
1944
1945} /* emlxs_mb_check_sparm() */
1946
1947
2322 mb->mbxCommand = MBX_READ_SPARM64;
2323
2324 return (1);
2325 }
2326
2327 mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (SERV_PARM);
2328 mb->un.varRdSparm.un.sp64.addrHigh = PADDR_HI(mp->phys);
2329 mb->un.varRdSparm.un.sp64.addrLow = PADDR_LO(mp->phys);

--- 114 unchanged lines hidden (view full) ---

2444 }
2445 }
2446
2447 return (0);
2448
2449} /* emlxs_mb_check_sparm() */
2450
2451
1948/* SLI3 */
1949static uint32_t
1950emlxs_reg_did_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq)
1951{
1952 emlxs_port_t *port = (emlxs_port_t *)mbq->port;
1953 MAILBOX *mb;
1954 MATCHMAP *mp;
1955 NODELIST *ndlp;
1956 emlxs_port_t *vport;
1957 SERV_PARM *sp;
1958 int32_t i;
1959 uint32_t control;
1960 uint32_t ldata;
1961 uint32_t ldid;
1962 uint16_t lrpi;
1963 uint16_t lvpi;
1964
2452
1965 mb = (MAILBOX *)mbq;
1966
2453
1967 if (mb->mbxStatus) {
1968 if (mb->mbxStatus == MBXERR_NO_RESOURCES) {
1969 control = mb->un.varRegLogin.un.sp.bdeSize;
1970 if (control == 0) {
1971 /* Special handle for vport PLOGI */
1972 if (mbq->iocbq == (uint8_t *)1) {
1973 mbq->iocbq = NULL;
1974 }
1975 return (0);
1976 }
1977 emlxs_mb_retry(hba, mbq);
1978 return (1);
1979 }
1980 if (mb->mbxStatus == MBXERR_RPI_FULL) {
1981 EMLXS_MSGF(EMLXS_CONTEXT,
1982 &emlxs_node_create_failed_msg,
1983 "Limit reached. count=%d", port->node_count);
1984 }
1985
1986 /* Special handle for vport PLOGI */
1987 if (mbq->iocbq == (uint8_t *)1) {
1988 mbq->iocbq = NULL;
1989 }
1990
1991 return (0);
1992 }
1993
1994 mp = (MATCHMAP *)mbq->bp;
1995 if (!mp) {
1996 return (0);
1997 }
1998
1999 ldata = mb->un.varWords[5];
2000 lvpi = (ldata & 0xffff) - hba->vpi_base;
2001 port = &VPORT(lvpi);
2002
2003 /* First copy command data */
2004 ldata = mb->un.varWords[0]; /* get rpi */
2005 lrpi = ldata & 0xffff;
2006
2007 ldata = mb->un.varWords[1]; /* get did */
2008 ldid = ldata & MASK_DID;
2009
2010 sp = (SERV_PARM *)mp->virt;
2011
2012 /* Create or update the node */
2013 ndlp = emlxs_node_create(port, ldid, lrpi, sp);
2014
2015 if (ndlp->nlp_DID == FABRIC_DID) {
2016 /* FLOGI/FDISC successfully completed on this port */
2017 mutex_enter(&EMLXS_PORT_LOCK);
2018 port->flag |= EMLXS_PORT_FLOGI_CMPL;
2019 mutex_exit(&EMLXS_PORT_LOCK);
2020
2021 /* If CLEAR_LA has been sent, then attempt to */
2022 /* register the vpi now */
2023 if (hba->state == FC_READY) {
2024 (void) emlxs_mb_reg_vpi(port, NULL);
2025 }
2026
2027 /*
2028 * If NPIV Fabric support has just been established on
2029 * the physical port, then notify the vports of the
2030 * link up
2031 */
2032 if ((lvpi == 0) &&
2033 (hba->flag & FC_NPIV_ENABLED) &&
2034 (hba->flag & FC_NPIV_SUPPORTED)) {
2035 /* Skip the physical port */
2036 for (i = 1; i < MAX_VPORTS; i++) {
2037 vport = &VPORT(i);
2038
2039 if (!(vport->flag & EMLXS_PORT_BOUND) ||
2040 !(vport->flag &
2041 EMLXS_PORT_ENABLE)) {
2042 continue;
2043 }
2044
2045 emlxs_port_online(vport);
2046 }
2047 }
2048 }
2049
2050 /* Check for special restricted login flag */
2051 if (mbq->iocbq == (uint8_t *)1) {
2052 mbq->iocbq = NULL;
2053 (void) emlxs_mb_unreg_node(port, ndlp, NULL, NULL, NULL);
2054 return (0);
2055 }
2056
2057 /* Needed for FCT trigger in emlxs_mb_deferred_cmpl */
2058 if (mbq->sbp) {
2059 ((emlxs_buf_t *)mbq->sbp)->node = ndlp;
2060 }
2061
2062#ifdef DHCHAP_SUPPORT
2063 if (mbq->sbp || mbq->ubp) {
2064 if (emlxs_dhc_auth_start(port, ndlp, mbq->sbp,
2065 mbq->ubp) == 0) {
2066 /* Auth started - auth completion will */
2067 /* handle sbp and ubp now */
2068 mbq->sbp = NULL;
2069 mbq->ubp = NULL;
2070 }
2071 }
2072#endif /* DHCHAP_SUPPORT */
2073
2074 return (0);
2075
2076} /* emlxs_reg_did_mbcmpl() */
2077
2078
2079/* SLI3 */
2080extern uint32_t
2081emlxs_mb_reg_did(emlxs_port_t *port, uint32_t did, SERV_PARM *param,
2082 emlxs_buf_t *sbp, fc_unsol_buf_t *ubp, IOCBQ *iocbq)
2083{
2084 emlxs_hba_t *hba = HBA;
2085 MATCHMAP *mp;
2086 MAILBOXQ *mbq;
2087 MAILBOX *mb;
2088 uint32_t rval;
2089
2090 if (hba->sli_mode == EMLXS_HBA_SLI4_MODE) {
2091 rval = emlxs_sli4_reg_did(port, did, param, sbp, ubp, iocbq);
2092 return (rval);
2093 }
2094
2095 /* Check for invalid node ids to register */
2096 if ((did == 0) && (!(hba->flag & FC_LOOPBACK_MODE))) {
2097 return (1);
2098 }
2099
2100 if (did & 0xff000000) {
2101 return (1);
2102 }
2103
2104 if ((rval = emlxs_mb_check_sparm(hba, param))) {
2105 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
2106 "Invalid service parameters. did=%06x rval=%d", did,
2107 rval);
2108
2109 return (1);
2110 }
2111
2112 /* Check if the node limit has been reached */
2113 if (port->node_count >= hba->max_nodes) {
2114 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
2115 "Limit reached. did=%06x count=%d", did,
2116 port->node_count);
2117
2118 return (1);
2119 }
2120
2121 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1))) {
2122 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
2123 "Unable to allocate mailbox. did=%x", did);
2124
2125 return (1);
2126 }
2127 mb = (MAILBOX *)mbq->mbox;
2128 bzero((void *)mb, MAILBOX_CMD_BSIZE);
2129
2130 /* Build login request */
2131 if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF, 1)) == 0) {
2132 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
2133
2134 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
2135 "Unable to allocate buffer. did=%x", did);
2136 return (1);
2137 }
2138 bcopy((void *)param, (void *)mp->virt, sizeof (SERV_PARM));
2139
2140 mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (SERV_PARM);
2141 mb->un.varRegLogin.un.sp64.addrHigh = PADDR_HI(mp->phys);
2142 mb->un.varRegLogin.un.sp64.addrLow = PADDR_LO(mp->phys);
2143 mb->un.varRegLogin.did = did;
2144 mb->un.varWords[30] = 0; /* flags */
2145 mb->mbxCommand = MBX_REG_LOGIN64;
2146 mb->mbxOwner = OWN_HOST;
2147 mb->un.varRegLogin.vpi = port->vpi;
2148 mb->un.varRegLogin.rpi = 0;
2149
2150 mbq->sbp = (void *)sbp;
2151 mbq->ubp = (void *)ubp;
2152 mbq->iocbq = (void *)iocbq;
2153 mbq->bp = (void *)mp;
2154 mbq->mbox_cmpl = emlxs_reg_did_mbcmpl;
2155 mbq->context = NULL;
2156 mbq->port = (void *)port;
2157
2158 rval = EMLXS_SLI_ISSUE_MBOX_CMD(hba, mbq, MBX_NOWAIT, 0);
2159 if ((rval != MBX_BUSY) && (rval != MBX_SUCCESS)) {
2160 emlxs_mem_put(hba, MEM_BUF, (void *)mp);
2161 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
2162
2163 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_node_create_failed_msg,
2164 "Unable to send mbox. did=%x", did);
2165 return (1);
2166 }
2167
2168 return (0);
2169
2170} /* emlxs_mb_reg_did() */
2171
2172/* SLI3 */
2173/*ARGSUSED*/
2174static uint32_t
2175emlxs_unreg_node_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq)
2176{
2177 emlxs_port_t *port = (emlxs_port_t *)mbq->port;
2178 MAILBOX *mb;
2179 NODELIST *node;
2180 uint16_t rpi;
2181
2182 node = (NODELIST *)mbq->context;
2183 mb = (MAILBOX *)mbq;
2184 rpi = (node)? node->nlp_Rpi:0xffff;
2185
2186 if (mb->mbxStatus) {
2187 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2188 "unreg_node_mbcmpl:failed. node=%p rpi=%x status=%x",
2189 node, rpi, mb->mbxStatus);
2190
2191 return (0);
2192 }
2193
2194 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2195 "unreg_node_mbcmpl: node=%p rpi=%x",
2196 node, rpi);
2197
2198 if (node) {
2199 emlxs_node_rm(port, node);
2200
2201 } else { /* All nodes */
2202 emlxs_node_destroy_all(port);
2203 }
2204
2205 return (0);
2206
2207} /* emlxs_unreg_node_mbcmpl */
2208
2209
2210/* SLI3 */
2211extern uint32_t
2212emlxs_mb_unreg_node(emlxs_port_t *port, NODELIST *node, emlxs_buf_t *sbp,
2213 fc_unsol_buf_t *ubp, IOCBQ *iocbq)
2214{
2215 emlxs_hba_t *hba = HBA;
2216 MAILBOXQ *mbq;
2217 MAILBOX *mb;
2218 uint16_t rpi;
2219 uint32_t rval;
2220
2221 if (hba->sli_mode == EMLXS_HBA_SLI4_MODE) {
2222 rval = emlxs_sli4_unreg_node(port, node, sbp, ubp, iocbq);
2223 return (rval);
2224 }
2225
2226 if (node) {
2227 /* Check for base node */
2228 if (node == &port->node_base) {
2229 /* just flush base node */
2230 (void) emlxs_tx_node_flush(port, &port->node_base,
2231 0, 0, 0);
2232 (void) emlxs_chipq_node_flush(port, 0,
2233 &port->node_base, 0);
2234
2235 port->did = 0;
2236
2237 /* Return now */
2238 return (1);
2239 }
2240
2241 rpi = (uint16_t)node->nlp_Rpi;
2242
2243 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2244 "unreg_node:%p rpi=%d", node, rpi);
2245
2246 /* This node must be (0xFFFFFE) which registered by vport */
2247 if (rpi == 0) {
2248 emlxs_node_rm(port, node);
2249 return (0);
2250 }
2251
2252 } else { /* Unreg all nodes */
2253 rpi = 0xffff;
2254
2255 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2256 "unreg_node: All");
2257 }
2258
2259 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1))) {
2260 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2261 "unreg_node:failed. Unable to allocate mbox");
2262 return (1);
2263 }
2264
2265 mb = (MAILBOX *)mbq->mbox;
2266 mb->un.varUnregLogin.rpi = rpi;
2267 mb->un.varUnregLogin.vpi = port->VPIobj.VPI;
2268
2269 mb->mbxCommand = MBX_UNREG_LOGIN;
2270 mb->mbxOwner = OWN_HOST;
2271 mbq->sbp = (void *)sbp;
2272 mbq->ubp = (void *)ubp;
2273 mbq->iocbq = (void *)iocbq;
2274 mbq->mbox_cmpl = emlxs_unreg_node_mbcmpl;
2275 mbq->context = (void *)node;
2276 mbq->port = (void *)port;
2277
2278 rval = EMLXS_SLI_ISSUE_MBOX_CMD(hba, mbq, MBX_NOWAIT, 0);
2279 if ((rval != MBX_BUSY) && (rval != MBX_SUCCESS)) {
2280 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2281 "unreg_node:failed. Unable to send request.");
2282
2283 emlxs_mem_put(hba, MEM_MBOX, (void *)mbq);
2284 return (1);
2285 }
2286
2287 return (0);
2288
2289} /* emlxs_mb_unreg_node() */
2290
2291
2292
2293
2294/*
2295 * emlxs_mb_set_var Issue a special debug mbox command to write slim
2296 */
2297/*ARGSUSED*/
2298extern void
2299emlxs_mb_set_var(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t addr,
2300 uint32_t value)
2301{

--- 177 unchanged lines hidden (view full) ---

2479 mutex_exit(&EMLXS_PORT_LOCK);
2480
2481 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2482 "reg_vpi:%d failed. Port did=0",
2483 port->vpi);
2484 return (1);
2485 }
2486
2454/*
2455 * emlxs_mb_set_var Issue a special debug mbox command to write slim
2456 */
2457/*ARGSUSED*/
2458extern void
2459emlxs_mb_set_var(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t addr,
2460 uint32_t value)
2461{

--- 177 unchanged lines hidden (view full) ---

2639 mutex_exit(&EMLXS_PORT_LOCK);
2640
2641 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2642 "reg_vpi:%d failed. Port did=0",
2643 port->vpi);
2644 return (1);
2645 }
2646
2487 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1))) {
2647 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX))) {
2488 mutex_exit(&EMLXS_PORT_LOCK);
2489
2490 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2491 "reg_vpi:%d failed. Unable to allocate mbox.",
2492 port->vpi);
2493 return (1);
2494 }
2495

--- 81 unchanged lines hidden (view full) ---

2577 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2578 "unreg_vpi:%d failed. Not registered. flag=%x",
2579 port->vpi, port->flag);
2580
2581 mutex_exit(&EMLXS_PORT_LOCK);
2582 return (0);
2583 }
2584
2648 mutex_exit(&EMLXS_PORT_LOCK);
2649
2650 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2651 "reg_vpi:%d failed. Unable to allocate mbox.",
2652 port->vpi);
2653 return (1);
2654 }
2655

--- 81 unchanged lines hidden (view full) ---

2737 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2738 "unreg_vpi:%d failed. Not registered. flag=%x",
2739 port->vpi, port->flag);
2740
2741 mutex_exit(&EMLXS_PORT_LOCK);
2742 return (0);
2743 }
2744
2585 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX, 1))) {
2745 if (!(mbq = (MAILBOXQ *)emlxs_mem_get(hba, MEM_MBOX))) {
2586 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2587 "unreg_vpi:%d failed. Unable to allocate mbox.",
2588 port->vpi);
2589
2590 mutex_exit(&EMLXS_PORT_LOCK);
2591 return (1);
2592 }
2593

--- 174 unchanged lines hidden (view full) ---

2768emlxs_mb_init(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t flag, uint32_t tmo)
2769{
2770 MATCHMAP *mp;
2771
2772 HBASTATS.MboxIssued++;
2773 hba->mbox_queue_flag = flag;
2774
2775 /* Set the Mailbox timer */
2746 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg,
2747 "unreg_vpi:%d failed. Unable to allocate mbox.",
2748 port->vpi);
2749
2750 mutex_exit(&EMLXS_PORT_LOCK);
2751 return (1);
2752 }
2753

--- 174 unchanged lines hidden (view full) ---

2928emlxs_mb_init(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t flag, uint32_t tmo)
2929{
2930 MATCHMAP *mp;
2931
2932 HBASTATS.MboxIssued++;
2933 hba->mbox_queue_flag = flag;
2934
2935 /* Set the Mailbox timer */
2776 hba->mbox_timer = hba->timer_tics + tmo;
2936 if (hba->timer_tics) {
2937 hba->mbox_timer = hba->timer_tics + tmo;
2938 } else {
2939 hba->mbox_timer = DRV_TIME + tmo;
2940 }
2777
2778 /* Initialize mailbox */
2779 mbq->flag &= MBQ_INIT_MASK;
2780 mbq->next = 0;
2781
2782 mutex_enter(&EMLXS_MBOX_LOCK);
2783 hba->mbox_mbq = (void *)mbq;
2784 mutex_exit(&EMLXS_MBOX_LOCK);

--- 59 unchanged lines hidden (view full) ---

2844
2845 hba->mbox_mbq = NULL;
2846 hba->mbox_queue_flag = 0;
2847 hba->mbox_timer = 0;
2848 mutex_exit(&EMLXS_MBOX_LOCK);
2849
2850 mutex_exit(&EMLXS_PORT_LOCK);
2851
2941
2942 /* Initialize mailbox */
2943 mbq->flag &= MBQ_INIT_MASK;
2944 mbq->next = 0;
2945
2946 mutex_enter(&EMLXS_MBOX_LOCK);
2947 hba->mbox_mbq = (void *)mbq;
2948 mutex_exit(&EMLXS_MBOX_LOCK);

--- 59 unchanged lines hidden (view full) ---

3008
3009 hba->mbox_mbq = NULL;
3010 hba->mbox_queue_flag = 0;
3011 hba->mbox_timer = 0;
3012 mutex_exit(&EMLXS_MBOX_LOCK);
3013
3014 mutex_exit(&EMLXS_PORT_LOCK);
3015
3016#ifdef SFCT_SUPPORT
3017 if (mb && mbox_sbp && mbox_sbp->fct_cmd) {
3018 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_detail_msg,
3019 "FCT mailbox: %s: status=%x",
3020 emlxs_mb_cmd_xlate(mb->mbxCommand),
3021 mb->mbxStatus);
3022 }
3023#endif /* SFCT_SUPPORT */
3024
2852 if (mbox_queue_flag == MBX_NOWAIT) {
2853 /* Check for deferred MBUF cleanup */
2854 if (mbox_bp) {
2855 emlxs_mem_put(hba, MEM_BUF, (void *)mbox_bp);
2856 }
2857 if (mbox_nonembed) {
2858 emlxs_mem_put(hba, MEM_BUF,
2859 (void *)mbox_nonembed);

--- 28 unchanged lines hidden (view full) ---

2888 /* Wake up the sleeping thread */
2889 if (mbox_queue_flag == MBX_SLEEP) {
2890 mutex_enter(&EMLXS_MBOX_LOCK);
2891 cv_broadcast(&EMLXS_MBOX_CV);
2892 mutex_exit(&EMLXS_MBOX_LOCK);
2893 }
2894 }
2895
3025 if (mbox_queue_flag == MBX_NOWAIT) {
3026 /* Check for deferred MBUF cleanup */
3027 if (mbox_bp) {
3028 emlxs_mem_put(hba, MEM_BUF, (void *)mbox_bp);
3029 }
3030 if (mbox_nonembed) {
3031 emlxs_mem_put(hba, MEM_BUF,
3032 (void *)mbox_nonembed);

--- 28 unchanged lines hidden (view full) ---

3061 /* Wake up the sleeping thread */
3062 if (mbox_queue_flag == MBX_SLEEP) {
3063 mutex_enter(&EMLXS_MBOX_LOCK);
3064 cv_broadcast(&EMLXS_MBOX_CV);
3065 mutex_exit(&EMLXS_MBOX_LOCK);
3066 }
3067 }
3068
2896#ifdef SFCT_SUPPORT
2897 if (mb && mbox_sbp && mbox_sbp->fct_cmd) {
2898 EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_fct_detail_msg,
2899 "FCT mailbox: %s: status=%x",
2900 emlxs_mb_cmd_xlate(mb->mbxCommand),
2901 (uint32_t)mb->mbxStatus);
2902 }
2903#endif /* SFCT_SUPPORT */
2904
2905 emlxs_mb_deferred_cmpl(port, mbxStatus, mbox_sbp, mbox_ubp, mbox_iocbq);
2906
2907 return;
2908
2909} /* emlxs_mb_fini() */
2910
2911
2912extern void
2913emlxs_mb_deferred_cmpl(emlxs_port_t *port, uint32_t mbxStatus, emlxs_buf_t *sbp,
2914 fc_unsol_buf_t *ubp, IOCBQ *iocbq)
2915{
2916 emlxs_hba_t *hba = HBA;
2917 emlxs_ub_priv_t *ub_priv;
2918
2919#ifdef SFCT_SUPPORT
3069 emlxs_mb_deferred_cmpl(port, mbxStatus, mbox_sbp, mbox_ubp, mbox_iocbq);
3070
3071 return;
3072
3073} /* emlxs_mb_fini() */
3074
3075
3076extern void
3077emlxs_mb_deferred_cmpl(emlxs_port_t *port, uint32_t mbxStatus, emlxs_buf_t *sbp,
3078 fc_unsol_buf_t *ubp, IOCBQ *iocbq)
3079{
3080 emlxs_hba_t *hba = HBA;
3081 emlxs_ub_priv_t *ub_priv;
3082
3083#ifdef SFCT_SUPPORT
2920 if ((mbxStatus == MBX_SUCCESS) && sbp && sbp->fct_cmd) {
2921 emlxs_buf_t *cmd_sbp = sbp;
3084 if (sbp && sbp->fct_cmd && (sbp->fct_state == EMLXS_FCT_REG_PENDING)) {
3085 mutex_enter(&EMLXS_PKT_LOCK);
3086 sbp->fct_flags |= EMLXS_FCT_REGISTERED;
3087 cv_broadcast(&EMLXS_PKT_CV);
3088 mutex_exit(&EMLXS_PKT_LOCK);
2922
3089
2923 if ((cmd_sbp->fct_state == EMLXS_FCT_REG_PENDING) &&
2924 (cmd_sbp->node)) {
2925
2926 mutex_enter(&EMLXS_PKT_LOCK);
2927 cmd_sbp->fct_flags |= EMLXS_FCT_REGISTERED;
2928 cv_broadcast(&EMLXS_PKT_CV);
2929 mutex_exit(&EMLXS_PKT_LOCK);
2930
2931 sbp = NULL;
2932 }
3090 sbp = NULL;
2933 }
2934#endif /* SFCT_SUPPORT */
2935
2936 /* Check for deferred pkt completion */
2937 if (sbp) {
2938 if (mbxStatus != MBX_SUCCESS) {
2939 /* Set error status */
2940 sbp->pkt_flags &= ~PACKET_STATE_VALID;

--- 80 unchanged lines hidden (view full) ---

3021
3022 count = sizeof (emlxs_mb_cmd_table) / sizeof (emlxs_table_t);
3023 for (i = 0; i < count; i++) {
3024 if (cmd == emlxs_mb_cmd_table[i].code) {
3025 return (emlxs_mb_cmd_table[i].string);
3026 }
3027 }
3028
3091 }
3092#endif /* SFCT_SUPPORT */
3093
3094 /* Check for deferred pkt completion */
3095 if (sbp) {
3096 if (mbxStatus != MBX_SUCCESS) {
3097 /* Set error status */
3098 sbp->pkt_flags &= ~PACKET_STATE_VALID;

--- 80 unchanged lines hidden (view full) ---

3179
3180 count = sizeof (emlxs_mb_cmd_table) / sizeof (emlxs_table_t);
3181 for (i = 0; i < count; i++) {
3182 if (cmd == emlxs_mb_cmd_table[i].code) {
3183 return (emlxs_mb_cmd_table[i].string);
3184 }
3185 }
3186
3029 (void) sprintf(buffer, "Cmd=0x%x", cmd);
3187 (void) snprintf(buffer, sizeof (buffer), "Cmd=0x%x", cmd);
3030 return (buffer);
3031
3032} /* emlxs_mb_cmd_xlate() */
3188 return (buffer);
3189
3190} /* emlxs_mb_cmd_xlate() */
3191
3192extern char *
3193emlxs_request_feature_xlate(uint32_t mask)
3194{
3195 static char buffer[64];
3196 uint32_t i;
3197
3198 bzero((char *)&buffer[0], 64);
3199 for (i = 0; i < 12; i++) {
3200 if (mask & (1<<i)) {
3201 (void) strlcat(buffer,
3202 emlxs_request_feature_table[i].string,
3203 sizeof (buffer));
3204 }
3205 }
3206 return (buffer);
3207}